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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 //////////////////////////////////////////////////////////////////////////////////////////////////// 96 // file halAESDMA.h 97 // @brief AESDMA HAL 98 // @author MStar Semiconductor,Inc. 99 //////////////////////////////////////////////////////////////////////////////////////////////////// 100 #ifndef __HAL_RSA_H__ 101 #define __HAL_RSA_H__ 102 103 104 //-------------------------------------------------------------------------------------------------- 105 // Driver Compiler Option 106 //-------------------------------------------------------------------------------------------------- 107 108 //-------------------------------------------------------------------------------------------------- 109 // AESDMA Hardware Abstraction Layer 110 //-------------------------------------------------------------------------------------------------- 111 112 // TSP Register 113 #define _TspPid ((REG_Pid*)(REG_PIDFLT_BASE)) 114 #define _TspSec ((REG_Sec*)(REG_SECFLT_BASE)) 115 116 #define DIGEST_SIZE_SHA1 5 //160-bit 117 #define DIGEST_SIZE_SHA256 8 //256-bit 118 #define SHA_MIU1_ENABLE 0x80000000 //Enable access MIU1 119 #define SHA_UNIT_SIZE 8 //64-bits 120 121 //-------------------------------------------------------------------------------------------------- 122 // Macro of bit operations 123 //-------------------------------------------------------------------------------------------------- 124 #define HAS_FLAG(flag, bit) ((flag) & (bit)) 125 #define SET_FLAG(flag, bit) ((flag)|= (bit)) 126 #define RESET_FLAG(flag, bit) ((flag)&= (~(bit))) 127 #define SET_FLAG1(flag, bit) ((flag)| (bit)) 128 #define RESET_FLAG1(flag, bit) ((flag)& (~(bit))) 129 130 131 typedef enum { 132 RAM_READ = 0x0, 133 RAM_WRITE = 0x1 134 } RAM_DIR_t; 135 136 137 typedef enum { 138 E_RSA_SW_RESET_OFF = 0x0, 139 E_RSA_SW_RESET_ON = 0x1 140 } RSA_SW_RESET_t; 141 142 typedef enum { 143 E_RSA_USE_SW_KEY = 0x0, 144 E_RSA_USE_HW_KEY = 0x1 145 } RSA_HW_KEY_t; 146 147 typedef enum { 148 E_RSA_USE_PRIV_KEY = 0x0, 149 E_RSA_USE_PUB_KEY = 0x1 150 } RSA_PUB_KEY_t; 151 152 typedef enum { 153 E_RSA_HW_PRI_KEY = 0x0, 154 E_RSA_HW_PUB_KEY1 = 0x1, 155 E_RSA_HW_PUB_KEY2 = 0x2 156 } RSA_PUB_KEY_SEL_t; 157 158 159 /// HW PARSER Mode 160 161 162 typedef enum 163 { 164 E_RSA_ADDRESS_E = 0, 165 E_RSA_ADDRESS_N, 166 E_RSA_ADDRESS_A, 167 E_RSA_ADDRESS_Z, 168 } RSA_IND32Address; 169 170 171 172 173 174 //////////////////////////////////////////////// 175 // HAL API 176 //////////////////////////////////////////////// 177 void HAL_RSA_ClearInt(void); 178 void HAL_RSA_Reset(void); 179 void HAL_RSA_Ind32Ctrl(MS_U8 u8dirction); 180 void HAL_RSA_LoadSram(MS_U32 *u32Buf, RSA_IND32Address eMode); 181 void HAL_RSA_SetKeyLength(MS_U32 u32keylen); 182 void HAL_RSA_SetKeyType(MS_U8 u8hwkey, MS_U8 u8pubkey); 183 void HAL_RSA_Rootkey_Sel(MS_U8 u8KeySrc); 184 void HAL_RSA_ExponetialStart(void); 185 MS_U32 HAL_RSA_GetStatus(void); 186 void HAL_RSA_FileOutStart(void); 187 void HAL_RSA_SetFileOutAddr(MS_U32 u32offset); 188 MS_U32 HAL_RSA_FileOut(void); 189 MS_U32 HAL_RSA_Get_RSA_IsFinished(void); 190 void HAL_RSA_SetBank(MS_VIRT u32NonPmBankAddr); 191 192 MS_BOOL HAL_RSA_SetSecureRange(MS_U32 u32addr, MS_U32 u32size); 193 194 void HAL_RSA_Hwkey_Switch(void); 195 MS_U32 HAL_RSA_Read_Hwkey_Switch(void); 196 197 #endif // #ifndef __HAL_TSP_H__ 198