1 //////////////////////////////////////////////////////////////////////////////// 2 // 3 // Copyright (c) 2006-2009 MStar Semiconductor, Inc. 4 // All rights reserved. 5 // 6 // Unless otherwise stipulated in writing, any and all information contained 7 // herein regardless in any format shall remain the sole proprietary of 8 // MStar Semiconductor Inc. and be kept in strict confidence 9 // ("MStar Confidential Information") by the recipient. 10 // Any unauthorized act including without limitation unauthorized disclosure, 11 // copying, use, reproduction, sale, distribution, modification, disassembling, 12 // reverse engineering and compiling of the contents of MStar Confidential 13 // Information is unlawful and strictly prohibited. MStar hereby reserves the 14 // rights to any and all damages, losses, costs and expenses resulting therefrom. 15 // 16 //////////////////////////////////////////////////////////////////////////////// 17 18 //////////////////////////////////////////////////////////////////////////////////////////////////// 19 // file halCIPHER.h 20 // @brief CIPHER HAL 21 // @author MStar Semiconductor,Inc. 22 //////////////////////////////////////////////////////////////////////////////////////////////////// 23 #ifndef __HAL_CIPHER_H__ 24 #define __HAL_CIPHER_H__ 25 26 #include "regCIPHER.h" 27 #include "drvCIPHER.h" 28 29 //-------------------------------------------------------------------------------------------------- 30 // Driver Compiler Option 31 //-------------------------------------------------------------------------------------------------- 32 33 //-------------------------------------------------------------------------------------------------- 34 // CIPHER Software Define 35 //-------------------------------------------------------------------------------------------------- 36 #define HAL_CIPHER_RESETKEY_TIMEOUT_VALUE (1000UL) 37 38 //-------------------------------------------------------------------------------------------------- 39 // CIPHER Hardware Abstraction Layer 40 //-------------------------------------------------------------------------------------------------- 41 42 #define HAL_CRYPTODMA_KEYLEN_MAX 16UL 43 #define HAL_CRYPTODMA_DIRDATA_MAX 16UL 44 #define HAL_CRYPTODMA_OTPHASH_UNIT 16UL 45 #define HAL_CRYPTODMA_OTPHASH_SIZE_MIN 32UL 46 #define HAL_CRYPTODMA_THREAD_ID_MAX 0xFFFFUL 47 #define HAL_CRYPTODMA_DMA_KEY_SLOT 4UL 48 #define HAL_CRYPTODMA_OTP_SCK_NUM 4UL 49 #define HAL_CRYPTODMA_CAVID_MAX 0x1FUL 50 //-------------------------------------------------------------------------------------------------- 51 // Macro of bit operations 52 //-------------------------------------------------------------------------------------------------- 53 #define HAS_FLAG(flag, bit) ((flag) & (bit)) 54 #define SET_FLAG(flag, bit) ((flag)|= (bit)) 55 #define RESET_FLAG(flag, bit) ((flag)&= (~(bit))) 56 #define SET_FLAG1(flag, bit) ((flag)| (bit)) 57 #define RESET_FLAG1(flag, bit) ((flag)& (~(bit))) 58 59 //////////////////////////////////////////////////////////////////////////////////////////////// 60 // QMEM base address 61 //////////////////////////////////////////////////////////////////////////////////////////////// 62 #define HAL_CIPHER_BASE_IQMEM 0x00000000UL 63 #define HAL_CIPHER_BASE_DQMEM 0x80000000UL 64 #define HAL_CIPHER_BASE_LUT 0x00000010 65 #define HAL_CIPHER_SIZE_LUT 256 66 #define HAL_CIPHER_BASE_M 0x00000110 67 #define HAL_CIPHER_SIZE_M 128 68 #define HAL_CIPHER_BASE_BC 0x00000190 69 #define HAL_CIPHER_SIZE_BC 16 70 71 //////////////////////////////////////////////////////////////////////////////////////////////// 72 // IRQ 73 //////////////////////////////////////////////////////////////////////////////////////////////// 74 #define CRYPTODMA_IRQ E_INT_FIQ_CA_CRYPTO_DMA //halIRQTBL.h CryptoDMA FIQ 56 75 76 //////////////////////////////////////////////////////////////////////////////////////////////// 77 // Except 78 //////////////////////////////////////////////////////////////////////////////////////////////// 79 #define HAL_CIPHER_EXCEPT_CAVID 0x0001UL 80 #define HAL_CIPHER_EXCEPT_DATA 0x0002UL 81 #define HAL_CIPHER_EXCEPT_ALGO 0x0004UL 82 #define HAL_CIPHER_EXCEPT_DMA_KEY 0x0008UL 83 #define HAL_CIPHER_EXCEPT_HMAC_KEY 0x0010UL 84 85 //////////////////////////////////////////////////////////////////////////////////////////////// 86 // AESDMA Compatible 87 //////////////////////////////////////////////////////////////////////////////////////////////// 88 #define HAL_CIPHER_KEYSLOT_BASE 0x10UL 89 90 typedef enum 91 { 92 E_CIPHER_CAVID1 = 0x0001, 93 E_CIPHER_CAVID2 = 0x0002, 94 E_CIPHER_CAVID3 = 0x0003, 95 E_CIPHER_CAVID4 = 0x0004, 96 E_CIPHER_CAVID5 = 0x0005, 97 E_CIPHER_CAVID6 = 0x0006, 98 }HAL_CIPHER_CAVID; 99 100 /// SHA Mode 101 typedef enum 102 { 103 E_HASH_SHA1 = 0, 104 E_HASH_SHA256, 105 E_HASH_MD5, 106 }HAL_CIPHER_HASHMODE; 107 108 typedef enum 109 { 110 E_DMA_ALGO_NONE = 0, 111 E_DMA_ALGO_AES = 1, 112 E_DMA_ALGO_DES = 2, 113 E_DMA_ALGO_TDES = 3, 114 E_DMA_ALGO_M6_S56_CCBC = 4 , 115 E_DMA_ALGO_M6_S56 =5 , 116 E_DMA_ALGO_M6_KE56 = 7 , 117 E_DMA_ALGO_RC4 = 8, 118 E_DMA_ALGO_RC4_128 = 9, 119 }HAL_CIPHER_ALGO; 120 121 typedef enum 122 { 123 E_DMA_MODE_NONE = 0, 124 E_DMA_MODE_ECB = 0, 125 E_DMA_MODE_CBC, 126 E_DMA_MODE_CTR, 127 E_DMA_MODE_CBC_MAC, 128 E_DMA_MODE_CTR_64, 129 E_DMA_MODE_CMAC_Key, 130 E_DMA_MODE_CMAC_Algo, 131 E_DMA_MODE_PCBC_ADD, 132 E_DMA_MODE_PCBC_XOR, 133 E_DMA_MODE_OTPHASH, 134 E_DMA_MODE_NUM, 135 136 }HAL_CIPHER_MODE; 137 138 typedef enum 139 { 140 // From KL 141 E_DMA_KSEL_SK0 = 0 , 142 E_DMA_KSEL_SK1 = 1 , 143 E_DMA_KSEL_SK2 = 2 , 144 E_DMA_KSEL_SK3 = 3 , 145 146 // From OTP 147 E_DMA_KSEL_MK0 = 4 , 148 E_DMA_KSEL_MK1 = 5 , 149 E_DMA_KSEL_CCCK = 6 , 150 E_DMA_KSEL_STRN = 7 , 151 152 // From CPU 153 E_DMA_KSEL_REGKEY, 154 155 //From NSK 156 E_DMA_KSEL_CAIP, 157 158 }HAL_CIPHER_KEYSRC; 159 160 typedef enum 161 { 162 E_DMA_SRC_DIRECT = 0 , 163 E_DMA_SRC_DRAM = 1 , 164 E_DMA_SRC_IQMEM = 2 , 165 E_DMA_SRC_DQMEM = 2 , 166 E_DMA_SRC_HW_INPUT = 3 167 }HAL_CIPHER_DATASRC; 168 169 typedef enum 170 { 171 E_DMA_DST_DRAM = 0 , 172 E_DMA_DST_REGFILE = 1 , 173 E_DMA_DST_IQMEM = 1 , 174 E_DMA_DST_DQMEM = 1 , 175 }HAL_CIPHER_DATADST; 176 177 typedef enum 178 { 179 E_DMA_RESIDUE_NONE = 0 , 180 E_DMA_RESIDUE_CLR = 0 , 181 E_DMA_RESIDUE_CTS = 1 , 182 E_DMA_RESIDUE_SCTE52 = 2 , 183 E_DMA_RESIDUE_NUM , 184 185 }HAL_CIPHER_RESIDUE; 186 187 typedef enum 188 { 189 E_DMA_SB_NONE = 0 , 190 E_DMA_SB_CLR = 0 , 191 E_DMA_SB_IV1 , 192 E_DMA_SB_IV2 , 193 E_DMA_SB_NUM , 194 195 }HAL_CIPHER_SHORTBLOCK; 196 197 typedef enum 198 { 199 E_DMA_INT_NONE = 0 , 200 E_DMA_INT_ENABLE = 1 , 201 E_DMA_INT_EN_WAIT = 2 , 202 203 }HAL_CIPHER_INTMODE; 204 205 typedef enum 206 { 207 E_CIPHER_HASH_IWC_PRV = 0, 208 E_CIPHER_HASH_IWC_MANUAL, 209 }HAL_CIPHER_IWCTYPE; 210 211 typedef enum 212 { 213 E_CIPHER_TYPE_DMA = 0 , 214 E_CIPHER_TYPE_SHA , 215 E_CIPHER_TYPE_OTPHASH , 216 217 }HAL_CIPHER_CMDTYPE; 218 219 typedef enum 220 { 221 E_PARSER_HDCPMODE_NONE = 0, 222 E_PARSER_HDCPMODE_HDCP20, 223 224 }HAL_CIPHER_PARSER_HDCPMODE; 225 226 typedef enum 227 { 228 E_PARSER_TSMODE_PES = 0, 229 E_PARSER_TSMODE_TS, 230 231 }HAL_CIPHER_PARSER_TSMODE; 232 233 typedef enum 234 { 235 E_PARSER_PKTMODE_188 = 0, 236 E_PARSER_PKTMODE_192, 237 238 }HAL_CIPHER_PARSER_PKTMODE; 239 240 typedef enum 241 { 242 E_PARSER_AUTOMODE_NONE = 0, 243 E_PARSER_AUTOMODE_EN, 244 245 }HAL_CIPHER_PARSER_AUTOMODE; 246 247 typedef enum 248 { 249 E_PARSER_ITMODE_NONE = 0, 250 E_PARSER_ITMODE_EN, 251 252 }HAL_CIPHER_PARSER_ITMODE; //Init trust 253 254 typedef enum 255 { 256 E_PARSER_CLEARMODE_NONE = 0, 257 E_PARSER_CLEARMODE_EN, 258 259 }HAL_CIPHER_PARSER_CLEARMODE; 260 261 //Tmp area, open to drv level latter 262 typedef struct 263 { 264 MS_U32 u32ObfIdxR; 265 MS_U32 u32ObfIdxW; 266 }DRV_CIPHER_OBF; 267 268 typedef enum 269 { 270 E_CIPHER_PARSER_TS_PKT192 = 0, 271 E_CIPHER_PARSER_TS_PKT192_CLEAR, 272 E_CIPHER_PARSER_TS_PKT188, 273 E_CIPHER_PARSER_TS_PKT188_CLEAR, 274 E_CIPHER_PARSER_HDCP20_PKT192, 275 E_CIPHER_PARSER_HDCP20_PKT192_CLEAR, 276 E_CIPHER_PARSER_HDCP20_PKT188, 277 E_CIPHER_PARSER_HDCP20_PKT188_CLEAR, 278 } CIPHER_PARSER_MODE; 279 280 typedef struct 281 { 282 MS_U8 *pu8PID0; 283 MS_U8 *pu8PID1; 284 }CIPHER_PARSER_PID; 285 286 typedef enum 287 { 288 E_CIPHER_PARSER_SCB_NONE = 0, 289 E_CIPHER_PARSER_SCB_10, 290 E_CIPHER_PARSER_SCB_11, 291 } CIPHER_PARSER_SCB; 292 293 typedef struct 294 { 295 CIPHER_PARSER_SCB eSCB; //Transport Stream Scramble Pattern, decide 10 or 11 or 1x need to scrambled (TS layer) 296 CIPHER_PARSER_SCB eFSCB; 297 MS_BOOL bTsScrbMask; //Transport Stream Mask 298 MS_BOOL bRmvScrb; //Remove Scramble 299 MS_BOOL bInScrb; //Insert Scramble 300 } CIPHER_PARSER_TSCFG; 301 302 303 typedef struct 304 { 305 DRV_CIPHER_ALGO stAlgo; 306 DRV_CIPHER_KEY stKey; 307 DRV_CIPHER_DATA stInput; 308 DRV_CIPHER_DATA stOutput; 309 MS_BOOL bDecrypt; 310 CIPHER_PARSER_MODE eParserMode; 311 CIPHER_PARSER_TSCFG stTSCfg; 312 CIPHER_PARSER_PID stPID; 313 DRV_CIPHER_KEY stKey2; 314 MS_U32 u32CAVid; 315 MS_BOOL bClearHead; 316 P_DrvCIPHER_EvtCallback pfCallback; 317 }CIPHER_PARSERCFG; 318 319 //////////////////////////////////////////////// 320 // HAL API 321 //////////////////////////////////////////////// 322 void HAL_CIPHER_SetBank(MS_VIRT u32BankAddr) ; 323 void HAL_CIPHER_ResetStatus(MS_BOOL RstDma , MS_BOOL RstSha); 324 void HAL_CIPHER_ResetException(void); 325 MS_BOOL HAL_CIPHER_ResetKey(MS_U32 u32KeyIdx); 326 void HAL_CIPHER_SetDbgLevel(CIPHER_DBGMSG_LEVEL eDBGMsgLevel); 327 328 void HAL_CIPHER_SWReset(void); 329 330 void HAL_CIPHER_DMA_Set_InputSrcFrom(CIPHER_MEM_TYPE InputSrcFrom, MS_U8* pu8Data, MS_U32 u32Size); 331 MS_BOOL HAL_CIPHER_DMA_Set_OutputDstTo(CIPHER_MEM_TYPE OutputDstTo, MS_U8* pu8Data, MS_U32 u32Size); 332 void HAL_CIPHER_DMA_Set_OutputDstKL(MS_BOOL bDstKL); 333 334 335 void HAL_CIPHER_DMA_Set_FileinDesc(MS_PHY FileinAddr, MS_U32 u32FileinNum); 336 void HAL_CIPHER_DMA_Set_FileoutDesc(MS_PHY FileoutSAddr, MS_PHY phyFileoutEAddr); 337 void HAL_CIPHER_OTPHash_Set_FileinDesc(MS_PHY u32FileinAddr, MS_U32 u32FileinNum, MS_U32 u32CurrentRound, CIPHER_MEM_TYPE eInputSrcFrom); 338 339 MS_BOOL HAL_CIPHER_DMA_Set_Key(DRV_CIPHER_KEY stKey); 340 void HAL_CIPHER_DMA_Set_IV(MS_U8* pu8IV, MS_U32 u32Size); 341 342 MS_BOOL HAL_CIPHER_DMA_Set_Data(MS_U8* pu8Data, MS_U32 u32Size); 343 void HAL_CIPHER_DMA_Set_Config(MS_BOOL OutputReg); 344 void HAL_CIPHER_DMA_Set_ReportMode(MS_BOOL RptInDram, MS_PHY u32DramAddr); 345 346 void HAL_CIPHER_DMA_Set_DataSwap(MS_BOOL InDataSwap , MS_BOOL OutDataSwap, 347 MS_BOOL DInByteSwap, MS_BOOL DOutByteSwap ); 348 349 void HAL_CIPHER_DMA_Set_Algo(DRV_CIPHER_ALGO stAlgo); 350 351 void HAL_CIPHER_DMA_Set_OTPHash(MS_U32 u32CurrentRound, MS_U32 u32OTPHashRound); 352 353 MS_BOOL HAL_CIPHER_DMA_Start(MS_BOOL Decrypt , HAL_CIPHER_INTMODE IntMode , MS_BOOL bWaitCmdQ, MS_U16 u16CmdID); 354 MS_BOOL HAL_CIPHER_OTPHash_Start(HAL_CIPHER_INTMODE IntMode , MS_BOOL bWaitCmdQ, MS_U16 u16CmdID); 355 MS_BOOL HAL_CIPHER_DMA_CmdDone(MS_U32 u32CmdID, MS_U32 *u32Ret); 356 357 void HAL_CIPHER_DMA_WriteCMDQ(MS_U32 u32Cmd); 358 359 MS_BOOL HAL_CIPHER_DMA_Set_CaVid(MS_U32 u32CAVid); 360 361 void HAL_CIPHER_DMA_GetRpt(MS_U32 *DmaRpt); 362 void HAL_CIPHER_DMA_GetData(MS_U8 *u8Data) ; 363 void HAL_CIPHER_DMA_AlgoTable_Init(void); 364 MS_BOOL HAL_CIPHER_DMA_CheckAlgo(HAL_CIPHER_ALGO eAlgo, HAL_CIPHER_MODE eMode, HAL_CIPHER_RESIDUE eRes, HAL_CIPHER_SHORTBLOCK eSB); 365 void HAL_CIPHER_Hash_SetMsgLength( MS_U32 u32Size ); 366 MS_BOOL HAL_CIPHER_Hash_SetMsg(MS_PHY u32MsgPAddr, MS_U32 u32Size ,MS_U32 u32SrcSel ); 367 void HAL_CIPHER_Hash_SetHOS(MS_BOOL bHos); 368 MS_BOOL HAL_CIPHER_Hash_Start(HAL_CIPHER_INTMODE IntMode , MS_BOOL bWaitCmdQ , MS_BOOL bRst, MS_U16 u16CmdID); 369 MS_BOOL HAL_CIPHER_Hash_Set_OuputAddr(MS_PHY u32OutputPAddr, MS_U32 u32DstSel); 370 MS_BOOL HAL_CIPHER_Hash_Set_InitWordCnt(HAL_CIPHER_IWCTYPE eIWCType, MS_U32 u32StartBytes); 371 MS_BOOL HAL_CIPHER_Hash_Set_IV(MS_U8* pu8IV, MS_U32 u32IVSize ,MS_U32 u32IVSel); 372 MS_BOOL HAL_CIPHER_Hash_Set_CaVid(MS_U32 u32CAVid); 373 void HAL_CIPHER_Hash_Set_Config(CIPHER_HASH_ALGO algo , MS_BOOL bAutoPad , MS_BOOL bInv16); 374 void HAL_CIPHER_Hash_GetRpt(MS_U32 *HashRpt, MS_U32 u32Size); 375 MS_BOOL HAL_CIPHER_Hash_SetHMACKey(DRV_CIPHER_HMAC_KEY stHMACKey, CIPHER_HMAC_KPAD eKpad, MS_BOOL bClear); 376 MS_BOOL HAL_CIPHER_Hash_CmdDone(MS_U32 u32CmdID, MS_U32 *u32Ret); 377 MS_BOOL HAL_CIPHER_Hash_Set_MsgSrcFrom(CIPHER_MEM_TYPE eMemType, MS_U32 *u32HashSrc); 378 MS_BOOL HAL_CIPHER_Hash_Set_OutputDstTo(CIPHER_MEM_TYPE eMemType, MS_U32 *u32HashDst); 379 void HAL_CIPHER_Hash_Set_ReportMode(MS_BOOL RptInDram, MS_U32 u32DramAddr); 380 void HAL_CIPHER_Hash_ExceptFilter(MS_U32 *pu32Exception, CIPHER_KEY_SRC eKeySrc, MS_U8 u8KeyIdx); 381 382 MS_U32 HAL_CIPHER_ReadException(MS_U32 u32ExcTmp); 383 void HAL_CIPHER_GetException(MS_U32 *pu32ExcFlag); 384 385 void HAL_CIPHER_IntEnable(void); 386 void HAL_CIPHER_IntClear(void); 387 388 //=============PARSER================================= 389 void HAL_CIPHER_PARSER_Set_Mode(CIPHER_PARSER_MODE eMode); 390 void HAL_CIPHER_PARSER_Set_PID(CIPHER_PARSER_PID stPID); 391 void HAL_CIPHER_PARSER_Set_SCB(CIPHER_PARSER_SCB eSCB); 392 void HAL_CIPHER_PARSER_Set_ForceSCB(MS_BOOL bInsert, CIPHER_PARSER_SCB eSCB); 393 MS_BOOL HAL_CIPHER_PARSER_Set_IV2(MS_U8 *pu8IV2, MS_U8 u8IVLen); 394 MS_BOOL HAL_CIPHER_PARSER_Set_Key2(DRV_CIPHER_KEY stKey); 395 void HAL_CIPHER_PARSER_Set_MaskSCB(MS_BOOL bEnable); 396 void HAL_CIPHER_PARSER_Rmv_SCB(MS_BOOL bRemove); 397 void HAL_CIPHER_PARSER_BypassPid(MS_BOOL bEnable); 398 void HAL_CIPHER_PARSER_Set_ClearStartMode(MS_BOOL bEnable); 399 //MISC Function 400 MS_BOOL HAL_CIPHER_Misc_Random(MS_U8 *pu8Buf, MS_U32 u32Size); 401 MS_BOOL HAL_CIPHER_Set_OBFIdx(MS_BOOL bDMA, MS_U8 u8ReadIdx, MS_U8 u8WriteIdx); 402 403 #endif // #ifndef __HAL_CIPHER_H__ 404 405