1 2 code U8 MST_HSPRule_IP_Index_Sub[PQ_HSPRule_IP_NUM_Sub]= 3 { 4 PQ_IP_HSP_Y_Sub, 5 PQ_IP_HSP_C_Sub, 6 PQ_IP_SRAM4_Sub, 7 PQ_IP_C_SRAM4_Sub, 8 }; 9 10 11 code U8 MST_HSPRule_Array_Sub[PQ_HSPRule_NUM_Sub][PQ_HSPRule_IP_NUM_Sub]= 12 { 13 {//PreV_ScalingDown_Interlace, 0 14 PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, 15 }, 16 {//PreV_ScalingDown_Progressive, 1 17 PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, PQ_IP_NULL, 18 }, 19 {//ScalingDown_00x_YUV, 2 20 PQ_IP_HSP_Y_SRAM_4_4Tap_Sub, PQ_IP_HSP_C_C_SRAM_4_Sub, PQ_IP_SRAM4_InvSinc4Tc4p4Fc60Apass0001Astop40_Sub, PQ_IP_C_SRAM4_C121_Sub, 21 }, 22 {//ScalingDown_00x_RGB, 3 23 PQ_IP_HSP_Y_Bilinear_Sub, PQ_IP_HSP_C_Bilinear_Sub, PQ_IP_NULL, PQ_IP_C_SRAM4_C121_Sub, 24 }, 25 {//ScalingDown_01x_YUV, 4 26 PQ_IP_HSP_Y_SRAM_4_4Tap_Sub, PQ_IP_HSP_C_C_SRAM_4_Sub, PQ_IP_SRAM4_InvSinc4Tc4p4Fc60Apass0001Astop40_Sub, PQ_IP_C_SRAM4_C121_Sub, 27 }, 28 {//ScalingDown_01x_RGB, 5 29 PQ_IP_HSP_Y_Bilinear_Sub, PQ_IP_HSP_C_Bilinear_Sub, PQ_IP_NULL, PQ_IP_C_SRAM4_C121_Sub, 30 }, 31 {//ScalingDown_02x_YUV, 6 32 PQ_IP_HSP_Y_SRAM_4_4Tap_Sub, PQ_IP_HSP_C_C_SRAM_4_Sub, PQ_IP_SRAM4_InvSinc4Tc4p4Fc60Apass0001Astop40_Sub, PQ_IP_C_SRAM4_C121_Sub, 33 }, 34 {//ScalingDown_02x_RGB, 7 35 PQ_IP_HSP_Y_Bilinear_Sub, PQ_IP_HSP_C_Bilinear_Sub, PQ_IP_NULL, PQ_IP_C_SRAM4_C121_Sub, 36 }, 37 {//ScalingDown_03x_YUV, 8 38 PQ_IP_HSP_Y_SRAM_4_4Tap_Sub, PQ_IP_HSP_C_C_SRAM_4_Sub, PQ_IP_SRAM4_InvSinc4Tc4p4Fc60Apass0001Astop40_Sub, PQ_IP_C_SRAM4_C121_Sub, 39 }, 40 {//ScalingDown_03x_RGB, 9 41 PQ_IP_HSP_Y_Bilinear_Sub, PQ_IP_HSP_C_Bilinear_Sub, PQ_IP_NULL, PQ_IP_C_SRAM4_C121_Sub, 42 }, 43 {//ScalingDown_04x_YUV, 10 44 PQ_IP_HSP_Y_SRAM_4_4Tap_Sub, PQ_IP_HSP_C_C_SRAM_4_Sub, PQ_IP_SRAM4_InvSinc4Tc4p4Fc60Apass0001Astop40_Sub, PQ_IP_C_SRAM4_C121_Sub, 45 }, 46 {//ScalingDown_04x_RGB, 11 47 PQ_IP_HSP_Y_Bilinear_Sub, PQ_IP_HSP_C_Bilinear_Sub, PQ_IP_NULL, PQ_IP_C_SRAM4_C121_Sub, 48 }, 49 {//ScalingDown_05x_YUV, 12 50 PQ_IP_HSP_Y_SRAM_4_4Tap_Sub, PQ_IP_HSP_C_C_SRAM_4_Sub, PQ_IP_SRAM4_InvSinc4Tc4p4Fc60Apass0001Astop40_Sub, PQ_IP_C_SRAM4_C121_Sub, 51 }, 52 {//ScalingDown_05x_RGB, 13 53 PQ_IP_HSP_Y_Bilinear_Sub, PQ_IP_HSP_C_Bilinear_Sub, PQ_IP_NULL, PQ_IP_C_SRAM4_C121_Sub, 54 }, 55 {//ScalingDown_06x_YUV, 14 56 PQ_IP_HSP_Y_SRAM_4_4Tap_Sub, PQ_IP_HSP_C_C_SRAM_4_Sub, PQ_IP_SRAM4_InvSinc4Tc4p4Fc60Apass0001Astop40_Sub, PQ_IP_C_SRAM4_C121_Sub, 57 }, 58 {//ScalingDown_06x_RGB, 15 59 PQ_IP_HSP_Y_Bilinear_Sub, PQ_IP_HSP_C_Bilinear_Sub, PQ_IP_NULL, PQ_IP_C_SRAM4_C121_Sub, 60 }, 61 {//ScalingDown_07x_YUV, 16 62 PQ_IP_HSP_Y_SRAM_4_4Tap_Sub, PQ_IP_HSP_C_C_SRAM_4_Sub, PQ_IP_SRAM4_InvSinc4Tc4p4Fc60Apass0001Astop40_Sub, PQ_IP_C_SRAM4_C121_Sub, 63 }, 64 {//ScalingDown_07x_RGB, 17 65 PQ_IP_HSP_Y_Bilinear_Sub, PQ_IP_HSP_C_Bilinear_Sub, PQ_IP_NULL, PQ_IP_C_SRAM4_C121_Sub, 66 }, 67 {//ScalingDown_08x_YUV, 18 68 PQ_IP_HSP_Y_SRAM_4_4Tap_Sub, PQ_IP_HSP_C_C_SRAM_4_Sub, PQ_IP_SRAM4_InvSinc4Tc4p4Fc60Apass0001Astop40_Sub, PQ_IP_C_SRAM4_C121_Sub, 69 }, 70 {//ScalingDown_08x_RGB, 19 71 PQ_IP_HSP_Y_Bilinear_Sub, PQ_IP_HSP_C_Bilinear_Sub, PQ_IP_NULL, PQ_IP_C_SRAM4_C121_Sub, 72 }, 73 {//ScalingDown_09x_YUV, 20 74 PQ_IP_HSP_Y_SRAM_4_4Tap_Sub, PQ_IP_HSP_C_C_SRAM_4_Sub, PQ_IP_SRAM4_InvSinc4Tc4p4Fc60Apass0001Astop40_Sub, PQ_IP_C_SRAM4_C121_Sub, 75 }, 76 {//ScalingDown_09x_RGB, 21 77 PQ_IP_HSP_Y_Bilinear_Sub, PQ_IP_HSP_C_Bilinear_Sub, PQ_IP_NULL, PQ_IP_C_SRAM4_C121_Sub, 78 }, 79 {//ScalingDown_10x_YUV, 22 80 PQ_IP_HSP_Y_Bypass_Sub, PQ_IP_HSP_C_Bypass_Sub, PQ_IP_NULL, PQ_IP_NULL, 81 }, 82 {//ScalingDown_10x_RGB, 23 83 PQ_IP_HSP_Y_Bypass_Sub, PQ_IP_HSP_C_Bypass_Sub, PQ_IP_NULL, PQ_IP_NULL, 84 }, 85 }; 86