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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 /////////////////////////////////////////////////////////////////////////////// 94 95 #ifndef _REG_PCMCIA_H_ 96 #define _REG_PCMCIA_H_ 97 98 //----------------------------------------------------------------------------- 99 // Hardware Capability 100 //----------------------------------------------------------------------------- 101 // Base address should be initial. 102 #define PCMCIA_RIU_MAP u32PCMCIA_RIU_BaseAdd //obtain in init 103 104 //----------------------------------------------------------------------------- 105 // Macro and Define 106 //----------------------------------------------------------------------------- 107 //hardware spec 108 #define REG_PCMCIA_PCM_MEM_IO_CMD 0x00UL 109 #define REG_PCMCIA_ADDR0 0x02UL 110 #define REG_PCMCIA_ADDR1 0x03UL 111 #define REG_PCMCIA_WRITE_DATA 0x04UL 112 #define REG_PCMCIA_FIRE_READ_DATA_CLEAR 0x06UL 113 #define REG_PCMCIA_READ_DATA 0x08UL 114 #define REG_PCMCIA_READ_DATA_DONE_BUS_IDLE 0x09UL 115 #define REG_PCMCIA_INT_MASK_CLEAR 0x0AUL 116 #define REG_PCMCIA_INT_MASK_CLEAR1 0x0BUL 117 #define REG_PCMCIA_STAT_INT_RAW_INT 0x0EUL 118 #define REG_PCMCIA_STAT_INT_RAW_INT1 0x0FUL 119 #define REG_PCMCIA_MODULE_VCC_OOB 0x10UL 120 121 #define PCMCIA_ATTRIBMEMORY_READ 0x03UL 122 #define PCMCIA_ATTRIBMEMORY_WRITE 0x04UL 123 #define PCMCIA_IO_READ 0x05UL 124 #define PCMCIA_IO_WRITE 0x06UL 125 126 #define REG_PCMCIA_BASE 0x3440UL 127 #define PCMCIA_BASE_ADDRESS ( PCMCIA_RIU_MAP + ( REG_PCMCIA_BASE * 2 ) ) 128 129 #if defined ( MCU_AEON ) 130 #define PCMCIA_RIU_DEFAULT_BASE_ADDR 0xA0000000UL; 131 #elif defined ( MCU_MIPS ) 132 #define PCMCIA_RIU_DEFAULT_BASE_ADDR 0xBF200000UL; 133 #endif 134 135 #define PCM_OOB_BIT_MASK 0x03UL 136 #define PCM_OOB_BIT_SHFT 6UL 137 138 #define PCM_OOB_CYCLE_EXTEND 0x3UL 139 // 00:th(CE)=4T (extend 3 active cycle) 140 // 01:th(CE)=3T (extend 2 active cycle) 141 // 10:th(CE)=2T (extend 1 active cycle) 142 // 11:th(CE)=1T 143 #define PCM_CLKGEN0_REG(addr) (*((volatile MS_U16*)(PCMCIA_RIU_MAP + 0x1600UL + ((addr)<<2UL)))) 144 #define REG_CLKGEN0_PCM_CLK 0x001AUL 145 #define REG_CLKGEN0_PCM_CLK_MASK 0x000FUL 146 #define REG_CLKGEN0_PCM_CLK_DIS 0x0001UL 147 //----------------------------------------------------------------------------- 148 // Type and Structure 149 //----------------------------------------------------------------------------- 150 151 #endif // _REG_PCMCIA_H_ 152