xref: /utopia/UTPA2-700.0.x/modules/mvop/hal/k6lite/mvop/halMVOP.h (revision 53ee8cc121a030b8d368113ac3e966b4705770ef)
1*53ee8cc1Swenshuai.xi //<MStar Software>
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77*53ee8cc1Swenshuai.xi //<MStar Software>
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92*53ee8cc1Swenshuai.xi //
93*53ee8cc1Swenshuai.xi ////////////////////////////////////////////////////////////////////////////////
94*53ee8cc1Swenshuai.xi 
95*53ee8cc1Swenshuai.xi #ifndef _HAL_MVOP_H_
96*53ee8cc1Swenshuai.xi #define _HAL_MVOP_H_
97*53ee8cc1Swenshuai.xi 
98*53ee8cc1Swenshuai.xi 
99*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
100*53ee8cc1Swenshuai.xi //  Macro and Define
101*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
102*53ee8cc1Swenshuai.xi #define STB_DC                  0   //0 for TV series MVOP; 1 for STB DC.
103*53ee8cc1Swenshuai.xi #define STB_DC_MODE
104*53ee8cc1Swenshuai.xi 
105*53ee8cc1Swenshuai.xi //Information from miu owner: miu group5 should be 256bits, less than group5 are 128bits.
106*53ee8cc1Swenshuai.xi #define MVOP_MIU_CLIENT_MAIN    MIU_CLIENT_MVOP_256BIT_R
107*53ee8cc1Swenshuai.xi #define MVOP_MIU_CLIENT_SUB     MIU_CLIENT_MVOP1_256BIT_R
108*53ee8cc1Swenshuai.xi 
109*53ee8cc1Swenshuai.xi #define _MVOP_128BIT_BUS        0//128-bit MIU bus
110*53ee8cc1Swenshuai.xi #define _MVOP_64BIT_BUS         1// 64-bit MIU bus
111*53ee8cc1Swenshuai.xi #define MVOP_BUS_WIDTH          _MVOP_128BIT_BUS
112*53ee8cc1Swenshuai.xi 
113*53ee8cc1Swenshuai.xi #define HAL_MVOP_MODULE_CNT     1
114*53ee8cc1Swenshuai.xi #if (HAL_MVOP_MODULE_CNT >= 2)
115*53ee8cc1Swenshuai.xi #define MVOP_SUPPORT_SUB        1
116*53ee8cc1Swenshuai.xi #else
117*53ee8cc1Swenshuai.xi #define MVOP_SUPPORT_SUB        0
118*53ee8cc1Swenshuai.xi #endif
119*53ee8cc1Swenshuai.xi #if (HAL_MVOP_MODULE_CNT >= 3)
120*53ee8cc1Swenshuai.xi #define MVOP_SUPPORT_3RD        1
121*53ee8cc1Swenshuai.xi #else
122*53ee8cc1Swenshuai.xi #define MVOP_SUPPORT_3RD        0
123*53ee8cc1Swenshuai.xi #endif
124*53ee8cc1Swenshuai.xi 
125*53ee8cc1Swenshuai.xi #define NO_MVOP_PATCH           1
126*53ee8cc1Swenshuai.xi #define ENABLE_3D_LR_MODE           1 //Enable 3D L/R feature
127*53ee8cc1Swenshuai.xi #define SUPPORT_3DLR_INST_VBLANK    0
128*53ee8cc1Swenshuai.xi #define SUPPORT_3DLR_ALT_SBS        1
129*53ee8cc1Swenshuai.xi 
130*53ee8cc1Swenshuai.xi #define SUPPORT_EVD_MODE        1
131*53ee8cc1Swenshuai.xi #define SUPPORT_VP9_MODE        1
132*53ee8cc1Swenshuai.xi 
133*53ee8cc1Swenshuai.xi #if (STB_DC == 0)
134*53ee8cc1Swenshuai.xi #define MVOP_BASE_ADD_BITS          31  //29 - 1 (MSB is signed bit) + 3 (unit in 8-byte)
135*53ee8cc1Swenshuai.xi #endif
136*53ee8cc1Swenshuai.xi 
137*53ee8cc1Swenshuai.xi #define SUPPORT_KERNAL_STR            1
138*53ee8cc1Swenshuai.xi 
139*53ee8cc1Swenshuai.xi #define MVOP_BANK_REGNUM 0x80UL
140*53ee8cc1Swenshuai.xi #define MVOP_CLK_REGNUM 0x10UL
141*53ee8cc1Swenshuai.xi 
142*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
143*53ee8cc1Swenshuai.xi //  Type and Structure
144*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
145*53ee8cc1Swenshuai.xi typedef enum
146*53ee8cc1Swenshuai.xi {
147*53ee8cc1Swenshuai.xi     HALMVOP_SYNCMODE,
148*53ee8cc1Swenshuai.xi     HALMVOP_FREERUNMODE,
149*53ee8cc1Swenshuai.xi     HALMVOP_27MHZ = 27000000ul,
150*53ee8cc1Swenshuai.xi     HALMVOP_54MHZ = 54000000ul,
151*53ee8cc1Swenshuai.xi     HALMVOP_320MHZ = 320000000ul,
152*53ee8cc1Swenshuai.xi     HALMVOP_108MHZ = 108000000ul,
153*53ee8cc1Swenshuai.xi     HALMVOP_123MHZ = 123000000ul,
154*53ee8cc1Swenshuai.xi     HALMVOP_144MHZ = 144000000ul,
155*53ee8cc1Swenshuai.xi     HALMVOP_160MHZ = 160000000ul,
156*53ee8cc1Swenshuai.xi     HALMVOP_172MHZ = 172000000ul,
157*53ee8cc1Swenshuai.xi     HALMVOP_192MHZ = 192000000ul,
158*53ee8cc1Swenshuai.xi     HALMVOP_CLK_MIU,
159*53ee8cc1Swenshuai.xi     HALMVOP_NOT_SUPPORT
160*53ee8cc1Swenshuai.xi }HALMVOPFREQUENCY;
161*53ee8cc1Swenshuai.xi 
162*53ee8cc1Swenshuai.xi typedef enum
163*53ee8cc1Swenshuai.xi {
164*53ee8cc1Swenshuai.xi     E_MVOP_MASK_DB_REG,
165*53ee8cc1Swenshuai.xi     E_MVOP_EN_DB_REG,
166*53ee8cc1Swenshuai.xi     E_MVOP_DEBUG_SEL,
167*53ee8cc1Swenshuai.xi     E_MVOP_UPDATE_SEL,
168*53ee8cc1Swenshuai.xi     E_MVOP_RST_START_SEL,
169*53ee8cc1Swenshuai.xi     E_MVOP_SC_VSYNC_SEL,
170*53ee8cc1Swenshuai.xi     E_MVOP_READ_IP_BASE_SEL,
171*53ee8cc1Swenshuai.xi     E_MVOP_CHKSUM_422_SWAP,
172*53ee8cc1Swenshuai.xi     E_MVOP_CHKSUM_FULL_C,
173*53ee8cc1Swenshuai.xi     E_MVOP_OFF_LATCH_CRC,
174*53ee8cc1Swenshuai.xi     E_MVOP_SEL_OP_FIELD ,
175*53ee8cc1Swenshuai.xi     E_MVOP_INV_OP_FIELD,
176*53ee8cc1Swenshuai.xi     E_MVOP_INV_OP_VS
177*53ee8cc1Swenshuai.xi }MVOPMSAKDBREGCTRL;
178*53ee8cc1Swenshuai.xi 
179*53ee8cc1Swenshuai.xi //for Kappa patch
180*53ee8cc1Swenshuai.xi typedef enum
181*53ee8cc1Swenshuai.xi {
182*53ee8cc1Swenshuai.xi     E_MVOP_DEB2MVD_FRAME_MODE,
183*53ee8cc1Swenshuai.xi     E_MVOP_DEB2MVD_FIELD_INV,
184*53ee8cc1Swenshuai.xi     E_MVOP_SEQ_FROM_MVD,
185*53ee8cc1Swenshuai.xi     E_MVOP_SIZE_FROM_MVD
186*53ee8cc1Swenshuai.xi }MVOPDEB2MVDFRAMECTRL;
187*53ee8cc1Swenshuai.xi 
188*53ee8cc1Swenshuai.xi typedef enum
189*53ee8cc1Swenshuai.xi {
190*53ee8cc1Swenshuai.xi     E_MVOP_BASE_FROM_IP,
191*53ee8cc1Swenshuai.xi     E_MVOP_SRC_FROM_MVD,
192*53ee8cc1Swenshuai.xi     E_MVOP_FIELD_FROM_MVD,
193*53ee8cc1Swenshuai.xi     E_MVOP_FIELD_FROM_MVD_INV,
194*53ee8cc1Swenshuai.xi     E_MVOP_PITCH_FROM_IP,
195*53ee8cc1Swenshuai.xi     E_MVOP_FMT_FROM_MVD,
196*53ee8cc1Swenshuai.xi     E_MVOP_FD_MASK_CLR,
197*53ee8cc1Swenshuai.xi     E_MVOP_FD_MASK_INV
198*53ee8cc1Swenshuai.xi #if (NO_MVOP_PATCH == 0)
199*53ee8cc1Swenshuai.xi   , E_MVOP_SEQ_FROM_MVD_PATCH,
200*53ee8cc1Swenshuai.xi     E_MVOP_SIZE_FROM_MVD_PATCH
201*53ee8cc1Swenshuai.xi #endif
202*53ee8cc1Swenshuai.xi }MVOPBASEFROMIPCTRL;
203*53ee8cc1Swenshuai.xi 
204*53ee8cc1Swenshuai.xi typedef struct
205*53ee8cc1Swenshuai.xi {
206*53ee8cc1Swenshuai.xi     MS_U8 u8Gp:4;
207*53ee8cc1Swenshuai.xi     MS_U8 u8BitPos:4;
208*53ee8cc1Swenshuai.xi }HALMVOPMIUCLIENTINFO;
209*53ee8cc1Swenshuai.xi 
210*53ee8cc1Swenshuai.xi typedef enum
211*53ee8cc1Swenshuai.xi {
212*53ee8cc1Swenshuai.xi     E_MVOP_SEL_MIU0         = 0,
213*53ee8cc1Swenshuai.xi     E_MVOP_SEL_MIU1         = 0x01,
214*53ee8cc1Swenshuai.xi     E_MVOP_SEL_MIU2         = 0x02,
215*53ee8cc1Swenshuai.xi     E_MVOP_SEL_MIU3         = 0x03,
216*53ee8cc1Swenshuai.xi     E_MVOP_SEL_NONE         = 0xFF,
217*53ee8cc1Swenshuai.xi 
218*53ee8cc1Swenshuai.xi } HALMVOPMIUSEL;
219*53ee8cc1Swenshuai.xi 
220*53ee8cc1Swenshuai.xi typedef struct
221*53ee8cc1Swenshuai.xi {
222*53ee8cc1Swenshuai.xi     MS_U16 MVOP_BANK[3][0x80];
223*53ee8cc1Swenshuai.xi     MS_U16 CLK_BANK[0x10];
224*53ee8cc1Swenshuai.xi 
225*53ee8cc1Swenshuai.xi }MVOP_STR_SAVE_AREA;
226*53ee8cc1Swenshuai.xi 
227*53ee8cc1Swenshuai.xi typedef enum
228*53ee8cc1Swenshuai.xi {
229*53ee8cc1Swenshuai.xi     E_MVOP_POWER_SUSPEND     = 1,    // State is backup in DRAM, components power off.
230*53ee8cc1Swenshuai.xi     E_MVOP_POWER_RESUME      = 2,    // Resume from Suspend or Hibernate mode
231*53ee8cc1Swenshuai.xi     E_MVOP_POWER_MECHANICAL  = 3,    // Full power off mode. System return to working state only after full reboot
232*53ee8cc1Swenshuai.xi     E_MVOP_POWER_SOFT_OFF    = 4,    // The system appears to be off, but some components remain powered for trigging boot-up.
233*53ee8cc1Swenshuai.xi } EN_MVOP_POWER_MODE;
234*53ee8cc1Swenshuai.xi 
235*53ee8cc1Swenshuai.xi typedef struct
236*53ee8cc1Swenshuai.xi {
237*53ee8cc1Swenshuai.xi     MVOP_DrvMirror enMirror;
238*53ee8cc1Swenshuai.xi     EN_MVOP_Output_3D_TYPE en3D;
239*53ee8cc1Swenshuai.xi     MS_BOOL bHSK;
240*53ee8cc1Swenshuai.xi     MS_BOOL bXCGenTiming;
241*53ee8cc1Swenshuai.xi     MVOP_SetCropPos stCropSt;
242*53ee8cc1Swenshuai.xi     MVOP_SetImageWH stCropSize;
243*53ee8cc1Swenshuai.xi     MS_BOOL bOneField;
244*53ee8cc1Swenshuai.xi     MS_BOOL b2P;
245*53ee8cc1Swenshuai.xi     MS_BOOL bForceP;
246*53ee8cc1Swenshuai.xi     MS_U32 u32Framerate;
247*53ee8cc1Swenshuai.xi }MVOP_FeatureMdb;
248*53ee8cc1Swenshuai.xi 
249*53ee8cc1Swenshuai.xi typedef struct
250*53ee8cc1Swenshuai.xi {
251*53ee8cc1Swenshuai.xi     MS_U32 u32RegYoffset;
252*53ee8cc1Swenshuai.xi     MS_U32 u32RegUVoffset;
253*53ee8cc1Swenshuai.xi     MS_U16 u16RegHsize;
254*53ee8cc1Swenshuai.xi     MS_U16 u16RegVsize;
255*53ee8cc1Swenshuai.xi     MS_U16 u16RegStrip;
256*53ee8cc1Swenshuai.xi     MS_BOOL bReg422;
257*53ee8cc1Swenshuai.xi     MS_BOOL bRegPMode;
258*53ee8cc1Swenshuai.xi     MS_BOOL bRegDramContd;
259*53ee8cc1Swenshuai.xi     MS_BOOL bRegField;
260*53ee8cc1Swenshuai.xi     MS_BOOL bReg422Pack;
261*53ee8cc1Swenshuai.xi     MS_BOOL bRegRGB;
262*53ee8cc1Swenshuai.xi     MS_BOOL bRegRGBType;
263*53ee8cc1Swenshuai.xi     MS_U8 u8RegDSIndex;
264*53ee8cc1Swenshuai.xi     MS_BOOL u8RegFDMask;
265*53ee8cc1Swenshuai.xi     MS_BOOL bRegMfdecEn;
266*53ee8cc1Swenshuai.xi     MS_U32 u32RegBitenAdd;
267*53ee8cc1Swenshuai.xi }MVOP_RegInputMdb;
268*53ee8cc1Swenshuai.xi 
269*53ee8cc1Swenshuai.xi typedef struct
270*53ee8cc1Swenshuai.xi {
271*53ee8cc1Swenshuai.xi     MS_BOOL bMFDEC_EN;
272*53ee8cc1Swenshuai.xi     MS_U8   u8MFDEC_ID;
273*53ee8cc1Swenshuai.xi     MS_U32  u32UNCOMPRESS_MODE;
274*53ee8cc1Swenshuai.xi     MS_PHY  u32BITLEN_FB_ADDR;         ///<0:8 bit EL y address, 1:8 bit EL uv address
275*53ee8cc1Swenshuai.xi     MS_U8   u8BITLEN_FB_MIU;           ///<0:8 bit EL y address, 1:8 bit EL uv address
276*53ee8cc1Swenshuai.xi     MS_U32  u32BITLEN_FB_PITCH;
277*53ee8cc1Swenshuai.xi     MS_BOOL bBITLEN_SHT_8;
278*53ee8cc1Swenshuai.xi }HALMVOPMFDECINFO;
279*53ee8cc1Swenshuai.xi 
280*53ee8cc1Swenshuai.xi typedef struct
281*53ee8cc1Swenshuai.xi {
282*53ee8cc1Swenshuai.xi     MS_U32 u32RegVtt;
283*53ee8cc1Swenshuai.xi     MS_U32 u32RegHtt;
284*53ee8cc1Swenshuai.xi     MS_U16 u16RegVImgst;
285*53ee8cc1Swenshuai.xi     MS_U16 u16RegHImgst;
286*53ee8cc1Swenshuai.xi     MS_BOOL bRegInterlace;
287*53ee8cc1Swenshuai.xi     MS_U8 u8RegFPS;
288*53ee8cc1Swenshuai.xi     MS_U16 u16RegExpFPS;
289*53ee8cc1Swenshuai.xi     MS_U16 u16RegHFreq;
290*53ee8cc1Swenshuai.xi     MS_U16 u16RegWidth;
291*53ee8cc1Swenshuai.xi     MS_U16 u16RegHeight;
292*53ee8cc1Swenshuai.xi     MS_BOOL bRegHDup;
293*53ee8cc1Swenshuai.xi     MS_BOOL bReg2P;
294*53ee8cc1Swenshuai.xi     HALMVOPFREQUENCY enRegCLOCK;
295*53ee8cc1Swenshuai.xi     MS_U16 u16RegVsForward;
296*53ee8cc1Swenshuai.xi }MVOP_RegOutputMdb;
297*53ee8cc1Swenshuai.xi 
298*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
299*53ee8cc1Swenshuai.xi //  Function and Variable
300*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
301*53ee8cc1Swenshuai.xi void HAL_MVOP_RegSetBase(MS_VIRT u32Base);
302*53ee8cc1Swenshuai.xi void HAL_MVOP_Init(void);
303*53ee8cc1Swenshuai.xi void HAL_MVOP_SetFieldInverse(MS_BOOL b2MVD, MS_BOOL b2IP);
304*53ee8cc1Swenshuai.xi void HAL_MVOP_SetChromaWeighting(MS_BOOL bEnable);
305*53ee8cc1Swenshuai.xi void HAL_MVOP_LoadReg(void);
306*53ee8cc1Swenshuai.xi void HAL_MVOP_SetMIUReqMask(MS_BOOL bEnable);
307*53ee8cc1Swenshuai.xi void HAL_MVOP_Enable(MS_BOOL bEnable, MS_U8 u8Framerate);
308*53ee8cc1Swenshuai.xi MS_BOOL HAL_MVOP_GetEnableState(void);
309*53ee8cc1Swenshuai.xi HALMVOPFREQUENCY HAL_MVOP_GetMaxFreerunClk(void);
310*53ee8cc1Swenshuai.xi HALMVOPFREQUENCY HAL_MVOP_Get4k2kClk(void);
311*53ee8cc1Swenshuai.xi void HAL_MVOP_SetFrequency(HALMVOPFREQUENCY enFrequency);
312*53ee8cc1Swenshuai.xi HALMVOPFREQUENCY HAL_MVOP_GetMaximumClk(void);
313*53ee8cc1Swenshuai.xi HALMVOPFREQUENCY HAL_MVOP_GetCurrentClk(void);
314*53ee8cc1Swenshuai.xi void HAL_MVOP_Rst(void);
315*53ee8cc1Swenshuai.xi void HAL_MVOP_SetBlackBG(void);
316*53ee8cc1Swenshuai.xi void HAL_MVOP_SetOutputInterlace(MS_BOOL bEnable, MS_U16 u16ECOVersion);
317*53ee8cc1Swenshuai.xi void HAL_MVOP_SetCropWindow(MVOP_InputCfg *pparam);
318*53ee8cc1Swenshuai.xi void HAL_MVOP_SetInputMode( VOPINPUTMODE mode, MVOP_InputCfg *pparam, MS_U16 u16ECOVersion );
319*53ee8cc1Swenshuai.xi void HAL_MVOP_EnableUVShift(MS_BOOL bEnable);
320*53ee8cc1Swenshuai.xi void HAL_MVOP_SetEnable60P(MS_BOOL bEnable);
321*53ee8cc1Swenshuai.xi void HAL_MVOP_SetEnable4k2kClk(MS_BOOL bEnable);
322*53ee8cc1Swenshuai.xi void HAL_MVOP_SetEnableFixClk(MS_BOOL bEnable);
323*53ee8cc1Swenshuai.xi void HAL_MVOP_SetVSyncMode(MS_U8 u8Mode);
324*53ee8cc1Swenshuai.xi void HAL_MVOP_SetOutputTiming( MVOP_Timing *ptiming );
325*53ee8cc1Swenshuai.xi void HAL_MVOP_SetDCClk(MS_U8 clkNum, MS_BOOL bEnable);
326*53ee8cc1Swenshuai.xi void HAL_MVOP_SetSynClk(MVOP_Timing *ptiming);
327*53ee8cc1Swenshuai.xi void HAL_MVOP_SetMonoMode(MS_BOOL bEnable);
328*53ee8cc1Swenshuai.xi void HAL_MVOP_SetH264HardwireMode(MS_U16 u16ECOVersion);
329*53ee8cc1Swenshuai.xi void HAL_MVOP_SetRMHardwireMode(MS_U16 u16ECOVersion);
330*53ee8cc1Swenshuai.xi void HAL_MVOP_SetJpegHardwireMode(void);
331*53ee8cc1Swenshuai.xi void HAL_MVOP_SetEVDHardwireMode(MS_U16 u16ECOVersion);
332*53ee8cc1Swenshuai.xi void HAL_MVOP_SetVP9HardwireMode(MS_U16 u16ECOVersion);
333*53ee8cc1Swenshuai.xi void HAL_MVOP_SetEVDFeature(MVOP_DevID eID, MVOP_EVDFeature* stEVDInput);
334*53ee8cc1Swenshuai.xi void HAL_MVOP_SetPattern(MVOP_Pattern enMVOPPattern);
335*53ee8cc1Swenshuai.xi MS_BOOL HAL_MVOP_SetTileFormat(MVOP_TileFormat eTileFmt);
336*53ee8cc1Swenshuai.xi MS_BOOL HAL_MVOP_SetRgbFormat(MVOP_RgbFormat eRgbFmt);
337*53ee8cc1Swenshuai.xi MS_BOOL HAL_MVOP_GetSupportRgbFormat(MVOP_RgbFormat eRgbFmt);
338*53ee8cc1Swenshuai.xi MS_BOOL HAL_MVOP_Enable3DLR(MS_BOOL bEnable);
339*53ee8cc1Swenshuai.xi MS_BOOL HAL_MVOP_Get3DLRMode(void);
340*53ee8cc1Swenshuai.xi MS_BOOL HAL_MVOP_GetTimingInfoFromRegisters(MVOP_TimingInfo_FromRegisters *mvopTimingInfo);
341*53ee8cc1Swenshuai.xi void HAL_MVOP_SetHorizontallMirrorMode(MS_BOOL bEnable);
342*53ee8cc1Swenshuai.xi void HAL_MVOP_SetVerticalMirrorMode(MS_BOOL bEnable);
343*53ee8cc1Swenshuai.xi void HAL_MVOP_SetYUVBaseAdd(MS_PHY u32YOffset, MS_PHY u32UVOffset, MS_BOOL bProgressive, MS_BOOL b422pack);
344*53ee8cc1Swenshuai.xi void HAL_MVOP_SetRepeatField(MVOP_RptFldMode eMode);
345*53ee8cc1Swenshuai.xi void HAL_MVOP_EnableFreerunMode(MS_BOOL bEnable);
346*53ee8cc1Swenshuai.xi MS_PHY HAL_MVOP_GetYBaseAdd(void);
347*53ee8cc1Swenshuai.xi MS_PHY HAL_MVOP_GetUVBaseAdd(void);
348*53ee8cc1Swenshuai.xi MS_BOOL HAL_MVOP_Set3DLRAltOutput(MS_BOOL bEnable);
349*53ee8cc1Swenshuai.xi MS_BOOL HAL_MVOP_Set3DLRAltOutput_VHalfScaling(MS_BOOL bEnable);
350*53ee8cc1Swenshuai.xi MS_BOOL HAL_MVOP_Set3DLRAltSBSOutput(MS_BOOL bEnable);
351*53ee8cc1Swenshuai.xi MS_BOOL HAL_MVOP_Get3DLRAltOutput(void);
352*53ee8cc1Swenshuai.xi MS_BOOL HAL_MVOP_Get3DLRAltSBSOutput(void);
353*53ee8cc1Swenshuai.xi EN_MVOP_Output_3D_TYPE HAL_MVOP_GetOutput3DType(void);
354*53ee8cc1Swenshuai.xi MS_BOOL HAL_MVOP_Set3DLR2ndCfg(MS_BOOL bEnable);
355*53ee8cc1Swenshuai.xi MS_BOOL HAL_MVOP_Get3DLR2ndCfg(void);
356*53ee8cc1Swenshuai.xi MVOP_DrvMirror HAL_MVOP_GetMirrorMode(MVOP_DevID eID);
357*53ee8cc1Swenshuai.xi MS_BOOL HAL_MVOP_SetVerDup(MS_BOOL bEnable);
358*53ee8cc1Swenshuai.xi MS_BOOL HAL_MVOP_GetVerDup(void);
359*53ee8cc1Swenshuai.xi MS_BOOL HAL_MVOP_SetVerx4Dup(MS_BOOL bEnable);
360*53ee8cc1Swenshuai.xi MS_BOOL HAL_MVOP_GetVerx4Dup(void);
361*53ee8cc1Swenshuai.xi MS_BOOL HAL_MVOP_SetHorx4Dup(MS_BOOL bEnable);
362*53ee8cc1Swenshuai.xi MS_BOOL HAL_MVOP_GetHorx4Dup(void);
363*53ee8cc1Swenshuai.xi MS_BOOL HAL_MVOP_SetYUVBaseAddMultiView(MVOP_BaseAddInput *stBaseAddInfo);
364*53ee8cc1Swenshuai.xi MS_BOOL HAL_MVOP_SetEVDYUVBaseAdd(MVOP_EVDBaseAddInput *stEVDBaseAddInfo);
365*53ee8cc1Swenshuai.xi MS_PHY HAL_MVOP_GetYBaseAddMultiView(MVOP_3DView eView);
366*53ee8cc1Swenshuai.xi MS_PHY HAL_MVOP_GetUVBaseAddMultiView(MVOP_3DView eView);
367*53ee8cc1Swenshuai.xi MS_U16 HAL_MVOP_GetTopVStart(MVOP_DevID eID);
368*53ee8cc1Swenshuai.xi MS_U16 HAL_MVOP_GetBottomVStart(MVOP_DevID eID);
369*53ee8cc1Swenshuai.xi MS_U16 HAL_MVOP_GetVCount(MVOP_DevID eID);
370*53ee8cc1Swenshuai.xi MS_BOOL HAL_MVOP_SetVC1RangeMap(MVOP_DevID eID, MVOP_VC1RangeMapInfo *stVC1RangeMapInfo);
371*53ee8cc1Swenshuai.xi MS_BOOL HAL_MVOP_Set420BWSaveMode(MS_BOOL bEnable);
372*53ee8cc1Swenshuai.xi void HAL_MVOP_SetRptPreVsyncFrame(MVOP_DevID eID, MS_BOOL bEnable);
373*53ee8cc1Swenshuai.xi void HAL_MVOP_PowerStateSuspend(void);
374*53ee8cc1Swenshuai.xi MVOP_HSMode HAL_MVOP_GetHandShakeMode(MVOP_DevID eID);
375*53ee8cc1Swenshuai.xi MS_BOOL HAL_MVOP_CheckSTCCW(void);
376*53ee8cc1Swenshuai.xi MS_BOOL HAL_MVOP_GetIsMiuIPControl(HALMVOPMIUCLIENTINFO stInfo);
377*53ee8cc1Swenshuai.xi void HAL_MVOP_SelMIU(MVOP_DevID eDevID, HALMVOPMIUSEL eMiuMSB0, HALMVOPMIUSEL eMiuMSB1, HALMVOPMIUSEL eMiuLSB0, HALMVOPMIUSEL eMiuLSB1);
378*53ee8cc1Swenshuai.xi MS_BOOL HAL_MVOP_GetIsOnlyMiuIPControl(void);
379*53ee8cc1Swenshuai.xi void HAL_MVOP_SetDCSRAMClk(MS_U8 clkNum, MS_BOOL bEnable);
380*53ee8cc1Swenshuai.xi void HAL_MVOP_SetEnable4k2k2P(MS_BOOL bEnable);
381*53ee8cc1Swenshuai.xi MS_BOOL HAL_MVOP_Get4k2k2PMode(MVOP_DevID eID);
382*53ee8cc1Swenshuai.xi HALMVOPFREQUENCY HAL_MVOP_SetDefaultClk(MVOP_DevID eDevID);
383*53ee8cc1Swenshuai.xi void HAL_MVOP_GetMaxFramerate(MVOP_DevID eDevID, MVOP_GetMaxFps* stStreamInfo);
384*53ee8cc1Swenshuai.xi MS_BOOL HAL_MVOP_GetIsSendingData(MVOP_DevID eDevID);
385*53ee8cc1Swenshuai.xi void HAL_MVOP_SetTimingFromXC(MVOP_DevID eID, MS_BOOL bEnable);
386*53ee8cc1Swenshuai.xi void HAL_MVOP_ResetReg(MVOP_DevID eDevID, MS_U16 u16ECONumber);
387*53ee8cc1Swenshuai.xi MS_BOOL HAL_MVOP_GetIsCurrentHSK(MVOP_DevID eID);
388*53ee8cc1Swenshuai.xi MS_BOOL HAL_MVOP_GetIsCurrentXCGenTiming(MVOP_DevID eID);
389*53ee8cc1Swenshuai.xi HALMVOPFREQUENCY HAL_MVOP_SetFixClk(MVOP_DevID eID, MS_U32 u32MVOPClk);
390*53ee8cc1Swenshuai.xi void HAL_MVOP_SetHandShakeMode(MVOP_DevID eID, MS_BOOL bEnable, MS_U8 u8Framerate);
391*53ee8cc1Swenshuai.xi void HAL_MVOP_SetCropforXC(MVOP_DevID eID, MVOP_XCGetCrop* stXCCrop, MS_U16 u16Width, MS_U16 u16Height);
392*53ee8cc1Swenshuai.xi MS_U16 HAL_MVOP_ReadBank(MVOP_DevID eID ,MS_U16 u16Length);
393*53ee8cc1Swenshuai.xi void HAL_MVOP_WriteBank(MVOP_DevID eID ,MS_U16 u16Length,MS_U16 u16Data);
394*53ee8cc1Swenshuai.xi MS_U16 HAL_MVOP_ReadClkBank(MS_U16 u16Length);
395*53ee8cc1Swenshuai.xi void HAL_MVOP_WriteClkBank(MS_U16 u16Length,MS_U16 u16Data);
396*53ee8cc1Swenshuai.xi void HAL_MVOP_SetInterlaceType(MVOP_DevID eDevID, MS_U16 u16ECONumber, MS_U8 u8Interlace);
397*53ee8cc1Swenshuai.xi MS_BOOL HAL_MVOP_GetIsMVOPSupportBLKBackground(MVOP_DevID eID);
398*53ee8cc1Swenshuai.xi void HAL_MVOP_SetSramPower(MVOP_DevID eID ,MS_BOOL bEnable);
399*53ee8cc1Swenshuai.xi void HAL_MVOP_Exit(MVOP_DevID eID);
400*53ee8cc1Swenshuai.xi void HAL_MVOP_UVSwapEnable(MVOP_DevID eID, MS_BOOL bEnable);
401*53ee8cc1Swenshuai.xi void HAL_MVOP_SetECONumber(MS_U16 u16ECOVersion);
402*53ee8cc1Swenshuai.xi void HAL_SetTSPCW(MVOP_DevID eID);
403*53ee8cc1Swenshuai.xi void HAL_MVOP_SetMFDECInfo(MVOP_DevID eID, HALMVOPMFDECINFO *pMFDECInfo);
404*53ee8cc1Swenshuai.xi //for sub mvop
405*53ee8cc1Swenshuai.xi void HAL_MVOP_SubRegSetBase(MS_VIRT u32Base);
406*53ee8cc1Swenshuai.xi void HAL_MVOP_SubInit(void);
407*53ee8cc1Swenshuai.xi void HAL_MVOP_SubSetFieldInverse(MS_BOOL b2MVD, MS_BOOL b2IP);
408*53ee8cc1Swenshuai.xi void HAL_MVOP_SubSetChromaWeighting(MS_BOOL bEnable);
409*53ee8cc1Swenshuai.xi void HAL_MVOP_SubLoadReg(void);
410*53ee8cc1Swenshuai.xi void HAL_MVOP_SubSetMIUReqMask(MS_BOOL bEnable);
411*53ee8cc1Swenshuai.xi void HAL_MVOP_SubRst(void);
412*53ee8cc1Swenshuai.xi void HAL_MVOP_SubEnable(MS_BOOL bEnable, MS_U8 u8Framerate);
413*53ee8cc1Swenshuai.xi MS_BOOL HAL_MVOP_SubGetEnableState(void);
414*53ee8cc1Swenshuai.xi HALMVOPFREQUENCY HAL_MVOP_SubGetMaxFreerunClk(void);
415*53ee8cc1Swenshuai.xi HALMVOPFREQUENCY HAL_MVOP_SubGet4k2kClk(void);
416*53ee8cc1Swenshuai.xi void HAL_MVOP_SubSetFrequency(HALMVOPFREQUENCY enFrequency);
417*53ee8cc1Swenshuai.xi void HAL_MVOP_SubSetOutputInterlace(MS_BOOL bEnable, MS_U16 u16ECOVersion);
418*53ee8cc1Swenshuai.xi void HAL_MVOP_SubSetPattern(MVOP_Pattern enMVOPPattern);
419*53ee8cc1Swenshuai.xi MS_BOOL HAL_MVOP_SubSetTileFormat(MVOP_TileFormat eTileFmt);
420*53ee8cc1Swenshuai.xi MS_BOOL HAL_MVOP_SubSetRgbFormat(MVOP_RgbFormat eRgbFmt);
421*53ee8cc1Swenshuai.xi MS_BOOL HAL_MVOP_SubEnable3DLR(MS_BOOL bEnable);
422*53ee8cc1Swenshuai.xi MS_BOOL HAL_MVOP_SubGet3DLRMode(void);
423*53ee8cc1Swenshuai.xi void HAL_MVOP_SubSetBlackBG(void);
424*53ee8cc1Swenshuai.xi void HAL_MVOP_SubSetCropWindow(MVOP_InputCfg *pparam);
425*53ee8cc1Swenshuai.xi void HAL_MVOP_SubSetInputMode( VOPINPUTMODE mode, MVOP_InputCfg *pparam, MS_U16 u16ECOVersion );
426*53ee8cc1Swenshuai.xi void HAL_MVOP_SubEnableUVShift(MS_BOOL bEnable);
427*53ee8cc1Swenshuai.xi void HAL_MVOP_SubSetEnable60P(MS_BOOL bEnable);
428*53ee8cc1Swenshuai.xi void HAL_MVOP_SubSetEnable4k2kClk(MS_BOOL bEnable);
429*53ee8cc1Swenshuai.xi void HAL_MVOP_SubSetOutputTiming( MVOP_Timing *ptiming );
430*53ee8cc1Swenshuai.xi void HAL_MVOP_SubSetDCClk(MS_U8 clkNum, MS_BOOL bEnable);
431*53ee8cc1Swenshuai.xi void HAL_MVOP_SubSetDCSRAMClk(MS_U8 clkNum, MS_BOOL bEnable);
432*53ee8cc1Swenshuai.xi void HAL_MVOP_SubSetSynClk(MVOP_Timing *ptiming);
433*53ee8cc1Swenshuai.xi void HAL_MVOP_SubSetMonoMode(MS_BOOL bEnable);
434*53ee8cc1Swenshuai.xi void HAL_MVOP_SubSetH264HardwireMode(MS_U16 u16ECOVersion);
435*53ee8cc1Swenshuai.xi void HAL_MVOP_SubSetRMHardwireMode(MS_U16 u16ECOVersion);
436*53ee8cc1Swenshuai.xi void HAL_MVOP_SubSetJpegHardwireMode(MS_U16 u16ECOVersion);
437*53ee8cc1Swenshuai.xi void HAL_MVOP_SubSetEVDHardwireMode(MS_U16 u16ECOVersion);
438*53ee8cc1Swenshuai.xi void HAL_MVOP_SubSetVP9HardwireMode(MS_U16 u16ECOVersion);
439*53ee8cc1Swenshuai.xi void HAL_MVOP_SubEnableMVDInterface(MS_BOOL bEnable);
440*53ee8cc1Swenshuai.xi MS_BOOL HAL_MVOP_SubGetTimingInfoFromRegisters(MVOP_TimingInfo_FromRegisters *pMvopTimingInfo);
441*53ee8cc1Swenshuai.xi void HAL_MVOP_SubSetHorizontallMirrorMode(MS_BOOL bEnable);
442*53ee8cc1Swenshuai.xi void HAL_MVOP_SubSetVerticalMirrorMode(MS_BOOL bEnable);
443*53ee8cc1Swenshuai.xi void HAL_MVOP_SubEnableFreerunMode(MS_BOOL bEnable);
444*53ee8cc1Swenshuai.xi void HAL_MVOP_SubSetYUVBaseAdd(MS_PHY u32YOffset, MS_PHY u32UVOffset, MS_BOOL bProgressive, MS_BOOL b422pack);
445*53ee8cc1Swenshuai.xi void HAL_MVOP_SubSetRepeatField(MVOP_RptFldMode eMode);
446*53ee8cc1Swenshuai.xi void HAL_MVOP_SubSetFDMaskFromMVD(MS_BOOL bEnable);
447*53ee8cc1Swenshuai.xi MS_PHY HAL_MVOP_SubGetYBaseAdd(void);
448*53ee8cc1Swenshuai.xi MS_PHY HAL_MVOP_SubGetUVBaseAdd(void);
449*53ee8cc1Swenshuai.xi MS_BOOL HAL_MVOP_SubSet420BWSaveMode(MS_BOOL bEnable, MS_U16 u16ECOVersion);
450*53ee8cc1Swenshuai.xi MS_BOOL HAL_MVOP_SubSetEVDYUVBaseAdd(MVOP_EVDBaseAddInput *stEVDBaseAddInfo);
451*53ee8cc1Swenshuai.xi MS_BOOL HAL_MVOP_SubCheckSTCCW(void);
452*53ee8cc1Swenshuai.xi void HAL_MVOP_SubSetEnable4k2k2P(MS_BOOL bEnable);
453*53ee8cc1Swenshuai.xi void HAL_MVOP_SubSetVSyncMode(MS_U8 u8Mode);
454*53ee8cc1Swenshuai.xi MS_BOOL HAL_MVOP_SubSet3DLRAltOutput_VHalfScaling(MS_BOOL bEnable);
455*53ee8cc1Swenshuai.xi MS_BOOL HAL_MVOP_SubSet3DLRAltOutput(MS_BOOL bEnable);
456*53ee8cc1Swenshuai.xi MS_BOOL HAL_MVOP_SubSet3DLRAltSBSOutput(MS_BOOL bEnable);
457*53ee8cc1Swenshuai.xi MS_BOOL HAL_MVOP_SubGet3DLRAltOutput(void);
458*53ee8cc1Swenshuai.xi MS_BOOL HAL_MVOP_SubGet3DLRAltSBSOutput(void);
459*53ee8cc1Swenshuai.xi EN_MVOP_Output_3D_TYPE HAL_MVOP_SubGetOutput3DType(void);
460*53ee8cc1Swenshuai.xi 
461*53ee8cc1Swenshuai.xi //for STB_DC
462*53ee8cc1Swenshuai.xi void HAL_MVOP_SetStartX(MVOP_DevID eID, MS_U16 u16Length);
463*53ee8cc1Swenshuai.xi void HAL_MVOP_SetStartY(MVOP_DevID eID, MS_U16 u16Length, MS_BOOL bIsInterlace);
464*53ee8cc1Swenshuai.xi void HAL_MVOP_SetPicWidthMinus(MVOP_DevID eID, MS_U16 u16Sizes, MS_U16 u16Width);
465*53ee8cc1Swenshuai.xi void HAL_MVOP_SetPicHeightMinus(MVOP_DevID eID, MS_U16 u16Sizes, MS_U16 u16Height);
466*53ee8cc1Swenshuai.xi void HAL_MVOP_MaskDBRegCtrl(MVOP_DevID eID, MS_BOOL bEnable ,MVOPMSAKDBREGCTRL eModeCtrl);
467*53ee8cc1Swenshuai.xi void HAL_MVOP_SetDeb2MVDFrameModeCtrl(MVOP_DevID eID, MS_BOOL bEnable, MVOPDEB2MVDFRAMECTRL eModeCtrl);
468*53ee8cc1Swenshuai.xi void HAL_MVOP_BaseFromIPCtrl(MVOP_DevID eID, MS_BOOL bEnable ,MVOPBASEFROMIPCTRL eModeCtrl );
469*53ee8cc1Swenshuai.xi 
470*53ee8cc1Swenshuai.xi #endif // _HAL_MVOP_H_
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