1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved.
5 // All software, firmware and related documentation herein ("MStar Software") are
6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by
7 // law, including, but not limited to, copyright law and international treaties.
8 // Any use, modification, reproduction, retransmission, or republication of all
9 // or part of MStar Software is expressly prohibited, unless prior written
10 // permission has been granted by MStar.
11 //
12 // By accessing, browsing and/or using MStar Software, you acknowledge that you
13 // have read, understood, and agree, to be bound by below terms ("Terms") and to
14 // comply with all applicable laws and regulations:
15 //
16 // 1. MStar shall retain any and all right, ownership and interest to MStar
17 // Software and any modification/derivatives thereof.
18 // No right, ownership, or interest to MStar Software and any
19 // modification/derivatives thereof is transferred to you under Terms.
20 //
21 // 2. You understand that MStar Software might include, incorporate or be
22 // supplied together with third party`s software and the use of MStar
23 // Software may require additional licenses from third parties.
24 // Therefore, you hereby agree it is your sole responsibility to separately
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26 // such third party`s software.
27 //
28 // 3. MStar Software and any modification/derivatives thereof shall be deemed as
29 // MStar`s confidential information and you agree to keep MStar`s
30 // confidential information in strictest confidence and not disclose to any
31 // third party.
32 //
33 // 4. MStar Software is provided on an "AS IS" basis without warranties of any
34 // kind. Any warranties are hereby expressly disclaimed by MStar, including
35 // without limitation, any warranties of merchantability, non-infringement of
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40 // In no event shall MStar be liable for any direct, indirect, incidental or
41 // consequential damages, including without limitation, lost of profit or
42 // revenues, lost or damage of data, and unauthorized system use.
43 // You agree that this Section 4 shall still apply without being affected
44 // even if MStar Software has been modified by MStar in accordance with your
45 // request or instruction for your use, except otherwise agreed by both
46 // parties in writing.
47 //
48 // 5. If requested, MStar may from time to time provide technical supports or
49 // services in relation with MStar Software to you for your use of
50 // MStar Software in conjunction with your or your customer`s product
51 // ("Services").
52 // You understand and agree that, except otherwise agreed by both parties in
53 // writing, Services are provided on an "AS IS" basis and the warranty
54 // disclaimer set forth in Section 4 above shall apply.
55 //
56 // 6. Nothing contained herein shall be construed as by implication, estoppels
57 // or otherwise:
58 // (a) conferring any license or right to use MStar name, trademark, service
59 // mark, symbol or any other identification;
60 // (b) obligating MStar or any of its affiliates to furnish any person,
61 // including without limitation, you and your customers, any assistance
62 // of any kind whatsoever, or any information; or
63 // (c) conferring any license or right under any intellectual property right.
64 //
65 // 7. These terms shall be governed by and construed in accordance with the laws
66 // of Taiwan, R.O.C., excluding its conflict of law rules.
67 // Any and all dispute arising out hereof or related hereto shall be finally
68 // settled by arbitration referred to the Chinese Arbitration Association,
69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration
70 // Rules of the Association by three (3) arbitrators appointed in accordance
71 // with the said Rules.
72 // The place of arbitration shall be in Taipei, Taiwan and the language shall
73 // be English.
74 // The arbitration award shall be final and binding to both parties.
75 //
76 //******************************************************************************
77 //<MStar Software>
78 #ifndef _ASM_MIPSREG_H
79 #define _ASM_MIPSREG_H
80
81 /*
82 * Coprocessor 0 register names
83 */
84 #define CP0_INDEX $0
85 #define CP0_RANDOM $1
86 #define CP0_ENTRYLO0 $2
87 #define CP0_ENTRYLO1 $3
88 #define CP0_CONF $3
89 #define CP0_CONTEXT $4
90 #define CP0_PAGEMASK $5
91 #define CP0_WIRED $6
92 #define CP0_INFO $7
93 #define CP0_BADVADDR $8
94 #define CP0_COUNT $9
95 #define CP0_ENTRYHI $10
96
97 /*
98 * Functions to access the R10000 performance counters. These are basically
99 * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit
100 * performance counter number encoded into bits 1 ... 5 of the instruction.
101 * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware
102 * disassembler these will look like an access to selection 0 or 1.
103 */
104
105 /*
106 * Macros to access the system control coprocessor
107 */
108 #define __read_32bit_c0_register(src, selectionection) \
109 ({ int __res; \
110 if (selectionection == 0) \
111 __asm__ __volatile__( \
112 "mfc0\t%0, " #src "\n\t" \
113 : "=r" (__res)); \
114 else \
115 __asm__ __volatile__( \
116 ".set\tmips32\n\t" \
117 "mfc0\t%0, " #src ", " #selectionection "\n\t" \
118 ".set\tmips0\n\t" \
119 : "=r" (__res)); \
120 __res; \
121 })
122
123
124 #define __write_32bit_c0_register(register, selection, val) \
125 do { \
126 if (selection == 0) \
127 __asm__ __volatile__( \
128 "mtc0\t%z0, " #register "\n\t" \
129 : : "Jr" ((unsigned int)(val))); \
130 else \
131 __asm__ __volatile__( \
132 ".set\tmips32\n\t" \
133 "mtc0\t%z0, " #register ", " #selection "\n\t" \
134 ".set\tmips0" \
135 : : "Jr" ((unsigned int)(val))); \
136 } while (0)
137
138
139 #define __read_ulong_c0_register(reg, selection) \
140 (unsigned long) __read_32bit_c0_register(reg, selection) ; \
141
142 #define __write_ulong_c0_register(reg, selection, val) \
143 do { \
144 __write_32bit_c0_register(reg, selection, val); \
145 } while (0)
146
147
148 #define write_c0_by_index(value) __write_32bit_c0_register($0, 0, value)
149 #define write_c0_entrylow0(value) __write_ulong_c0_register($2, 0, value)
150 #define write_c0_entrylow1(value) __write_ulong_c0_register($3, 0, value)
151 #define read_c0_by_pagemask() __read_32bit_c0_register($5, 0)
152 #define write_c0_by_pagemask(value) __write_32bit_c0_register($5, 0, value)
153 #define read_c0_with_wired() __read_32bit_c0_register($6, 0)
154 #define write_c0_with_wired(value) __write_32bit_c0_register($6, 0, value)
155 #define read_c0_entryhigh() __read_ulong_c0_register($10, 0)
156 #define write_c0_entryhigh(value) __write_ulong_c0_register($10, 0, value)
157
158
159 /*
160 * TLB operations.
161 *
162 * It is responsibility of the caller to take care of any TLB hazards.
163 */
tlb_index_write(void)164 static inline void tlb_index_write(void)
165 {
166 __asm__ __volatile__(
167 ".set noreorder\n\t"
168 "tlbwi\n\t"
169 ".set reorder");
170 }
171
172
173 #endif /* _ASM_MIPSREG_H */
174