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93 ///////////////////////////////////////////////////////////////////////////////
94
95 ///////////////////////////////////////////////////////////////////////////////////////////////////
96 ///
97 /// file halMMIO.c
98 /// @brief memory map io (MMIO) HAL
99 /// @author MStar Semiconductor Inc.
100 ///////////////////////////////////////////////////////////////////////////////////////////////////
101
102
103 //-------------------------------------------------------------------------------------------------
104 // Include Files
105 //-------------------------------------------------------------------------------------------------
106
107 #include "MsCommon.h"
108 #include "halMMIO.h"
109 #include "drvMMIO.h"
110
111 // for getting mapped IO base from DRV
112 extern MS_VIRT _virtPM_Bank ;
113 extern MS_U32 _u32PM_Bank_SIZE ;
114 extern MS_VIRT _virtNonPM_Bank ;
115 extern MS_U32 _u32NonPM_Bank_SIZE ;
116 extern MS_VIRT _virtFRC_Bank ; //frcr2_integration###
117 extern MS_U32 _u32FRC_Bank_SIZE ; //frcr2_integration###
118
119 //-------------------------------------------------------------------------------------------------
120 // Driver Compiler Options
121 //-------------------------------------------------------------------------------------------------
122
123
124 //--------------------------------------------------------------------------------------------------
125 // Global Variables
126 //--------------------------------------------------------------------------------------------------
127 MS_VIRT virt_ge0_mmio_base;
128
129
130 //-------------------------------------------------------------------------------------------------
131 // Local Defines
132 //-------------------------------------------------------------------------------------------------
133 #ifdef MSOS_TYPE_LINUX
134 // assume linux always running on mips
135 #define HAL_MMIO_PM_BASE 0x1f000000UL
136 #define HAL_MMIO_PM_SIZE 0x00A00000UL
137 #define HAL_MMIO_NONPM_BASE 0x1f200000UL
138 #define HAL_MMIO_NONPM_SIZE 0x01000000UL
139 #define HAL_MMIO_FLASH_BASE0 0x14000000UL
140 #define HAL_MMIO_FLASH_SIZE0 0x01000000UL
141 #define HAL_MMIO_FRC_BASE 0x1f800000UL //frcr2_integration###
142 #define HAL_MMIO_FRC_SIZE 0x00013600UL //frcr2_integration###
143 #elif defined(MSOS_TYPE_LINUX_KERNEL)
144 #ifdef CONFIG_UTOPIA_FRAMEWORK_KERNEL_DRIVER_64BIT
145 extern ptrdiff_t mstar_pm_base;
146 #define RIU_BASE mstar_pm_base
147 #else
148 #define RIU_BASE 0xfd000000UL
149 #endif
150 #define HAL_MMIO_PM_BASE RIU_BASE
151 #define HAL_MMIO_PM_SIZE 0x00A00000UL
152 #define HAL_MMIO_NONPM_BASE RIU_BASE+0x200000UL
153 #define HAL_MMIO_NONPM_SIZE 0x01000000UL
154 #define HAL_MMIO_FLASH_BASE0 0x14000000UL
155 #define HAL_MMIO_FLASH_SIZE0 0x01000000UL
156 #define HAL_MMIO_FRC_BASE RIU_BASE+0x800000UL //0x1f800000UL //frcr2_integration###
157 #define HAL_MMIO_FRC_SIZE 0x00013600UL //frcr2_integration###
158 #else
159 #if defined (MCU_AEON)
160 #define HAL_MMIO_PM_BASE 0xFA000000UL
161 #define HAL_MMIO_PM_SIZE 0x00007B80UL
162 #define HAL_MMIO_NONPM_BASE 0xFA200000UL
163 #define HAL_MMIO_NONPM_SIZE 0x00025600UL
164 #define HAL_MMIO_FLASH_BASE0 0xA1000000UL // non-cache // 0xA1000000 for cache
165 #define HAL_MMIO_FLASH_SIZE0 0x1000000UL
166 #define HAL_MMIO_FRC_BASE 0xFA800000UL //frcr2_integration###
167 #define HAL_MMIO_FRC_SIZE 0x00013600UL //frcr2_integration###
168 #elif defined (MCU_ARM_CA7)
169 #define HAL_MMIO_PM_BASE 0x1f000000UL
170 #define HAL_MMIO_PM_SIZE 0x00007B80UL
171 #define HAL_MMIO_NONPM_BASE 0x1f200000UL
172 #define HAL_MMIO_NONPM_SIZE 0x00025600UL
173 #define HAL_MMIO_FLASH_BASE0 0x14000000UL
174 #define HAL_MMIO_FLASH_SIZE0 0x1000000UL
175 #define HAL_MMIO_FRC_BASE 0x1f800000UL //frcr2_integration###
176 #define HAL_MMIO_FRC_SIZE 0x00013600UL //frcr2_integration###
177 #elif defined (MCU_ARM_CA53)
178 #define HAL_MMIO_PM_BASE 0x1f000000UL
179 #define HAL_MMIO_PM_SIZE 0x00007B80UL
180 #define HAL_MMIO_NONPM_BASE 0x1f200000UL
181 #define HAL_MMIO_NONPM_SIZE 0x00025600UL
182 #define HAL_MMIO_FLASH_BASE0 0x14000000UL
183 #define HAL_MMIO_FLASH_SIZE0 0x1000000UL
184 #define HAL_MMIO_FRC_BASE 0x1f800000UL //frcr2_integration###
185 #define HAL_MMIO_FRC_SIZE 0x00013600UL //frcr2_integration###
186 #else
187 #error "Please choose MCU";
188 #endif
189 #endif
190
191
192 //-------------------------------------------------------------------------------------------------
193 // Local Structurs
194 //-------------------------------------------------------------------------------------------------
195
196
197 //-------------------------------------------------------------------------------------------------
198 // Global Variables
199 //-------------------------------------------------------------------------------------------------
200
201
202 //-------------------------------------------------------------------------------------------------
203 // Local Variables
204 //-------------------------------------------------------------------------------------------------
205
206
207 //-------------------------------------------------------------------------------------------------
208 // Debug Functions
209 //-------------------------------------------------------------------------------------------------
210
211
212 //-------------------------------------------------------------------------------------------------
213 // Local Functions
214 //-------------------------------------------------------------------------------------------------
215
216
217 //-------------------------------------------------------------------------------------------------
218 // Global Functions
219 //-------------------------------------------------------------------------------------------------
HAL_MMIO_GetType(MS_U32 u32Module)220 MS_U16 HAL_MMIO_GetType(MS_U32 u32Module)
221 {
222 switch (u32Module)
223 {
224 //HAL_MMIO_PM_BANK
225 case MS_MODULE_PM :
226 case MS_MODULE_IR :
227 case MS_MODULE_ISP :
228 case MS_MODULE_PWS :
229 return DRV_MMIO_PM_BANK;
230
231 //HAL_MMIO_NONPM_BANK
232 case MS_MODULE_HW :
233 case MS_MODULE_CHIPTOP :
234 case MS_MODULE_MIU :
235 case MS_MODULE_ACE :
236 case MS_MODULE_AUDIO :
237 case MS_MODULE_AVD :
238 case MS_MODULE_BDMA :
239 case MS_MODULE_DLC :
240 case MS_MODULE_DMD :
241 case MS_MODULE_GE :
242 case MS_MODULE_GOP :
243 case MS_MODULE_GPIO :
244 case MS_MODULE_HVD :
245 case MS_MODULE_HWI2C :
246 case MS_MODULE_IRQ :
247 case MS_MODULE_JPD :
248 case MS_MODULE_MBX :
249 case MS_MODULE_MFE :
250 case MS_MODULE_MHEG5 :
251 case MS_MODULE_MVD :
252 case MS_MODULE_MVOP :
253 case MS_MODULE_RVD :
254 case MS_MODULE_TSP :
255 case MS_MODULE_UART :
256 case MS_MODULE_VPU :
257 case MS_MODULE_XC :
258 case MS_MODULE_PCMCIA :
259 case MS_MODULE_PFSH :
260 case MS_MODULE_PNL :
261 case MS_MODULE_PWM :
262 case MS_MODULE_SEM :
263 case MS_MODULE_VBI :
264 case MS_MODULE_VIF :
265 case MS_MODULE_DIP :
266 case MS_MODULE_MPIF :
267 case MS_MODULE_MMFILEIN :
268 case MS_MODULE_GPD :
269 case MS_MODULE_TSO :
270 case MS_MODULE_CMDQ :
271 return DRV_MMIO_NONPM_BANK;
272
273 case MS_MODULE_SC :
274 return DRV_MMIO_SC_BANK;
275
276 //HAL_MMIO_FLASH_BANK0
277 case MS_MODULE_FLASH :
278 return DRV_MMIO_FLASH_BANK0;
279 case MS_MODULE_FRC : //frcr2_integration###
280 return DRV_MMIO_FRC_BANK; //frcr2_integration###
281
282 default:
283 return 0xFFFF; //undefine type
284 }
285
286 return 0xFFFF; //undefine type
287 }
288
289
HAL_MMIO_GetBase(MS_PHY * virtBaseAddr,MS_PHY * pu32BaseSize,MS_U32 u32BankType)290 MS_BOOL HAL_MMIO_GetBase(MS_PHY* virtBaseAddr, MS_PHY* pu32BaseSize, MS_U32 u32BankType)
291 {
292 MS_BOOL bRet = TRUE;
293
294 *virtBaseAddr = 0;
295 *pu32BaseSize = 0;
296 switch (u32BankType)
297 {
298 case DRV_MMIO_PM_BANK:
299 *virtBaseAddr = (MS_PHY)HAL_MMIO_PM_BASE;
300 *pu32BaseSize = (MS_PHY)HAL_MMIO_PM_SIZE;
301 break;
302 case DRV_MMIO_NONPM_BANK:
303 *virtBaseAddr = (MS_PHY)HAL_MMIO_NONPM_BASE;
304 *pu32BaseSize = (MS_PHY)HAL_MMIO_NONPM_SIZE;
305 break;
306 case DRV_MMIO_FLASH_BANK0:
307 *virtBaseAddr = (MS_PHY)HAL_MMIO_FLASH_BASE0;
308 *pu32BaseSize = (MS_PHY)HAL_MMIO_FLASH_SIZE0;
309 break;
310 case DRV_MMIO_FRC_BANK:
311 *virtBaseAddr = (MS_PHY)HAL_MMIO_FRC_BASE;
312 *pu32BaseSize = (MS_PHY)HAL_MMIO_FRC_SIZE;
313 break;
314 default:
315 // MS_ASSERT(0);
316 bRet = FALSE;
317 break;
318 }
319
320 return bRet;
321 }
322
323
324 // @NOTE: Only run after MMIO_Init
HAL_MMIO_GetIPBase(MS_VIRT * virtBaseAddr,MS_U16 u16BankType)325 MS_BOOL HAL_MMIO_GetIPBase(MS_VIRT *virtBaseAddr, MS_U16 u16BankType)
326 {
327 *virtBaseAddr = 0;
328
329 // if MMIO_Init is not yet initialized.
330 if ( (_u32PM_Bank_SIZE == 0x0) || (_u32NonPM_Bank_SIZE == 0x0) || (_u32FRC_Bank_SIZE == 0x0) ) //frcr2_integration###
331 {
332 return FALSE;
333 }
334
335 switch (u16BankType)
336 {
337 case DRV_MMIO_SC_BANK:
338 *virtBaseAddr =_virtNonPM_Bank + 0x00005200; // 0xBF220C00, 0xBF220C80
339 break;
340 default:
341 return FALSE;
342 }
343
344 return TRUE;
345 }
346
347 #if defined(__aarch64__) || defined(__arm__)
348 #ifndef MSOS_TYPE_LINUX
_chip_flush_miu_pipe(void)349 static void _chip_flush_miu_pipe(void)
350 {
351 unsigned int dwReadData = 0;
352
353
354 //toggle the flush miu pipe fire bit
355 *(volatile unsigned int *)(HAL_MMIO_PM_BASE + (0x10188A << 1)) &= ~(0x0001);
356 *(volatile unsigned int *)(HAL_MMIO_PM_BASE + (0x10188A << 1)) |= 0x0001;
357
358 do
359 {
360 dwReadData = *(volatile unsigned int *)(HAL_MMIO_PM_BASE+ (0x1018A0 << 1));
361 dwReadData &= BIT(12); //Check Status of Flush Pipe Finish
362
363 } while(dwReadData == 0);
364 }
365 #endif
366 #endif
367
HAL_MMIO_FlushMemory(void)368 void HAL_MMIO_FlushMemory(void)
369 {
370 #if defined(__aarch64__) || defined(__arm__)
371 #ifndef MSOS_TYPE_LINUX
372 _chip_flush_miu_pipe();
373 #endif
374 #endif
375 }
376
HAL_MMIO_ReadMemory(void)377 void HAL_MMIO_ReadMemory(void)
378 {
379 #if defined(__aarch64__) || defined(__arm__)
380 #ifndef MSOS_TYPE_LINUX
381 _chip_flush_miu_pipe();
382 #endif
383 #endif
384 }
385
386
387