xref: /utopia/UTPA2-700.0.x/modules/msos/drv/mmio/drvMMIO.c (revision 53ee8cc121a030b8d368113ac3e966b4705770ef)
1*53ee8cc1Swenshuai.xi //<MStar Software>
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77*53ee8cc1Swenshuai.xi //<MStar Software>
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93*53ee8cc1Swenshuai.xi ////////////////////////////////////////////////////////////////////////////////
94*53ee8cc1Swenshuai.xi 
95*53ee8cc1Swenshuai.xi ///////////////////////////////////////////////////////////////////////////////////////////////////
96*53ee8cc1Swenshuai.xi ///
97*53ee8cc1Swenshuai.xi /// file    drvMMIO.c
98*53ee8cc1Swenshuai.xi /// @brief  MMIO SYS Driver Interface
99*53ee8cc1Swenshuai.xi /// @author MStar Semiconductor Inc.
100*53ee8cc1Swenshuai.xi ///////////////////////////////////////////////////////////////////////////////////////////////////
101*53ee8cc1Swenshuai.xi 
102*53ee8cc1Swenshuai.xi 
103*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
104*53ee8cc1Swenshuai.xi //  Include Files
105*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
106*53ee8cc1Swenshuai.xi 
107*53ee8cc1Swenshuai.xi #ifdef MSOS_TYPE_LINUX
108*53ee8cc1Swenshuai.xi 
109*53ee8cc1Swenshuai.xi #include <unistd.h>
110*53ee8cc1Swenshuai.xi #include <fcntl.h>
111*53ee8cc1Swenshuai.xi #include <sys/ioctl.h>
112*53ee8cc1Swenshuai.xi #include <sys/mman.h>
113*53ee8cc1Swenshuai.xi #include "MsCommon.h"
114*53ee8cc1Swenshuai.xi #include "drvMMIO.h"
115*53ee8cc1Swenshuai.xi #include "halMMIO.h"
116*53ee8cc1Swenshuai.xi #include "regCHIP.h"
117*53ee8cc1Swenshuai.xi 
118*53ee8cc1Swenshuai.xi /* Use 'I' as magic number */
119*53ee8cc1Swenshuai.xi #define MIOMAP_IOC_MAGIC                    'I'
120*53ee8cc1Swenshuai.xi #define MMIO_IOC_SET_MAP                    _IOW (MIOMAP_IOC_MAGIC, 0x01, MIOMap_Info_t)
121*53ee8cc1Swenshuai.xi 
122*53ee8cc1Swenshuai.xi /* MIOMAP_IOC_INFO */
123*53ee8cc1Swenshuai.xi typedef struct
124*53ee8cc1Swenshuai.xi {
125*53ee8cc1Swenshuai.xi     MS_U64                                  virtAddr;
126*53ee8cc1Swenshuai.xi     MS_U64                                  u32Size;
127*53ee8cc1Swenshuai.xi } MIOMap_Info_t;
128*53ee8cc1Swenshuai.xi 
129*53ee8cc1Swenshuai.xi #else // #ifdef MSOS_TYPE_LINUX
130*53ee8cc1Swenshuai.xi 
131*53ee8cc1Swenshuai.xi #include "MsCommon.h"
132*53ee8cc1Swenshuai.xi #include "drvMMIO.h"
133*53ee8cc1Swenshuai.xi #include "halMMIO.h"
134*53ee8cc1Swenshuai.xi #include "regCHIP.h"
135*53ee8cc1Swenshuai.xi 
136*53ee8cc1Swenshuai.xi #endif
137*53ee8cc1Swenshuai.xi #include "MsVersion.h"
138*53ee8cc1Swenshuai.xi #include "ULog.h"
139*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
140*53ee8cc1Swenshuai.xi //  Driver Compiler Options
141*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
142*53ee8cc1Swenshuai.xi #ifdef MS_DEBUG
143*53ee8cc1Swenshuai.xi #define MMIO_DEBUG
144*53ee8cc1Swenshuai.xi #endif
145*53ee8cc1Swenshuai.xi 
146*53ee8cc1Swenshuai.xi 
147*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
148*53ee8cc1Swenshuai.xi //  Local Defines
149*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
150*53ee8cc1Swenshuai.xi #ifdef MMIO_DEBUG
151*53ee8cc1Swenshuai.xi     #define MMIO_ERROR(fmt, args...)         MS_DEBUG_MSG(ULOGE("MMIO","[%06d]     " fmt, __LINE__, ##args))
152*53ee8cc1Swenshuai.xi     #define MMIO_WARN(fmt, args...)         MS_DEBUG_MSG(ULOGW("MMIO","[%06d]     " fmt, __LINE__, ##args))
153*53ee8cc1Swenshuai.xi     #define MMIO_PRINT(fmt, args...)         MS_DEBUG_MSG(ULOGI("MMIO", "[%06d]     " fmt, __LINE__, ##args))
154*53ee8cc1Swenshuai.xi     #define MMIO_ASSERT(_bool, _f)          if (!(_bool)) { MS_DEBUG_MSG(ULOGF("MMIO",_f)); MS_ASSERT(0);) }
155*53ee8cc1Swenshuai.xi #else
156*53ee8cc1Swenshuai.xi     #define MMIO_ERROR(fmt, args...)        MS_DEBUG_MSG(while (0))
157*53ee8cc1Swenshuai.xi     #define MMIO_WARN(fmt, args...)         MS_DEBUG_MSG(while (0))
158*53ee8cc1Swenshuai.xi     #define MMIO_PRINT(fmt, args...)        MS_DEBUG_MSG(while (0))
159*53ee8cc1Swenshuai.xi     #define MMIO_ASSERT(_bool, _f)          if (!(_bool)) { MS_DEBUG_MSG((_f)); }
160*53ee8cc1Swenshuai.xi #endif
161*53ee8cc1Swenshuai.xi 
162*53ee8cc1Swenshuai.xi 
163*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
164*53ee8cc1Swenshuai.xi //  Local Structurs
165*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
166*53ee8cc1Swenshuai.xi 
167*53ee8cc1Swenshuai.xi 
168*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
169*53ee8cc1Swenshuai.xi //  Global Variables
170*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
171*53ee8cc1Swenshuai.xi #ifdef MSOS_TYPE_LINUX
172*53ee8cc1Swenshuai.xi MS_VIRT                               _virtPM_Bank                 = 0x0 ;
173*53ee8cc1Swenshuai.xi MS_PHY                              _u32PM_Bank_SIZE            = 0x0 ;
174*53ee8cc1Swenshuai.xi MS_VIRT                               _virtNonPM_Bank              = 0x0 ;
175*53ee8cc1Swenshuai.xi MS_PHY                              _u32NonPM_Bank_SIZE         = 0x0 ;
176*53ee8cc1Swenshuai.xi MS_VIRT                               _virtFlash_Bank0             = 0x0 ;
177*53ee8cc1Swenshuai.xi MS_PHY                              _u32Flash_Bank0_SIZE        = 0x0 ;
178*53ee8cc1Swenshuai.xi MS_VIRT                               _virtOTP_Bank                = 0x0 ;
179*53ee8cc1Swenshuai.xi MS_PHY                              _u32OTP_BankSize            = 0x0 ;
180*53ee8cc1Swenshuai.xi MS_VIRT                               _virtOTP_Bank2               = 0x0 ;  //OTP raw data area
181*53ee8cc1Swenshuai.xi MS_PHY                              _u32OTP_Bank2Size           = 0x0 ;
182*53ee8cc1Swenshuai.xi 
183*53ee8cc1Swenshuai.xi MS_VIRT                               _virtFRC_Bank                = 0x0 ;
184*53ee8cc1Swenshuai.xi MS_PHY                              _u32FRC_Bank_SIZE           = 0x0 ;
185*53ee8cc1Swenshuai.xi 
186*53ee8cc1Swenshuai.xi MS_VIRT                               _virtNSK_Bank                = 0x0 ; // U3 Only
187*53ee8cc1Swenshuai.xi MS_PHY                               _u32NSK_BankSize            = 0x0 ;
188*53ee8cc1Swenshuai.xi 
189*53ee8cc1Swenshuai.xi MS_VIRT                               _virtSPRAM_Bank              = 0x0 ; // Scratchpad memory K2 Only
190*53ee8cc1Swenshuai.xi MS_PHY                              _u32SPRAM_BankSize          = 0x0 ;
191*53ee8cc1Swenshuai.xi #else
192*53ee8cc1Swenshuai.xi MS_PHY                              _virtPM_Bank                 = 0x0 ;
193*53ee8cc1Swenshuai.xi MS_PHY                              _u32PM_Bank_SIZE            = 0x0 ;
194*53ee8cc1Swenshuai.xi MS_PHY                              _virtNonPM_Bank              = 0x0 ;
195*53ee8cc1Swenshuai.xi MS_PHY                              _u32NonPM_Bank_SIZE         = 0x0 ;
196*53ee8cc1Swenshuai.xi MS_PHY                              _virtFlash_Bank0             = 0x0 ;
197*53ee8cc1Swenshuai.xi MS_PHY                              _u32Flash_Bank0_SIZE        = 0x0 ;
198*53ee8cc1Swenshuai.xi MS_PHY                              _virtOTP_Bank                = 0x0 ;
199*53ee8cc1Swenshuai.xi MS_PHY                              _u32OTP_BankSize            = 0x0 ;
200*53ee8cc1Swenshuai.xi MS_PHY                              _virtOTP_Bank2               = 0x0 ;  //OTP raw data area
201*53ee8cc1Swenshuai.xi MS_PHY                              _u32OTP_Bank2Size           = 0x0 ;
202*53ee8cc1Swenshuai.xi 
203*53ee8cc1Swenshuai.xi MS_PHY                              _virtFRC_Bank                = 0x0 ;
204*53ee8cc1Swenshuai.xi MS_PHY                              _u32FRC_Bank_SIZE           = 0x0 ;
205*53ee8cc1Swenshuai.xi 
206*53ee8cc1Swenshuai.xi MS_PHY                               _virtNSK_Bank                = 0x0 ; // U3 Only
207*53ee8cc1Swenshuai.xi MS_PHY                               _u32NSK_BankSize            = 0x0 ;
208*53ee8cc1Swenshuai.xi 
209*53ee8cc1Swenshuai.xi MS_PHY                              _virtSPRAM_Bank              = 0x0 ; // Scratchpad memory K2 Only
210*53ee8cc1Swenshuai.xi MS_PHY                              _u32SPRAM_BankSize          = 0x0 ;
211*53ee8cc1Swenshuai.xi 
212*53ee8cc1Swenshuai.xi #endif
213*53ee8cc1Swenshuai.xi static MSIF_Version _drv_mmio_version = {
214*53ee8cc1Swenshuai.xi     .DDI = { MMIO_DRV_VERSION },
215*53ee8cc1Swenshuai.xi };
216*53ee8cc1Swenshuai.xi ////////////////////////////////////////////////////////////////////////////////
217*53ee8cc1Swenshuai.xi /// @brief \b Function  \b Name: MDrv_MSOS_GetLibVer
218*53ee8cc1Swenshuai.xi /// @brief \b Function  \b Description: Show the MSOS driver version
219*53ee8cc1Swenshuai.xi /// @param ppVersion    \b Out: Library version string
220*53ee8cc1Swenshuai.xi /// @return             \b Result
221*53ee8cc1Swenshuai.xi ////////////////////////////////////////////////////////////////////////////////
MDrv_MMIO_GetLibVer(const MSIF_Version ** ppVersion)222*53ee8cc1Swenshuai.xi MS_BOOL MDrv_MMIO_GetLibVer(const MSIF_Version **ppVersion)
223*53ee8cc1Swenshuai.xi {
224*53ee8cc1Swenshuai.xi     if (!ppVersion)
225*53ee8cc1Swenshuai.xi         return FALSE;
226*53ee8cc1Swenshuai.xi 
227*53ee8cc1Swenshuai.xi     *ppVersion = &_drv_mmio_version;
228*53ee8cc1Swenshuai.xi     return TRUE;
229*53ee8cc1Swenshuai.xi }
230*53ee8cc1Swenshuai.xi 
231*53ee8cc1Swenshuai.xi #ifdef MSOS_TYPE_LINUX
232*53ee8cc1Swenshuai.xi 
233*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
234*53ee8cc1Swenshuai.xi //  Local Variables
235*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
236*53ee8cc1Swenshuai.xi static MS_S32                       _s32MIOMapFd                = -1;
237*53ee8cc1Swenshuai.xi 
238*53ee8cc1Swenshuai.xi 
239*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
240*53ee8cc1Swenshuai.xi //  Debug Functions
241*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
242*53ee8cc1Swenshuai.xi 
243*53ee8cc1Swenshuai.xi 
244*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
245*53ee8cc1Swenshuai.xi //  Local Functions
246*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
247*53ee8cc1Swenshuai.xi 
248*53ee8cc1Swenshuai.xi 
249*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
250*53ee8cc1Swenshuai.xi //  Global Functions
251*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
252*53ee8cc1Swenshuai.xi 
MDrv_MMIO_Init(void)253*53ee8cc1Swenshuai.xi MS_BOOL MDrv_MMIO_Init(void)
254*53ee8cc1Swenshuai.xi {
255*53ee8cc1Swenshuai.xi     MIOMap_Info_t       stMIOMapInfo;
256*53ee8cc1Swenshuai.xi 
257*53ee8cc1Swenshuai.xi     MS_PHY              PM_Bank ;
258*53ee8cc1Swenshuai.xi     MS_PHY              PM_Bank_SIZE ;
259*53ee8cc1Swenshuai.xi     MS_PHY              NonPM_Bank ;
260*53ee8cc1Swenshuai.xi     MS_PHY              NonPM_Bank_SIZE ;
261*53ee8cc1Swenshuai.xi     MS_PHY              Flash_Bank0 ;
262*53ee8cc1Swenshuai.xi     MS_PHY              Flash_Bank0_SIZE ;
263*53ee8cc1Swenshuai.xi     MS_PHY              FRC_Bank ;
264*53ee8cc1Swenshuai.xi     MS_PHY              FRC_Bank_SIZE ;
265*53ee8cc1Swenshuai.xi     MS_PHY              bank_addr = 0;
266*53ee8cc1Swenshuai.xi     MS_PHY              bank_size = 0;
267*53ee8cc1Swenshuai.xi 
268*53ee8cc1Swenshuai.xi     if (0 <= _s32MIOMapFd)
269*53ee8cc1Swenshuai.xi     {
270*53ee8cc1Swenshuai.xi         MMIO_WARN("%s is initiated more than once\n", __FUNCTION__);
271*53ee8cc1Swenshuai.xi         return FALSE;
272*53ee8cc1Swenshuai.xi     }
273*53ee8cc1Swenshuai.xi 
274*53ee8cc1Swenshuai.xi     if (0 > (_s32MIOMapFd = open("/dev/miomap", O_RDWR)))
275*53ee8cc1Swenshuai.xi     {
276*53ee8cc1Swenshuai.xi         MMIO_ERROR("Open /dev/miomap fail\n");
277*53ee8cc1Swenshuai.xi         MS_ASSERT(0);
278*53ee8cc1Swenshuai.xi         return FALSE;
279*53ee8cc1Swenshuai.xi     }
280*53ee8cc1Swenshuai.xi 
281*53ee8cc1Swenshuai.xi 
282*53ee8cc1Swenshuai.xi     if (FALSE == HAL_MMIO_GetBase(&PM_Bank, &PM_Bank_SIZE, DRV_MMIO_PM_BANK))
283*53ee8cc1Swenshuai.xi     {
284*53ee8cc1Swenshuai.xi         MS_ASSERT(0);
285*53ee8cc1Swenshuai.xi     }
286*53ee8cc1Swenshuai.xi     if (FALSE == HAL_MMIO_GetBase(&NonPM_Bank, &NonPM_Bank_SIZE, DRV_MMIO_NONPM_BANK))
287*53ee8cc1Swenshuai.xi     {
288*53ee8cc1Swenshuai.xi         MS_ASSERT(0);
289*53ee8cc1Swenshuai.xi     }
290*53ee8cc1Swenshuai.xi     if (FALSE == HAL_MMIO_GetBase(&Flash_Bank0, &Flash_Bank0_SIZE, DRV_MMIO_FLASH_BANK0))
291*53ee8cc1Swenshuai.xi     {
292*53ee8cc1Swenshuai.xi         MS_ASSERT(0);
293*53ee8cc1Swenshuai.xi     }
294*53ee8cc1Swenshuai.xi 
295*53ee8cc1Swenshuai.xi     if (FALSE == HAL_MMIO_GetBase(&FRC_Bank, &FRC_Bank_SIZE, DRV_MMIO_FRC_BANK))
296*53ee8cc1Swenshuai.xi     {
297*53ee8cc1Swenshuai.xi         MS_ASSERT(0);
298*53ee8cc1Swenshuai.xi     }
299*53ee8cc1Swenshuai.xi 
300*53ee8cc1Swenshuai.xi     if (PM_Bank_SIZE)
301*53ee8cc1Swenshuai.xi     {
302*53ee8cc1Swenshuai.xi         stMIOMapInfo.virtAddr = PM_Bank ;
303*53ee8cc1Swenshuai.xi         stMIOMapInfo.u32Size = PM_Bank_SIZE ;
304*53ee8cc1Swenshuai.xi         if (ioctl(_s32MIOMapFd, MMIO_IOC_SET_MAP , &stMIOMapInfo))
305*53ee8cc1Swenshuai.xi         {
306*53ee8cc1Swenshuai.xi             return FALSE;
307*53ee8cc1Swenshuai.xi         }
308*53ee8cc1Swenshuai.xi         if ((MS_VIRT)MAP_FAILED == (_virtPM_Bank= (MS_VIRT)mmap(0, stMIOMapInfo.u32Size, PROT_READ| PROT_WRITE, MAP_SHARED, _s32MIOMapFd, 0)))
309*53ee8cc1Swenshuai.xi         {
310*53ee8cc1Swenshuai.xi             MS_ASSERT(0);
311*53ee8cc1Swenshuai.xi             return FALSE;
312*53ee8cc1Swenshuai.xi         }
313*53ee8cc1Swenshuai.xi         _u32PM_Bank_SIZE = PM_Bank_SIZE ;
314*53ee8cc1Swenshuai.xi         MMIO_PRINT("PM Bank mapping success. Base=[%lx], Size=[%x]\n", (MS_VIRT)_virtPM_Bank, (MS_PHY)_u32PM_Bank_SIZE);
315*53ee8cc1Swenshuai.xi     }
316*53ee8cc1Swenshuai.xi 
317*53ee8cc1Swenshuai.xi     if (NonPM_Bank_SIZE)
318*53ee8cc1Swenshuai.xi     {
319*53ee8cc1Swenshuai.xi         stMIOMapInfo.virtAddr = NonPM_Bank ;
320*53ee8cc1Swenshuai.xi         stMIOMapInfo.u32Size = NonPM_Bank_SIZE ;
321*53ee8cc1Swenshuai.xi         if (ioctl(_s32MIOMapFd, MMIO_IOC_SET_MAP , &stMIOMapInfo))
322*53ee8cc1Swenshuai.xi         {
323*53ee8cc1Swenshuai.xi             return FALSE;
324*53ee8cc1Swenshuai.xi         }
325*53ee8cc1Swenshuai.xi         if ((MS_VIRT)MAP_FAILED == (_virtNonPM_Bank= (MS_VIRT)mmap(0, stMIOMapInfo.u32Size, PROT_READ| PROT_WRITE, MAP_SHARED, _s32MIOMapFd, 0)))
326*53ee8cc1Swenshuai.xi         {
327*53ee8cc1Swenshuai.xi             MS_ASSERT(0);
328*53ee8cc1Swenshuai.xi             return FALSE;
329*53ee8cc1Swenshuai.xi         }
330*53ee8cc1Swenshuai.xi         _u32NonPM_Bank_SIZE  = NonPM_Bank_SIZE ;
331*53ee8cc1Swenshuai.xi         MMIO_PRINT("NonPM Bank mapping success. Base=[%lx], Size=[%x]\n",(MS_VIRT) _virtNonPM_Bank, (MS_PHY)_u32NonPM_Bank_SIZE);
332*53ee8cc1Swenshuai.xi     }
333*53ee8cc1Swenshuai.xi 
334*53ee8cc1Swenshuai.xi     if (Flash_Bank0_SIZE)
335*53ee8cc1Swenshuai.xi     {
336*53ee8cc1Swenshuai.xi         stMIOMapInfo.virtAddr = Flash_Bank0 ;
337*53ee8cc1Swenshuai.xi         stMIOMapInfo.u32Size = Flash_Bank0_SIZE ;
338*53ee8cc1Swenshuai.xi         if (ioctl(_s32MIOMapFd, MMIO_IOC_SET_MAP , &stMIOMapInfo))
339*53ee8cc1Swenshuai.xi         {
340*53ee8cc1Swenshuai.xi             return FALSE;
341*53ee8cc1Swenshuai.xi         }
342*53ee8cc1Swenshuai.xi         if ((MS_VIRT)MAP_FAILED == (_virtFlash_Bank0= (MS_VIRT)mmap(0, stMIOMapInfo.u32Size, PROT_READ| PROT_WRITE, MAP_SHARED, _s32MIOMapFd, 0)))
343*53ee8cc1Swenshuai.xi         {
344*53ee8cc1Swenshuai.xi             MS_ASSERT(0);
345*53ee8cc1Swenshuai.xi             return FALSE;
346*53ee8cc1Swenshuai.xi         }
347*53ee8cc1Swenshuai.xi         _u32Flash_Bank0_SIZE = Flash_Bank0_SIZE ;
348*53ee8cc1Swenshuai.xi         MMIO_PRINT("Flash Bank0 mapping success. Base=[%lx], Size=[%x]\n", (MS_PHY)_virtFlash_Bank0, (MS_PHY)_u32Flash_Bank0_SIZE);
349*53ee8cc1Swenshuai.xi     }
350*53ee8cc1Swenshuai.xi 
351*53ee8cc1Swenshuai.xi     if (FRC_Bank_SIZE)
352*53ee8cc1Swenshuai.xi     {
353*53ee8cc1Swenshuai.xi         stMIOMapInfo.virtAddr = FRC_Bank ;
354*53ee8cc1Swenshuai.xi         stMIOMapInfo.u32Size = FRC_Bank_SIZE ;
355*53ee8cc1Swenshuai.xi         if (ioctl(_s32MIOMapFd, MMIO_IOC_SET_MAP , &stMIOMapInfo))
356*53ee8cc1Swenshuai.xi         {
357*53ee8cc1Swenshuai.xi             return FALSE;
358*53ee8cc1Swenshuai.xi         }
359*53ee8cc1Swenshuai.xi         if ((MS_VIRT)MAP_FAILED == (_virtFRC_Bank= (MS_VIRT)mmap(0, stMIOMapInfo.u32Size, PROT_READ| PROT_WRITE, MAP_SHARED, _s32MIOMapFd, 0)))
360*53ee8cc1Swenshuai.xi         {
361*53ee8cc1Swenshuai.xi             MS_ASSERT(0);
362*53ee8cc1Swenshuai.xi             return FALSE;
363*53ee8cc1Swenshuai.xi         }
364*53ee8cc1Swenshuai.xi         _u32FRC_Bank_SIZE  = FRC_Bank_SIZE ;
365*53ee8cc1Swenshuai.xi         MMIO_PRINT("FRC Bank mapping success. Base=[%lx], Size=[%x]\n",(MS_VIRT) _virtFRC_Bank, (MS_PHY)_u32FRC_Bank_SIZE);
366*53ee8cc1Swenshuai.xi     }
367*53ee8cc1Swenshuai.xi /*
368*53ee8cc1Swenshuai.xi     Not every chip support OTP / NSK, the return value of MMIO_GetBase could be FALSE
369*53ee8cc1Swenshuai.xi */
370*53ee8cc1Swenshuai.xi 
371*53ee8cc1Swenshuai.xi     if (HAL_MMIO_GetBase(&bank_addr, &bank_size, DRV_MMIO_OTP_BANK))
372*53ee8cc1Swenshuai.xi     {
373*53ee8cc1Swenshuai.xi         stMIOMapInfo.virtAddr = bank_addr;
374*53ee8cc1Swenshuai.xi         stMIOMapInfo.u32Size = bank_size;
375*53ee8cc1Swenshuai.xi         if (ioctl(_s32MIOMapFd, MMIO_IOC_SET_MAP, &stMIOMapInfo))
376*53ee8cc1Swenshuai.xi         {
377*53ee8cc1Swenshuai.xi             return FALSE;
378*53ee8cc1Swenshuai.xi         }
379*53ee8cc1Swenshuai.xi         _virtOTP_Bank = (MS_VIRT)mmap(0, stMIOMapInfo.u32Size, PROT_READ | PROT_WRITE, MAP_SHARED, _s32MIOMapFd, 0);
380*53ee8cc1Swenshuai.xi         if ((MS_VIRT)MAP_FAILED == _virtOTP_Bank)
381*53ee8cc1Swenshuai.xi         {
382*53ee8cc1Swenshuai.xi             _virtOTP_Bank = 0x0;
383*53ee8cc1Swenshuai.xi             MS_ASSERT(0);
384*53ee8cc1Swenshuai.xi             return FALSE;
385*53ee8cc1Swenshuai.xi         }
386*53ee8cc1Swenshuai.xi         _u32OTP_BankSize = bank_size;
387*53ee8cc1Swenshuai.xi         MMIO_PRINT("OTP Bank mapping success. Base=[%lx], Size=[%x]\n", (MS_VIRT)_virtOTP_Bank, (MS_PHY)_u32OTP_BankSize);
388*53ee8cc1Swenshuai.xi     }
389*53ee8cc1Swenshuai.xi 
390*53ee8cc1Swenshuai.xi /*    map OTP base for OTP readable area (OTP raw data)   */
391*53ee8cc1Swenshuai.xi     if (HAL_MMIO_GetBase(&bank_addr, &bank_size, DRV_MMIO_OTP_BANK2))
392*53ee8cc1Swenshuai.xi     {
393*53ee8cc1Swenshuai.xi         stMIOMapInfo.virtAddr = bank_addr;
394*53ee8cc1Swenshuai.xi         stMIOMapInfo.u32Size = bank_size;
395*53ee8cc1Swenshuai.xi         if (ioctl(_s32MIOMapFd, MMIO_IOC_SET_MAP, &stMIOMapInfo))
396*53ee8cc1Swenshuai.xi         {
397*53ee8cc1Swenshuai.xi             return FALSE;
398*53ee8cc1Swenshuai.xi         }
399*53ee8cc1Swenshuai.xi         _virtOTP_Bank2 = (MS_VIRT)mmap(0, stMIOMapInfo.u32Size, PROT_READ | PROT_WRITE, MAP_SHARED, _s32MIOMapFd, 0);
400*53ee8cc1Swenshuai.xi         if ((MS_VIRT)MAP_FAILED == _virtOTP_Bank2)
401*53ee8cc1Swenshuai.xi         {
402*53ee8cc1Swenshuai.xi             _virtOTP_Bank2 = 0x0;
403*53ee8cc1Swenshuai.xi             MS_ASSERT(0);
404*53ee8cc1Swenshuai.xi             return FALSE;
405*53ee8cc1Swenshuai.xi         }
406*53ee8cc1Swenshuai.xi         _u32OTP_Bank2Size = bank_size;
407*53ee8cc1Swenshuai.xi //        MMIO_PRINT("OTP Bank RAW mapping success. Base=[%lx], Size=[%x]\n", (MS_VIRT)_u32OTP_Bank2, (MS_PHY)_u32OTP_Bank2Size);
408*53ee8cc1Swenshuai.xi     }
409*53ee8cc1Swenshuai.xi 
410*53ee8cc1Swenshuai.xi     // K2 Only Scratchpad memory/SPRAM
411*53ee8cc1Swenshuai.xi     if (HAL_MMIO_GetBase(&bank_addr, &bank_size, DRV_MMIO_SPRAM_BANK))
412*53ee8cc1Swenshuai.xi     {
413*53ee8cc1Swenshuai.xi         stMIOMapInfo.virtAddr = bank_addr;
414*53ee8cc1Swenshuai.xi         stMIOMapInfo.u32Size = bank_size;
415*53ee8cc1Swenshuai.xi         if (ioctl(_s32MIOMapFd, MMIO_IOC_SET_MAP, &stMIOMapInfo))
416*53ee8cc1Swenshuai.xi         {
417*53ee8cc1Swenshuai.xi             return FALSE;
418*53ee8cc1Swenshuai.xi         }
419*53ee8cc1Swenshuai.xi         _virtSPRAM_Bank = (MS_VIRT)mmap(0, stMIOMapInfo.u32Size, PROT_READ | PROT_WRITE, MAP_SHARED, _s32MIOMapFd, 0);
420*53ee8cc1Swenshuai.xi         if ((MS_VIRT)MAP_FAILED == _virtSPRAM_Bank)
421*53ee8cc1Swenshuai.xi         {
422*53ee8cc1Swenshuai.xi             _virtSPRAM_Bank = 0x0;
423*53ee8cc1Swenshuai.xi             MS_ASSERT(0);
424*53ee8cc1Swenshuai.xi             return FALSE;
425*53ee8cc1Swenshuai.xi         }
426*53ee8cc1Swenshuai.xi         _u32SPRAM_BankSize = bank_size;
427*53ee8cc1Swenshuai.xi         MMIO_PRINT("SPRAM Bank mapping success. Base=[%lx], Size=[%x]\n", (MS_VIRT)_virtSPRAM_Bank, (MS_PHY)_u32SPRAM_BankSize);
428*53ee8cc1Swenshuai.xi     }
429*53ee8cc1Swenshuai.xi 
430*53ee8cc1Swenshuai.xi     // U3 Only
431*53ee8cc1Swenshuai.xi     if (HAL_MMIO_GetBase(&bank_addr, &bank_size, DRV_MMIO_NSK_BANK))
432*53ee8cc1Swenshuai.xi     {
433*53ee8cc1Swenshuai.xi         stMIOMapInfo.virtAddr = bank_addr;
434*53ee8cc1Swenshuai.xi         stMIOMapInfo.u32Size = bank_size;
435*53ee8cc1Swenshuai.xi         if (ioctl(_s32MIOMapFd, MMIO_IOC_SET_MAP, &stMIOMapInfo))
436*53ee8cc1Swenshuai.xi         {
437*53ee8cc1Swenshuai.xi             return FALSE;
438*53ee8cc1Swenshuai.xi         }
439*53ee8cc1Swenshuai.xi         _virtNSK_Bank = (MS_VIRT)mmap(0, stMIOMapInfo.u32Size, PROT_READ | PROT_WRITE, MAP_SHARED, _s32MIOMapFd, 0);
440*53ee8cc1Swenshuai.xi         if ((MS_VIRT)MAP_FAILED == _virtNSK_Bank)
441*53ee8cc1Swenshuai.xi         {
442*53ee8cc1Swenshuai.xi             _virtNSK_Bank = 0x0;
443*53ee8cc1Swenshuai.xi             MS_ASSERT(0);
444*53ee8cc1Swenshuai.xi             return FALSE;
445*53ee8cc1Swenshuai.xi         }
446*53ee8cc1Swenshuai.xi         _u32NSK_BankSize = bank_size;
447*53ee8cc1Swenshuai.xi //        MMIO_PRINT("NSK Bank mapping success. Base=[%lx], Size=[%x]\n", (MS_VIRT)_u32NSK_Bank, (MS_PHY)_u32NSK_BankSize);
448*53ee8cc1Swenshuai.xi     }
449*53ee8cc1Swenshuai.xi 
450*53ee8cc1Swenshuai.xi     return TRUE;
451*53ee8cc1Swenshuai.xi 
452*53ee8cc1Swenshuai.xi }
453*53ee8cc1Swenshuai.xi 
454*53ee8cc1Swenshuai.xi 
MDrv_MMIO_Close(void)455*53ee8cc1Swenshuai.xi MS_BOOL MDrv_MMIO_Close(void)
456*53ee8cc1Swenshuai.xi {
457*53ee8cc1Swenshuai.xi     if (0 > _s32MIOMapFd)
458*53ee8cc1Swenshuai.xi     {
459*53ee8cc1Swenshuai.xi         MMIO_WARN("%s is closed before initiated\n", __FUNCTION__);
460*53ee8cc1Swenshuai.xi         return FALSE;
461*53ee8cc1Swenshuai.xi     }
462*53ee8cc1Swenshuai.xi     munmap((void *)_virtPM_Bank, _u32PM_Bank_SIZE);
463*53ee8cc1Swenshuai.xi     munmap((void *)_virtNonPM_Bank, _u32NonPM_Bank_SIZE );
464*53ee8cc1Swenshuai.xi     munmap((void *)_virtFlash_Bank0, _u32Flash_Bank0_SIZE);
465*53ee8cc1Swenshuai.xi     munmap((void *)_virtFRC_Bank, _u32FRC_Bank_SIZE);
466*53ee8cc1Swenshuai.xi     close(_s32MIOMapFd);
467*53ee8cc1Swenshuai.xi     _s32MIOMapFd = -1;
468*53ee8cc1Swenshuai.xi     return TRUE;
469*53ee8cc1Swenshuai.xi }
470*53ee8cc1Swenshuai.xi 
471*53ee8cc1Swenshuai.xi 
MDrv_MMIO_GetBASE(MS_VIRT * virtBaseaddr,MS_PHY * u32Basesize,MS_U32 u32Module)472*53ee8cc1Swenshuai.xi MS_BOOL MDrv_MMIO_GetBASE(MS_VIRT *virtBaseaddr, MS_PHY *u32Basesize, MS_U32 u32Module)
473*53ee8cc1Swenshuai.xi {
474*53ee8cc1Swenshuai.xi 
475*53ee8cc1Swenshuai.xi     MS_U16              u16Type;
476*53ee8cc1Swenshuai.xi 
477*53ee8cc1Swenshuai.xi     u16Type = HAL_MMIO_GetType(u32Module);
478*53ee8cc1Swenshuai.xi 
479*53ee8cc1Swenshuai.xi     if (u16Type == DRV_MMIO_PM_BANK)
480*53ee8cc1Swenshuai.xi     {
481*53ee8cc1Swenshuai.xi         *virtBaseaddr = _virtPM_Bank;
482*53ee8cc1Swenshuai.xi         *u32Basesize = _u32PM_Bank_SIZE;
483*53ee8cc1Swenshuai.xi         return TRUE ;
484*53ee8cc1Swenshuai.xi     }
485*53ee8cc1Swenshuai.xi     if (u16Type == DRV_MMIO_NONPM_BANK)
486*53ee8cc1Swenshuai.xi     {
487*53ee8cc1Swenshuai.xi         *virtBaseaddr = _virtNonPM_Bank;
488*53ee8cc1Swenshuai.xi         *u32Basesize = _u32NonPM_Bank_SIZE;
489*53ee8cc1Swenshuai.xi         return TRUE ;
490*53ee8cc1Swenshuai.xi     }
491*53ee8cc1Swenshuai.xi     if (u16Type == DRV_MMIO_FLASH_BANK0 )
492*53ee8cc1Swenshuai.xi     {
493*53ee8cc1Swenshuai.xi         *virtBaseaddr = _virtFlash_Bank0;
494*53ee8cc1Swenshuai.xi         *u32Basesize = _u32Flash_Bank0_SIZE;
495*53ee8cc1Swenshuai.xi         return TRUE ;
496*53ee8cc1Swenshuai.xi     }
497*53ee8cc1Swenshuai.xi     if ((u16Type == DRV_MMIO_OTP_BANK) && (_u32OTP_BankSize)) // not support if BankSize = 0
498*53ee8cc1Swenshuai.xi     {
499*53ee8cc1Swenshuai.xi         *virtBaseaddr = _virtOTP_Bank;
500*53ee8cc1Swenshuai.xi         *u32Basesize = _u32OTP_BankSize;
501*53ee8cc1Swenshuai.xi         return TRUE ;
502*53ee8cc1Swenshuai.xi     }
503*53ee8cc1Swenshuai.xi     if ((u16Type == DRV_MMIO_OTP_BANK2) && (_u32OTP_Bank2Size)) // not support if BankSize = 0
504*53ee8cc1Swenshuai.xi     {
505*53ee8cc1Swenshuai.xi         *virtBaseaddr = _virtOTP_Bank2;
506*53ee8cc1Swenshuai.xi         *u32Basesize = _u32OTP_Bank2Size;
507*53ee8cc1Swenshuai.xi         return TRUE ;
508*53ee8cc1Swenshuai.xi     }
509*53ee8cc1Swenshuai.xi     if (((u16Type == DRV_MMIO_SPRAM_BANK) && (_u32SPRAM_BankSize))) // not support if BankSize = 0
510*53ee8cc1Swenshuai.xi     {
511*53ee8cc1Swenshuai.xi         *virtBaseaddr = _virtSPRAM_Bank;
512*53ee8cc1Swenshuai.xi         *u32Basesize = _u32SPRAM_BankSize;
513*53ee8cc1Swenshuai.xi         return TRUE ;
514*53ee8cc1Swenshuai.xi     }
515*53ee8cc1Swenshuai.xi     if (u16Type == DRV_MMIO_FRC_BANK)
516*53ee8cc1Swenshuai.xi     {
517*53ee8cc1Swenshuai.xi         *virtBaseaddr = _virtFRC_Bank;
518*53ee8cc1Swenshuai.xi         *u32Basesize = _u32FRC_Bank_SIZE;
519*53ee8cc1Swenshuai.xi         return TRUE ;
520*53ee8cc1Swenshuai.xi     }
521*53ee8cc1Swenshuai.xi 
522*53ee8cc1Swenshuai.xi     // Particular HW base address
523*53ee8cc1Swenshuai.xi     if (HAL_MMIO_GetIPBase(virtBaseaddr, u16Type))
524*53ee8cc1Swenshuai.xi     {
525*53ee8cc1Swenshuai.xi         *u32Basesize = 0;
526*53ee8cc1Swenshuai.xi         return TRUE;
527*53ee8cc1Swenshuai.xi     }
528*53ee8cc1Swenshuai.xi 
529*53ee8cc1Swenshuai.xi     return FALSE ;
530*53ee8cc1Swenshuai.xi 
531*53ee8cc1Swenshuai.xi }
532*53ee8cc1Swenshuai.xi 
533*53ee8cc1Swenshuai.xi 
534*53ee8cc1Swenshuai.xi #else // #ifdef MSOS_TYPE_LINUX
535*53ee8cc1Swenshuai.xi 
536*53ee8cc1Swenshuai.xi 
537*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
538*53ee8cc1Swenshuai.xi //  Local Variables
539*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
540*53ee8cc1Swenshuai.xi 
541*53ee8cc1Swenshuai.xi 
542*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
543*53ee8cc1Swenshuai.xi //  Debug Functions
544*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
545*53ee8cc1Swenshuai.xi 
546*53ee8cc1Swenshuai.xi 
547*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
548*53ee8cc1Swenshuai.xi //  Local Functions
549*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
550*53ee8cc1Swenshuai.xi 
551*53ee8cc1Swenshuai.xi 
552*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
553*53ee8cc1Swenshuai.xi //  Global Functions
554*53ee8cc1Swenshuai.xi //-------------------------------------------------------------------------------------------------
555*53ee8cc1Swenshuai.xi 
MDrv_MMIO_Init(void)556*53ee8cc1Swenshuai.xi MS_BOOL MDrv_MMIO_Init(void)
557*53ee8cc1Swenshuai.xi {
558*53ee8cc1Swenshuai.xi     // @TODO: remove the getbase code in MMIO_GetBASE?
559*53ee8cc1Swenshuai.xi     HAL_MMIO_GetBase(&_virtPM_Bank,      &_u32PM_Bank_SIZE,      DRV_MMIO_PM_BANK);
560*53ee8cc1Swenshuai.xi     HAL_MMIO_GetBase(&_virtNonPM_Bank,   &_u32NonPM_Bank_SIZE,   DRV_MMIO_NONPM_BANK);
561*53ee8cc1Swenshuai.xi     HAL_MMIO_GetBase(&_virtFlash_Bank0,  &_u32Flash_Bank0_SIZE,  DRV_MMIO_FLASH_BANK0);
562*53ee8cc1Swenshuai.xi     HAL_MMIO_GetBase(&_virtOTP_Bank,     &_u32OTP_BankSize,      DRV_MMIO_OTP_BANK); // query DRV_MMIO capability to HAL
563*53ee8cc1Swenshuai.xi     HAL_MMIO_GetBase(&_virtOTP_Bank2,    &_u32OTP_Bank2Size,     DRV_MMIO_OTP_BANK2); // query DRV_MMIO capability to HAL
564*53ee8cc1Swenshuai.xi     HAL_MMIO_GetBase(&_virtSPRAM_Bank,     &_u32SPRAM_BankSize,      DRV_MMIO_SPRAM_BANK);
565*53ee8cc1Swenshuai.xi     HAL_MMIO_GetBase(&_virtFRC_Bank,   &_u32FRC_Bank_SIZE,   DRV_MMIO_FRC_BANK);
566*53ee8cc1Swenshuai.xi 
567*53ee8cc1Swenshuai.xi     // U3 Only
568*53ee8cc1Swenshuai.xi     HAL_MMIO_GetBase(&_virtNSK_Bank,     &_u32NSK_BankSize,      DRV_MMIO_NSK_BANK); // U3 Only
569*53ee8cc1Swenshuai.xi 
570*53ee8cc1Swenshuai.xi     return TRUE;
571*53ee8cc1Swenshuai.xi 
572*53ee8cc1Swenshuai.xi }
573*53ee8cc1Swenshuai.xi #if defined(MSOS_TYPE_LINUX_KERNEL)
574*53ee8cc1Swenshuai.xi EXPORT_SYMBOL(MDrv_MMIO_Init);
575*53ee8cc1Swenshuai.xi #endif
576*53ee8cc1Swenshuai.xi 
577*53ee8cc1Swenshuai.xi 
578*53ee8cc1Swenshuai.xi 
MDrv_MMIO_Close(void)579*53ee8cc1Swenshuai.xi MS_BOOL MDrv_MMIO_Close(void)
580*53ee8cc1Swenshuai.xi {
581*53ee8cc1Swenshuai.xi     return TRUE;
582*53ee8cc1Swenshuai.xi }
583*53ee8cc1Swenshuai.xi 
584*53ee8cc1Swenshuai.xi 
MDrv_MMIO_GetBASE(MS_VIRT * virtBaseaddr,MS_PHY * u32Basesize,MS_U32 u32Module)585*53ee8cc1Swenshuai.xi MS_BOOL MDrv_MMIO_GetBASE(MS_VIRT *virtBaseaddr, MS_PHY *u32Basesize, MS_U32 u32Module)
586*53ee8cc1Swenshuai.xi {
587*53ee8cc1Swenshuai.xi 
588*53ee8cc1Swenshuai.xi     MS_BOOL             bRet;
589*53ee8cc1Swenshuai.xi     MS_U16              u16Type;
590*53ee8cc1Swenshuai.xi 	MS_PHY virtBasetemp = 0;
591*53ee8cc1Swenshuai.xi 	MS_PHY pu32Basetemp = 0;
592*53ee8cc1Swenshuai.xi 
593*53ee8cc1Swenshuai.xi     u16Type = HAL_MMIO_GetType(u32Module);
594*53ee8cc1Swenshuai.xi 
595*53ee8cc1Swenshuai.xi     // @TODO: Leave only in MMIO_Init?
596*53ee8cc1Swenshuai.xi     switch (u16Type)
597*53ee8cc1Swenshuai.xi     {
598*53ee8cc1Swenshuai.xi     case DRV_MMIO_PM_BANK:
599*53ee8cc1Swenshuai.xi 		bRet = HAL_MMIO_GetBase(&virtBasetemp, &pu32Basetemp, DRV_MMIO_PM_BANK);
600*53ee8cc1Swenshuai.xi 		*virtBaseaddr = virtBasetemp;
601*53ee8cc1Swenshuai.xi 		*u32Basesize = pu32Basetemp;
602*53ee8cc1Swenshuai.xi         break;
603*53ee8cc1Swenshuai.xi     case DRV_MMIO_NONPM_BANK:
604*53ee8cc1Swenshuai.xi 		bRet = HAL_MMIO_GetBase(&virtBasetemp, &pu32Basetemp, DRV_MMIO_NONPM_BANK);
605*53ee8cc1Swenshuai.xi 		*virtBaseaddr = virtBasetemp;
606*53ee8cc1Swenshuai.xi 		*u32Basesize = pu32Basetemp;
607*53ee8cc1Swenshuai.xi         break;
608*53ee8cc1Swenshuai.xi     case DRV_MMIO_FLASH_BANK0:
609*53ee8cc1Swenshuai.xi 		bRet = HAL_MMIO_GetBase(&virtBasetemp, &pu32Basetemp, DRV_MMIO_FLASH_BANK0);
610*53ee8cc1Swenshuai.xi 		*virtBaseaddr = virtBasetemp;
611*53ee8cc1Swenshuai.xi 		*u32Basesize = pu32Basetemp;
612*53ee8cc1Swenshuai.xi         break;
613*53ee8cc1Swenshuai.xi     case DRV_MMIO_OTP_BANK:
614*53ee8cc1Swenshuai.xi 		bRet = HAL_MMIO_GetBase(&virtBasetemp, &pu32Basetemp, DRV_MMIO_OTP_BANK); // query DRV_MMIO capability to HAL
615*53ee8cc1Swenshuai.xi 		*virtBaseaddr = virtBasetemp;
616*53ee8cc1Swenshuai.xi 		*u32Basesize = pu32Basetemp;
617*53ee8cc1Swenshuai.xi         break;
618*53ee8cc1Swenshuai.xi     case DRV_MMIO_OTP_BANK2:
619*53ee8cc1Swenshuai.xi 		bRet = HAL_MMIO_GetBase(&virtBasetemp, &pu32Basetemp, DRV_MMIO_OTP_BANK2); // query DRV_MMIO capability to HAL
620*53ee8cc1Swenshuai.xi 		*virtBaseaddr = virtBasetemp;
621*53ee8cc1Swenshuai.xi 		*u32Basesize = pu32Basetemp;
622*53ee8cc1Swenshuai.xi         break;
623*53ee8cc1Swenshuai.xi     case DRV_MMIO_SPRAM_BANK:
624*53ee8cc1Swenshuai.xi 		bRet = HAL_MMIO_GetBase(&virtBasetemp, &pu32Basetemp, DRV_MMIO_SPRAM_BANK); // query DRV_MMIO capability to HAL
625*53ee8cc1Swenshuai.xi 		*virtBaseaddr = virtBasetemp;
626*53ee8cc1Swenshuai.xi 		*u32Basesize = pu32Basetemp;
627*53ee8cc1Swenshuai.xi         break;
628*53ee8cc1Swenshuai.xi     case DRV_MMIO_FRC_BANK:
629*53ee8cc1Swenshuai.xi 		bRet = HAL_MMIO_GetBase(&virtBasetemp, &pu32Basetemp, DRV_MMIO_FRC_BANK);
630*53ee8cc1Swenshuai.xi 		*virtBaseaddr = virtBasetemp;
631*53ee8cc1Swenshuai.xi 		*u32Basesize = pu32Basetemp;
632*53ee8cc1Swenshuai.xi         break;
633*53ee8cc1Swenshuai.xi     default:
634*53ee8cc1Swenshuai.xi         bRet = FALSE;
635*53ee8cc1Swenshuai.xi         break;
636*53ee8cc1Swenshuai.xi     }
637*53ee8cc1Swenshuai.xi 
638*53ee8cc1Swenshuai.xi     // specific HW base address
639*53ee8cc1Swenshuai.xi     if (bRet == FALSE)
640*53ee8cc1Swenshuai.xi     {
641*53ee8cc1Swenshuai.xi         bRet = HAL_MMIO_GetIPBase((MS_VIRT*)virtBaseaddr, u16Type);
642*53ee8cc1Swenshuai.xi     }
643*53ee8cc1Swenshuai.xi 
644*53ee8cc1Swenshuai.xi     return bRet;
645*53ee8cc1Swenshuai.xi 
646*53ee8cc1Swenshuai.xi }
647*53ee8cc1Swenshuai.xi 
648*53ee8cc1Swenshuai.xi #endif
649