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77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
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93 ////////////////////////////////////////////////////////////////////////////////
94
95 ///////////////////////////////////////////////////////////////////////////////////////////////////
96 ///
97 /// file drvMMIO.c
98 /// @brief MMIO SYS Driver Interface
99 /// @author MStar Semiconductor Inc.
100 ///////////////////////////////////////////////////////////////////////////////////////////////////
101
102
103 //-------------------------------------------------------------------------------------------------
104 // Include Files
105 //-------------------------------------------------------------------------------------------------
106
107 #ifdef MSOS_TYPE_LINUX
108
109 #include <unistd.h>
110 #include <fcntl.h>
111 #include <sys/ioctl.h>
112 #include <sys/mman.h>
113 #include "MsCommon.h"
114 #include "drvMMIO.h"
115 #include "halMMIO.h"
116 #include "regCHIP.h"
117
118 /* Use 'I' as magic number */
119 #define MIOMAP_IOC_MAGIC 'I'
120 #define MMIO_IOC_SET_MAP _IOW (MIOMAP_IOC_MAGIC, 0x01, MIOMap_Info_t)
121
122 /* MIOMAP_IOC_INFO */
123 typedef struct
124 {
125 MS_U64 virtAddr;
126 MS_U64 u32Size;
127 } MIOMap_Info_t;
128
129 #else // #ifdef MSOS_TYPE_LINUX
130
131 #include "MsCommon.h"
132 #include "drvMMIO.h"
133 #include "halMMIO.h"
134 #include "regCHIP.h"
135
136 #endif
137 #include "MsVersion.h"
138 #include "ULog.h"
139 //-------------------------------------------------------------------------------------------------
140 // Driver Compiler Options
141 //-------------------------------------------------------------------------------------------------
142 #ifdef MS_DEBUG
143 #define MMIO_DEBUG
144 #endif
145
146
147 //-------------------------------------------------------------------------------------------------
148 // Local Defines
149 //-------------------------------------------------------------------------------------------------
150 #ifdef MMIO_DEBUG
151 #define MMIO_ERROR(fmt, args...) MS_DEBUG_MSG(ULOGE("MMIO","[%06d] " fmt, __LINE__, ##args))
152 #define MMIO_WARN(fmt, args...) MS_DEBUG_MSG(ULOGW("MMIO","[%06d] " fmt, __LINE__, ##args))
153 #define MMIO_PRINT(fmt, args...) MS_DEBUG_MSG(ULOGI("MMIO", "[%06d] " fmt, __LINE__, ##args))
154 #define MMIO_ASSERT(_bool, _f) if (!(_bool)) { MS_DEBUG_MSG(ULOGF("MMIO",_f)); MS_ASSERT(0);) }
155 #else
156 #define MMIO_ERROR(fmt, args...) MS_DEBUG_MSG(while (0))
157 #define MMIO_WARN(fmt, args...) MS_DEBUG_MSG(while (0))
158 #define MMIO_PRINT(fmt, args...) MS_DEBUG_MSG(while (0))
159 #define MMIO_ASSERT(_bool, _f) if (!(_bool)) { MS_DEBUG_MSG((_f)); }
160 #endif
161
162
163 //-------------------------------------------------------------------------------------------------
164 // Local Structurs
165 //-------------------------------------------------------------------------------------------------
166
167
168 //-------------------------------------------------------------------------------------------------
169 // Global Variables
170 //-------------------------------------------------------------------------------------------------
171 #ifdef MSOS_TYPE_LINUX
172 MS_VIRT _virtPM_Bank = 0x0 ;
173 MS_PHY _u32PM_Bank_SIZE = 0x0 ;
174 MS_VIRT _virtNonPM_Bank = 0x0 ;
175 MS_PHY _u32NonPM_Bank_SIZE = 0x0 ;
176 MS_VIRT _virtFlash_Bank0 = 0x0 ;
177 MS_PHY _u32Flash_Bank0_SIZE = 0x0 ;
178 MS_VIRT _virtOTP_Bank = 0x0 ;
179 MS_PHY _u32OTP_BankSize = 0x0 ;
180 MS_VIRT _virtOTP_Bank2 = 0x0 ; //OTP raw data area
181 MS_PHY _u32OTP_Bank2Size = 0x0 ;
182
183 MS_VIRT _virtFRC_Bank = 0x0 ;
184 MS_PHY _u32FRC_Bank_SIZE = 0x0 ;
185
186 MS_VIRT _virtNSK_Bank = 0x0 ; // U3 Only
187 MS_PHY _u32NSK_BankSize = 0x0 ;
188
189 MS_VIRT _virtSPRAM_Bank = 0x0 ; // Scratchpad memory K2 Only
190 MS_PHY _u32SPRAM_BankSize = 0x0 ;
191 #else
192 MS_PHY _virtPM_Bank = 0x0 ;
193 MS_PHY _u32PM_Bank_SIZE = 0x0 ;
194 MS_PHY _virtNonPM_Bank = 0x0 ;
195 MS_PHY _u32NonPM_Bank_SIZE = 0x0 ;
196 MS_PHY _virtFlash_Bank0 = 0x0 ;
197 MS_PHY _u32Flash_Bank0_SIZE = 0x0 ;
198 MS_PHY _virtOTP_Bank = 0x0 ;
199 MS_PHY _u32OTP_BankSize = 0x0 ;
200 MS_PHY _virtOTP_Bank2 = 0x0 ; //OTP raw data area
201 MS_PHY _u32OTP_Bank2Size = 0x0 ;
202
203 MS_PHY _virtFRC_Bank = 0x0 ;
204 MS_PHY _u32FRC_Bank_SIZE = 0x0 ;
205
206 MS_PHY _virtNSK_Bank = 0x0 ; // U3 Only
207 MS_PHY _u32NSK_BankSize = 0x0 ;
208
209 MS_PHY _virtSPRAM_Bank = 0x0 ; // Scratchpad memory K2 Only
210 MS_PHY _u32SPRAM_BankSize = 0x0 ;
211
212 #endif
213 static MSIF_Version _drv_mmio_version = {
214 .DDI = { MMIO_DRV_VERSION },
215 };
216 ////////////////////////////////////////////////////////////////////////////////
217 /// @brief \b Function \b Name: MDrv_MSOS_GetLibVer
218 /// @brief \b Function \b Description: Show the MSOS driver version
219 /// @param ppVersion \b Out: Library version string
220 /// @return \b Result
221 ////////////////////////////////////////////////////////////////////////////////
MDrv_MMIO_GetLibVer(const MSIF_Version ** ppVersion)222 MS_BOOL MDrv_MMIO_GetLibVer(const MSIF_Version **ppVersion)
223 {
224 if (!ppVersion)
225 return FALSE;
226
227 *ppVersion = &_drv_mmio_version;
228 return TRUE;
229 }
230
231 #ifdef MSOS_TYPE_LINUX
232
233 //-------------------------------------------------------------------------------------------------
234 // Local Variables
235 //-------------------------------------------------------------------------------------------------
236 static MS_S32 _s32MIOMapFd = -1;
237
238
239 //-------------------------------------------------------------------------------------------------
240 // Debug Functions
241 //-------------------------------------------------------------------------------------------------
242
243
244 //-------------------------------------------------------------------------------------------------
245 // Local Functions
246 //-------------------------------------------------------------------------------------------------
247
248
249 //-------------------------------------------------------------------------------------------------
250 // Global Functions
251 //-------------------------------------------------------------------------------------------------
252
MDrv_MMIO_Init(void)253 MS_BOOL MDrv_MMIO_Init(void)
254 {
255 MIOMap_Info_t stMIOMapInfo;
256
257 MS_PHY PM_Bank ;
258 MS_PHY PM_Bank_SIZE ;
259 MS_PHY NonPM_Bank ;
260 MS_PHY NonPM_Bank_SIZE ;
261 MS_PHY Flash_Bank0 ;
262 MS_PHY Flash_Bank0_SIZE ;
263 MS_PHY FRC_Bank ;
264 MS_PHY FRC_Bank_SIZE ;
265 MS_PHY bank_addr = 0;
266 MS_PHY bank_size = 0;
267
268 if (0 <= _s32MIOMapFd)
269 {
270 MMIO_WARN("%s is initiated more than once\n", __FUNCTION__);
271 return FALSE;
272 }
273
274 if (0 > (_s32MIOMapFd = open("/dev/miomap", O_RDWR)))
275 {
276 MMIO_ERROR("Open /dev/miomap fail\n");
277 MS_ASSERT(0);
278 return FALSE;
279 }
280
281
282 if (FALSE == HAL_MMIO_GetBase(&PM_Bank, &PM_Bank_SIZE, DRV_MMIO_PM_BANK))
283 {
284 MS_ASSERT(0);
285 }
286 if (FALSE == HAL_MMIO_GetBase(&NonPM_Bank, &NonPM_Bank_SIZE, DRV_MMIO_NONPM_BANK))
287 {
288 MS_ASSERT(0);
289 }
290 if (FALSE == HAL_MMIO_GetBase(&Flash_Bank0, &Flash_Bank0_SIZE, DRV_MMIO_FLASH_BANK0))
291 {
292 MS_ASSERT(0);
293 }
294
295 if (FALSE == HAL_MMIO_GetBase(&FRC_Bank, &FRC_Bank_SIZE, DRV_MMIO_FRC_BANK))
296 {
297 MS_ASSERT(0);
298 }
299
300 if (PM_Bank_SIZE)
301 {
302 stMIOMapInfo.virtAddr = PM_Bank ;
303 stMIOMapInfo.u32Size = PM_Bank_SIZE ;
304 if (ioctl(_s32MIOMapFd, MMIO_IOC_SET_MAP , &stMIOMapInfo))
305 {
306 return FALSE;
307 }
308 if ((MS_VIRT)MAP_FAILED == (_virtPM_Bank= (MS_VIRT)mmap(0, stMIOMapInfo.u32Size, PROT_READ| PROT_WRITE, MAP_SHARED, _s32MIOMapFd, 0)))
309 {
310 MS_ASSERT(0);
311 return FALSE;
312 }
313 _u32PM_Bank_SIZE = PM_Bank_SIZE ;
314 MMIO_PRINT("PM Bank mapping success. Base=[%lx], Size=[%x]\n", (MS_VIRT)_virtPM_Bank, (MS_PHY)_u32PM_Bank_SIZE);
315 }
316
317 if (NonPM_Bank_SIZE)
318 {
319 stMIOMapInfo.virtAddr = NonPM_Bank ;
320 stMIOMapInfo.u32Size = NonPM_Bank_SIZE ;
321 if (ioctl(_s32MIOMapFd, MMIO_IOC_SET_MAP , &stMIOMapInfo))
322 {
323 return FALSE;
324 }
325 if ((MS_VIRT)MAP_FAILED == (_virtNonPM_Bank= (MS_VIRT)mmap(0, stMIOMapInfo.u32Size, PROT_READ| PROT_WRITE, MAP_SHARED, _s32MIOMapFd, 0)))
326 {
327 MS_ASSERT(0);
328 return FALSE;
329 }
330 _u32NonPM_Bank_SIZE = NonPM_Bank_SIZE ;
331 MMIO_PRINT("NonPM Bank mapping success. Base=[%lx], Size=[%x]\n",(MS_VIRT) _virtNonPM_Bank, (MS_PHY)_u32NonPM_Bank_SIZE);
332 }
333
334 if (Flash_Bank0_SIZE)
335 {
336 stMIOMapInfo.virtAddr = Flash_Bank0 ;
337 stMIOMapInfo.u32Size = Flash_Bank0_SIZE ;
338 if (ioctl(_s32MIOMapFd, MMIO_IOC_SET_MAP , &stMIOMapInfo))
339 {
340 return FALSE;
341 }
342 if ((MS_VIRT)MAP_FAILED == (_virtFlash_Bank0= (MS_VIRT)mmap(0, stMIOMapInfo.u32Size, PROT_READ| PROT_WRITE, MAP_SHARED, _s32MIOMapFd, 0)))
343 {
344 MS_ASSERT(0);
345 return FALSE;
346 }
347 _u32Flash_Bank0_SIZE = Flash_Bank0_SIZE ;
348 MMIO_PRINT("Flash Bank0 mapping success. Base=[%lx], Size=[%x]\n", (MS_PHY)_virtFlash_Bank0, (MS_PHY)_u32Flash_Bank0_SIZE);
349 }
350
351 if (FRC_Bank_SIZE)
352 {
353 stMIOMapInfo.virtAddr = FRC_Bank ;
354 stMIOMapInfo.u32Size = FRC_Bank_SIZE ;
355 if (ioctl(_s32MIOMapFd, MMIO_IOC_SET_MAP , &stMIOMapInfo))
356 {
357 return FALSE;
358 }
359 if ((MS_VIRT)MAP_FAILED == (_virtFRC_Bank= (MS_VIRT)mmap(0, stMIOMapInfo.u32Size, PROT_READ| PROT_WRITE, MAP_SHARED, _s32MIOMapFd, 0)))
360 {
361 MS_ASSERT(0);
362 return FALSE;
363 }
364 _u32FRC_Bank_SIZE = FRC_Bank_SIZE ;
365 MMIO_PRINT("FRC Bank mapping success. Base=[%lx], Size=[%x]\n",(MS_VIRT) _virtFRC_Bank, (MS_PHY)_u32FRC_Bank_SIZE);
366 }
367 /*
368 Not every chip support OTP / NSK, the return value of MMIO_GetBase could be FALSE
369 */
370
371 if (HAL_MMIO_GetBase(&bank_addr, &bank_size, DRV_MMIO_OTP_BANK))
372 {
373 stMIOMapInfo.virtAddr = bank_addr;
374 stMIOMapInfo.u32Size = bank_size;
375 if (ioctl(_s32MIOMapFd, MMIO_IOC_SET_MAP, &stMIOMapInfo))
376 {
377 return FALSE;
378 }
379 _virtOTP_Bank = (MS_VIRT)mmap(0, stMIOMapInfo.u32Size, PROT_READ | PROT_WRITE, MAP_SHARED, _s32MIOMapFd, 0);
380 if ((MS_VIRT)MAP_FAILED == _virtOTP_Bank)
381 {
382 _virtOTP_Bank = 0x0;
383 MS_ASSERT(0);
384 return FALSE;
385 }
386 _u32OTP_BankSize = bank_size;
387 MMIO_PRINT("OTP Bank mapping success. Base=[%lx], Size=[%x]\n", (MS_VIRT)_virtOTP_Bank, (MS_PHY)_u32OTP_BankSize);
388 }
389
390 /* map OTP base for OTP readable area (OTP raw data) */
391 if (HAL_MMIO_GetBase(&bank_addr, &bank_size, DRV_MMIO_OTP_BANK2))
392 {
393 stMIOMapInfo.virtAddr = bank_addr;
394 stMIOMapInfo.u32Size = bank_size;
395 if (ioctl(_s32MIOMapFd, MMIO_IOC_SET_MAP, &stMIOMapInfo))
396 {
397 return FALSE;
398 }
399 _virtOTP_Bank2 = (MS_VIRT)mmap(0, stMIOMapInfo.u32Size, PROT_READ | PROT_WRITE, MAP_SHARED, _s32MIOMapFd, 0);
400 if ((MS_VIRT)MAP_FAILED == _virtOTP_Bank2)
401 {
402 _virtOTP_Bank2 = 0x0;
403 MS_ASSERT(0);
404 return FALSE;
405 }
406 _u32OTP_Bank2Size = bank_size;
407 // MMIO_PRINT("OTP Bank RAW mapping success. Base=[%lx], Size=[%x]\n", (MS_VIRT)_u32OTP_Bank2, (MS_PHY)_u32OTP_Bank2Size);
408 }
409
410 // K2 Only Scratchpad memory/SPRAM
411 if (HAL_MMIO_GetBase(&bank_addr, &bank_size, DRV_MMIO_SPRAM_BANK))
412 {
413 stMIOMapInfo.virtAddr = bank_addr;
414 stMIOMapInfo.u32Size = bank_size;
415 if (ioctl(_s32MIOMapFd, MMIO_IOC_SET_MAP, &stMIOMapInfo))
416 {
417 return FALSE;
418 }
419 _virtSPRAM_Bank = (MS_VIRT)mmap(0, stMIOMapInfo.u32Size, PROT_READ | PROT_WRITE, MAP_SHARED, _s32MIOMapFd, 0);
420 if ((MS_VIRT)MAP_FAILED == _virtSPRAM_Bank)
421 {
422 _virtSPRAM_Bank = 0x0;
423 MS_ASSERT(0);
424 return FALSE;
425 }
426 _u32SPRAM_BankSize = bank_size;
427 MMIO_PRINT("SPRAM Bank mapping success. Base=[%lx], Size=[%x]\n", (MS_VIRT)_virtSPRAM_Bank, (MS_PHY)_u32SPRAM_BankSize);
428 }
429
430 // U3 Only
431 if (HAL_MMIO_GetBase(&bank_addr, &bank_size, DRV_MMIO_NSK_BANK))
432 {
433 stMIOMapInfo.virtAddr = bank_addr;
434 stMIOMapInfo.u32Size = bank_size;
435 if (ioctl(_s32MIOMapFd, MMIO_IOC_SET_MAP, &stMIOMapInfo))
436 {
437 return FALSE;
438 }
439 _virtNSK_Bank = (MS_VIRT)mmap(0, stMIOMapInfo.u32Size, PROT_READ | PROT_WRITE, MAP_SHARED, _s32MIOMapFd, 0);
440 if ((MS_VIRT)MAP_FAILED == _virtNSK_Bank)
441 {
442 _virtNSK_Bank = 0x0;
443 MS_ASSERT(0);
444 return FALSE;
445 }
446 _u32NSK_BankSize = bank_size;
447 // MMIO_PRINT("NSK Bank mapping success. Base=[%lx], Size=[%x]\n", (MS_VIRT)_u32NSK_Bank, (MS_PHY)_u32NSK_BankSize);
448 }
449
450 return TRUE;
451
452 }
453
454
MDrv_MMIO_Close(void)455 MS_BOOL MDrv_MMIO_Close(void)
456 {
457 if (0 > _s32MIOMapFd)
458 {
459 MMIO_WARN("%s is closed before initiated\n", __FUNCTION__);
460 return FALSE;
461 }
462 munmap((void *)_virtPM_Bank, _u32PM_Bank_SIZE);
463 munmap((void *)_virtNonPM_Bank, _u32NonPM_Bank_SIZE );
464 munmap((void *)_virtFlash_Bank0, _u32Flash_Bank0_SIZE);
465 munmap((void *)_virtFRC_Bank, _u32FRC_Bank_SIZE);
466 close(_s32MIOMapFd);
467 _s32MIOMapFd = -1;
468 return TRUE;
469 }
470
471
MDrv_MMIO_GetBASE(MS_VIRT * virtBaseaddr,MS_PHY * u32Basesize,MS_U32 u32Module)472 MS_BOOL MDrv_MMIO_GetBASE(MS_VIRT *virtBaseaddr, MS_PHY *u32Basesize, MS_U32 u32Module)
473 {
474
475 MS_U16 u16Type;
476
477 u16Type = HAL_MMIO_GetType(u32Module);
478
479 if (u16Type == DRV_MMIO_PM_BANK)
480 {
481 *virtBaseaddr = _virtPM_Bank;
482 *u32Basesize = _u32PM_Bank_SIZE;
483 return TRUE ;
484 }
485 if (u16Type == DRV_MMIO_NONPM_BANK)
486 {
487 *virtBaseaddr = _virtNonPM_Bank;
488 *u32Basesize = _u32NonPM_Bank_SIZE;
489 return TRUE ;
490 }
491 if (u16Type == DRV_MMIO_FLASH_BANK0 )
492 {
493 *virtBaseaddr = _virtFlash_Bank0;
494 *u32Basesize = _u32Flash_Bank0_SIZE;
495 return TRUE ;
496 }
497 if ((u16Type == DRV_MMIO_OTP_BANK) && (_u32OTP_BankSize)) // not support if BankSize = 0
498 {
499 *virtBaseaddr = _virtOTP_Bank;
500 *u32Basesize = _u32OTP_BankSize;
501 return TRUE ;
502 }
503 if ((u16Type == DRV_MMIO_OTP_BANK2) && (_u32OTP_Bank2Size)) // not support if BankSize = 0
504 {
505 *virtBaseaddr = _virtOTP_Bank2;
506 *u32Basesize = _u32OTP_Bank2Size;
507 return TRUE ;
508 }
509 if (((u16Type == DRV_MMIO_SPRAM_BANK) && (_u32SPRAM_BankSize))) // not support if BankSize = 0
510 {
511 *virtBaseaddr = _virtSPRAM_Bank;
512 *u32Basesize = _u32SPRAM_BankSize;
513 return TRUE ;
514 }
515 if (u16Type == DRV_MMIO_FRC_BANK)
516 {
517 *virtBaseaddr = _virtFRC_Bank;
518 *u32Basesize = _u32FRC_Bank_SIZE;
519 return TRUE ;
520 }
521
522 // Particular HW base address
523 if (HAL_MMIO_GetIPBase(virtBaseaddr, u16Type))
524 {
525 *u32Basesize = 0;
526 return TRUE;
527 }
528
529 return FALSE ;
530
531 }
532
533
534 #else // #ifdef MSOS_TYPE_LINUX
535
536
537 //-------------------------------------------------------------------------------------------------
538 // Local Variables
539 //-------------------------------------------------------------------------------------------------
540
541
542 //-------------------------------------------------------------------------------------------------
543 // Debug Functions
544 //-------------------------------------------------------------------------------------------------
545
546
547 //-------------------------------------------------------------------------------------------------
548 // Local Functions
549 //-------------------------------------------------------------------------------------------------
550
551
552 //-------------------------------------------------------------------------------------------------
553 // Global Functions
554 //-------------------------------------------------------------------------------------------------
555
MDrv_MMIO_Init(void)556 MS_BOOL MDrv_MMIO_Init(void)
557 {
558 // @TODO: remove the getbase code in MMIO_GetBASE?
559 HAL_MMIO_GetBase(&_virtPM_Bank, &_u32PM_Bank_SIZE, DRV_MMIO_PM_BANK);
560 HAL_MMIO_GetBase(&_virtNonPM_Bank, &_u32NonPM_Bank_SIZE, DRV_MMIO_NONPM_BANK);
561 HAL_MMIO_GetBase(&_virtFlash_Bank0, &_u32Flash_Bank0_SIZE, DRV_MMIO_FLASH_BANK0);
562 HAL_MMIO_GetBase(&_virtOTP_Bank, &_u32OTP_BankSize, DRV_MMIO_OTP_BANK); // query DRV_MMIO capability to HAL
563 HAL_MMIO_GetBase(&_virtOTP_Bank2, &_u32OTP_Bank2Size, DRV_MMIO_OTP_BANK2); // query DRV_MMIO capability to HAL
564 HAL_MMIO_GetBase(&_virtSPRAM_Bank, &_u32SPRAM_BankSize, DRV_MMIO_SPRAM_BANK);
565 HAL_MMIO_GetBase(&_virtFRC_Bank, &_u32FRC_Bank_SIZE, DRV_MMIO_FRC_BANK);
566
567 // U3 Only
568 HAL_MMIO_GetBase(&_virtNSK_Bank, &_u32NSK_BankSize, DRV_MMIO_NSK_BANK); // U3 Only
569
570 return TRUE;
571
572 }
573 #if defined(MSOS_TYPE_LINUX_KERNEL)
574 EXPORT_SYMBOL(MDrv_MMIO_Init);
575 #endif
576
577
578
MDrv_MMIO_Close(void)579 MS_BOOL MDrv_MMIO_Close(void)
580 {
581 return TRUE;
582 }
583
584
MDrv_MMIO_GetBASE(MS_VIRT * virtBaseaddr,MS_PHY * u32Basesize,MS_U32 u32Module)585 MS_BOOL MDrv_MMIO_GetBASE(MS_VIRT *virtBaseaddr, MS_PHY *u32Basesize, MS_U32 u32Module)
586 {
587
588 MS_BOOL bRet;
589 MS_U16 u16Type;
590 MS_PHY virtBasetemp = 0;
591 MS_PHY pu32Basetemp = 0;
592
593 u16Type = HAL_MMIO_GetType(u32Module);
594
595 // @TODO: Leave only in MMIO_Init?
596 switch (u16Type)
597 {
598 case DRV_MMIO_PM_BANK:
599 bRet = HAL_MMIO_GetBase(&virtBasetemp, &pu32Basetemp, DRV_MMIO_PM_BANK);
600 *virtBaseaddr = virtBasetemp;
601 *u32Basesize = pu32Basetemp;
602 break;
603 case DRV_MMIO_NONPM_BANK:
604 bRet = HAL_MMIO_GetBase(&virtBasetemp, &pu32Basetemp, DRV_MMIO_NONPM_BANK);
605 *virtBaseaddr = virtBasetemp;
606 *u32Basesize = pu32Basetemp;
607 break;
608 case DRV_MMIO_FLASH_BANK0:
609 bRet = HAL_MMIO_GetBase(&virtBasetemp, &pu32Basetemp, DRV_MMIO_FLASH_BANK0);
610 *virtBaseaddr = virtBasetemp;
611 *u32Basesize = pu32Basetemp;
612 break;
613 case DRV_MMIO_OTP_BANK:
614 bRet = HAL_MMIO_GetBase(&virtBasetemp, &pu32Basetemp, DRV_MMIO_OTP_BANK); // query DRV_MMIO capability to HAL
615 *virtBaseaddr = virtBasetemp;
616 *u32Basesize = pu32Basetemp;
617 break;
618 case DRV_MMIO_OTP_BANK2:
619 bRet = HAL_MMIO_GetBase(&virtBasetemp, &pu32Basetemp, DRV_MMIO_OTP_BANK2); // query DRV_MMIO capability to HAL
620 *virtBaseaddr = virtBasetemp;
621 *u32Basesize = pu32Basetemp;
622 break;
623 case DRV_MMIO_SPRAM_BANK:
624 bRet = HAL_MMIO_GetBase(&virtBasetemp, &pu32Basetemp, DRV_MMIO_SPRAM_BANK); // query DRV_MMIO capability to HAL
625 *virtBaseaddr = virtBasetemp;
626 *u32Basesize = pu32Basetemp;
627 break;
628 case DRV_MMIO_FRC_BANK:
629 bRet = HAL_MMIO_GetBase(&virtBasetemp, &pu32Basetemp, DRV_MMIO_FRC_BANK);
630 *virtBaseaddr = virtBasetemp;
631 *u32Basesize = pu32Basetemp;
632 break;
633 default:
634 bRet = FALSE;
635 break;
636 }
637
638 // specific HW base address
639 if (bRet == FALSE)
640 {
641 bRet = HAL_MMIO_GetIPBase((MS_VIRT*)virtBaseaddr, u16Type);
642 }
643
644 return bRet;
645
646 }
647
648 #endif
649