1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved.
5 // All software, firmware and related documentation herein ("MStar Software") are
6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by
7 // law, including, but not limited to, copyright law and international treaties.
8 // Any use, modification, reproduction, retransmission, or republication of all
9 // or part of MStar Software is expressly prohibited, unless prior written
10 // permission has been granted by MStar.
11 //
12 // By accessing, browsing and/or using MStar Software, you acknowledge that you
13 // have read, understood, and agree, to be bound by below terms ("Terms") and to
14 // comply with all applicable laws and regulations:
15 //
16 // 1. MStar shall retain any and all right, ownership and interest to MStar
17 // Software and any modification/derivatives thereof.
18 // No right, ownership, or interest to MStar Software and any
19 // modification/derivatives thereof is transferred to you under Terms.
20 //
21 // 2. You understand that MStar Software might include, incorporate or be
22 // supplied together with third party`s software and the use of MStar
23 // Software may require additional licenses from third parties.
24 // Therefore, you hereby agree it is your sole responsibility to separately
25 // obtain any and all third party right and license necessary for your use of
26 // such third party`s software.
27 //
28 // 3. MStar Software and any modification/derivatives thereof shall be deemed as
29 // MStar`s confidential information and you agree to keep MStar`s
30 // confidential information in strictest confidence and not disclose to any
31 // third party.
32 //
33 // 4. MStar Software is provided on an "AS IS" basis without warranties of any
34 // kind. Any warranties are hereby expressly disclaimed by MStar, including
35 // without limitation, any warranties of merchantability, non-infringement of
36 // intellectual property rights, fitness for a particular purpose, error free
37 // and in conformity with any international standard. You agree to waive any
38 // claim against MStar for any loss, damage, cost or expense that you may
39 // incur related to your use of MStar Software.
40 // In no event shall MStar be liable for any direct, indirect, incidental or
41 // consequential damages, including without limitation, lost of profit or
42 // revenues, lost or damage of data, and unauthorized system use.
43 // You agree that this Section 4 shall still apply without being affected
44 // even if MStar Software has been modified by MStar in accordance with your
45 // request or instruction for your use, except otherwise agreed by both
46 // parties in writing.
47 //
48 // 5. If requested, MStar may from time to time provide technical supports or
49 // services in relation with MStar Software to you for your use of
50 // MStar Software in conjunction with your or your customer`s product
51 // ("Services").
52 // You understand and agree that, except otherwise agreed by both parties in
53 // writing, Services are provided on an "AS IS" basis and the warranty
54 // disclaimer set forth in Section 4 above shall apply.
55 //
56 // 6. Nothing contained herein shall be construed as by implication, estoppels
57 // or otherwise:
58 // (a) conferring any license or right to use MStar name, trademark, service
59 // mark, symbol or any other identification;
60 // (b) obligating MStar or any of its affiliates to furnish any person,
61 // including without limitation, you and your customers, any assistance
62 // of any kind whatsoever, or any information; or
63 // (c) conferring any license or right under any intellectual property right.
64 //
65 // 7. These terms shall be governed by and construed in accordance with the laws
66 // of Taiwan, R.O.C., excluding its conflict of law rules.
67 // Any and all dispute arising out hereof or related hereto shall be finally
68 // settled by arbitration referred to the Chinese Arbitration Association,
69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration
70 // Rules of the Association by three (3) arbitrators appointed in accordance
71 // with the said Rules.
72 // The place of arbitration shall be in Taipei, Taiwan and the language shall
73 // be English.
74 // The arbitration award shall be final and binding to both parties.
75 //
76 //******************************************************************************
77 //<MStar Software>
78 #define _MSINIT_C_
79
80 #include "mdrv_mfc_platform.h"
81 #include "mdrv_mfc.h"
82 #include "mdrv_mfc_fb.h"
83
84 #if(CODESIZE_SEL == CODESIZE_ALL)
85
86 //chip top
87 code MST_MFC_RegUnitType_t tInitializeChip[]=
88 {
89 // chip top
90 {0x1E03, 0x07},
91 #ifdef Packet_QFP
92 {0x1E04, 0x0C},
93 #endif
94 //{0x1E05, 0x00}, //_BIT4 | _BIT0
95 //{0x1E0B, 0x10}, //ckg_fclk
96 //{0x1E0C, 0x00}, //_BIT4 | _BIT0
97 //{0x1E0D, 0x00}, // _BIT0
98 {0x1E0E, 0x00}, // _BIT0
99 //{0x1E0F, 0x00}, // _BIT5
100 //{0x1E11, 0x46},//0x00, // _BIT0 //_BIT5 |_BIT4
101
102 {0x1E0A, 0x00},
103 {0x1E1E, 0x00},
104 {0x1E36, 0x40}, // set reg_enable_pad 1
105 {0x1E37, 0x00}, // set reg_enable_pad 1
106 {0x1E3E, 0x00},
107 {0x1E3F, 0x00},
108 {0x1E42, 0x95},
109 {0x1E43, 0xf0},
110 {0x1E46, 0x70}, // [3:2] reg_gpio_i2cm_out
111 // [5;4] reg_gpio_i2cm_oen
112 // [6] reg_mod_gate, od clock gating
113 {0x1E47, 0x00},
114 {_END_OF_TBL_, _END_OF_TBL_},
115 };
116
117 code U8 tClockSel[][5] =
118 {
119 //1E0F 1E10 1E11 1E05 1E0B
120 {0x40, 0x00, 0x04, 0x00, 0x18}, //_RSDS //0x10 to 18
121 {0x32, 0x00, 0x46, 0x60, 0x18}, //_MIN_LVDS //0x12 to 0x18
122 {0x10, 0x00, 0x00, 0x00, 0x18}, //_LVDS or _TTL //0x10 to 0x18 //F_Clk to AuPLL_Clk //Cloud090616
123 };
124
MDrv_MFC_InitializeChip(void)125 void MDrv_MFC_InitializeChip(void)
126 {
127 U8 ucIdx;
128
129 if (gmfcSysInfo.u8PanelType == _RSDS)
130 ucIdx = 0;
131 else if ((gmfcSysInfo.u8PanelType == _MINI_LVDS)||(gmfcSysInfo.u8PanelType == _MINI_LVDS_GIP)||( gmfcSysInfo.u8PanelType == _MINI_LVDS_GIP_V5))
132 ucIdx = 1;
133 else
134 ucIdx = 2; // _LVDS or _TTL
135
136 MDrv_MFC_WriteByte(0x1E0F, tClockSel[ucIdx][0]); // [7:4]rsds clk:[6]=1:1/2,[5]=1:inverse,[4]=1:gating; [3:0]misc clk
137 MDrv_MFC_WriteByte(0x1E10, tClockSel[ucIdx][1]);
138 MDrv_MFC_WriteByte(0x1E11, tClockSel[ucIdx][2]);
139 MDrv_MFC_WriteByte(0x1E05, tClockSel[ucIdx][3]);
140 MDrv_MFC_WriteByte(0x1E0B, tClockSel[ucIdx][4]);
141 if(gmfcMiuBaseAddr.u8OdMode == OD_MODE_555)
142 MDrv_MFC_WriteByte(0x1E04, 0x00);
143 else
144 MDrv_MFC_WriteByte(0x1E04, 0x0C);
145 MDrv_MFC_WriteRegsTbl(0x1E00, tInitializeChip); // initialize all of bank
146 MDrv_MFC_WriteByte(0x1E23, 0x5F); //Control GPIO-12,GPIO-14; 0:out , 1:in
147
148 //putstr("\r\n MDrv_MFC_InitializeChip()");
149 }
150
151
152 code MST_MFC_RegUnitType_t tPowerDownChip[]=
153 {
154 {0x3220, 0x00},
155 {0x3221, 0x00},
156 {0x3222, 0x00},
157 {0x3223, 0x00},
158 {0x3224, 0x00},
159 {0x3225, 0x00},
160 {0x3226, 0x00},
161 {0x3227, 0x00},
162 {0x3228, 0xFF},
163 {0x3229, 0xFF},
164 {0x322A, 0xFF},
165 {0x322B, 0xFF},
166 {0x322C, 0xFF},
167 {0x322D, 0xFF},
168 {0x322E, 0xFF},
169 {0x322F, 0xFF},
170 {_END_OF_TBL_, _END_OF_TBL_},
171 };
172
173 #if 0
174 void MDrv_MFC_PowerDownChip(void)
175 {
176 MDrv_MFC_WriteByte(0x2a06, 0x20); //lpll_pd
177 MDrv_MFC_WriteByte(0x324e, 0x00); //diable ck ib
178 MDrv_MFC_WriteByte(0x3250, 0x80); //mod regu pd
179 MDrv_MFC_WriteByte(0x1e80, 0x80); //mpll pd
180 MDrv_MFC_WriteByte(0x1e02, 0x02); //[1]pd_all,[0]reg_ckf_all_dft=1
181 MDrv_MFC_WriteByte(0x1225, 0x02); //ddr_pd
182 MDrv_MFC_WriteByte(0x2216, 0x18); //[4]bandgap_pd,[3]lvds regu pd
183 MDrv_MFC_WriteByte(0x221e, 0x18); //[4]bandgap_pd,[3]lvds regu pd
184 MDrv_MFC_WriteByte(0x2210, 0x28); //[5]lvds limit amp pd,[3]PHDAC pd
185 MDrv_MFC_WriteByte(0x2214, 0x28); //[5]lvds limit amp pd,[3]PHDAC pd
186 MDrv_MFC_WriteByte(0x224e, 0x07); //[2]bandgap pd,[1]first ch regu pd,[0]second ch regu pd
187 MDrv_MFC_WriteByte(0x2228, 0x08); //[3] osc 400 pd
188 MDrv_MFC_WriteByte(0x2278, 0x00); //disable all clock
189 MDrv_MFC_WriteByte(0x220c, 0x40); //disable lvds clock gen
190 MDrv_MFC_WriteByte(0x1e06, 0x00); //mcu clock = dft live
191 MDrv_MFC_WriteByte(0x1e36, 0x00); //all pad output disable
192 MDrv_MFC_WriteByte(0x1203, 0xf0); //ddr output disable
193 MDrv_MFC_WriteByte(0x1e0e, 0x41); //[6]disable op2_sramclk,[0]disable odclk
194 MDrv_MFC_WriteByte(0x1e0f, 0x11); //[4]disable rsds_clk,[0]disable misc_clk
195 MDrv_MFC_WriteByte(0x1e11, 0x01); //[0]disable mod_clk
196 MDrv_MFC_WriteByte(0x1e04, 0x01); //[0]disable miu clk
197 MDrv_MFC_WriteByte(0x1e3e, 0x01); //[0]disable pafrc clk
198 MDrv_MFC_WriteRegsTbl(0x3200, tPowerDownChip); // initialize all of bank
199 }
200 #endif
201
MDrv_MFC_PowerDownChipU3(void)202 void MDrv_MFC_PowerDownChipU3(void)
203 {
204 if(gmfcSysInfo.u8ChipRevision==U02)
205 {
206 MDrv_MFC_WriteBit(0x3000, 1, _BIT1); //op2 power gatting
207
208 //MDrv_MFC_WriteByteMask(0x2987, 0 , _BIT0); //disable mfc power gatting
209 //MDrv_MFC_WriteByteMask(0x266F, 0 , _BIT1); //disable mfc power gatting
210 }
211 MDrv_MFC_Write2Bytes(0x28B6, 0x0000); //OD
212 MDrv_MFC_WriteBit(0x3104, 1, _BIT0); //MFT
213 MDrv_MFC_WriteByteMask(0x2161, _BIT5|_BIT4 , _BIT5|_BIT4); //opm
214 MDrv_MFC_WriteByteMask(0x266E, _BIT7|_BIT6 |_BIT3|_BIT2|_BIT1|_BIT0, _BIT7|_BIT6| _BIT3|_BIT2|_BIT1|_BIT0);
215 }
216
217 #endif
218