xref: /utopia/UTPA2-700.0.x/modules/mbx/hal/mooney/mbx/halMBX.h (revision 53ee8cc121a030b8d368113ac3e966b4705770ef)
1*53ee8cc1Swenshuai.xi //<MStar Software>
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93*53ee8cc1Swenshuai.xi ////////////////////////////////////////////////////////////////////////////////
94*53ee8cc1Swenshuai.xi 
95*53ee8cc1Swenshuai.xi ///////////////////////////////////////////////////////////////////////////////////////////////////
96*53ee8cc1Swenshuai.xi /// @file   halMBX.h
97*53ee8cc1Swenshuai.xi /// @brief  MStar Mailbox HAL Driver DDI
98*53ee8cc1Swenshuai.xi /// @author MStar Semiconductor Inc.
99*53ee8cc1Swenshuai.xi /// @attention
100*53ee8cc1Swenshuai.xi /// <b><em></em></b>
101*53ee8cc1Swenshuai.xi ///////////////////////////////////////////////////////////////////////////////////////////////////
102*53ee8cc1Swenshuai.xi 
103*53ee8cc1Swenshuai.xi #ifndef _HAL_MBX_H
104*53ee8cc1Swenshuai.xi #define _HAL_MBX_H
105*53ee8cc1Swenshuai.xi 
106*53ee8cc1Swenshuai.xi #ifdef _HAL_MBX_C
107*53ee8cc1Swenshuai.xi #define INTERFACE
108*53ee8cc1Swenshuai.xi #else
109*53ee8cc1Swenshuai.xi #define INTERFACE extern
110*53ee8cc1Swenshuai.xi #endif
111*53ee8cc1Swenshuai.xi 
112*53ee8cc1Swenshuai.xi //=============================================================================
113*53ee8cc1Swenshuai.xi // Includs
114*53ee8cc1Swenshuai.xi //=============================================================================
115*53ee8cc1Swenshuai.xi 
116*53ee8cc1Swenshuai.xi //=============================================================================
117*53ee8cc1Swenshuai.xi // Defines & Macros
118*53ee8cc1Swenshuai.xi 
119*53ee8cc1Swenshuai.xi //=============================================================================
120*53ee8cc1Swenshuai.xi //busy bit Set/Clear/Get
121*53ee8cc1Swenshuai.xi #define   _BUSY_S(arg)  {\
122*53ee8cc1Swenshuai.xi                             MS_U8 val; \
123*53ee8cc1Swenshuai.xi                             val = REG8_MBX_GROUP(arg, REG8_MBX_STATE_1);\
124*53ee8cc1Swenshuai.xi                             REG8_MBX_GROUP(arg, REG8_MBX_STATE_1) = val | MBX_STATE1_BUSY;\
125*53ee8cc1Swenshuai.xi                          }
126*53ee8cc1Swenshuai.xi 
127*53ee8cc1Swenshuai.xi #define   _BUSY_C(arg)  {\
128*53ee8cc1Swenshuai.xi                             MS_U8 val; \
129*53ee8cc1Swenshuai.xi                             val = REG8_MBX_GROUP(arg, REG8_MBX_STATE_1);\
130*53ee8cc1Swenshuai.xi                             REG8_MBX_GROUP(arg, REG8_MBX_STATE_1) = val & ~MBX_STATE1_BUSY;\
131*53ee8cc1Swenshuai.xi                          }
132*53ee8cc1Swenshuai.xi 
133*53ee8cc1Swenshuai.xi #define   _BUSY(arg)    (REG8_MBX_GROUP(arg, REG8_MBX_STATE_1) & MBX_STATE1_BUSY);
134*53ee8cc1Swenshuai.xi 
135*53ee8cc1Swenshuai.xi //////////////////////////////////////////////////////////////
136*53ee8cc1Swenshuai.xi //error bit Set/Clear/Get
137*53ee8cc1Swenshuai.xi #define   _ERR_S(arg)   {\
138*53ee8cc1Swenshuai.xi                             MS_U8 val;\
139*53ee8cc1Swenshuai.xi                             val = REG8_MBX_GROUP(arg, REG8_MBX_STATE_1);\
140*53ee8cc1Swenshuai.xi                             REG8_MBX_GROUP(arg, REG8_MBX_STATE_1) = val | MBX_STATE1_ERROR;\
141*53ee8cc1Swenshuai.xi                          }
142*53ee8cc1Swenshuai.xi 
143*53ee8cc1Swenshuai.xi #define   _ERR_C(arg)   {\
144*53ee8cc1Swenshuai.xi                             MS_U8 val;\
145*53ee8cc1Swenshuai.xi                             val = REG8_MBX_GROUP(arg, REG8_MBX_STATE_1);\
146*53ee8cc1Swenshuai.xi                             REG8_MBX_GROUP(arg, REG8_MBX_STATE_1) = val & ~MBX_STATE1_ERROR;\
147*53ee8cc1Swenshuai.xi                          }
148*53ee8cc1Swenshuai.xi 
149*53ee8cc1Swenshuai.xi #define   _ERR(arg)    (REG8_MBX_GROUP(arg, REG8_MBX_STATE_1) & MBX_STATE1_ERROR)
150*53ee8cc1Swenshuai.xi 
151*53ee8cc1Swenshuai.xi //////////////////////////////////////////////////////////////
152*53ee8cc1Swenshuai.xi //disabled bit Set/Clear/Get
153*53ee8cc1Swenshuai.xi #define   _DISABLED_S(arg)   {\
154*53ee8cc1Swenshuai.xi                             MS_U8 val;\
155*53ee8cc1Swenshuai.xi                             val = REG8_MBX_GROUP(arg, REG8_MBX_STATE_1);\
156*53ee8cc1Swenshuai.xi                             REG8_MBX_GROUP(arg, REG8_MBX_STATE_1) = val | MBX_STATE1_DISABLED;\
157*53ee8cc1Swenshuai.xi                          }
158*53ee8cc1Swenshuai.xi 
159*53ee8cc1Swenshuai.xi #define   _DISABLED_C(arg)   {\
160*53ee8cc1Swenshuai.xi                             MS_U8 val;\
161*53ee8cc1Swenshuai.xi                             val = REG8_MBX_GROUP(arg, REG8_MBX_STATE_1);\
162*53ee8cc1Swenshuai.xi                             REG8_MBX_GROUP(arg, REG8_MBX_STATE_1) = val & ~MBX_STATE1_DISABLED;\
163*53ee8cc1Swenshuai.xi                          }
164*53ee8cc1Swenshuai.xi 
165*53ee8cc1Swenshuai.xi #define   _DISABLED(arg)    (REG8_MBX_GROUP(arg, REG8_MBX_STATE_1) & MBX_STATE1_DISABLED)
166*53ee8cc1Swenshuai.xi 
167*53ee8cc1Swenshuai.xi ////////////////////////////////////////////////////////////////////////
168*53ee8cc1Swenshuai.xi //overflow bit Set/Clear/Get
169*53ee8cc1Swenshuai.xi #define   _OVERFLOW_S(arg)  {\
170*53ee8cc1Swenshuai.xi                                 MS_U8 val;\
171*53ee8cc1Swenshuai.xi                                 val = REG8_MBX_GROUP(arg, REG8_MBX_STATE_1);\
172*53ee8cc1Swenshuai.xi                                 REG8_MBX_GROUP(arg, REG8_MBX_STATE_1) = val | MBX_STATE1_OVERFLOW;\
173*53ee8cc1Swenshuai.xi                               }
174*53ee8cc1Swenshuai.xi 
175*53ee8cc1Swenshuai.xi #define   _OVERFLOW_C(arg)  {\
176*53ee8cc1Swenshuai.xi                                 MS_U8 val;\
177*53ee8cc1Swenshuai.xi                                 val = REG8_MBX_GROUP(arg, REG8_MBX_STATE_1);\
178*53ee8cc1Swenshuai.xi                                 REG8_MBX_GROUP(arg, REG8_MBX_STATE_1) = val & ~MBX_STATE1_OVERFLOW;\
179*53ee8cc1Swenshuai.xi                               }
180*53ee8cc1Swenshuai.xi 
181*53ee8cc1Swenshuai.xi #define   _OVERFLOW(arg)   (REG8_MBX_GROUP(arg, REG8_MBX_STATE_1) & MBX_STATE1_OVERFLOW)
182*53ee8cc1Swenshuai.xi 
183*53ee8cc1Swenshuai.xi ////////////////////////////////////////////////////////////////////////
184*53ee8cc1Swenshuai.xi //status bit clear
185*53ee8cc1Swenshuai.xi #define   _S1_C(arg)   {\
186*53ee8cc1Swenshuai.xi                             MS_U8 val;\
187*53ee8cc1Swenshuai.xi                             val = REG8_MBX_GROUP(arg, REG8_MBX_STATE_1);\
188*53ee8cc1Swenshuai.xi                             REG8_MBX_GROUP(arg, REG8_MBX_STATE_1) = val & ~(MBX_STATE1_DISABLED | MBX_STATE1_OVERFLOW | MBX_STATE1_ERROR | MBX_STATE1_BUSY);\
189*53ee8cc1Swenshuai.xi                         }
190*53ee8cc1Swenshuai.xi 
191*53ee8cc1Swenshuai.xi ////////////////////////////////////////////////////////////////////////
192*53ee8cc1Swenshuai.xi //fire bit Set/Clear/Get
193*53ee8cc1Swenshuai.xi #define   _FIRE_S(arg)  {\
194*53ee8cc1Swenshuai.xi                             MS_U8 val;\
195*53ee8cc1Swenshuai.xi                             val = REG8_MBX_GROUP(arg, REG8_MBX_CTRL);\
196*53ee8cc1Swenshuai.xi                             REG8_MBX_GROUP(arg, REG8_MBX_CTRL) = val | MBX_CTRL_FIRE;\
197*53ee8cc1Swenshuai.xi                          }
198*53ee8cc1Swenshuai.xi 
199*53ee8cc1Swenshuai.xi #define   _FIRE_C(arg)  {\
200*53ee8cc1Swenshuai.xi                             MS_U8 val;\
201*53ee8cc1Swenshuai.xi                             val = REG8_MBX_GROUP(arg, REG8_MBX_CTRL);\
202*53ee8cc1Swenshuai.xi                             REG8_MBX_GROUP(arg, REG8_MBX_CTRL) = val & ~MBX_CTRL_FIRE;\
203*53ee8cc1Swenshuai.xi                          }
204*53ee8cc1Swenshuai.xi 
205*53ee8cc1Swenshuai.xi #define   _FIRE(arg)   (REG8_MBX_GROUP(arg, REG8_MBX_CTRL) & MBX_CTRL_FIRE)
206*53ee8cc1Swenshuai.xi 
207*53ee8cc1Swenshuai.xi ////////////////////////////////////////////////////////////////////////
208*53ee8cc1Swenshuai.xi //readback bit Set/Clear/Get
209*53ee8cc1Swenshuai.xi #define   _READBACK_S(arg)   {\
210*53ee8cc1Swenshuai.xi                                   MS_U8 val;\
211*53ee8cc1Swenshuai.xi                                   val = REG8_MBX_GROUP(arg, REG8_MBX_CTRL);\
212*53ee8cc1Swenshuai.xi                                   REG8_MBX_GROUP(arg, REG8_MBX_CTRL) = val | MBX_CTRL_READBACK;\
213*53ee8cc1Swenshuai.xi                                }
214*53ee8cc1Swenshuai.xi 
215*53ee8cc1Swenshuai.xi #define   _READBACK_C(arg)   {\
216*53ee8cc1Swenshuai.xi                                   MS_U8 val;\
217*53ee8cc1Swenshuai.xi                                   val = REG8_MBX_GROUP(arg, REG8_MBX_CTRL);\
218*53ee8cc1Swenshuai.xi                                   REG8_MBX_GROUP(arg, REG8_MBX_CTRL) = val & ~MBX_CTRL_READBACK;\
219*53ee8cc1Swenshuai.xi                                }
220*53ee8cc1Swenshuai.xi 
221*53ee8cc1Swenshuai.xi #define   _READBACK(arg)   (REG8_MBX_GROUP(arg, REG8_MBX_CTRL) & MBX_CTRL_READBACK)
222*53ee8cc1Swenshuai.xi 
223*53ee8cc1Swenshuai.xi ////////////////////////////////////////////////////////////////////////
224*53ee8cc1Swenshuai.xi //instant bit Set/Clear/Get
225*53ee8cc1Swenshuai.xi #define   _INSTANT_S(arg)   {\
226*53ee8cc1Swenshuai.xi                                   MS_U8 val;\
227*53ee8cc1Swenshuai.xi                                   val = REG8_MBX_GROUP(arg, REG8_MBX_CTRL);\
228*53ee8cc1Swenshuai.xi                                   REG8_MBX_GROUP(arg, REG8_MBX_CTRL) = val | MBX_CTRL_INSTANT;\
229*53ee8cc1Swenshuai.xi                               }
230*53ee8cc1Swenshuai.xi 
231*53ee8cc1Swenshuai.xi #define   _INSTANT_C(arg)   {\
232*53ee8cc1Swenshuai.xi                                   MS_U8 val;\
233*53ee8cc1Swenshuai.xi                                   val = REG8_MBX_GROUP(arg, REG8_MBX_CTRL);\
234*53ee8cc1Swenshuai.xi                                   REG8_MBX_GROUP(arg, REG8_MBX_CTRL) = val & ~MBX_CTRL_INSTANT;\
235*53ee8cc1Swenshuai.xi                               }
236*53ee8cc1Swenshuai.xi 
237*53ee8cc1Swenshuai.xi #define   _INSTANT(arg)   (REG8_MBX_GROUP(arg, REG8_MBX_CTRL) & MBX_CTRL_INSTANT)
238*53ee8cc1Swenshuai.xi 
239*53ee8cc1Swenshuai.xi //=============================================================================
240*53ee8cc1Swenshuai.xi // Type and Structure Declaration
241*53ee8cc1Swenshuai.xi //=============================================================================
242*53ee8cc1Swenshuai.xi 
243*53ee8cc1Swenshuai.xi //=============================================================================
244*53ee8cc1Swenshuai.xi // Enums
245*53ee8cc1Swenshuai.xi /// MBX HAL Recv Status Define
246*53ee8cc1Swenshuai.xi typedef enum
247*53ee8cc1Swenshuai.xi {
248*53ee8cc1Swenshuai.xi     /// Recv Success
249*53ee8cc1Swenshuai.xi     E_MBXHAL_RECV_SUCCESS = 0,
250*53ee8cc1Swenshuai.xi     /// Recv Error: OverFlow
251*53ee8cc1Swenshuai.xi     E_MBXHAL_RECV_OVERFLOW = 1,
252*53ee8cc1Swenshuai.xi     /// Recv Error: Not Enabled
253*53ee8cc1Swenshuai.xi     E_MBXHAL_RECV_DISABLED = 2,
254*53ee8cc1Swenshuai.xi } MBXHAL_Recv_Status;
255*53ee8cc1Swenshuai.xi 
256*53ee8cc1Swenshuai.xi /// MBX HAL Fire Status Define
257*53ee8cc1Swenshuai.xi typedef enum
258*53ee8cc1Swenshuai.xi {
259*53ee8cc1Swenshuai.xi     /// Fire Success
260*53ee8cc1Swenshuai.xi     E_MBXHAL_FIRE_SUCCESS = 0,
261*53ee8cc1Swenshuai.xi     /// Still Firing
262*53ee8cc1Swenshuai.xi     E_MBXHAL_FIRE_ONGOING = 1,
263*53ee8cc1Swenshuai.xi     /// Fire Error: Overflow:
264*53ee8cc1Swenshuai.xi     E_MBXHAL_FIRE_OVERFLOW = 2,
265*53ee8cc1Swenshuai.xi     /// Fire Error: Not Enabled
266*53ee8cc1Swenshuai.xi     E_MBXHAL_FIRE_DISABLED = 3,
267*53ee8cc1Swenshuai.xi } MBXHAL_Fire_Status;
268*53ee8cc1Swenshuai.xi 
269*53ee8cc1Swenshuai.xi //=============================================================================
270*53ee8cc1Swenshuai.xi // Mailbox HAL Driver Function
271*53ee8cc1Swenshuai.xi //=============================================================================
272*53ee8cc1Swenshuai.xi 
273*53ee8cc1Swenshuai.xi INTERFACE MBX_Result MHAL_MBX_ClearAll (MBX_Msg* pMbxMsg, MBX_ROLE_ID eSrcRole);
274*53ee8cc1Swenshuai.xi 
275*53ee8cc1Swenshuai.xi INTERFACE MBX_Result MHAL_MBX_Init(MBX_ROLE_ID eHostRole, MS_VIRT virtRIUBaseAddrMBX);
276*53ee8cc1Swenshuai.xi INTERFACE MBX_Result MHAL_MBX_SetConfig(MBX_ROLE_ID eHostRole);
277*53ee8cc1Swenshuai.xi 
278*53ee8cc1Swenshuai.xi INTERFACE MBX_Result MHAL_MBX_SetInformation(MBX_ROLE_ID eTargetRole, MS_VIRT virtRIUBaseAddrMBX, MS_U8 *pU8Info, MS_U8 u8Size);
279*53ee8cc1Swenshuai.xi INTERFACE MBX_Result MHAL_MBX_GetInformation(MBX_ROLE_ID eTargetRole, MS_VIRT virtRIUBaseAddrMBX, MS_U8 *pU8Info, MS_U8 u8Size);
280*53ee8cc1Swenshuai.xi 
281*53ee8cc1Swenshuai.xi INTERFACE MBX_Result MHAL_MBX_Fire(MBX_Msg* pMbxMsg, MBX_ROLE_ID eSrcRole);
282*53ee8cc1Swenshuai.xi INTERFACE MBX_Result MHAL_MBX_GetFireStatus(MBX_ROLE_ID eSrcRole, MBX_ROLE_ID eDstRole, MBXHAL_Fire_Status *pFireStatus);
283*53ee8cc1Swenshuai.xi 
284*53ee8cc1Swenshuai.xi INTERFACE MBX_Result MHAL_MBX_Recv(MBX_Msg* pMbxMsg, MBX_ROLE_ID eDstRole);
285*53ee8cc1Swenshuai.xi INTERFACE MBX_Result MHAL_MBX_RecvEnd(MBX_ROLE_ID eSrcRole, MBX_ROLE_ID eDstRole, MBXHAL_Recv_Status eRecvSatus);
286*53ee8cc1Swenshuai.xi 
287*53ee8cc1Swenshuai.xi #undef INTERFACE
288*53ee8cc1Swenshuai.xi #endif //_HAL_MBX_H
289*53ee8cc1Swenshuai.xi 
290