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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 /////////////////////////////////////////////////////////////////////////////////////////////////// 96 /// @file halMBX.h 97 /// @brief MStar Mailbox HAL Driver DDI 98 /// @author MStar Semiconductor Inc. 99 /// @attention 100 /// <b><em></em></b> 101 /////////////////////////////////////////////////////////////////////////////////////////////////// 102 103 #ifndef _HAL_MBX_H 104 #define _HAL_MBX_H 105 106 #ifdef _HAL_MBX_C 107 #define INTERFACE 108 #else 109 #define INTERFACE extern 110 #endif 111 112 //============================================================================= 113 // Includs 114 //============================================================================= 115 116 //============================================================================= 117 // Defines & Macros 118 119 //============================================================================= 120 //busy bit Set/Clear/Get 121 #define _BUSY_S(arg) {\ 122 MS_U8 val; \ 123 val = REG8_MBX_GROUP(arg, REG8_MBX_STATE_1);\ 124 REG8_MBX_GROUP(arg, REG8_MBX_STATE_1) = val | MBX_STATE1_BUSY;\ 125 } 126 127 #define _BUSY_C(arg) {\ 128 MS_U8 val; \ 129 val = REG8_MBX_GROUP(arg, REG8_MBX_STATE_1);\ 130 REG8_MBX_GROUP(arg, REG8_MBX_STATE_1) = val & ~MBX_STATE1_BUSY;\ 131 } 132 133 #define _BUSY(arg) (REG8_MBX_GROUP(arg, REG8_MBX_STATE_1) & MBX_STATE1_BUSY); 134 135 ////////////////////////////////////////////////////////////// 136 //error bit Set/Clear/Get 137 #define _ERR_S(arg) {\ 138 MS_U8 val;\ 139 val = REG8_MBX_GROUP(arg, REG8_MBX_STATE_1);\ 140 REG8_MBX_GROUP(arg, REG8_MBX_STATE_1) = val | MBX_STATE1_ERROR;\ 141 } 142 143 #define _ERR_C(arg) {\ 144 MS_U8 val;\ 145 val = REG8_MBX_GROUP(arg, REG8_MBX_STATE_1);\ 146 REG8_MBX_GROUP(arg, REG8_MBX_STATE_1) = val & ~MBX_STATE1_ERROR;\ 147 } 148 149 #define _ERR(arg) (REG8_MBX_GROUP(arg, REG8_MBX_STATE_1) & MBX_STATE1_ERROR) 150 151 ////////////////////////////////////////////////////////////// 152 //disabled bit Set/Clear/Get 153 #define _DISABLED_S(arg) {\ 154 MS_U8 val;\ 155 val = REG8_MBX_GROUP(arg, REG8_MBX_STATE_1);\ 156 REG8_MBX_GROUP(arg, REG8_MBX_STATE_1) = val | MBX_STATE1_DISABLED;\ 157 } 158 159 #define _DISABLED_C(arg) {\ 160 MS_U8 val;\ 161 val = REG8_MBX_GROUP(arg, REG8_MBX_STATE_1);\ 162 REG8_MBX_GROUP(arg, REG8_MBX_STATE_1) = val & ~MBX_STATE1_DISABLED;\ 163 } 164 165 #define _DISABLED(arg) (REG8_MBX_GROUP(arg, REG8_MBX_STATE_1) & MBX_STATE1_DISABLED) 166 167 //////////////////////////////////////////////////////////////////////// 168 //overflow bit Set/Clear/Get 169 #define _OVERFLOW_S(arg) {\ 170 MS_U8 val;\ 171 val = REG8_MBX_GROUP(arg, REG8_MBX_STATE_1);\ 172 REG8_MBX_GROUP(arg, REG8_MBX_STATE_1) = val | MBX_STATE1_OVERFLOW;\ 173 } 174 175 #define _OVERFLOW_C(arg) {\ 176 MS_U8 val;\ 177 val = REG8_MBX_GROUP(arg, REG8_MBX_STATE_1);\ 178 REG8_MBX_GROUP(arg, REG8_MBX_STATE_1) = val & ~MBX_STATE1_OVERFLOW;\ 179 } 180 181 #define _OVERFLOW(arg) (REG8_MBX_GROUP(arg, REG8_MBX_STATE_1) & MBX_STATE1_OVERFLOW) 182 183 //////////////////////////////////////////////////////////////////////// 184 //status bit clear 185 #define _S1_C(arg) {\ 186 MS_U8 val;\ 187 val = REG8_MBX_GROUP(arg, REG8_MBX_STATE_1);\ 188 REG8_MBX_GROUP(arg, REG8_MBX_STATE_1) = val & ~(MBX_STATE1_DISABLED | MBX_STATE1_OVERFLOW | MBX_STATE1_ERROR | MBX_STATE1_BUSY);\ 189 } 190 191 //////////////////////////////////////////////////////////////////////// 192 //fire bit Set/Clear/Get 193 #define _FIRE_S(arg) {\ 194 MS_U8 val;\ 195 val = REG8_MBX_GROUP(arg, REG8_MBX_CTRL);\ 196 REG8_MBX_GROUP(arg, REG8_MBX_CTRL) = val | MBX_CTRL_FIRE;\ 197 } 198 199 #define _FIRE_C(arg) {\ 200 MS_U8 val;\ 201 val = REG8_MBX_GROUP(arg, REG8_MBX_CTRL);\ 202 REG8_MBX_GROUP(arg, REG8_MBX_CTRL) = val & ~MBX_CTRL_FIRE;\ 203 } 204 205 #define _FIRE(arg) (REG8_MBX_GROUP(arg, REG8_MBX_CTRL) & MBX_CTRL_FIRE) 206 207 //////////////////////////////////////////////////////////////////////// 208 //readback bit Set/Clear/Get 209 #define _READBACK_S(arg) {\ 210 MS_U8 val;\ 211 val = REG8_MBX_GROUP(arg, REG8_MBX_CTRL);\ 212 REG8_MBX_GROUP(arg, REG8_MBX_CTRL) = val | MBX_CTRL_READBACK;\ 213 } 214 215 #define _READBACK_C(arg) {\ 216 MS_U8 val;\ 217 val = REG8_MBX_GROUP(arg, REG8_MBX_CTRL);\ 218 REG8_MBX_GROUP(arg, REG8_MBX_CTRL) = val & ~MBX_CTRL_READBACK;\ 219 } 220 221 #define _READBACK(arg) (REG8_MBX_GROUP(arg, REG8_MBX_CTRL) & MBX_CTRL_READBACK) 222 223 //////////////////////////////////////////////////////////////////////// 224 //instant bit Set/Clear/Get 225 #define _INSTANT_S(arg) {\ 226 MS_U8 val;\ 227 val = REG8_MBX_GROUP(arg, REG8_MBX_CTRL);\ 228 REG8_MBX_GROUP(arg, REG8_MBX_CTRL) = val | MBX_CTRL_INSTANT;\ 229 } 230 231 #define _INSTANT_C(arg) {\ 232 MS_U8 val;\ 233 val = REG8_MBX_GROUP(arg, REG8_MBX_CTRL);\ 234 REG8_MBX_GROUP(arg, REG8_MBX_CTRL) = val & ~MBX_CTRL_INSTANT;\ 235 } 236 237 #define _INSTANT(arg) (REG8_MBX_GROUP(arg, REG8_MBX_CTRL) & MBX_CTRL_INSTANT) 238 239 //============================================================================= 240 // Type and Structure Declaration 241 //============================================================================= 242 243 //============================================================================= 244 // Enums 245 /// MBX HAL Recv Status Define 246 typedef enum 247 { 248 /// Recv Success 249 E_MBXHAL_RECV_SUCCESS = 0, 250 /// Recv Error: OverFlow 251 E_MBXHAL_RECV_OVERFLOW = 1, 252 /// Recv Error: Not Enabled 253 E_MBXHAL_RECV_DISABLED = 2, 254 } MBXHAL_Recv_Status; 255 256 /// MBX HAL Fire Status Define 257 typedef enum 258 { 259 /// Fire Success 260 E_MBXHAL_FIRE_SUCCESS = 0, 261 /// Still Firing 262 E_MBXHAL_FIRE_ONGOING = 1, 263 /// Fire Error: Overflow: 264 E_MBXHAL_FIRE_OVERFLOW = 2, 265 /// Fire Error: Not Enabled 266 E_MBXHAL_FIRE_DISABLED = 3, 267 } MBXHAL_Fire_Status; 268 269 //============================================================================= 270 // Mailbox HAL Driver Function 271 //============================================================================= 272 273 INTERFACE MBX_Result MHAL_MBX_ClearAll (MBX_Msg* pMbxMsg, MBX_ROLE_ID eSrcRole); 274 275 INTERFACE MBX_Result MHAL_MBX_Init(MBX_ROLE_ID eHostRole, MS_VIRT virtRIUBaseAddrMBX); 276 INTERFACE MBX_Result MHAL_MBX_SetConfig(MBX_ROLE_ID eHostRole); 277 278 INTERFACE MBX_Result MHAL_MBX_SetInformation(MBX_ROLE_ID eTargetRole, MS_VIRT virtRIUBaseAddrMBX, MS_U8 *pU8Info, MS_U8 u8Size); 279 INTERFACE MBX_Result MHAL_MBX_GetInformation(MBX_ROLE_ID eTargetRole, MS_VIRT virtRIUBaseAddrMBX, MS_U8 *pU8Info, MS_U8 u8Size); 280 281 INTERFACE MBX_Result MHAL_MBX_Fire(MBX_Msg* pMbxMsg, MBX_ROLE_ID eSrcRole); 282 INTERFACE MBX_Result MHAL_MBX_GetFireStatus(MBX_ROLE_ID eSrcRole, MBX_ROLE_ID eDstRole, MBXHAL_Fire_Status *pFireStatus); 283 284 INTERFACE MBX_Result MHAL_MBX_Recv(MBX_Msg* pMbxMsg, MBX_ROLE_ID eDstRole); 285 INTERFACE MBX_Result MHAL_MBX_RecvEnd(MBX_ROLE_ID eSrcRole, MBX_ROLE_ID eDstRole, MBXHAL_Recv_Status eRecvSatus); 286 287 #undef INTERFACE 288 #endif //_HAL_MBX_H 289 290