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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 /////////////////////////////////////////////////////////////////////////////////////////////////// 96 /// @file regMBXINT.h 97 /// @brief MStar Mailbox Driver DDI 98 /// @author MStar Semiconductor Inc. 99 /// @attention 100 /// <b><em>For INT_FIQMASK_AEON2MIPS, maybe has issues with big-endient, but seems pm won't use this bit\n 101 /// so just skip it now. </em></b> 102 /////////////////////////////////////////////////////////////////////////////////////////////////// 103 104 #ifndef _MHAL_MBX_INTERRUPT_REG_H 105 #define _MHAL_MBX_INTERRUPT_REG_H 106 107 //============================================================================= 108 // Includs 109 //============================================================================= 110 111 //============================================================================= 112 // Defines & Macros 113 //============================================================================= 114 #define RIU_MAP _virtRIUBaseAddrMBXINT 115 116 #define RIU ((MS_U16 volatile *) RIU_MAP) 117 #define RIU8 ((MS_U8 volatile *) RIU_MAP) 118 119 120 #define REG_FIQ_MASK_BASE (0xC80<<1) 121 #define FIQ_REG(address) RIU[address*2+REG_FIQ_MASK_BASE] 122 #define REG_FIQ_H1_48_63 0x0027 123 #define INT_FIQMASK_H3_H2 BIT(0) 124 #define INT_FIQMASK_H3_AEON BIT(1) 125 #define INT_FIQMASK_H3_PM BIT(2) 126 127 #define REG_FIQ_H1_32_47 0x0026 128 #define INT_FIQMASK_PM_H3 BIT(4) 129 #define INT_FIQMASK_PM_H2 BIT(5) 130 #define INT_FIQMASK_PM_AEON BIT(6) 131 132 #define INT_FIQMASK_AEON_H3 BIT(8) 133 #define INT_FIQMASK_AEON_H2 BIT(9) 134 #define INT_FIQMASK_AEON_PM BIT(10) 135 136 #define INT_FIQMASK_H2_H3 BIT(12) 137 #define INT_FIQMASK_H2_AEON BIT(13) 138 #define INT_FIQMASK_H2_PM BIT(14) 139 140 #define REG_FIQS_H1_32_47 0x002e 141 #define REG_FIQS_H1_48_63 0x002f 142 143 144 145 146 #define REG_CPU_INT_BASE (0x2A0<<1) 147 #define CPU_INT_REG(address) RIU[address*2+REG_CPU_INT_BASE] 148 #define REG_INT_PMFIRE 0x0000 149 #define INT_PM_AEON BIT(0) 150 #define INT_PM_H2 BIT(1) 151 #define INT_PM_H3 BIT(2) 152 153 #define REG_INT_AEONFIRE 0x0002 154 #define INT_AEON_PM BIT(0) 155 #define INT_AEON_H2 BIT(1) 156 #define INT_AEON_H3 BIT(2) 157 158 #define REG_INT_H2FIRE 0x0004 159 #define INT_H2_PM BIT(0) 160 #define INT_H2_AEON BIT(1) 161 #define INT_H2_H3 BIT(2) 162 163 #define REG_INT_H3FIRE 0x0004 164 #define INT_H3_PM BIT(0) 165 #define INT_H3_AEON BIT(1) 166 #define INT_H3_H2 BIT(2) 167 168 #endif //_MHAL_MBX_INTERRUPT_REG_H 169 170 171