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///////////////////////////////////////////////////////////////////////////////////////////////////
/// @file   regMBXINT.h
/// @brief  MStar Mailbox Driver DDI
/// @author MStar Semiconductor Inc.
/// @attention
/// <b><em>For INT_FIQMASK_AEON2MIPS, maybe has issues with big-endient, but seems pm won't use this bit\n
/// so just skip it now. </em></b>
///////////////////////////////////////////////////////////////////////////////////////////////////

#ifndef _MHAL_MBX_INTERRUPT_REG_H
#define _MHAL_MBX_INTERRUPT_REG_H

//=============================================================================
// Includs
//=============================================================================

//=============================================================================
// Defines & Macros
//=============================================================================
#define RIU_MAP _virtRIUBaseAddrMBXINT

#define RIU     ((MS_U16 volatile *) RIU_MAP)
#define RIU8    ((MS_U8  volatile *) RIU_MAP)


#define REG_FIQ_MASK_BASE                (0xC80<<1)
#define FIQ_REG(address)                 RIU[address*2+REG_FIQ_MASK_BASE]
#define REG_FIQ_H1_48_63                 0x0027
    #define INT_FIQMASK_H3_H2            BIT(0)
    #define INT_FIQMASK_H3_AEON          BIT(1)
    #define INT_FIQMASK_H3_PM            BIT(2)

#define REG_FIQ_H1_32_47                 0x0026
    #define INT_FIQMASK_PM_H3           BIT(4)
    #define INT_FIQMASK_PM_H2           BIT(5)
    #define INT_FIQMASK_PM_AEON         BIT(6)

    #define INT_FIQMASK_AEON_H3         BIT(8)
    #define INT_FIQMASK_AEON_H2         BIT(9)
    #define INT_FIQMASK_AEON_PM         BIT(10)

    #define INT_FIQMASK_H2_H3           BIT(12)
    #define INT_FIQMASK_H2_AEON         BIT(13)
    #define INT_FIQMASK_H2_PM           BIT(14)

#define REG_FIQS_H1_32_47               0x002e
#define REG_FIQS_H1_48_63               0x002f




#define REG_CPU_INT_BASE                 (0x2A0<<1)
#define CPU_INT_REG(address)             RIU[address*2+REG_CPU_INT_BASE]
#define REG_INT_PMFIRE                   0x0000
    #define INT_PM_AEON                  BIT(0)
    #define INT_PM_H2                    BIT(1)
    #define INT_PM_H3                    BIT(2)

#define REG_INT_AEONFIRE                 0x0002
    #define INT_AEON_PM                  BIT(0)
    #define INT_AEON_H2                  BIT(1)
    #define INT_AEON_H3                  BIT(2)

#define REG_INT_H2FIRE                   0x0004
    #define INT_H2_PM                    BIT(0)
    #define INT_H2_AEON                  BIT(1)
    #define INT_H2_H3                    BIT(2)

#define REG_INT_H3FIRE                   0x0004
    #define INT_H3_PM                    BIT(0)
    #define INT_H3_AEON                  BIT(1)
    #define INT_H3_H2                    BIT(2)

#endif //_MHAL_MBX_INTERRUPT_REG_H