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MStar hereby reserves the 92 // rights to any and all damages, losses, costs and expenses resulting therefrom. 93 // 94 //////////////////////////////////////////////////////////////////////////////// 95 96 /////////////////////////////////////////////////////////////////////////////////////////////////// 97 /// 98 /// file regLDMA.h 99 /// @brief Master local dimming Dma Register Definition 100 /// @author MStar Semiconductor Inc. 101 /////////////////////////////////////////////////////////////////////////////////////////////////// 102 103 #ifndef _REG_LDMA_H_ 104 #define _REG_LDMA_H_ 105 106 //------------------------------------------------------------------------------------------------- 107 // Include File 108 //------------------------------------------------------------------------------------------------- 109 110 //------------------------------------------------------------------------------------------------- 111 // Hardware Capability 112 //------------------------------------------------------------------------------------------------- 113 114 //------------------------------------------------------------------------------------------------- 115 // Macro and Define 116 //------------------------------------------------------------------------------------------------- 117 118 #define LDMA_MAX_SPI_CMD_NUM (10) 119 120 // BASEADDR & BK 121 #define BASEADDR_RIU 0xBF000000 122 123 #define REG_LDMA0_BASE (0x2D00*2) //102D 124 #define REG_LDMA1_BASE (0x2D00*2+0x40*2) 125 126 //102D dma bank register 127 #define REG_MENULOAD_CTRL_MODE (0x00) 128 #define REG_MENULOAD_CTRL_MODE_MSK (BIT0|BIT1) 129 130 #define REG_SPI_8BIT_MD (0x00) 131 #define REG_SPI_8BIT_MD_MSK (BIT2) 132 133 #define REG_RGB_MODE (0x00) 134 #define REG_RGB_MODE_MSK (BIT3) 135 136 #define REG_HYBRID_MODE (0x00) 137 #define REG_HYBRID_MODE_MSK (BIT4) 138 139 #define REG_SPI_10BIT_MD (0x00) 140 #define REG_SPI_10BIT_MD_MSK (BIT5) 141 142 #define REG_SPI_16BIT_MD (0x00) 143 #define REG_SPI_16BIT_MD_MSK (BIT6) 144 145 #define REG_USE_HW_LOOP_MD (0x00) 146 #define REG_USE_HW_LOOP_MD_MSK (BIT7) 147 148 #define REG_MENULOAD_BUSY (0x00) 149 #define REG_MENULOAD_BUSY_MSK (BIT8) 150 151 #define REG_MENULOAD_DONE (0x00) 152 #define REG_MENULOAD_DONE_MSK (BIT9) 153 154 #define REG_MENULOAD_NUMBER (0x01) 155 #define REG_MENULOAD_NUMBER_MSK (0xFFF) 156 157 #define REG_MENULOAD_ABORTED_ONCE (0x02) 158 #define REG_MENULOAD_ABORTED_ONCE_MSK (BIT0) 159 160 #define REG_DMA2LD_BUSY (0x02) 161 #define REG_DMA2LD_BUSY_MSK (BIT1) 162 163 #define REG_SYNC_TRIG0_SEL (0x03) 164 #define REG_SYNC_TRIG0_SEL_MSK (BIT0) 165 #define REG_SYNC_TRIG1_SEL (0x03) 166 #define REG_SYNC_TRIG1_SEL_MSK (BIT1) 167 #define REG_SYNC_TRIG2_SEL (0x03) 168 #define REG_SYNC_TRIG2_SEL_MSK (BIT2) 169 170 #define REG_MENULOAD_REALTIME_TRIG (0x04) 171 #define REG_MENULOAD_ABORT (0x05) 172 #define REG_MENULOAD_ENABLE (0x06) 173 #define REG_DEST_BASE_ADDR (0x8) 174 #define REG_SRC_BASE_ADDR (0x9) 175 176 #define REG_START_CODE (0x0b) 177 #define REG_COMMAND (0x0c) 178 #define REG_CHKSUM_MD (0x0d) 179 #define REG_CHKSUM_MD_MSK (BIT0|BIT1|BIT2) 180 181 #define REG_CMD_LENGTH (0x20) 182 #define REG_COMMAND1 (0x21) 183 #define REG_COMMAND2 (0x22) 184 #define REG_COMMAND3 (0x23) 185 #define REG_COMMAND4 (0x24) 186 #define REG_COMMAND5 (0x25) 187 #define REG_COMMAND6 (0x26) 188 #define REG_COMMAND7 (0x27) 189 #define REG_COMMAND8 (0x28) 190 191 #define REG_TRIG_DELAY0_CNT0 (0x2a) 192 #define REG_TRIG_DELAY0_CNT1 (0x2b) 193 #define REG_TRIG_DELAY1_CNT0 (0x2c) 194 #define REG_TRIG_DELAY1_CNT1 (0x2d) 195 #define REG_TRIG_DELAY_CTRL (0x2e) 196 197 #endif 198