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92 //
93 // File Name: mhal_CEC.c
94 // Description: For CEC functions.
95 ////////////////////////////////////////////////////////////////////////////////
96
97
98 #define _MHAL_CEC_C_
99
100 #include <string.h>
101 #include "MsCommon.h"
102 #include "cec_hwreg_utility2.h"
103 #include "cec_Analog_Reg.h"
104 #include "MsOS.h"
105 #include "apiCEC.h"
106 #include "MsIRQ.h"
107 #include "mhal_CEC.h"
108 #include "asmCPU.h"
109
110 extern MS_VIRT CEC_RIU_BASE;
111 extern InterruptNum gCECIRQ;
112 extern MS_U8 g_u8CecVendorID[3];
113 extern MS_U8 g_u8RetryCnt;
114
115 #define PM_REG_WRITE MDrv_WriteByte
116 #define PM_REG_READ MDrv_ReadByte
117
118
119 #define MST_XTAL_CLOCK_HZ (12000000UL) /* Temp define */
120
121 #define _NOP_ MAsm_CPU_Nop();
122
123 #if(defined(CONFIG_MLOG))
124 #include "ULog.h"
125
126 #define MHAL_CEC_MSG_INFO(format, args...) //ULOGI("CEC", format, ##args)
127 #define MHAL_CEC_MSG_WARNING(format, args...) ULOGW("CEC", format, ##args)
128 #define MHAL_CEC_MSG_DEBUG(format, args...) ULOGD("CEC", format, ##args)
129 #define MHAL_CEC_MSG_ERROR(format, args...) ULOGE("CEC", format, ##args)
130 #define MHAL_CEC_MSG_FATAL(format, args...) ULOGF("CEC", format, ##args)
131
132 #else
133 #define MHAL_CEC_MSG_INFO(format, args...) //printf(format, ##args)
134 #define MHAL_CEC_MSG_WARNING(format, args...) printf(format, ##args)
135 #define MHAL_CEC_MSG_DEBUG(format, args...) printf(format, ##args)
136 #define MHAL_CEC_MSG_ERROR(format, args...) printf(format, ##args)
137 #define MHAL_CEC_MSG_FATAL(format, args...) printf(format, ##args)
138
139 #endif
140
mhal_CEC_PortSelect(MsCEC_INPUT_PORT InputPort)141 void mhal_CEC_PortSelect(MsCEC_INPUT_PORT InputPort)
142 {
143
144 }
145
mhal_CEC_init_riu_base(MS_VIRT u32riu_base,MS_VIRT u32PMriu_base)146 void mhal_CEC_init_riu_base(MS_VIRT u32riu_base, MS_VIRT u32PMriu_base)
147 {
148 CEC_RIU_BASE = u32PMriu_base;
149 }
150
151
mhal_CEC_HeaderSwap(MS_U8 value)152 MS_U8 mhal_CEC_HeaderSwap(MS_U8 value)
153 {
154 return(((value&0x0f)<<4)+((value&0xf0)>>4));
155 }
156
mhal_CEC_SendFrame(MS_U8 header,MS_U8 opcode,MS_U8 * operand,MS_U8 len)157 MS_U8 mhal_CEC_SendFrame(MS_U8 header, MS_U8 opcode, MS_U8* operand, MS_U8 len)
158 {
159 MS_U8 i, cnt, *ptr, res;
160 MS_U8 u8waitcnt;
161
162 // clear CEC TX INT status
163 PM_REG_WRITE(H_BK_CEC(0x12), 0x0E);
164 PM_REG_WRITE(H_BK_CEC(0x12), 0x00);
165 PM_REG_WRITE( L_BK_CEC(0x18), header );
166 PM_REG_WRITE( H_BK_CEC(0x18), opcode );
167
168 MHAL_CEC_MSG_INFO("\r\n/******** CEC Tx **********/\r\n");
169 MHAL_CEC_MSG_INFO("CEC Tx FIFO= 0x%x", (MS_U8)header);
170 MHAL_CEC_MSG_INFO(" 0x%x", (MS_U8)opcode);
171
172 if(len > 0)
173 {
174 ptr=operand;
175 for(i=0;i<len;i++)
176 {
177 PM_REG_WRITE( L_BK_CEC(0x19)+i , *(ptr+i) );
178 MHAL_CEC_MSG_INFO(" 0x%x", *(operand+i));
179 }
180 MHAL_CEC_MSG_INFO("\r\n/**************************/\r\n");
181 }
182
183 if((PM_REG_READ(L_BK_CEC(0x05))== 1) && (PM_REG_READ(H_BK_CEC(0x05))== 0)) // CEC idle
184 {
185 MHAL_CEC_MSG_INFO("*** CEC idle!!! ***\n");
186
187 // CEC transmit length
188 //if((opcode==0x00)&&(operand==NULL)&&(len==0))
189 if((opcode==0x00)&&(len==0))
190 {
191 PM_REG_WRITE(L_BK_CEC(0x00), 0); //polling message
192 u8waitcnt = 5;
193 }
194 else
195 {
196 PM_REG_WRITE(L_BK_CEC(0x00), (len+1));
197 u8waitcnt = 4 * (len+2);
198 }
199
200 //The total time,
201 //(1). successful, 4.5 ms + 10 * 2.4 ms * N = 4.5 ms + 24 * N
202 // = 28.5 ms (1), or 52.5 ms (2), ....
203 //(2). NAK, (4.5 ms + 10 * 2.4 ms) * 1 + (4.5 ms + 10 * 2.4 ms +7.2 ms(3 bit time)) * retry (3)
204 // = 28.5 + 35.2 * 3 = 133.6 ms
205
206 cnt=0;
207 MsOS_DelayTask(20);
208
209 do
210 {
211 MsOS_DelayTask(10);
212 if(cnt++>=u8waitcnt)
213 break;
214 } while((PM_REG_READ(H_BK_CEC(0x11))&0x0E)==0);
215 res = (PM_REG_READ(H_BK_CEC(0x11))&0x0E);
216
217 if(cnt>=u8waitcnt)
218 res |= E_CEC_SYSTEM_BUSY;
219
220 // clear CEC TX INT status
221 PM_REG_WRITE(H_BK_CEC(0x12), 0x0E);
222 PM_REG_WRITE(H_BK_CEC(0x12), 0x00);
223 }
224 else
225 {
226 MHAL_CEC_MSG_INFO("*** system busy!!! ***\n");
227
228 res = E_CEC_SYSTEM_BUSY;
229 }
230
231 return res;
232 }
233
mhal_CEC_SendFramex(MS_U8 header,MS_U8 opcode,MS_U8 * operand,MS_U8 len)234 MS_U8 mhal_CEC_SendFramex(MS_U8 header, MS_U8 opcode, MS_U8* operand, MS_U8 len)
235 {
236 MS_U8 i, cnt, *ptr, res;
237 MS_U8 u8waitcnt;
238 volatile MS_U16 k, m;
239 // clear CEC TX INT status
240 PM_REG_WRITE(H_BK_CEC(0x12), 0x0E);
241 PM_REG_WRITE(H_BK_CEC(0x12), 0x00);
242 PM_REG_WRITE( L_BK_CEC(0x18), header );
243 PM_REG_WRITE( H_BK_CEC(0x18), opcode );
244
245 MHAL_CEC_MSG_INFO("\r\n/******** CEC Tx **********/\r\n");
246 MHAL_CEC_MSG_INFO("CEC Tx FIFO= 0x%x", (MS_U8)header);
247 MHAL_CEC_MSG_INFO(" 0x%x", (MS_U8)opcode);
248
249 if(len > 0)
250 {
251 ptr=operand;
252 for(i=0;i<len;i++)
253 {
254 PM_REG_WRITE( L_BK_CEC(0x19)+i , *(ptr+i) );
255 MHAL_CEC_MSG_INFO(" 0x%x", *(operand+i));
256 }
257 MHAL_CEC_MSG_INFO("\r\n/**************************/\r\n");
258 }
259
260 if((PM_REG_READ(L_BK_CEC(0x05))== 1) && (PM_REG_READ(H_BK_CEC(0x05))== 0)) // CEC idle
261 {
262 MHAL_CEC_MSG_INFO("*** CEC idle!!! ***\n");
263
264 // CEC transmit length
265 //if((opcode==0x00)&&(operand==NULL)&&(len==0))
266 if((opcode==0x00)&&(len==0))
267 {
268 PM_REG_WRITE(L_BK_CEC(0x00), 0); //polling message
269 u8waitcnt = 5;
270 }
271 else
272 {
273 PM_REG_WRITE(L_BK_CEC(0x00), (len+1));
274 u8waitcnt = 30;
275 }
276
277 //The total time,
278 //(1). successful, 4.5 ms + 10 * 2.4 ms * N = 4.5 ms + 24 * N
279 // = 28.5 ms (1), or 52.5 ms (2), ....
280 //(2). NAK, (4.5 ms + 10 * 2.4 ms) * 1 + (4.5 ms + 10 * 2.4 ms +7.2 ms(3 bit time)) * retry (3)
281 // = 28.5 + 35.2 * 3 = 133.6 ms
282
283
284 cnt=0;
285 //MsOS_DelayTask(20);
286 for(k = 0; k< 20000; k++)
287 {
288 _NOP_
289 _NOP_
290 _NOP_
291 }
292
293
294 do
295 {
296 //MsOS_DelayTask(10);
297 for(k = 0; k< 20000; k++)
298 {
299 for(m=0;m<50;m++)
300 {
301 _NOP_
302 _NOP_
303 _NOP_
304 _NOP_
305 _NOP_
306 }
307 }
308 if(cnt++>=u8waitcnt)
309 break;
310 } while((PM_REG_READ(H_BK_CEC(0x11))&0x0E)==0);
311
312 res = (PM_REG_READ(H_BK_CEC(0x11))&0x0E);
313
314 if(cnt>=u8waitcnt)
315 res |= E_CEC_SYSTEM_BUSY;
316
317 // clear CEC TX INT status
318 PM_REG_WRITE(H_BK_CEC(0x12), 0x0E);
319 PM_REG_WRITE(H_BK_CEC(0x12), 0x00);
320 }
321 else
322 {
323 MHAL_CEC_MSG_INFO("*** system busy!!! ***\n");
324
325 res = E_CEC_SYSTEM_BUSY;
326 }
327
328 return res;
329 }
330
331
mhal_CEC_SetMyAddress(MS_U8 mylogicaladdress)332 void mhal_CEC_SetMyAddress(MS_U8 mylogicaladdress)
333 {
334 PM_REG_WRITE(L_BK_CEC(0x02), (PM_REG_READ(L_BK_CEC(0x02)) & 0x0F) |(mylogicaladdress<<4));
335 }
336
mhal_CEC_INTEn(MS_BOOL bflag)337 void mhal_CEC_INTEn(MS_BOOL bflag)
338 {
339 if(bflag) // unmask
340 PM_REG_WRITE(L_BK_CEC(0x13), 0x1E); //REG_HDMI_INT_MASK
341
342 else // Mask CEC interrupt
343 #if ENABLE_CEC_MULTIPLE
344 PM_REG_WRITE(L_BK_CEC(0x13), 0x7F); //REG_HDMI_INT_MASK
345 #else
346 PM_REG_WRITE(L_BK_CEC(0x13), 0x1F); //REG_HDMI_INT_MASK
347 #endif
348
349 }
350
351
mhal_CEC_Init(MS_U32 u32XTAL_CLK_Hz)352 void mhal_CEC_Init(MS_U32 u32XTAL_CLK_Hz)
353 {
354 MS_U16 reg_val0, reg_val1;
355
356 #if ENABLE_CEC_INT
357
358 // CEC irq clear
359 PM_REG_WRITE(H_BK_CEC(0x12), 0x1F);
360 PM_REG_WRITE(H_BK_CEC(0x12), 0x00);
361 // CEC irq mask control -only enable CEC rx irq
362 PM_REG_WRITE(L_BK_CEC(0x13), 0x1E);
363 // CEC interrupt mask for PM/normal function
364 PM_REG_WRITE(L_BK_CEC(0x30), 0x08); // 11_30[3] = 1 Interrupt clear type select (Level), clear by itself
365
366 gCECIRQ = E_INT_IRQ_CEC; // IRQ52
367 #endif
368
369 PM_REG_WRITE(L_BK_CEC(0x14),0x01); // [1]: clock source from Xtal;[0]: Power down CEC controller select
370 PM_REG_WRITE(H_BK_CEC(0x03),PM_REG_READ(H_BK_CEC(0x03))&(~ BIT(4))); // [4]: Standby mode;
371 PM_REG_WRITE(H_BK_CEC(0x00),0x10|RETRY_CNT); // retry times
372 PM_REG_WRITE(L_BK_CEC(0x01),0x80); // [5]:CEC clock no gate; [7]: Enable CEC controller
373 PM_REG_WRITE(H_BK_CEC(0x01),(BusFreeTime<<4)|(ReTxInterval)); // CNT1=ReTxInterval; CNT2=BusFreeTime;
374 PM_REG_WRITE(L_BK_CEC(0x02),(E_LA_TV<<4)|(FrameInterval)); // CNT3=FrameInterval; [7:4]=logical address: TV
375 #if ENABLE_CEC_MULTIPLE
376 PM_REG_WRITE(L_BK_CEC(0x30),PM_REG_READ(L_BK_CEC(0x30))|BIT(0)); // enable CEC multiple function
377 #endif
378 reg_val0=(MST_XTAL_CLOCK_HZ%100000l)*0.00016+0.5;
379 PM_REG_WRITE(H_BK_CEC(0x02),(MST_XTAL_CLOCK_HZ/100000l)); // CEC time unit by Xtal(integer)
380 reg_val1 = PM_REG_READ(L_BK_CEC(0x03));
381 PM_REG_WRITE(L_BK_CEC(0x03), ((reg_val1 & 0xF0) | reg_val0)); // CEC time unit by Xtal(fractional)
382
383 PM_REG_WRITE(L_BK_CEC(0x11), 0xFF); // clear CEC status
384
385
386 }
387
mhal_CEC_IsMessageReceived(void)388 MS_BOOL mhal_CEC_IsMessageReceived(void)
389 {
390 return (PM_REG_READ(H_BK_CEC(0x11))& 0x01 ? TRUE : FALSE);
391 }
392
mhal_CEC_ReceivedMessageLen(void)393 MS_U8 mhal_CEC_ReceivedMessageLen(void)
394 {
395 return ((PM_REG_READ(L_BK_CEC(0x04)) & 0x1F) + 1);
396 }
397
mhal_CEC_GetMessageByte(MS_U8 idx)398 MS_U8 mhal_CEC_GetMessageByte(MS_U8 idx)
399 {
400 return (PM_REG_READ(L_BK_CEC(0x20) + idx));
401 }
402
mhal_CEC_ClearRxStatus(void)403 void mhal_CEC_ClearRxStatus(void)
404 {
405 // clear RX INT status
406 PM_REG_WRITE(H_BK_CEC(0x12), 0x11);
407 PM_REG_WRITE(H_BK_CEC(0x12), 0x00);
408 // clear RX NACK status
409 PM_REG_WRITE(L_BK_CEC(0x11), 0xFF);
410 }
411
412 /***************************************************************************************/
413 /// config cec wake up
414 /***************************************************************************************/
415
mhal_CEC_ConfigWakeUp(void)416 void mhal_CEC_ConfigWakeUp(void)
417 {
418 MS_U16 reg_val0, reg_val1;
419 MHAL_CEC_MSG_INFO("\r\n Here do the PM config cec wakeup \r\n");
420
421 //XBYTE[0x250C] &= ~BIT0;
422 MDrv_WriteByte( REG_COMBO_PHY0_P0_0C_H, MDrv_ReadByte(REG_COMBO_PHY0_P0_0C_H) &(~ BIT(4)));
423
424
425 //(1) enable chiptop clk_mcu & clk_pram
426 #if 0
427 XBYTE[0x0E00] = 0x03;
428 //enable PM_Sleep's clk_mcu and _pram
429 Drv_WriteByte(L_BK_PMSLP(0x00), 0x03);
430 XBYTE[0x0E01] = 0x0F;
431 //0x0C; Ken 20080916 for calibration to 1Mz
432 MDrv_WriteByte(H_BK_PMSLP(0x00), 0x0F);
433 #endif
434
435
436 //(2) HDMI CEC settings
437 PM_REG_WRITE(H_BK_CEC(0x00),0x10|g_u8RetryCnt); // retry times
438 PM_REG_WRITE(L_BK_CEC(0x01),0x80); // [5]:CEC clock no gate; [7]: Enable CEC controller
439 PM_REG_WRITE(H_BK_CEC(0x01),0x63); // CNT1=3; CNT2 = 6;
440 PM_REG_WRITE(L_BK_CEC(0x02),0x07); // CNT3=7; logical address: TV
441
442 reg_val0=(MST_XTAL_CLOCK_HZ%100000l)*0.00016+0.5;
443 PM_REG_WRITE(H_BK_CEC(0x02),(MST_XTAL_CLOCK_HZ/100000l)); // CEC time unit by Xtal(integer)
444
445 reg_val1 = PM_REG_READ(L_BK_CEC(0x03));
446 PM_REG_WRITE(L_BK_CEC(0x03), ((reg_val1 & 0xF0) | reg_val0)); // CEC time unit by Xtal(fractional)
447
448
449 //(3) PM Sleep: wakeup enable sources
450 //PM_REG_WRITE(L_BK_PMMCU(0x00),0x01); // reg_cec_enw
451
452
453 //(4) PM CEC power down controller settings
454 // Mask CEC interrupt in standby mode
455 PM_REG_WRITE(L_BK_CEC(0x13),0xFF);
456 // select power down SW CEC controller
457 PM_REG_WRITE(L_BK_CEC(0x14),0x01); // [1]: clock source from Xtal;[0]: Power down CEC controller select
458 PM_REG_WRITE(L_BK_CEC(0x01),0x00); // [5]:CEC clock no gate; [7]: Disable CEC controller
459 PM_REG_WRITE(L_BK_CEC(0x01),0x80); // [5]:CEC clock no gate; [7]: Enable CEC controller
460 #if 0//ENABLE_SW_CEC_WAKEUP
461 PM_REG_WRITE(H_BK_CEC(0x03),PM_REG_READ(H_BK_CEC(0x03))&(~ BIT(4))); // [4]: Standby mode;
462 #else
463 PM_REG_WRITE(H_BK_CEC(0x03),PM_REG_READ(H_BK_CEC(0x03))|(BIT(4))); // [4]: sleep mode;
464 #endif
465
466
467 //(5) PM CEC wakeup opcode settings
468 // OPCODE0: 0x04(Image view on)
469 // OPCODE1: 0x0D(Text view on)
470 // OPCODE2: 0x44 0x40(Power)
471 // 0x44 0x6D(Power ON Function)
472 // OPCODE3: N/A
473 // OPCODE4: 0x82(Active source) length = 2
474 PM_REG_WRITE(L_BK_CEC(0x07), 0x37); // Enable OP0~2 and OP4
475 PM_REG_WRITE(H_BK_CEC(0x07), 0x24); // Eanble OPCODE2's operand
476
477 PM_REG_WRITE(L_BK_CEC(0x08), E_MSG_OTP_IMAGE_VIEW_ON); // OPCODE0: Image View On
478 PM_REG_WRITE(H_BK_CEC(0x08), E_MSG_OTP_TEXT_VIEW_ON); // OPCODE1: Text View ON
479
480 PM_REG_WRITE(L_BK_CEC(0x09), E_MSG_UI_PRESS); // OPCODE2: E_MSG_UI_PRESS
481 PM_REG_WRITE(H_BK_CEC(0x0B), E_MSG_UI_POWER); // OPCODE2 operand: Power
482 PM_REG_WRITE(L_BK_CEC(0x0C), E_MSG_UI_POWER_ON_FUN); // OPCODE2 operand: Power ON
483
484 PM_REG_WRITE(L_BK_CEC(0x0A), E_MSG_ACTIVE_SOURCE); // OPCODE4: Active source
485
486 // [2:0]: CEC version 1.4; [7]: OP4 is broadcast message
487 PM_REG_WRITE(H_BK_CEC(0x0D), 0x80 | HDMI_CEC_VERSION);
488
489
490 //(6) Device(TV) Vendor ID for customer (Big Endian)
491 // It depends end-customer's vendor ID
492 MHAL_CEC_MSG_INFO("!!!!!!!!!!!!!!!!!!!Change this Vendor ID according to customer!!!!!!!!!!!!!!!!\n");
493 PM_REG_WRITE(L_BK_CEC(0x0F), g_u8CecVendorID[0]); // Device Vendor ID
494 PM_REG_WRITE(H_BK_CEC(0x0F), g_u8CecVendorID[1]); // Device Vendor ID
495 PM_REG_WRITE(L_BK_CEC(0x10), g_u8CecVendorID[2]); // Device Vendor ID
496
497 // [2:0]: Feature abort reason - "Not in correct mode to respond"
498 PM_REG_WRITE(H_BK_CEC(0x10), E_MSG_AR_CANNOTRESPOND );
499
500
501 //(7) Device Physical address: default is 0x00 0x00 0x00
502 PM_REG_WRITE(L_BK_CEC(0x0E), 0x00); // Physical address 0.0
503 PM_REG_WRITE(H_BK_CEC(0x0E), 0x00); // Physical address 0.0
504 PM_REG_WRITE(H_BK_CEC(0x14), 0x00); // Device type: TV
505
506
507 //(8) Clear CEC status
508 PM_REG_WRITE(L_BK_CEC(0x11), 0x7F); // Clear CEC wakeup status
509 PM_REG_WRITE(H_BK_CEC(0x12), 0x1F); // Clear RX/TX/RF/LA/NACK status status
510 PM_REG_WRITE(H_BK_CEC(0x12), 0x00);
511 }
512
mhal_CEC_Enabled(MS_BOOL bEnableFlag)513 void mhal_CEC_Enabled(MS_BOOL bEnableFlag)
514 {
515 if(bEnableFlag)
516 PM_REG_WRITE(L_BK_CEC(0x01),0x80); //Enable PM CEC controller
517 else
518 PM_REG_WRITE(L_BK_CEC(0x01),0x00); //Disable PM CEC controller
519 }
520
mhal_CEC_TxStatus(void)521 MS_U8 mhal_CEC_TxStatus(void)
522 {
523 return (PM_REG_READ(H_BK_CEC(0x11))&0x0E);
524 }
525
mhal_CEC_Device_Is_Tx(void)526 MS_BOOL mhal_CEC_Device_Is_Tx(void)
527 {
528 return CEC_DEVICE_IS_SOURCE;
529 }
530