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92 //
93 // File Name: mhal_CEC.c
94 // Description: For CEC functions.
95 ////////////////////////////////////////////////////////////////////////////////
96
97
98 #define _MHAL_CEC_C_
99
100 #ifdef MSOS_TYPE_LINUX_KERNEL
101 #include <linux/string.h>
102 #else
103 #include "string.h"
104 #endif
105 #include "MsCommon.h"
106 #include "cec_hwreg_utility2.h"
107 #include "cec_Analog_Reg.h"
108 #include "MsOS.h"
109 #include "apiCEC.h"
110 #include "MsIRQ.h"
111 #include "mhal_CEC.h"
112 #include "asmCPU.h"
113
114 MS_VIRT CEC_RIU_BASE;
115
116 #define PM_REG_WRITE MDrv_WriteByte
117 #define PM_REG_READ MDrv_ReadByte
118
119
120 #define MST_XTAL_CLOCK_HZ (12000000UL) /* Temp define */
121
122 #define _NOP_ MAsm_CPU_Nop();
123
124 #if(defined(CONFIG_MLOG))
125 #include "ULog.h"
126
127 #define MHAL_CEC_MSG_INFO(format, args...) //ULOGI("CEC", format, ##args)
128 #define MHAL_CEC_MSG_WARNING(format, args...) ULOGW("CEC", format, ##args)
129 #define MHAL_CEC_MSG_DEBUG(format, args...) ULOGD("CEC", format, ##args)
130 #define MHAL_CEC_MSG_ERROR(format, args...) ULOGE("CEC", format, ##args)
131 #define MHAL_CEC_MSG_FATAL(format, args...) ULOGF("CEC", format, ##args)
132
133 #else
134 #define MHAL_CEC_MSG_INFO(format, args...) //printf(format, ##args)
135 #define MHAL_CEC_MSG_WARNING(format, args...) printf(format, ##args)
136 #define MHAL_CEC_MSG_DEBUG(format, args...) printf(format, ##args)
137 #define MHAL_CEC_MSG_ERROR(format, args...) printf(format, ##args)
138 #define MHAL_CEC_MSG_FATAL(format, args...) printf(format, ##args)
139
140 #endif
141
mhal_CEC_PortSelect(MsCEC_INPUT_PORT InputPort)142 void mhal_CEC_PortSelect(MsCEC_INPUT_PORT InputPort)
143 {
144
145 }
146
mhal_CEC_init_riu_base(MS_VIRT u32riu_base,MS_VIRT u32PMriu_base)147 void mhal_CEC_init_riu_base(MS_VIRT u32riu_base, MS_VIRT u32PMriu_base)
148 {
149 CEC_RIU_BASE = u32PMriu_base;
150 }
151
152
mhal_CEC_HeaderSwap(MS_U8 value)153 MS_U8 mhal_CEC_HeaderSwap(MS_U8 value)
154 {
155 return(((value&0x0f)<<4)+((value&0xf0)>>4));
156 }
157
mhal_CEC_SendFrame(MS_U8 header,MS_U8 opcode,MS_U8 * operand,MS_U8 len)158 MS_U8 mhal_CEC_SendFrame(MS_U8 header, MS_U8 opcode, MS_U8* operand, MS_U8 len)
159 {
160 MS_U8 i, cnt, *ptr, res;
161 MS_U8 u8waitcnt;
162
163 // clear CEC TX INT status
164 PM_REG_WRITE(H_BK_CEC(0x12), 0x0E);
165 PM_REG_WRITE(H_BK_CEC(0x12), 0x00);
166 PM_REG_WRITE( L_BK_CEC(0x18), header );
167 PM_REG_WRITE( H_BK_CEC(0x18), opcode );
168
169 MHAL_CEC_MSG_INFO("\r\n/******** CEC Tx **********/\r\n");
170 MHAL_CEC_MSG_INFO("CEC Tx FIFO= 0x%x", (MS_U8)header);
171 MHAL_CEC_MSG_INFO(" 0x%x", (MS_U8)opcode);
172
173 if(len > 0)
174 {
175 ptr=operand;
176 for(i=0;i<len;i++)
177 {
178 PM_REG_WRITE( L_BK_CEC(0x19)+i , *(ptr+i) );
179 MHAL_CEC_MSG_INFO(" 0x%x", *(operand+i));
180 }
181 MHAL_CEC_MSG_INFO("\r\n/**************************/\r\n");
182 }
183
184 if((PM_REG_READ(L_BK_CEC(0x05))== 1) && (PM_REG_READ(H_BK_CEC(0x05))== 0)) // CEC idle
185 {
186 MHAL_CEC_MSG_INFO("*** CEC idle!!! ***\n");
187
188 // CEC transmit length
189 //if((opcode==0x00)&&(operand==NULL)&&(len==0))
190 if((opcode==0x00)&&(len==0))
191 {
192 PM_REG_WRITE(L_BK_CEC(0x00), 0); //polling message
193 u8waitcnt = 5;
194 }
195 else
196 {
197 PM_REG_WRITE(L_BK_CEC(0x00), (len+1));
198 u8waitcnt = 4 * (len+2);
199 }
200
201 //The total time,
202 //(1). successful, 4.5 ms + 10 * 2.4 ms * N = 4.5 ms + 24 * N
203 // = 28.5 ms (1), or 52.5 ms (2), ....
204 //(2). NAK, (4.5 ms + 10 * 2.4 ms) * 1 + (4.5 ms + 10 * 2.4 ms +7.2 ms(3 bit time)) * retry (3)
205 // = 28.5 + 35.2 * 3 = 133.6 ms
206
207 cnt=0;
208 MsOS_DelayTask(20);
209
210 do
211 {
212 MsOS_DelayTask(10);
213 if(cnt++>=u8waitcnt)
214 break;
215 } while((PM_REG_READ(H_BK_CEC(0x11))&0x0E)==0);
216 res = (PM_REG_READ(H_BK_CEC(0x11))&0x0E);
217
218 if(cnt>=u8waitcnt)
219 res |= E_CEC_SYSTEM_BUSY;
220
221 // clear CEC TX INT status
222 PM_REG_WRITE(H_BK_CEC(0x12), 0x0E);
223 PM_REG_WRITE(H_BK_CEC(0x12), 0x00);
224 }
225 else
226 {
227 MHAL_CEC_MSG_INFO("*** system busy!!! ***\n");
228
229 res = E_CEC_SYSTEM_BUSY;
230 }
231
232 return res;
233 }
234
mhal_CEC_SendFramex(MS_U8 header,MS_U8 opcode,MS_U8 * operand,MS_U8 len)235 MS_U8 mhal_CEC_SendFramex(MS_U8 header, MS_U8 opcode, MS_U8* operand, MS_U8 len)
236 {
237 MS_U8 i, cnt, *ptr, res;
238 MS_U8 u8waitcnt;
239 volatile MS_U16 k, m;
240 // clear CEC TX INT status
241 PM_REG_WRITE(H_BK_CEC(0x12), 0x0E);
242 PM_REG_WRITE(H_BK_CEC(0x12), 0x00);
243 PM_REG_WRITE( L_BK_CEC(0x18), header );
244 PM_REG_WRITE( H_BK_CEC(0x18), opcode );
245
246 MHAL_CEC_MSG_INFO("\r\n/******** CEC Tx **********/\r\n");
247 MHAL_CEC_MSG_INFO("CEC Tx FIFO= 0x%x", (MS_U8)header);
248 MHAL_CEC_MSG_INFO(" 0x%x", (MS_U8)opcode);
249
250 if(len > 0)
251 {
252 ptr=operand;
253 for(i=0;i<len;i++)
254 {
255 PM_REG_WRITE( L_BK_CEC(0x19)+i , *(ptr+i) );
256 MHAL_CEC_MSG_INFO(" 0x%x", *(operand+i));
257 }
258 MHAL_CEC_MSG_INFO("\r\n/**************************/\r\n");
259 }
260
261 if((PM_REG_READ(L_BK_CEC(0x05))== 1) && (PM_REG_READ(H_BK_CEC(0x05))== 0)) // CEC idle
262 {
263 MHAL_CEC_MSG_INFO("*** CEC idle!!! ***\n");
264
265 // CEC transmit length
266 //if((opcode==0x00)&&(operand==NULL)&&(len==0))
267 if((opcode==0x00)&&(len==0))
268 {
269 PM_REG_WRITE(L_BK_CEC(0x00), 0); //polling message
270 u8waitcnt = 5;
271 }
272 else
273 {
274 PM_REG_WRITE(L_BK_CEC(0x00), (len+1));
275 u8waitcnt = 30;
276 }
277
278 //The total time,
279 //(1). successful, 4.5 ms + 10 * 2.4 ms * N = 4.5 ms + 24 * N
280 // = 28.5 ms (1), or 52.5 ms (2), ....
281 //(2). NAK, (4.5 ms + 10 * 2.4 ms) * 1 + (4.5 ms + 10 * 2.4 ms +7.2 ms(3 bit time)) * retry (3)
282 // = 28.5 + 35.2 * 3 = 133.6 ms
283
284
285 cnt=0;
286 //MsOS_DelayTask(20);
287 for(k = 0; k< 20000; k++)
288 {
289 _NOP_
290 _NOP_
291 _NOP_
292 }
293
294
295 do
296 {
297 //MsOS_DelayTask(10);
298 for(k = 0; k< 20000; k++)
299 {
300 for(m=0;m<50;m++)
301 {
302 _NOP_
303 _NOP_
304 _NOP_
305 _NOP_
306 _NOP_
307 }
308 }
309 if(cnt++>=u8waitcnt)
310 break;
311 } while((PM_REG_READ(H_BK_CEC(0x11))&0x0E)==0);
312
313 res = (PM_REG_READ(H_BK_CEC(0x11))&0x0E);
314
315 if(cnt>=u8waitcnt)
316 res |= E_CEC_SYSTEM_BUSY;
317
318 // clear CEC TX INT status
319 PM_REG_WRITE(H_BK_CEC(0x12), 0x0E);
320 PM_REG_WRITE(H_BK_CEC(0x12), 0x00);
321 }
322 else
323 {
324 MHAL_CEC_MSG_INFO("*** system busy!!! ***\n");
325
326 res = E_CEC_SYSTEM_BUSY;
327 }
328
329 return res;
330 }
331
332
mhal_CEC_SetMyAddress(MS_U8 mylogicaladdress)333 void mhal_CEC_SetMyAddress(MS_U8 mylogicaladdress)
334 {
335 PM_REG_WRITE(L_BK_CEC(0x02), (PM_REG_READ(L_BK_CEC(0x02)) & 0x0F) |(mylogicaladdress<<4));
336 }
337
mhal_CEC_INTEn(MS_BOOL bflag)338 void mhal_CEC_INTEn(MS_BOOL bflag)
339 {
340 if(bflag) // unmask
341 PM_REG_WRITE(L_BK_CEC(0x13), 0x1E); //REG_HDMI_INT_MASK
342
343 else // Mask CEC interrupt
344 #if ENABLE_CEC_MULTIPLE
345 PM_REG_WRITE(L_BK_CEC(0x13), 0x7F); //REG_HDMI_INT_MASK
346 #else
347 PM_REG_WRITE(L_BK_CEC(0x13), 0x1F); //REG_HDMI_INT_MASK
348 #endif
349
350 }
351
352
mhal_CEC_Init(MS_U32 u32XTAL_CLK_Hz,MsCEC_DEVICELA DeviceLA,MS_U8 ucRetryCnt)353 void mhal_CEC_Init(MS_U32 u32XTAL_CLK_Hz, MsCEC_DEVICELA DeviceLA, MS_U8 ucRetryCnt)
354 {
355 MS_U16 reg_val0, reg_val1;
356
357 #if ENABLE_CEC_INT
358
359 // CEC irq clear
360 PM_REG_WRITE(H_BK_CEC(0x12), 0x1F);
361 PM_REG_WRITE(H_BK_CEC(0x12), 0x00);
362 // CEC irq mask control -only enable CEC rx irq
363 PM_REG_WRITE(L_BK_CEC(0x13), 0x1E);
364 // CEC interrupt mask for PM/normal function
365 PM_REG_WRITE(L_BK_CEC(0x30), 0x08); // 11_30[3] = 1 Interrupt clear type select (Level), clear by itself
366
367 #endif
368
369 PM_REG_WRITE(L_BK_CEC(0x14),0x01); // [1]: clock source from Xtal;[0]: Power down CEC controller select
370 PM_REG_WRITE(H_BK_CEC(0x03),PM_REG_READ(H_BK_CEC(0x03))&(~ BIT(4))); // [4]: Standby mode;
371 PM_REG_WRITE(H_BK_CEC(0x00),0x10|ucRetryCnt); // retry times
372 PM_REG_WRITE(L_BK_CEC(0x01),0x80); // [5]:CEC clock no gate; [7]: Enable CEC controller
373 PM_REG_WRITE(H_BK_CEC(0x01),(BusFreeTime<<4)|(ReTxInterval)); // CNT1=ReTxInterval; CNT2=BusFreeTime;
374 PM_REG_WRITE(L_BK_CEC(0x02),(DeviceLA<<4)|(FrameInterval)); // CNT3=FrameInterval; [7:4]=logical address: TV
375 #if ENABLE_CEC_MULTIPLE
376 PM_REG_WRITE(L_BK_CEC(0x30),PM_REG_READ(L_BK_CEC(0x30))|BIT(0)); // enable CEC multiple function
377 #endif
378 //reg_val0=(u32XTAL_CLK_Hz%100000l)*0.00016+0.5;
379 reg_val0=((u32XTAL_CLK_Hz%100000UL)*160+500000UL)/1000000UL;
380
381 PM_REG_WRITE(H_BK_CEC(0x02),(u32XTAL_CLK_Hz/100000UL)); // CEC time unit by Xtal(integer)
382 reg_val1 = PM_REG_READ(L_BK_CEC(0x03));
383 PM_REG_WRITE(L_BK_CEC(0x03), ((reg_val1 & 0xF0) | reg_val0)); // CEC time unit by Xtal(fractional)
384
385 PM_REG_WRITE(L_BK_CEC(0x11), 0xFF); // clear CEC status
386
387
388 }
389
mhal_CEC_IsMessageReceived(void)390 MS_BOOL mhal_CEC_IsMessageReceived(void)
391 {
392 return (PM_REG_READ(H_BK_CEC(0x11))& 0x01 ? TRUE : FALSE);
393 }
394
mhal_CEC_ReceivedMessageLen(void)395 MS_U8 mhal_CEC_ReceivedMessageLen(void)
396 {
397 return ((PM_REG_READ(L_BK_CEC(0x04)) & 0x1F) + 1);
398 }
399
mhal_CEC_GetMessageByte(MS_U8 idx)400 MS_U8 mhal_CEC_GetMessageByte(MS_U8 idx)
401 {
402 return (PM_REG_READ(L_BK_CEC(0x20) + idx));
403 }
404
mhal_CEC_ClearRxStatus(void)405 void mhal_CEC_ClearRxStatus(void)
406 {
407 // clear RX INT status
408 PM_REG_WRITE(H_BK_CEC(0x12), 0x11);
409 PM_REG_WRITE(H_BK_CEC(0x12), 0x00);
410 // clear RX NACK status
411 PM_REG_WRITE(L_BK_CEC(0x11), 0xFF);
412 }
413
414 /***************************************************************************************/
415 /// config cec wake up
416 /***************************************************************************************/
417
mhal_CEC_ConfigWakeUp(MS_U8 ucRetryCount,MS_U8 * ucVendorID,MS_U32 u32XTAL_CLK_Hz,MS_U8 * ucPA,MsCEC_DEVICE_TYPE eType,MS_BOOL bIsSrc)418 void mhal_CEC_ConfigWakeUp(MS_U8 ucRetryCount, MS_U8* ucVendorID, MS_U32 u32XTAL_CLK_Hz, MS_U8* ucPA, MsCEC_DEVICE_TYPE eType, MS_BOOL bIsSrc)
419 {
420 MS_U16 reg_val0, reg_val1;
421 MHAL_CEC_MSG_INFO("\r\n Here do the PM config cec wakeup \r\n");
422
423 //XBYTE[0x250C] &= ~BIT0;
424 MDrv_WriteByte( REG_COMBO_PHY0_P0_0C_H, MDrv_ReadByte(REG_COMBO_PHY0_P0_0C_H) &(~ BIT(4)));
425
426
427 //(1) enable chiptop clk_mcu & clk_pram
428 #if 0
429 XBYTE[0x0E00] = 0x03;
430 //enable PM_Sleep's clk_mcu and _pram
431 Drv_WriteByte(L_BK_PMSLP(0x00), 0x03);
432 XBYTE[0x0E01] = 0x0F;
433 //0x0C; Ken 20080916 for calibration to 1Mz
434 MDrv_WriteByte(H_BK_PMSLP(0x00), 0x0F);
435 #endif
436
437
438 //(2) HDMI CEC settings
439 PM_REG_WRITE(H_BK_CEC(0x00),0x10|ucRetryCount); // retry times
440 PM_REG_WRITE(L_BK_CEC(0x01),0x80); // [5]:CEC clock no gate; [7]: Enable CEC controller
441 PM_REG_WRITE(H_BK_CEC(0x01),(BusFreeTime<<4)|(ReTxInterval)); // CNT1=ReTxInterval; CNT2=BusFreeTime;
442 //PM_REG_WRITE(L_BK_CEC(0x02),0x07); // CNT3=7; logical address: TV
443
444 //reg_val0=(MST_XTAL_CLOCK_HZ%100000l)*0.00016+0.5;
445 reg_val0=((u32XTAL_CLK_Hz%100000UL)*160+500000UL)/1000000UL;
446
447 PM_REG_WRITE(H_BK_CEC(0x02),(u32XTAL_CLK_Hz/100000l)); // CEC time unit by Xtal(integer)
448
449 reg_val1 = PM_REG_READ(L_BK_CEC(0x03));
450 PM_REG_WRITE(L_BK_CEC(0x03), ((reg_val1 & 0xF0) | reg_val0)); // CEC time unit by Xtal(fractional)
451
452
453 //(3) PM Sleep: wakeup enable sources
454 //PM_REG_WRITE(L_BK_PMMCU(0x00),0x01); // reg_cec_enw
455
456
457 //(4) PM CEC power down controller settings
458 // Mask CEC interrupt in standby mode
459 PM_REG_WRITE(L_BK_CEC(0x13),0xFF);
460 // select power down SW CEC controller
461 PM_REG_WRITE(L_BK_CEC(0x14),0x01); // [1]: clock source from Xtal;[0]: Power down CEC controller select
462 PM_REG_WRITE(L_BK_CEC(0x01),0x00); // [5]:CEC clock no gate; [7]: Disable CEC controller
463 PM_REG_WRITE(L_BK_CEC(0x01),0x80); // [5]:CEC clock no gate; [7]: Enable CEC controller
464 #if 0//ENABLE_SW_CEC_WAKEUP
465 PM_REG_WRITE(H_BK_CEC(0x03),PM_REG_READ(H_BK_CEC(0x03))&(~ BIT(4))); // [4]: Standby mode;
466 #else
467 PM_REG_WRITE(H_BK_CEC(0x03),PM_REG_READ(H_BK_CEC(0x03))|(BIT(4))); // [4]: sleep mode;
468 #endif
469
470 if(bIsSrc) // STB
471 {
472 //(5) PM CEC wakeup opcode settings
473 // OPCODE0: N/A
474 // OPCODE1: N/A
475 // OPCODE2: 0x44 0x40(Power)
476 // 0x44 0x6D(Power ON Function)
477 // OPCODE3: N/A
478 // OPCODE4: 0x86(Set stream path)
479 PM_REG_WRITE(L_BK_CEC(0x07), 0x34); // Enable OP2 and OP4
480 PM_REG_WRITE(H_BK_CEC(0x07), 0x24); // Eanble OPCODE2's operand
481
482 PM_REG_WRITE(L_BK_CEC(0x09), E_MSG_UI_PRESS); // OPCODE2: User Control Pressed
483 PM_REG_WRITE(H_BK_CEC(0x0B), E_MSG_UI_POWER); // OPCODE2 operand: Power
484 PM_REG_WRITE(L_BK_CEC(0x0C), E_MSG_UI_POWER_ON_FUN); // OPCODE2 operand: Power ON Function
485
486 PM_REG_WRITE(L_BK_CEC(0x0A), E_MSG_RC_SET_STREM_PATH); // OPCODE4: Set stream path
487
488 // [2:0]: CEC version 1.4; [7]: OP4 is broadcast message
489 PM_REG_WRITE(H_BK_CEC(0x0D), 0x80 | HDMI_CEC_VERSION);
490
491
492 //(6) Device(TV) Vendor ID for customer (Big Endian)
493 // It depends end-customer's vendor ID
494 MHAL_CEC_MSG_INFO("!!!!!!!!!!!!!!!!!!!Change this Vendor ID according to customer!!!!!!!!!!!!!!!!\n");
495 PM_REG_WRITE(L_BK_CEC(0x0F), ucVendorID[0]); // Device Vendor ID
496 PM_REG_WRITE(H_BK_CEC(0x0F), ucVendorID[1]); // Device Vendor ID
497 PM_REG_WRITE(L_BK_CEC(0x10), ucVendorID[2]); // Device Vendor ID
498
499 // ignore messages sent from initiator LA = 0xF when sleep mode
500 // [10:8]: Feature abort reason - "Not in correct mode to respond"
501 PM_REG_WRITE(H_BK_CEC(0x10), BIT(7)|(0xF<<3)|E_MSG_AR_CANNOTRESPOND ); // pm_CEC_10[14:11]: reg_ignor_addr_sw; [15]: reg_ignor_enb_sw
502
503
504 //(7) Device Physical address: default is 0x00 0x00 0x00
505 PM_REG_WRITE(L_BK_CEC(0x0E), ucPA[0]); // Physical address
506 PM_REG_WRITE(H_BK_CEC(0x0E), ucPA[1]); // Physical address
507 PM_REG_WRITE(H_BK_CEC(0x14), eType & 0xFF); // Device type
508 }
509 else // TV
510 {
511 PM_REG_WRITE(L_BK_CEC(0x02),0x07); // CNT3=7; logical address: TV
512
513 //(5) PM CEC wakeup opcode settings
514 // OPCODE0: 0x04(Image view on)
515 // OPCODE1: 0x0D(Text view on)
516 // OPCODE2: 0x44 0x40(Power)
517 // 0x44 0x6D(Power ON Function)
518 // OPCODE3: N/A
519 // OPCODE4: 0x82(Active source) length = 2 (HDMI2.0 removed)
520 PM_REG_WRITE(L_BK_CEC(0x07), 0x27); // pm_CEC_07[4:0]: Enable OP0~2, disable OP3~4; [5]: OP2 second operand enable
521 PM_REG_WRITE(H_BK_CEC(0x07), 0x04); // pm_CEC_07[11:8]: Eanble OP2 operand; [15:12]: disable OP4 length
522
523 PM_REG_WRITE(L_BK_CEC(0x08), E_MSG_OTP_IMAGE_VIEW_ON); // OPCODE0: Image View On
524 PM_REG_WRITE(H_BK_CEC(0x08), E_MSG_OTP_TEXT_VIEW_ON); // OPCODE1: Text View ON
525
526 PM_REG_WRITE(L_BK_CEC(0x09), E_MSG_UI_PRESS); // OPCODE2: User Control Pressed
527 PM_REG_WRITE(H_BK_CEC(0x0B), E_MSG_UI_POWER); // OPCODE2 operand: Power
528 PM_REG_WRITE(L_BK_CEC(0x0C), E_MSG_UI_POWER_ON_FUN); // OPCODE2 operand: Power ON Function
529
530 //PM_REG_WRITE(L_BK_CEC(0x0A), E_MSG_ACTIVE_SOURCE); // OPCODE4: Active source (HDMI2.0 removed)
531
532 // [2:0]: CEC version 1.4; [7]: OP4 is broadcast message
533 PM_REG_WRITE(H_BK_CEC(0x0D), 0x80 | HDMI_CEC_VERSION);
534
535
536 //(6) Device(TV) Vendor ID for customer (Big Endian)
537 // It depends end-customer's vendor ID
538 MHAL_CEC_MSG_INFO("!!!!!!!!!!!!!!!!!!!Change this Vendor ID according to customer!!!!!!!!!!!!!!!!\n");
539 PM_REG_WRITE(L_BK_CEC(0x0F), ucVendorID[0]); // Device Vendor ID
540 PM_REG_WRITE(H_BK_CEC(0x0F), ucVendorID[1]); // Device Vendor ID
541 PM_REG_WRITE(L_BK_CEC(0x10), ucVendorID[2]); // Device Vendor ID
542
543 // ignore messages sent from initiator LA = 0xF when sleep mode
544 // [10:8]: Feature abort reason - "Not in correct mode to respond"
545 PM_REG_WRITE(H_BK_CEC(0x10), BIT(7)|(0xF<<3)|E_MSG_AR_CANNOTRESPOND ); // pm_CEC_10[14:11]: reg_ignor_addr_sw; [15]: reg_ignor_enb_sw
546
547
548 //(7) Device Physical address: default is 0x00 0x00 0x00
549 PM_REG_WRITE(L_BK_CEC(0x0E), 0x00); // Physical address 0.0
550 PM_REG_WRITE(H_BK_CEC(0x0E), 0x00); // Physical address 0.0
551 PM_REG_WRITE(H_BK_CEC(0x14), 0x00); // Device type: TV
552 }
553
554
555 //(8) Clear CEC status
556 PM_REG_WRITE(L_BK_CEC(0x11), 0xFF); // Clear CEC wakeup status
557 PM_REG_WRITE(H_BK_CEC(0x12), 0x1F); // Clear RX/TX/RF/LA/NACK status status
558 PM_REG_WRITE(H_BK_CEC(0x12), 0x00);
559 }
560
mhal_CEC_Enabled(MS_BOOL bEnableFlag)561 void mhal_CEC_Enabled(MS_BOOL bEnableFlag)
562 {
563 if(bEnableFlag)
564 PM_REG_WRITE(L_BK_CEC(0x01),0x80); //Enable PM CEC controller
565 else
566 PM_REG_WRITE(L_BK_CEC(0x01),0x00); //Disable PM CEC controller
567 }
568
mhal_CEC_TxStatus(void)569 MS_U8 mhal_CEC_TxStatus(void)
570 {
571 return (PM_REG_READ(H_BK_CEC(0x11))&0x0E);
572 }
573
mhal_CEC_Device_Is_Tx(void)574 MS_BOOL mhal_CEC_Device_Is_Tx(void)
575 {
576 return CEC_DEVICE_IS_SOURCE;
577 }
mhal_CEC_SetRetryCount(MS_U8 ucRetryCount)578 void mhal_CEC_SetRetryCount(MS_U8 ucRetryCount)
579 {
580 PM_REG_WRITE(H_BK_CEC(0x00),ucRetryCount|(PM_REG_READ(H_BK_CEC(0x00))& 0xF8)); // retry times
581 }
582
583 #if ENABLE_CEC_MULTIPLE
mhal_CEC_SetMyAddress2(MS_U8 mylogicaladdress)584 void mhal_CEC_SetMyAddress2(MS_U8 mylogicaladdress)
585 {
586 PM_REG_WRITE(H_BK_CEC(0x30), (PM_REG_READ(H_BK_CEC(0x30)) & 0xF0) |(mylogicaladdress));
587 }
588
mhal_CEC_IsMessageReceived2(void)589 MS_BOOL mhal_CEC_IsMessageReceived2(void)
590 {
591 return (PM_REG_READ(H_BK_CEC(0x11))& 0x20 ? TRUE : FALSE);
592 }
593
mhal_CEC_ReceivedMessageLen2(void)594 MS_U8 mhal_CEC_ReceivedMessageLen2(void)
595 {
596 return ((PM_REG_READ(L_BK_CEC(0x31)) & 0x1F) + 1);
597 }
598
mhal_CEC_GetMessageByte2(MS_U8 idx)599 MS_U8 mhal_CEC_GetMessageByte2(MS_U8 idx)
600 {
601 return (PM_REG_READ(L_BK_CEC(0x28) + idx));
602 }
603
mhal_CEC_ClearRxStatus2(void)604 void mhal_CEC_ClearRxStatus2(void)
605 {
606 // clear RX INT status
607 PM_REG_WRITE(H_BK_CEC(0x12), 0x60);
608 PM_REG_WRITE(H_BK_CEC(0x12), 0x00);
609 // clear RX NACK status
610 PM_REG_WRITE(L_BK_CEC(0x11), 0xFF);
611 }
612 #endif
613
614
615