1 //<MStar Software> 2 //****************************************************************************** 3 // MStar Software 4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. 5 // All software, firmware and related documentation herein ("MStar Software") are 6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by 7 // law, including, but not limited to, copyright law and international treaties. 8 // Any use, modification, reproduction, retransmission, or republication of all 9 // or part of MStar Software is expressly prohibited, unless prior written 10 // permission has been granted by MStar. 11 // 12 // By accessing, browsing and/or using MStar Software, you acknowledge that you 13 // have read, understood, and agree, to be bound by below terms ("Terms") and to 14 // comply with all applicable laws and regulations: 15 // 16 // 1. MStar shall retain any and all right, ownership and interest to MStar 17 // Software and any modification/derivatives thereof. 18 // No right, ownership, or interest to MStar Software and any 19 // modification/derivatives thereof is transferred to you under Terms. 20 // 21 // 2. You understand that MStar Software might include, incorporate or be 22 // supplied together with third party`s software and the use of MStar 23 // Software may require additional licenses from third parties. 24 // Therefore, you hereby agree it is your sole responsibility to separately 25 // obtain any and all third party right and license necessary for your use of 26 // such third party`s software. 27 // 28 // 3. MStar Software and any modification/derivatives thereof shall be deemed as 29 // MStar`s confidential information and you agree to keep MStar`s 30 // confidential information in strictest confidence and not disclose to any 31 // third party. 32 // 33 // 4. MStar Software is provided on an "AS IS" basis without warranties of any 34 // kind. Any warranties are hereby expressly disclaimed by MStar, including 35 // without limitation, any warranties of merchantability, non-infringement of 36 // intellectual property rights, fitness for a particular purpose, error free 37 // and in conformity with any international standard. You agree to waive any 38 // claim against MStar for any loss, damage, cost or expense that you may 39 // incur related to your use of MStar Software. 40 // In no event shall MStar be liable for any direct, indirect, incidental or 41 // consequential damages, including without limitation, lost of profit or 42 // revenues, lost or damage of data, and unauthorized system use. 43 // You agree that this Section 4 shall still apply without being affected 44 // even if MStar Software has been modified by MStar in accordance with your 45 // request or instruction for your use, except otherwise agreed by both 46 // parties in writing. 47 // 48 // 5. If requested, MStar may from time to time provide technical supports or 49 // services in relation with MStar Software to you for your use of 50 // MStar Software in conjunction with your or your customer`s product 51 // ("Services"). 52 // You understand and agree that, except otherwise agreed by both parties in 53 // writing, Services are provided on an "AS IS" basis and the warranty 54 // disclaimer set forth in Section 4 above shall apply. 55 // 56 // 6. Nothing contained herein shall be construed as by implication, estoppels 57 // or otherwise: 58 // (a) conferring any license or right to use MStar name, trademark, service 59 // mark, symbol or any other identification; 60 // (b) obligating MStar or any of its affiliates to furnish any person, 61 // including without limitation, you and your customers, any assistance 62 // of any kind whatsoever, or any information; or 63 // (c) conferring any license or right under any intellectual property right. 64 // 65 // 7. These terms shall be governed by and construed in accordance with the laws 66 // of Taiwan, R.O.C., excluding its conflict of law rules. 67 // Any and all dispute arising out hereof or related hereto shall be finally 68 // settled by arbitration referred to the Chinese Arbitration Association, 69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration 70 // Rules of the Association by three (3) arbitrators appointed in accordance 71 // with the said Rules. 72 // The place of arbitration shall be in Taipei, Taiwan and the language shall 73 // be English. 74 // The arbitration award shall be final and binding to both parties. 75 // 76 //****************************************************************************** 77 //<MStar Software> 78 //////////////////////////////////////////////////////////////////////////////// 79 // 80 // Copyright (c) 2006-2007 MStar Semiconductor, Inc. 81 // All rights reserved. 82 // 83 // Unless otherwise stipulated in writing, any and all information contained 84 // herein regardless in any format shall remain the sole proprietary of 85 // MStar Semiconductor Inc. and be kept in strict confidence 86 // (��MStar Confidential Information��) by the recipient. 87 // Any unauthorized act including without limitation unauthorized disclosure, 88 // copying, use, reproduction, sale, distribution, modification, disassembling, 89 // reverse engineering and compiling of the contents of MStar Confidential 90 // Information is unlawful and strictly prohibited. MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 /////////////////////////////////////////////////////////////////////////////////////////////////// 96 /// 97 /// @file drvHDMITx.h 98 /// @author MStar Semiconductor Inc. 99 /// @brief HDMI Tx Driver Interface 100 /////////////////////////////////////////////////////////////////////////////////////////////////// 101 102 #ifndef _DRV_HDMITX_H_ 103 #define _DRV_HDMITX_H_ 104 105 106 #ifdef __cplusplus 107 extern "C" 108 { 109 #endif 110 111 #include "halHDMITx.h" 112 #ifdef CUSTOMER_NDS 113 #include "apiHDMITx_NDS.h" 114 #endif // CUSTOMER_NDS 115 116 //------------------------------------------------------------------------------------------------- 117 // Driver Capability 118 //------------------------------------------------------------------------------------------------- 119 120 121 //------------------------------------------------------------------------------------------------- 122 // Macro and Define 123 //------------------------------------------------------------------------------------------------- 124 #define HDMITX_EDID_BLK_SIZE 128U //wilson@kano 125 #define HDMITX_CEA_DAT_BLK_TYPE_NUM 8U //wilson@kano 126 127 128 #ifdef MSOS_TYPE_LINUX_KERNEL 129 #define HDMITX_ISR_ENABLE 1U 130 #else 131 #define HDMITX_ISR_ENABLE 1U 132 #endif 133 134 //------------------------------------------------------------------------------------------------- 135 // Type and Structure 136 //------------------------------------------------------------------------------------------------- 137 138 typedef enum 139 { 140 E_HDMITX_POOL_ID_INTERNAL_0 = 0, // just for test, please refine. 141 E_HDMITX_POOL_ID_MAX, // just for test, please refine. 142 } E_HDMITX_POOL_ID; 143 144 145 //*********************// 146 // DVI / HDMI // 147 //*********************// 148 149 /* 150 Bit1: 151 - 0: DVI 152 - 1: HDMI 153 Bit0: 154 - 0: without HDCP 155 - 1: with HDCP 156 */ 157 typedef enum 158 { 159 E_HDMITX_DVI = 0, // DVI without HDCP 160 E_HDMITX_DVI_HDCP = 1, // DVI with HDCP 161 E_HDMITX_HDMI = 2, // HDMI without HDCP 162 E_HDMITX_HDMI_HDCP = 3, // HDMI with HDCP 163 } MsHDMITX_OUTPUT_MODE; 164 165 typedef enum 166 { 167 E_HDMITX_EVENT_RUN = 0x00000001U, 168 E_HDMITX_EVENT_IRQ = 0x00000002U, 169 //wilson@kano 170 E_HDMITX_EVENT_RXTIMER = 0x00000004U, 171 E_HDMITX_EVENT_CECRX = 0x00000008U, 172 173 E_HdcpTX_EVENT_RUN = 0x00000010U, 174 E_HdcpTX_EVENT_IRQ = 0x00000020U, 175 E_HdcpTX_EVENT_RITIMER = 0x00000040U, 176 177 #if 0 178 E_HDMITX_EVENT_RITIMER = 0x00000004, 179 E_HDMITX_EVENT_RXTIMER = 0x00000008, 180 E_HDMITX_EVENT_CECRX = 0x00000010, 181 #endif 182 } MDrvHDMITXEvent; 183 184 #if 0 185 typedef enum //wilson@kano 186 { 187 E_HdcpTX_EVENT_RUN = 0x00000001, 188 E_HdcpTX_EVENT_IRQ = 0x00000002, 189 E_HdcpTX_EVENT_RITIMER = 0x00000004, 190 } MDrvHdcpTXEvent; 191 #endif 192 193 typedef enum 194 { 195 //wilson@kano 196 E_HDMITX_FSM_PENDING = 0, 197 E_HDMITX_FSM_VALIDATE_EDID = 1, 198 E_HDMITX_FSM_PRE_TRANSMIT = 2, 199 E_HDMITX_FSM_TRANSMIT = 3, 200 E_HDMITX_FSM_DONE = 4, 201 #if 0 202 E_HDMITX_FSM_PENDING = 0, 203 E_HDMITX_FSM_CHECK_HPD = 1, 204 E_HDMITX_FSM_VALIDATE_EDID = 2, 205 E_HDMITX_FSM_HDCP_AUTH_WAIT_RX = 3, 206 E_HDMITX_FSM_HDCP_AUTH_CHECK_R0 = 4, 207 E_HDMITX_FSM_HDCP_AUTH_CHECK_REPEATER = 5, 208 E_HDMITX_FSM_HDCP_AUTH_DONE = 6, 209 E_HDMITX_FSM_HDCP_AUTH_FAIL = 7, 210 #endif 211 } MDrvHDMITX_FSM_STATE; 212 213 typedef enum 214 { 215 E_NORMAL_OUTPUT = 0, // still display normally 216 E_HDCP_ENCRYPTION = 1, // HDCP encryption to show snow screen 217 E_BLUE_SCREEN = 2, // blue screen 218 } MDrvHDMITX_UNHDCPRX_CONTROL; 219 220 typedef enum 221 { 222 E_CHECK_NOT_READY = 0, 223 E_CHECK_REVOKED = 1, 224 E_CHECK_NOT_REVOKED = 2, 225 }MDrvHDMITX_REVOCATION_STATE; 226 227 typedef enum 228 { 229 E_RXFail_NORMAL_OUTPUT = 0, // still display normally 230 E_RXFail_HDCP_ENCRYPTION = 1, // HDCP encryption to show snow screen 231 E_RXFail_BLUE_SCREEN = 2, // blue screen 232 } MDrvHDMITX_HDCPRXFail_CONTROL; 233 234 typedef enum 235 { 236 E_HDMITX_HDCP_RESET = 0x01, 237 E_HDMITX_HDCP_WAITING_ACTIVE_RX = 0x02, 238 E_HDMITX_HDCP_CHECK_REPEATER_READY = 0x03, 239 E_HDMITX_HDCP_CHECK_R0 = 0x04, 240 E_HDMITX_HDCP_AUTH_DONE = 0x05, 241 E_HDMITX_HDCP_AUTH_FAIL = 0x06, 242 243 // bit[7:6]=00 for checking valid rx 244 E_HDMITX_HDCP_RX_IS_NOT_VALID = 0x00, // 00 00 245 E_HDMITX_HDCP_RX_IS_VALID = 0x10, // 00 01 246 E_HDMITX_HDCP_RX_KEY_FAIL = 0x20, // 00 10 247 E_HDMITX_HDCP_TX_KEY_FAIL = 0x30, // 00 11 248 E_HDMITX_HDCP_RX_KEY_REVOKED = 0x0F, // 00 00 11 11 249 250 // bit[7:6]=01 for repeater 251 E_HDMITX_HDCP_REPEATER_TIMEOUT = 0x40, // 01 00 252 E_HDMITX_HDCP_REPEATER_READY = 0x50, // 01 01 253 E_HDMITX_HDCP_REPEATER_NOT_READY = 0x60, // 01 10 254 E_HDMITX_HDCP_REPEATER_VALID = 0x70, // 01 11 255 256 // bit[7:6]=10 for SHA1 257 E_HDMITX_HDCP_REPEATER_SHA1_FAIL = 0x80, // 10 00 258 E_HDMITX_HDCP_REPEATER_SHA1_PASS = 0x90, // 10 01 259 260 // bit[7:6]=11 for Ri 261 E_HDMITX_HDCP_SYNC_RI_FAIL = 0xC0, // 11 00 262 E_HDMITX_HDCP_SYNC_RI_PASS = 0xD0 // 11 01 263 }MsHDMITX_HDCP_AUTH_STATUS; 264 265 typedef enum 266 { 267 HDCP14Tx_MainState_A0 = 0x00, 268 HDCP14Tx_MainState_A1andA2 = 0x01, 269 // HDCP14Tx_MainState_A2 = 0x02, 270 HDCP14Tx_MainState_A3 = 0x03, 271 HDCP14Tx_MainState_A4 = 0x04, 272 HDCP14Tx_MainState_A5 = 0x05, 273 HDCP14Tx_MainState_A6 = 0x06, 274 HDCP14Tx_MainState_A7 = 0x07, 275 HDCP14Tx_MainState_A8 = 0x08, 276 HDCP14Tx_MainState_A9 = 0x09, 277 } enHDCP14Tx_MainStates; 278 279 typedef enum 280 { 281 HDCP14Tx_SubFSM_IDLE = 0x00, 282 HDCP14Tx_SubFSM_ExchangeKSV = 0x01, 283 HDCP14Tx_SubFSM_VerifyBksv = 0x02, 284 HDCP14Tx_SubFSM_Computation = 0x03, 285 HDCP14Tx_SubFSM_CheckR0 = 0x04, 286 HDCP14Tx_SubFSM_AuthDone = 0x05, 287 HDCP14Tx_SubFSM_PollingRdyBit = 0x06, 288 HDCP14Tx_SubFSM_AuthWithRepeater = 0x07, 289 HDCP14Tx_SubFSM_CheckRi = 0x08, 290 HDCP14Tx_SubFSM_AuthFail = 0x09 291 } enHDCP14Tx_SubStates; 292 293 typedef struct __attribute__ ((packed)) 294 { 295 MS_BOOL hdcp_Rx_valid; 296 //MS_BOOL hdmitx_hdcp_flag; ///< hdmitx hdcp encryption on/off 297 298 enHDCP14Tx_MainStates hdcp14tx_MainState; 299 enHDCP14Tx_SubStates hdcp14tx_SubState; 300 enHDCP14Tx_SubStates hdcp14tx_PreSubState; 301 302 // HDCP 303 MS_BOOL hdmitx_HdcpUseInternalKey_flag; ///< hdmitx HDCP key source 304 MS_BOOL hdmitx_HdcpStartAuth_flag; ///< hdmitx HDCP start authentication flag 305 MS_BOOL hdmitx_HdcpAuthDone_flag; ///< hdmitx HDCP authentication done flag 306 MS_BOOL hdmitx_HdcpCheckRepeater_flag; ///< hdmitx HDCP check repeater flag 307 308 // CEC 309 MsHDMITX_HDCP_AUTH_STATUS hdmitx_HDCPAuth_Status; ///< hdmitx HDCP authentication status 310 MDrvHDMITX_UNHDCPRX_CONTROL hdmitx_unHDCPRx_Control; ///< hdmitx unHDCP Rx ouput way 311 MDrvHDMITX_HDCPRXFail_CONTROL hdmitx_HDCPRxFail_Control; ///< hdmitx HDCP Rx fail output way 312 313 MS_U8 hdcp_srmlist[5116]; // maximum length of the 1st generation 314 MS_U8 hdcp_revocationlist[5068]; // 5x max number of device 315 MS_BOOL revocationlist_ready; // revocationlist update flag 316 MS_U8 revocation_size; 317 MDrvHDMITX_REVOCATION_STATE revocation_state; // revocation check state 318 319 MS_U8 HDCP_AKSV[5]; 320 MS_U8 HDCP_BKSV[5]; 321 MS_U8 ucBStatus[2]; 322 MS_BOOL HDCP_74_check; 323 MS_U32 u32AlignDummy; 324 } MDrvHdcpTx_PARAMETER_LIST; //wilson@kano 325 326 enum enCEA_DATABLK_TAG_CODE //wilson@kano 327 { 328 CEATag_Reserved_0 = 0, 329 CEATag_AudioBlk = 1, 330 CEATag_VideoBlk = 2, 331 CEATag_VendorSpecific = 3, 332 CEATag_SpeakerAlloc = 4, 333 CEATag_VESA_DTCBlk = 5, 334 CEATag_Reserved_1 = 6, 335 CEATag_UseExtTag = 7 336 }; 337 338 enum enCEA_DATABLK_EXT_TAG_CODE //wilson@kano 339 { 340 CEAExtTag_VideoCap_DB = 0, 341 CEAExtTag_VSVideo_DB = 1, 342 CEAExtTag_VESADisplayDev_DB = 2, 343 CEAExtTag_VESAVideoTimingBlk = 3, 344 CEAExtTag_ReservedHDMIVideoDB = 4, 345 CEAExtTag_ColorimetryDB = 5, 346 CEAExtTag_HDRStaticMetaDB = 6, 347 CEAExtTag_YCbCr420VideoDB = 14, 348 CEAExtTag_YCbCr420CapMapDB = 15, 349 CEAExtTag_ReservedCEAMiscAudio = 16, 350 CEAExtTag_VSAudioDB = 17, 351 CEAExtTag_ReservedHDMIAudioDB = 18, 352 CEAExtTag_InfoFrameDB = 32 353 }; 354 355 typedef struct __attribute__ ((packed)) 356 { 357 MsHDMITX_AVI_VIC VideoTiming; 358 MsHDMITX_EDID_3D_STRUCTURE_ALL Video3DInfo; 359 MS_U32 u32AlignDummy; 360 } stHDMITX_RXEDID_VIDEO_INFO; //wilson@kano 361 362 typedef struct __attribute__ ((packed)) 363 { 364 MS_U8 EdidBlk0[HDMITX_EDID_BLK_SIZE]; 365 MS_U8 EdidBlk1[HDMITX_EDID_BLK_SIZE]; 366 MS_U8 ManufacturerID[3]; 367 MS_U8 CEADataBlkLen[HDMITX_CEA_DAT_BLK_TYPE_NUM]; 368 MS_U8 PhyAddr[2]; 369 MS_BOOL SupportHdmi; 370 371 //HF-VSDB, scdc relative 372 MS_U8 HF_VSDBVerInfo; 373 MS_U8 MaxTmdsCharRate; 374 #if 0 375 MS_BOOL SupportIndependView; 376 MS_BOOL SupportDualView; 377 MS_BOOL Support3DOsdDisparity; 378 #endif 379 MS_BOOL SupportLTEScramble; 380 MS_BOOL SupportSCDC; 381 MS_BOOL SupportRR; //read request 382 MS_U8 YUV420DeepColorInfo; 383 384 MS_BOOL AudSupportAI; 385 #if 0 386 MS_BOOL b3DPresent; 387 MS_U8 b3dMultiPresent; 388 MS_U8 Hdmi3DLen; 389 MS_BOOL Support2D_50Hz; 390 MS_BOOL Support2D_60Hz; 391 MS_BOOL Support3D_50Hz; 392 MS_BOOL Support3D_60Hz; 393 #endif 394 MsHDMITX_VIDEO_COLORDEPTH_VAL ColorDepthInfo; 395 396 // data block content 397 MS_U8 AudioDataBlk[32]; 398 MS_U8 VideoDataBlk[32]; 399 MS_U8 VendorDataBlk[32]; 400 MS_U8 SpeakerAllocDataBlk[32]; 401 MS_U8 VESA_DTCDataBlk[32]; 402 MS_U8 HdmiVICList[7]; //this field has only 3 bits 403 MS_U8 HdmiVICLen; 404 #if 0 405 stHDMITX_RXEDID_VIDEO_INFO SupVidTiming[32]; 406 #endif 407 408 MS_U8 HDMI_VSDB[32]; 409 MS_U8 HDMI_VSDB_Len; 410 MS_U8 HF_VSDB[32]; 411 MS_U8 HF_VSDB_Len; 412 413 //for 420 414 MS_BOOL Support420ColorFmt; 415 MS_U8 YCbCr420VidDataBlk[32]; 416 MS_U8 YCbCr420CapMapDataBlk[32]; 417 418 //for colorimetry 419 MS_U8 ExtColorimetry; 420 421 //for HDR 422 MS_BOOL bSupportHDR; 423 MS_U8 HDRStaticDataBlk[32]; 424 MS_U32 u32AlignDummy; 425 426 } stHDMITX_RxEDID_Info; //wilson@kano 427 428 typedef struct __attribute__ ((packed)) 429 { 430 MS_BOOL bHDMITxTaskIdCreated; 431 MS_BOOL bHDMITxEventIdCreated; 432 MS_BOOL bCheckRxTimerIdCreated; 433 434 MS_BOOL hdmitx_hdcp_flag; ///< hdmitx hdcp encryption on/off 435 MS_BOOL hdmitx_enable_flag; ///< hdmitx module actived 436 MS_BOOL hdmitx_tmds_flag; ///< hdmitx tmds on/off 437 MS_BOOL hdmitx_video_flag; ///< hdmitx video on/off 438 MS_BOOL hdmitx_audio_flag; ///< hdmitx audio on/off 439 MS_BOOL hdmitx_csc_flag; ///< hdmitx csc on/off 440 //MS_BOOL hdmitx_audio_supportAI; ///< hdmitx audio support AI 441 MS_BOOL hdmitx_RB_swap_flag; ///< hdmitx R/B swap 442 MS_BOOL hdmitx_force_mode; ///< hdmitx output force mode: auto/force 443 MS_BOOL hdmitx_force_output_color; ///< hdmitx output force color format: auto/force 444 MS_BOOL hdmitx_AFD_override_mode; ///< hdmitx AFD override mode: auto/override 445 MS_BOOL hdmitx_edid_ready; ///< hdmitx get ready to Rx's EDID 446 MS_BOOL hdmitx_avmute_flag; ///< hdmitx AVMUTE status 447 448 // CEC 449 MS_BOOL hdmitx_CECEnable_flag; ///< hdmitx CEC enable flag 450 451 MDrvHDMITX_FSM_STATE hdmitx_fsm_state; ///< hdmitx fsm state 452 MDrvHDMITX_FSM_STATE hdmitx_fsm_prestate; ///< hdmitx fsm pre-state 453 MsHDMITX_RX_STATUS hdmitx_preRX_status; ///< hdmitx previous Rx status 454 455 MsHDMITX_OUTPUT_MODE output_mode; ///< output DVI / HDMI mode 456 MsHDMITX_OUTPUT_MODE force_output_mode; ///< output DVI / HDMI mode 457 MsHDMITX_COLORIMETRY colorimetry; 458 MsHDMITX_EXT_COLORIMETRY ext_colorimetry; 459 MsHDMITX_YCC_QUANT_RANGE enYCCQuantRange; 460 MsHDMITX_VIDEO_COLORDEPTH_VAL output_colordepth_val; // output video color depth 461 MsHDMITX_VIDEO_TIMING output_video_timing; ///< output video timing 462 MsHDMITX_VIDEO_TIMING output_video_prevtiming; ///< output video previous timing 463 MsHDMITX_VIDEO_COLOR_FORMAT input_color; ///< RGB444 / YUV444 464 MsHDMITX_VIDEO_COLOR_FORMAT output_color; ///< RGB444 / YUV444 465 MsHDMITX_YCC_QUANT_RANGE input_range; 466 MsHDMITX_YCC_QUANT_RANGE output_range; 467 MsHDMITX_VIDEO_COLOR_FORMAT force_output_color; ///< RGB444 / YUV444 468 MsHDMITX_VIDEO_ASPECT_RATIO output_aspect_ratio; // Aspect ratio 469 MsHDMITX_VIDEO_SCAN_INFO output_scan_info; // overscan / underscan 470 MsHDMITX_VIDEO_AFD_RATIO output_afd_ratio; // AFD 471 MS_U8 output_activeformat_present; // Active format information present 472 MsHDMITX_AUDIO_FREQUENCY output_audio_frequncy; ///< audio sampling frequency 473 MsHDMITX_AUDIO_CHANNEL_COUNT output_audio_channel; // audio channel count 474 MsHDMITX_AUDIO_CODING_TYPE output_audio_type; // audio coding type 475 476 MsHDMITX_ANALOG_TUNING analog_setting; // HDMI Tx Pre-emphasis and Double termination 477 478 MS_U8 ubSSCEn; 479 MS_VIRT u32PMRIUBaseAddress; 480 481 #if !defined (__aarch64__) 482 MS_U32 u32AlignDummy0; 483 #endif 484 485 MS_PHY u32PMBankSize; 486 487 #if (defined(MSOS_TYPE_LINUX_KERNEL)) 488 MS_VIRT u32CoproRIUBase; 489 #if !defined (__aarch64__) 490 MS_U32 u32AlignDummy1; 491 #endif 492 #endif 493 494 MS_BOOL hdmitx_bypass_flag; //RxTxBypass 495 496 //EDID 497 stHDMITX_RxEDID_Info RxEdidInfo; //wilson@kano 498 499 //wilson@kano: sorting previous EDID relative items 500 //map to ColorDepthInfo //MsHDMITX_VIDEO_COLORDEPTH_VAL edid_colordepth_val; // EDID video color depth 501 //map to PhyAddr[]//MS_U8 edid_phyadr[2]; // EDID physical address 502 //map to VideoDataBlk//MS_U8 short_video_descriptor[32]; // short video descriptor of EDID 503 //map to AudioDataBlk//MS_U8 short_audio_descriptor[32]; // short audio descriptor of EDID 504 //map to CEADataBlkLen//MS_U8 data_block_length[8]; // data block length of each data block 505 //map to ManufacturerID//MS_U8 id_manufacturer_name[3]; // ID Manufacturer Name 506 //map to EdidBlk0//MS_U8 edid_block0[128]; //EDID's 1st 128 data 507 //map to EdidBlk1//MS_U8 edid_block1[128]; //EDID's 2nd 128 data 508 //map to Support2D_50Hz//MS_BOOL edid_2D_50hz_support; 509 //map to Support2D_60Hz//MS_BOOL edid_2D_60hz_support; 510 //map to Support3D_50Hz//MS_BOOL edid_3D_50hz_support; 511 //map to Support3D_60Hz//MS_BOOL edid_3D_60hz_support; 512 //map to 3DPresent//MS_BOOL edid_3D_present; 513 //map to SupportHdmi//MS_BOOL edid_HDMI_support; 514 //SupVidTiming//MsHDMITX_EDID_3D_SUPPORT_TIMING edid_3D_support_timing[32]; 515 } MDrvHDMITX_PARAMETER_LIST; //wilson@kano 516 517 // debug mask definition 518 #define HDMITX_DBG 0x01U ///< Debug PQ Table 519 #define HDMITX_DBG_HDCP 0x02U ///< Debug S RULE 520 #define HDMITX_DBG_UTILTX 0x04U ///< Debug S RULE 521 522 /** 523 * @brief HDMI Status 524 */ 525 typedef struct 526 { 527 MS_BOOL bIsInitialized; 528 MS_BOOL bIsRunning; 529 }MS_HDMI_TX_Status; 530 531 typedef struct 532 { 533 MS_BOOL bIsInitialized; 534 MS_BOOL bIsRunning; 535 }MS_HDCP_TX_Status; 536 537 // Debug 538 /** 539 * @brief HDMI Info 540 */ 541 typedef struct 542 { 543 MS_U8 Reserved; 544 }MS_HDMI_TX_INFO; 545 546 typedef struct 547 { 548 // HDMI Tx Current, Pre-emphasis and Double termination 549 MS_U8 tm_txcurrent; // TX current control(U4: 0x11302B[13:12], K1: 0x11302B[13:11]) 550 MS_U8 tm_pren2; // pre-emphasis mode control, 0x11302D[5] 551 MS_U8 tm_precon; // TM_PRECON, 0x11302E[7:4] 552 MS_U8 tm_pren; // pre-emphasis enable, 0x11302E[11:8] 553 MS_U8 tm_tenpre; // Double termination pre-emphasis enable, 0x11302F[3:0] 554 MS_U8 tm_ten; // Double termination enable, 0x11302F[7:4] 555 } drvHDMITX_ANALOG_TUNING; 556 557 typedef enum 558 { 559 E_HDMITX_TIMING_ERR_NONE = 0x00000000, 560 E_HDMITX_TIMING_ERR_CFG_ERR = 0x00000001, 561 E_HDMITX_TIMING_ERR_EDID_ERR = 0x00000002, 562 E_HDMITX_TIMING_ERR_COLOR_FMT = 0x00000004, 563 E_HDMITX_TIMING_ERR_COLOR_DEPTH = 0x00000008, 564 E_HDMITX_TIMING_ERR_TIMING = 0x00000010, 565 E_HDMITX_TIMING_ERR_HW_LIMIT = 0x00000020, 566 E_HDMITX_TIMING_ERR_SW_LIMIT = 0x00000040, 567 E_HDMITX_TIMING_ERR_SINK_LIMIT = 0x00000080, 568 E_HDMITX_TIMING_ERR_MAX = 0xFFFFFFFF 569 }MsHDMITX_TIMING_ERROR; 570 571 //------------------------------------------------------------------------------------------------- 572 // Function Prototype 573 //------------------------------------------------------------------------------------------------- 574 #ifdef MDRV_HDMITX_C 575 #define INTERFACED 576 #else 577 #define INTERFACED extern 578 #endif 579 580 INTERFACED void* pu32HDMITXInst; 581 INTERFACED void* pu32HDMITXRes[E_HDMITX_POOL_ID_MAX]; 582 583 INTERFACED MS_U32 MDrv_HDMITx_Get_Semaphore(void *pInstance); 584 INTERFACED MS_U32 MDrv_HDMITx_Release_Semaphore(void *pInstance); 585 586 /*********************************************************************/ 587 /* */ 588 /* HDCP22 Relative */ 589 /* */ 590 /*********************************************************************/ 591 INTERFACED MS_BOOL MDrv_HDMITx_HDCP2AccessX74(MS_U8 u8PortIdx, MS_U8 u8OffsetAddr, MS_U8 u8OpCode, MS_U8 *pu8RdBuf, MS_U8 *pu8WRBuff, MS_U16 u16RdLen, MS_U16 u16WRLen); 592 INTERFACED void MDrv_HDMITx_HDCP2TxInit(MS_U8 u8PortIdx, MS_BOOL bEnable); 593 INTERFACED void MDrv_HDMITx_HDCP2TxEnableEncryptEnable(MS_U8 u8PortIdx, MS_BOOL bEnable); 594 INTERFACED void MDrv_HDMITx_HDCP2TxFillCipherKey(MS_U8 u8PortIdx, MS_U8 *pu8Riv, MS_U8 *pu8KsXORLC128); 595 596 INTERFACED void MDrv_HDCPTx_SetAksv2R0Interval(MS_U32 u32Interval); 597 INTERFACED void MDrv_HDCPTx_SetUnHDCPRxCtrl(void* pInstance, MDrvHDMITX_UNHDCPRX_CONTROL enUnHDCPCtrl); 598 INTERFACED void MDrv_HDCPTx_SetHDCPRxFailCtrl(void* pInstance, MDrvHDMITX_UNHDCPRX_CONTROL enUnHDCPCtrl); 599 INTERFACED MS_BOOL MDrv_HDCPTx_GetAuthDoneFlag(void* pInstance); //wilson@kano 600 INTERFACED void MDrv_HDCPTx_GetHdcpKey(void* pInstance, MS_BOOL useinternalkey, MS_U8 *data); 601 INTERFACED MS_BOOL MDrv_HDCPTx_GetBksv(void* pInstance, MS_U8 *pucData); 602 INTERFACED MS_BOOL MDrv_HDCPTx_GetAksv(void* pInstance, MS_U8 *pucData); 603 INTERFACED void MDrv_HDCPTx_GetRevocationKeyList(void* pInstance, MS_U8 *data, MS_U16 size); 604 INTERFACED enHDCP14Tx_SubStates MDrv_HDCPTx_GetPreState(void* pInstance); 605 INTERFACED MS_BOOL MDrv_HDCPTx_GetRxValid(void* pInstance); //wilson@kano 606 INTERFACED MS_BOOL MDrv_HDCPTx_GetKSVList(MS_U8 *pu8Bstatus, MS_U8* pu8KSVList, MS_U16 u16BufLen, MS_U16 *pu16KSVLength); 607 INTERFACED MS_BOOL MDrv_HDCPTx_CheckAuthFailFlag(void* pInstance); 608 INTERFACED MDrvHDMITX_REVOCATION_STATE MDrv_HDCPTx_RevocationKey_Check(void* pInstance); 609 INTERFACED MS_BOOL MDrv_HDCPTx_IsSRMSignatureValid(MS_U8 *data, MS_U32 size); 610 INTERFACED void MDrv_HDCPTx_StartAuth(void* pInstance, MS_BOOL bFlag); 611 /////////////////////////// HDMI TX relative 612 INTERFACED MS_BOOL MDrv_HDMITx_EdidChecking(void* pInstance); 613 INTERFACED MS_BOOL MDrv_HDMITx_GetHdcpEnFlag(void* pInstance); 614 INTERFACED MsHDMITX_OUTPUT_MODE MDrv_HDMITx_GetOutputMode(void* pInstance); 615 INTERFACED MS_BOOL MDrv_HDMITx_GetRxStatus(void); 616 INTERFACED MsHDMITX_RX_STATUS MDrv_HDMITx_GetFullRxStatus(void* pInstance); 617 INTERFACED MsHDMITX_VIDEO_COLORDEPTH_VAL MDrv_HDMITx_GetDeepColorMode(void* pInstance); 618 INTERFACED MsHDMITX_VIDEO_TIMING MDrv_HDMITx_GetOutputTiming(void* pInstance); 619 INTERFACED MsHDMITX_VIDEO_COLOR_FORMAT MDrv_HDMITx_GetColorFormat(void* pInstance); 620 INTERFACED MsHDMITX_VIDEO_COLORDEPTH_VAL MDrv_HDMITx_GetRxDCInfoFromEDID(void* pInstance); 621 INTERFACED MS_BOOL MDrv_HDMITx_GetEdidRdyFlag(void* pInstance); 622 INTERFACED void MDrv_HDMITx_GetRxVideoFormatFromEDID(void* pInstance, MS_U8 *pu8Buffer, MS_U8 u8BufSize); 623 INTERFACED void MDrv_HDMITx_GetDataBlockLengthFromEDID(void* pInstance, MS_U8 *pu8Length, MS_U8 u8TagCode); 624 INTERFACED void MDrv_HDMITx_GetRxAudioFormatFromEDID(void* pInstance, MS_U8 *pu8Buffer, MS_U8 u8BufSize); 625 INTERFACED MS_BOOL MDrv_HDMITx_EdidGetHDMISupportFlag(void* pInstance); 626 INTERFACED void MDrv_HDMITx_GetRxIDManufacturerName(void* pInstance, MS_U8 *pu8Buffer); 627 INTERFACED void MDrv_HDMITx_GetEDIDData(void* pInstance, MS_U8 *pu8Buffer, MS_BOOL BlockIdx); 628 INTERFACED void MDrv_HDMITx_GetRx3DStructureFromEDID(void* pInstance, MsHDMITX_VIDEO_TIMING timing, MsHDMITX_EDID_3D_STRUCTURE_ALL *p3DStructure); 629 INTERFACED MS_U32 MDrv_HDMITx_GetAudioCTS(void); 630 INTERFACED MS_BOOL MDrv_HDMITx_GetAVMUTEStatus(void* pInstance); 631 INTERFACED MS_BOOL MDrv_HDMITx_GetLibVer(const MSIF_Version **ppVersion); 632 INTERFACED MS_BOOL MDrv_HDMITx_GetInfo(MS_HDMI_TX_INFO *pInfo); 633 INTERFACED MS_BOOL MDrv_HDMITx_GetStatus(MS_HDMI_TX_Status *pStatus); 634 INTERFACED void MDrv_HDMITx_GetEDIDPhyAdr(void* pInstance, MS_U8* pucData); 635 INTERFACED MS_BOOL MDrv_HDMITx_GetVICListFromEDID(void* pInstance, MS_U8 *pu8Buffer, MS_U8 u8BufSize); 636 INTERFACED MS_BOOL MDrv_HDMITx_GetColorFormatFromEDID(void* pInstance, MsHDMITX_VIDEO_TIMING timing, MsHDMITX_EDID_COLOR_FORMAT *pColorFmt); 637 INTERFACED void MDrv_HDMITx_GetAudioDataBlock(void* pInstance, MS_U8* pu8Data, MS_U32 u32DataLen, MS_U32* pu32RealLen); 638 INTERFACED void MDrv_HDMITx_GetVideoDataBlock(void* pInstance, MS_U8* pu8Data, MS_U32 u32DataLen, MS_U32* pu32RealLen); 639 INTERFACED void MDrv_HDMITx_GetVSDB(void* pInstance, MS_U8* pu8Data, MS_U32 u32DataLen, MS_U32* pu32RealLen); 640 INTERFACED void MDrv_HDMITx_GetHFVSDB(void* pInstance, MS_U8* pu8Data, MS_U32 u32DataLen, MS_U32* pu32RealLen); 641 INTERFACED void MDrv_HDMITx_GetColorimetryDataBlock(void* pInstance, MS_U8* pu8Data, MS_U32 u32DataLen, MS_U32* pu32RealLen); 642 INTERFACED void MDrv_HDMITx_GetHDRStaticMetaDataBlock(void* pInstance, MS_U8* pu8Data, MS_U32 u32DataLen, MS_U32* pu32RealLen); 643 INTERFACED void MDrv_HDMITx_Get420VideoDataBlock(void* pInstance, MS_U8* pu8Data, MS_U32 u32DataLen, MS_U32* pu32RealLen); 644 INTERFACED void MDrv_HDMITx_Get420CapabilityMapDataBlock(void* pInstance, MS_U8* pu8Data, MS_U32 u32DataLen, MS_U32* pu32RealLen); 645 INTERFACED void MDrv_HDMITx_SetTMDSOnOff(void* pInstance, MS_BOOL state); 646 INTERFACED MS_U32 MDrv_HDMITx_GetTMDSStatus(void* pInstance); 647 INTERFACED void MDrv_HDMITx_SetHDMITxMode(void* pInstance, MsHDMITX_OUTPUT_MODE mode); 648 INTERFACED void MDrv_HDMITx_SetDeepColorMode(void* pInstance, MsHDMITX_VIDEO_COLORDEPTH_VAL enDeepColorMode); 649 INTERFACED void MDrv_HDMITx_SetRBChannelSwap(void* pInstance, MS_BOOL state); //wilson@kano 650 INTERFACED void MDrv_HDMITx_SetVideoOnOff(void* pInstance, MS_BOOL state); 651 INTERFACED void MDrv_HDMITx_SetColorFormat(void* pInstance, MsHDMITX_VIDEO_COLOR_FORMAT enInColor, MsHDMITX_VIDEO_COLOR_FORMAT enOutColor); 652 INTERFACED MS_BOOL MDrv_HDMITx_ColorandRange_Transform(void* pInstance, MsHDMITX_VIDEO_COLOR_FORMAT incolor, MsHDMITX_VIDEO_COLOR_FORMAT outcolor, MsHDMITX_YCC_QUANT_RANGE inange, MsHDMITX_YCC_QUANT_RANGE outrange); 653 INTERFACED void MDrv_HDMITx_SetAVMUTE(void* pInstance, MS_BOOL bflag); 654 INTERFACED void MDrv_HDMITx_Set_VS_InfoFrame(void* pInstance, MsHDMITX_VIDEO_VS_FORMAT enVSFmt, MsHDMITX_VIDEO_4k2k_VIC enVid4K2KVic, MsHDMITX_VIDEO_3D_STRUCTURE enVid3DStruct); 655 INTERFACED void MDrv_HDMITx_SetVideoOutputMode(void* pInstance, MsHDMITX_VIDEO_TIMING enVidTiming); 656 INTERFACED void MDrv_HDMITx_SetVideoOutputModeByCustomer(void* pInstance, MsHDMITX_VIDEO_TIMING enVidTiming, stHDMITX_TIMING_INFO_BY_CUSTOMER stTimingInfo); 657 INTERFACED void MDrv_HDMITx_SetVideoOutputAsepctRatio(void* pInstance, MsHDMITX_VIDEO_ASPECT_RATIO enOutputAR); 658 INTERFACED void MDrv_HDMITx_SetVideoOutputOverscan_AFD(void* pInstance, MS_U8 ucA0, MS_BOOL bAFDOverwrite, MsHDMITX_VIDEO_SCAN_INFO enScanInfo, MsHDMITX_VIDEO_AFD_RATIO enAFDRatio); 659 INTERFACED void MDrv_HDMITx_SetAudioOnOff(void* pInstance, MS_BOOL state); 660 INTERFACED void MDrv_HDMITx_SetAudioFrequency(void* pInstance, MsHDMITX_AUDIO_FREQUENCY enAudFreq); 661 INTERFACED void MDrv_HDMITx_SetAudioChCnt(void* pInstance, MsHDMITX_AUDIO_CHANNEL_COUNT enChCnt); 662 INTERFACED void MDrv_HDMITx_SetAudioFmt(void* pInstance, MsHDMITX_AUDIO_CODING_TYPE enAudFmt); 663 INTERFACED void MDrv_HDMITx_SetAudioSourceFormat(MsHDMITX_AUDIO_SOURCE_FORMAT fmt); 664 INTERFACED void MDrv_HDMITx_SetHDCPOnOff(void* pInstance, MS_BOOL state); 665 INTERFACED void MDrv_HDMITx_SetHDCPFlag(void* pInstance, MS_BOOL bEnableHdcp); 666 INTERFACED MS_BOOL MDrv_HDMITx_SetDbgLevel(MS_U16 u16DbgSwitch); 667 INTERFACED void MDrv_HDMITx_SetHPDGpioPin(MS_U8 u8pin); 668 INTERFACED void MDrv_HDMITx_SetCECOnOff(void* pInstance, MS_BOOL bflag); 669 INTERFACED void MDrv_HDMITx_SetAVIInfoExtColorimetry(void* pInstance, MsHDMITX_EXT_COLORIMETRY enExtColorimetry, MsHDMITX_YCC_QUANT_RANGE enYccQuantRange); 670 INTERFACED MS_U8 MDrv_HDMITx_SetAVIInfoColorimetry(void* pInstance, MsHDMITX_COLORIMETRY enColorimetry); 671 INTERFACED MS_BOOL MDrv_HDMITx_GetCECStatus(void* pInstance); 672 INTERFACED void MDrv_HDMITx_Power_OnOff(MS_BOOL bEnable); 673 INTERFACED void MDrv_HDMITx_TurnOnOff(void *pInstance, MS_BOOL state); 674 INTERFACED void MDrv_HDMITx_EnablePacketGen(MS_BOOL bflag); 675 INTERFACED void MDrv_HDMITx_PKT_User_Define_Clear(void); 676 INTERFACED void MDrv_HDMITx_PKT_User_Define(MsHDMITX_PACKET_TYPE packet_type, MS_BOOL def_flag, MsHDMITX_PACKET_PROCESS def_process, MS_U8 def_fcnt); 677 INTERFACED MS_BOOL MDrv_HDMITx_PKT_Content_Define(MsHDMITX_PACKET_TYPE packet_type, MS_U8* data, MS_U8 length); 678 INTERFACED void MDrv_HDMITx_MuteAudioFIFO(MS_BOOL bflag); 679 INTERFACED void MDrv_HDMITx_AnalogTuning(void* pInstance, drvHDMITX_ANALOG_TUNING *pInfo); 680 INTERFACED void MDrv_HDMITx_ForceHDMIOutputMode(void* pInstance, MS_BOOL bflag, MsHDMITX_OUTPUT_MODE output_mode); 681 INTERFACED MS_BOOL MDrv_HDMITx_ForceHDMIOutputColorFormat(void* pInstance, MS_BOOL bflag, MsHDMITX_VIDEO_COLOR_FORMAT output_color); 682 INTERFACED void MDrv_HDMITx_DisableRegWrite(MS_BOOL bFlag); 683 INTERFACED MS_BOOL MDrv_HDMITx_RxBypass_Mode(void* pInstance, MsHDMITX_INPUT_FREQ freq, MS_BOOL bflag); 684 INTERFACED MS_BOOL MDrv_HDMITx_Disable_RxBypass(void* pInstance); 685 INTERFACED MS_BOOL MDrv_HDMITx_IsSupportDVIMode(void); 686 INTERFACED MS_U32 MDrv_HDMITx_SetPowerState(void* pInstance, EN_POWER_MODE u16PowerState); 687 INTERFACED void MDrv_HDMITx_DisableTMDSCtrl(MS_BOOL bFlag); 688 INTERFACED void MDrv_HDMITx_Exhibit(void* pInstance); 689 INTERFACED MS_BOOL MDrv_HDMITxHDCPTx_Init(void* pInstance); //wilson@kano 690 INTERFACED MS_BOOL MDrv_HDMITx_SSC_Enable(void* pInstance, MS_U8 ubSSCEn); 691 INTERFACED MsHDMITX_TIMING_ERROR MDrv_HDMITx_CheckLegalTiming(void* pInstance, MsHDMITX_OUTPUT_MODE eOutputMode, MsHDMITX_VIDEO_TIMING idx, MsHDMITX_VIDEO_COLOR_FORMAT incolor_fmt, MsHDMITX_VIDEO_COLOR_FORMAT outcolor_fmt, MsHDMITX_VIDEO_COLORDEPTH_VAL color_depth); 692 INTERFACED MsHDMITX_TIMING_ERROR MDrv_HDMITx_CheckEDIDTiming(void* pInstance, MsHDMITX_AVI_VIC eVIC, MS_U32 uiPxlClk, MsHDMITX_VIDEO_COLOR_FORMAT incolor_fmt, MsHDMITX_VIDEO_COLOR_FORMAT outcolor_fmt, MsHDMITX_VIDEO_COLORDEPTH_VAL color_depth); 693 INTERFACED MsHDMITX_TIMING_ERROR MDrv_HDMITx_CheckEDIDColorFormat(void* pInstance, MsHDMITX_VIDEO_TIMING idx, MsHDMITX_AVI_VIC eVIC, MsHDMITX_VIDEO_COLOR_FORMAT incolor_fmt, MsHDMITX_VIDEO_COLOR_FORMAT outcolor_fmt, MsHDMITX_VIDEO_COLORDEPTH_VAL color_depth); 694 INTERFACED MsHDMITX_TIMING_ERROR MDrv_HDMITx_CheckEDIDColorDepth(void* pInstance, MsHDMITX_VIDEO_COLOR_FORMAT outcolor_fmt, MsHDMITX_VIDEO_COLORDEPTH_VAL color_depth); 695 696 #ifdef CONFIG_UTOPIA_PROC_DBG_SUPPORT 697 INTERFACED void MDrv_HDMITx_MDCMDEchoCommand(void* pInstance, MS_U64* u64ReqHdl, char* pcCmdLine); 698 INTERFACED void MDrv_HDMITx_MDCMDGetInfo(void* pInstance, MS_U64* u64ReqHdl); 699 #endif 700 701 #ifdef __cplusplus 702 } 703 #endif 704 705 #endif // _DRV_HDMITX_H_ 706 707