1 //<MStar Software> 2 //****************************************************************************** 3 // MStar Software 4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. 5 // All software, firmware and related documentation herein ("MStar Software") are 6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by 7 // law, including, but not limited to, copyright law and international treaties. 8 // Any use, modification, reproduction, retransmission, or republication of all 9 // or part of MStar Software is expressly prohibited, unless prior written 10 // permission has been granted by MStar. 11 // 12 // By accessing, browsing and/or using MStar Software, you acknowledge that you 13 // have read, understood, and agree, to be bound by below terms ("Terms") and to 14 // comply with all applicable laws and regulations: 15 // 16 // 1. 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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 #ifndef _REG_GOP_H_ 96 #define _REG_GOP_H_ 97 98 //------------------------------------------------------------------------------------------------- 99 // Hardware Capability 100 //------------------------------------------------------------------------------------------------- 101 102 103 //------------------------------------------------------------------------------------------------- 104 // Macro and Define 105 //------------------------------------------------------------------------------------------------- 106 //---------------------------------------------------------------------------- 107 // HW IP Reg Base Adr 108 //---------------------------------------------------------------------------- 109 #define GOP_REG_BASE 0x1F00UL 110 #define GE_REG_BASE 0x2800UL 111 #define SC1_REG_BASE 0x2F00UL 112 #define CKG_REG_BASE 0x0B00UL 113 #define MIU0_REG_BASE 0x0600UL 114 #define MIU_REG_BASE 0x1200UL 115 #define MIU2_REG_BASE 0x162000 116 #define MVOP_REG_BASE 0x1400UL 117 #define SC1_DIRREG_BASE 0x130000UL 118 #define AFBC_REG_BASE 0x113100 119 120 //---------------------------------------------------------------------------- 121 // Scaler Reg 122 //---------------------------------------------------------------------------- 123 #define XC_REG(bk, reg) (SC1_REG_BASE+((MS_U32)(bk)<<16) + (reg) * 2) 124 125 #define REG_SC_BK00_00_L XC_REG(0x00, 0x00) 126 #define REG_SC_BK00_05_L XC_REG(0x00, 0x05) 127 #define REG_SC_BK00_06_L XC_REG(0x00, 0x06) 128 #define REG_SC_BK01_02_L XC_REG(0x01, 0x02) 129 #define REG_SC_BK01_05_L XC_REG(0x01, 0x05) 130 #define REG_SC_BK01_1E_L XC_REG(0x01, 0x1E) 131 #define REG_SC_BK01_21_L XC_REG(0x01, 0x21) 132 #define REG_SC_BK02_5F_L XC_REG(0x02, 0x5F) 133 #define REG_SC_BK0F_2B_L XC_REG(0x0F, 0x2B) 134 #define REG_SC_BK10_23_L XC_REG(0x10, 0x23) 135 #define REG_SC_BK10_5B_L XC_REG(0x10, 0x5B) 136 #define REG_SC_BK12_03_L XC_REG(0x12, 0x03) 137 #define REG_SC_BK37_22_L XC_REG(0x37, 0x22) 138 #define REG_SC_BK37_24_L XC_REG(0x37, 0x24) 139 #define REG_SC_BK37_28_L XC_REG(0x37, 0x28) 140 #define REG_SC_BK3D_0D_L XC_REG(0x3D, 0x0D) 141 #define REG_SC_BK40_22_L XC_REG(0x40, 0x22) 142 #define REG_SC_BK40_23_L XC_REG(0x40, 0x23) 143 #define REG_SC_BK40_24_L XC_REG(0x40, 0x24) 144 #define REG_SC_BK40_25_L XC_REG(0x40, 0x25) 145 #define REG_SC_BK7F_10_L XC_REG(0x7F, 0x10) 146 #define REG_SC_BK7F_11_L XC_REG(0x7F, 0x11) 147 #define REG_SC_BK7F_18_L XC_REG(0x7F, 0x18) 148 #define REG_SC_BKC9_50_L XC_REG(0xC9, 0x50) 149 #define REG_SC_BKC9_51_L XC_REG(0xC9, 0x51) 150 #define REG_SC_BKC9_52_L XC_REG(0xC9, 0x52) 151 #define REG_SC_BKCB_48_L XC_REG(0xCB, 0x48) 152 153 #define REG_SC_BK80_05_L XC_REG(0x80, 0x05) 154 155 #define GOP_SC_BANKSEL REG_SC_BK00_00_L 156 #define GOP_SC_CHANNELSYNC REG_SC_BK00_05_L 157 #define GOP_SC1_CHANNELSYNC REG_SC_BK80_05_L 158 #define IPMUX0_BLENDING_ENABLE GOP_BIT13 159 #define IPMUX1_BLENDING_ENABLE GOP_BIT12 160 #define GOP_SC_GOPEN REG_SC_BK00_06_L 161 #define GOP_SC_IP_SYNC REG_SC_BK01_02_L 162 #define GOP_SC_IP_MAIN_HSTART REG_SC_BK01_05_L 163 #define GOP_SC_IP_MAIN_INTERLACE REG_SC_BK01_1E_L 164 #define GOP_SC_IP_MAIN_USR_INTERLACE REG_SC_BK01_21_L 165 #define GOP_SC_IP2GOP_SRCSEL REG_SC_BK02_5F_L 166 #define GOP_SC_OSD_CHECK_ALPHA REG_SC_BK0F_2B_L 167 #define GOP_SC_VOPNBL REG_SC_BK10_23_L 168 #define GOP_SC_GOPENMODE1 REG_SC_BK10_5B_L 169 #define GOP_SC_MIRRORCFG REG_SC_BK12_03_L 170 #define GOP_SC_OCMIXER REG_SC_BK37_22_L 171 #define GOP_SC_OCMISC REG_SC_BK37_24_L 172 #define GOP_SC_OCALPHA REG_SC_BK37_28_L 173 #define GOP_SC_FRC_LAYER1_L_EN REG_SC_BK40_22_L 174 #define GOP_SC_FRC_LAYER1_R_EN REG_SC_BK40_23_L 175 #define GOP_SC_FRC_LAYER2_L_EN REG_SC_BK40_24_L 176 #define GOP_SC_FRC_LAYER2_R_EN REG_SC_BK40_25_L 177 #define GOP_SC_MIU_SEL REG_SC_BK7F_10_L 178 #define GOP_SC_MIU_IP_SEL REG_SC_BK7F_11_L 179 #define GOP_SC_4K120_EN0 REG_SC_BKC9_50_L 180 #define GOP_SC_4K120_EN1 REG_SC_BKC9_51_L 181 #define GOP_SC_4K120_EN2 REG_SC_BKC9_52_L 182 #define GOP_SC_GOP_HSYNC_START REG_SC_BKCB_48_L 183 //---------------------------------------------------------------------------- 184 // MVOP Reg 185 //---------------------------------------------------------------------------- 186 #define GOP_MVOP_MIRRORCFG (MVOP_REG_BASE+0x76) 187 188 189 190 //---------------------------------------------------------------------------- 191 // GE Reg 192 //---------------------------------------------------------------------------- 193 #define GOP_GE_FMT_BLT (GE_REG_BASE+(0x01*2)) 194 #define GOP_GE_EN_CMDQ BIT(0) 195 #define GOP_GE_EN_VCMDQ BIT(1) 196 197 #define GOP_GE_VQ_FIFO_STATUS_L (GE_REG_BASE+(0x04*2)) 198 #define GOP_GE_VQ_FIFO_STATUS_H (GE_REG_BASE+(0x05*2)) 199 200 #define GOP_GE_STATUS (GE_REG_BASE+(0x07*2)) 201 #define GOP_GE_BUSY BIT(0) 202 #define GOP_GE_CMDQ1_STATUS BMASK(7:3) 203 #define GOP_GE_CMDQ2_STATUS BMASK(15:11) 204 205 #define GOP_GE_TAG (GE_REG_BASE+(0x2C*2)) 206 207 #define GOP_GE_DBBASE0 (GE_REG_BASE+(0x26*2)) 208 #define GOP_GE_DBBASE1 (GE_REG_BASE+(0x27*2)) 209 #define GOP_GE_DBPIT (GE_REG_BASE+(0x33*2)) 210 #define GOP_GE_FBFMT (GE_REG_BASE+(0x34*2)) 211 #define GOP_GE_SRCW (GE_REG_BASE+(0x6e*2)) 212 #define GOP_GE_SRCH (GE_REG_BASE+(0x6f*2)) 213 214 215 //---------------------------------------------------------------------------- 216 // ChipTop Reg 217 //---------------------------------------------------------------------------- 218 /* GOP0 and GOP1 CLK */ 219 #define GOP_GOPCLK (CKG_REG_BASE+(0x40<<1)) 220 #define CKG_GOPG0_DISABLE_CLK ~(GOP_BIT0) 221 #define CKG_GOPG0_ODCLK (0<<2) 222 #define CKG_GOPG0_IDCLK2 (1 << 2) 223 #define CKG_GOPG0_IDCLK1 (2 << 2) 224 #define CKG_GOPG0_OCC_FRCCLK (3 << 2) 225 #define CKG_GOPG0_MIXERCLK_VE (4 << 2) 226 #define CKG_GOPG0_FCLK (8 << 2) 227 #define CKG_GOPG0_DISABLE_CLK_MASK (GOP_BIT0) 228 #define CKG_GOPG0_MASK (GOP_BIT5 | GOP_BIT4 | GOP_BIT3 | GOP_BIT2) 229 230 #define CKG_GOPG1_DISABLE_CLK ~(GOP_BIT8) 231 #define CKG_GOPG1_ODCLK (0 << 10) 232 #define CKG_GOPG1_IDCLK2 (1 << 10) 233 #define CKG_GOPG1_IDCLK1 (2 << 10) 234 #define CKG_GOPG1_OCC_FRCCLK (3 << 10) 235 #define CKG_GOPG1_MIXERCLK_VE (4 << 10) 236 #define CKG_GOPG1_FCLK (8 << 10) 237 #define CKG_GOPG1_DISABLE_CLK_MASK (GOP_BIT8) 238 #define CKG_GOPG1_MASK (GOP_BIT13 | GOP_BIT12 | GOP_BIT11 | GOP_BIT10) 239 240 #define CKG_GOPG0_SCALING (CKG_REG_BASE+0x88) 241 #define CKG_GOPG0_MG (CKG_REG_BASE+0xFE) 242 #define CKG_GOPG0_MG_MASK (GOP_BIT3 | GOP_BIT2) 243 #define CKG_GOPG2_MG_MASK (GOP_BIT7 | GOP_BIT6) 244 245 /* GOP2 and GOPDWIN CLK */ 246 #define GOP_GOP2CLK (CKG_REG_BASE+(0x41<<1)) 247 #define CKG_GOPG2_DISABLE_CLK ~(GOP_BIT0) 248 #define CKG_GOPG2_ODCLK (0<<2) 249 #define CKG_GOPG2_IDCLK2 (1 << 2) 250 #define CKG_GOPG2_IDCLK1 (2 << 2) 251 #define CKG_GOPG2_OCC_FRCCLK (3 << 2) 252 #define CKG_GOPG2_MIXERCLK_VE (4 << 2) 253 #define CKG_GOPG2_FCLK (8 << 2) 254 #define CKG_GOPG2_DISABLE_CLK_MASK (GOP_BIT0) 255 #define CKG_GOPG2_MASK (GOP_BIT5 |GOP_BIT4 | GOP_BIT3 | GOP_BIT2) 256 257 #define CKG_GOPD_CLK_IDCLK2 (0 << 10) 258 #define CKG_GOPD_CLK_ODCLK (1 << 10) 259 #define CKG_GOPD_CLK_DC0CLK (2 << 10) 260 #define CKG_GOPD_CLK_SUBDC0CLK (3 << 10) 261 #define CKG_GOPD_CLK_MIXERCLK_VE (4 << 10) 262 #define CKG_GOPD_MASK (GOP_BIT12 | GOP_BIT11 | GOP_BIT10) 263 264 265 /* GOP3 CLK*/ 266 #define GOP_GOP3CLK (CKG_REG_BASE+(0x42<<1)) 267 #define CKG_GOPG3_ODCLK (0<<2) 268 #define CKG_GOPG3_IDCLK2 (1 << 2) 269 #define CKG_GOPG3_IDCLK1 (2 << 2) 270 #define CKG_GOPG3_OCC_FRCCLK (3 << 2) 271 #define CKG_GOPG3_MIXERCLK_VE (4 << 2) 272 #define CKG_GOPG3_FCLK (8 << 2) 273 #define CKG_GOPG3_DISABLE_CLK_MASK (GOP_BIT0) 274 #define CKG_GOPG3_MASK (GOP_BIT5 | GOP_BIT4 | GOP_BIT3 | GOP_BIT2) 275 #define CKG_GOPD_DISABLE_CLK ~(GOP_BIT8) 276 277 278 /* GOP4 CLK*/ 279 #define GOP_GOP4CLK (CKG_REG_BASE+(0x7E<<1)) 280 #define CKG_GOPG4_ODCLK (0 << 10) 281 #define CKG_GOPG4_IDCLK2 (1 << 10) 282 #define CKG_GOPG4_IDCLK1 (2 << 10) 283 #define CKG_GOPG4_OCC_FRCCLK (3 << 10) 284 #define CKG_GOPG4_MIXERCLK_VE (4 << 10) 285 #define CKG_GOPG4_FCLK (9 << 10) 286 #define CKG_GOPG4_DISABLE_CLK_MASK (GOP_BIT8) 287 #define CKG_GOPG4_MASK (GOP_BIT13 |GOP_BIT12 | GOP_BIT11 | GOP_BIT10) 288 289 290 /* SRAM CLK */ 291 #define GOP_SRAMCLK (CKG_REG_BASE+(0x43<<1)) 292 #define CKG_SRAM0_DISABLE_CLK (GOP_BIT0) 293 #define CKG_SRAM1_DISABLE_CLK (GOP_BIT8) 294 #define CKG_SRAM0_MASK (GOP_BIT0|GOP_BIT1) 295 #define CKG_SRAM1_MASK (GOP_BIT8|GOP_BIT9) 296 297 /* LINE BUFFER SRAM CLK */ 298 #define GOP_LB_SRAMCLK (CKG_REG_BASE+(0x45<<1)) 299 #define CKG_LB_SRAM1_DISABLE_CLK (GOP_BIT0) /*GOP1*/ 300 #define CKG_LB_SRAM2_DISABLE_CLK (GOP_BIT4) /*GOP2*/ 301 #define CKG_LB_SRAM1_MASK (GOP_BIT2|GOP_BIT3) 302 #define CKG_LB_SRAM2_MASK (GOP_BIT6|GOP_BIT7) 303 304 /*AFBC CLK*/ 305 #define GOP_AFBCCLK (CKG_REG_BASE+(0x46<<1)) 306 #define CKG_AFBCCLK_DISABLE_CLK (GOP_BIT0) 307 #define CKG_AFBCCLK_432 (0 << 2) 308 #define CKG_AFBCCLK_216 (1 << 2) 309 #define CKG_AFBCCLK_DISABLE_CLK_MASK (GOP_BIT0|GOP_BIT1|GOP_BIT2|GOP_BIT3) 310 311 //---------------------------------------------------------------------------- 312 // MIU Reg 313 //---------------------------------------------------------------------------- 314 #define GOP_CLIENT_REG 0x7E 315 #define GOP_MIU_GROUP (MIU0_REG_BASE+(GOP_CLIENT_REG*2)) 316 317 #define USE_XCBANK_MIU_SELECT 1 318 #if USE_XCBANK_MIU_SELECT==1 319 #define GOP_MIU_GROUP1 REG_SC_BK7F_10_L 320 #define GOP_MIU_GROUP2 REG_SC_BK7F_18_L 321 #else 322 #define GOP_MIU_GROUP1 (MIU_REG_BASE+(GOP_CLIENT_REG*2)) 323 #define GOP_MIU_GROUP2 (MIU2_REG_BASE+(GOP_CLIENT_REG*2)) 324 #endif 325 326 /*Define each gop miu clint bit*/ 327 #define GOP_MIU_CLIENT_DWIN 0xFF 328 #define GOP_MIU_CLIENT_GOP0 0x5 329 #define GOP_MIU_CLIENT_GOP1 0x6 330 #define GOP_MIU_CLIENT_GOP2 0x7 331 #define GOP_MIU_CLIENT_GOP3 0x8 332 #define GOP_MIU_CLIENT_GOP4 0x6 333 #define GOP_MIU_CLIENT_GOP5 0xff 334 335 //---------------------------------------------------------------------------- 336 // VE Reg 337 //---------------------------------------------------------------------------- 338 #define GOP_VE_TVS_OSD_EN 0x60 339 #define GOP_VE_TVS_OSD1_EN 0x61 340 341 //---------------------------------------------------------------------------- 342 // GOP Reg 343 //---------------------------------------------------------------------------- 344 #define GOP_REG(bk, reg) (GOP_REG_BASE+((MS_U32)(bk)<<16) + (reg) * 2) 345 #define __GOP_REG(reg) (GOP_REG_BASE+(reg) * 2) 346 #define GOP_REG_DIRECT_BASE (0x120200) 347 #define GOP_REG_GOP4_BK_OFFSET 0x1900 348 #define GOP_REG_GOP4_GW_OFFSET 0x1C00 349 #define GOP_REG_GOP4_ST_OFFSET 0x1D00 350 351 #define GOP_REG_VAL(x) (1<<x) 352 353 //MUX Setting 354 #define GOP_MUX_SHIFT 0x3 355 #define GOP_REGMUX_MASK BMASK((GOP_MUX_SHIFT-1):0) 356 #define GOP_MUX0_MASK (GOP_REGMUX_MASK<<(GOP_MUX_SHIFT*0)) 357 #define GOP_MUX1_MASK (GOP_REGMUX_MASK<<(GOP_MUX_SHIFT*1)) 358 #define GOP_MUX2_MASK (GOP_REGMUX_MASK<<(GOP_MUX_SHIFT*2)) 359 #define GOP_MUX3_MASK (GOP_REGMUX_MASK<<(GOP_MUX_SHIFT*3)) 360 #define GOP_MUX4_MASK (GOP_REGMUX_MASK<<(GOP_MUX_SHIFT*4)) 361 362 //IP and VOP MUX Setting 363 #define GOP_IP_MAIN_MUX_SHIFT 0 364 #define GOP_IP_MAIN_MUX_MASK (BMASK((GOP_MUX_SHIFT-1):0))<<GOP_IP_MAIN_MUX_SHIFT 365 #define GOP_IP_SUB_MUX_SHIFT 3 366 #define GOP_IP_SUB_MUX_MASK (BMASK((GOP_MUX_SHIFT-1):0))<<GOP_IP_SUB_MUX_SHIFT 367 #define GOP_IP_VOP0_MUX_SHIFT 6 368 #define GOP_IP_VOP0_MUX_MASK (BMASK((GOP_MUX_SHIFT-1):0))<<GOP_IP_VOP0_MUX_SHIFT 369 #define GOP_IP_VOP1_MUX_SHIFT 9 370 #define GOP_IP_VOP1_MUX_MASK (BMASK((GOP_MUX_SHIFT-1):0))<<GOP_IP_VOP1_MUX_SHIFT 371 372 373 //IP and VOP MUX Setting 374 #define GOP_Mix_MUX0_SHIFT 0 375 #define GOP_Mix_MUX0_MASK (BMASK((GOP_MUX_SHIFT-1):0))<<GOP_Mix_MUX0_SHIFT 376 #define GOP_Mix_MUX1_SHIFT 3 377 #define GOP_Mix_MUX1_MASK (BMASK((GOP_MUX_SHIFT-1):0))<<GOP_Mix_MUX1_SHIFT 378 #define GOP_VE0_MUX_SHIFT 6 379 #define GOP_VE0_MUX_MASK (BMASK((GOP_MUX_SHIFT-1):0))<<GOP_VE0_MUX_SHIFT 380 #define GOP_VE1_MUX_SHIFT 9 381 #define GOP_VE1_MUX_MASK (BMASK((GOP_MUX_SHIFT-1):0))<<GOP_VE1_MUX_SHIFT 382 383 384 //4k2k FRC MUX Setting 385 #define GOP_FRC_MUX_SHIFT 0x3 386 #define GOP_FRC_REGMUX_MASK BMASK((GOP_MUX_SHIFT-1):0) 387 #define GOP_FRC_MUX0_MASK (GOP_REGMUX_MASK<<(GOP_MUX_SHIFT*0)) 388 #define GOP_FRC_MUX1_MASK (GOP_REGMUX_MASK<<(GOP_MUX_SHIFT*1)) 389 #define GOP_FRC_MUX2_MASK (GOP_REGMUX_MASK<<(GOP_MUX_SHIFT*2)) 390 #define GOP_FRC_MUX3_MASK (GOP_REGMUX_MASK<<(GOP_MUX_SHIFT*3)) 391 392 //4K@120 MUX Setting 393 #define GOP_4K120_MUX_COUNT 3 394 #define GOP_4K120_MUX_SHIFT 0x2 395 #define GOP_4K120_REGMUX_MASK BMASK((GOP_4K120_MUX_SHIFT-1):0) 396 #define GOP_4K120_MUX0_MASK (GOP_4K120_REGMUX_MASK<<(GOP_4K120_MUX_SHIFT*0)) 397 #define GOP_4K120_MUX1_MASK (GOP_4K120_REGMUX_MASK<<(GOP_4K120_MUX_SHIFT*1)) 398 #define GOP_4K120_MUX2_MASK (GOP_4K120_REGMUX_MASK<<(GOP_4K120_MUX_SHIFT*2)) 399 #define GOP_4K120MUX_MUX0 0 400 #define GOP_4K120MUX_MUX1 1 401 #define GOP_4K120MUX_MUX2 2 402 403 // for gwin color format mask 404 #define GOP_REG_COLORTYPE_MASK BMASK(4:0) 405 #define GOP_REG_COLORTYPE_SHIFT 4 406 407 //DIP Setting 408 #define GOP_DIP_MUX_SHIFT 12 409 #define GOP_DIP_MUX_MASK (BMASK((GOP_MUX_SHIFT-1):0))<<GOP_DIP_MUX_SHIFT 410 411 #define GOP_BANK_OFFSET 0x3 412 #define GOP_4G_OFST 0x0 413 #define GOP_2G_OFST (0x1*GOP_BANK_OFFSET) 414 #define GOP_1G_OFST (0x2*GOP_BANK_OFFSET) 415 #define GOP_1GX_OFST (0x3*GOP_BANK_OFFSET) 416 #define GOP_DW_OFST (0x4*GOP_BANK_OFFSET) 417 #define GOP_1GS0_OFST 0xE 418 #define GOP_1GS1_OFST 0x11 419 #define GOP_AFBC_OFST 0x31 420 421 #define GOP_OFFSET_WR 8 422 #define GOP_VAL_WR GOP_REG_VAL(GOP_OFFSET_WR) 423 #define GOP_OFFSET_FWR 9 424 #define GOP_VAL_FWR GOP_REG_VAL(GOP_OFFSET_FWR) 425 #define GOP_OFFSET_FCLR 11 426 #define GOP_VAL_FCL GOP_REG_VAL(GOP_OFFSET_FCLR) 427 #define GOP4G_OFFSET_WR_ACK 12 428 #define GOP4G_VAL_WR_ACK GOP_REG_VAL(GOP4G_OFFSET_WR_ACK) 429 #define GOP2G_OFFSET_WR_ACK 13 430 #define GOP2G_VAL_WR_ACK GOP_REG_VAL(GOP2G_OFFSET_WR_ACK) 431 #define GOPD_OFFSET_WR_ACK 14 432 #define GOPD_VAL_WR_ACK GOP_REG_VAL(GOPD_OFFSET_WR_ACK) 433 #define GOP1G_OFFSET_WR_ACK 15 434 #define GOP1G_VAL_WR_ACK GOP_REG_VAL(GOPD_OFFSET_WR_ACK) 435 #define GOP_VAL_ACK(x) GOP_REG_VAL(GOP4G_OFFSET_WR_ACK+x) 436 437 #define GOP_4G_CTRL0 GOP_REG(GOP_4G_OFST, 0x00) 438 #define GOP_4G_CTRL1 GOP_REG(GOP_4G_OFST, 0x01) 439 #define GOP_4G_RATE GOP_REG(GOP_4G_OFST, 0x02) 440 #define GOP_4G_PALDATA_L GOP_REG(GOP_4G_OFST, 0x03) 441 #define GOP_4G_PALDATA_H GOP_REG(GOP_4G_OFST, 0x04) 442 #define GOP_4G_PALCTRL GOP_REG(GOP_4G_OFST, 0x05) 443 #define GOP_4G_REGDMA_END GOP_REG(GOP_4G_OFST, 0x06) 444 #define GOP_4G_REGDMA_STR GOP_REG(GOP_4G_OFST, 0x07) 445 #define GOP_4G_INT GOP_REG(GOP_4G_OFST, 0x08) 446 #define GOP_4G_HWSTATE GOP_REG(GOP_4G_OFST, 0x09) 447 #define GOP_4G_SVM_HSTR GOP_REG(GOP_4G_OFST, 0x0a) 448 #define GOP_4G_SVM_HEND GOP_REG(GOP_4G_OFST, 0x0b) 449 #define GOP_4G_SVM_VSTR GOP_REG(GOP_4G_OFST, 0x0c) 450 #define GOP_4G_SVM_VEND GOP_REG(GOP_4G_OFST, 0x0d) 451 #define GOP_4G_RDMA_HT GOP_REG(GOP_4G_OFST, 0x0e) 452 #define GOP_4G_HS_PIPE GOP_REG(GOP_4G_OFST, 0x0f) 453 #define GOP_4G_SLOW GOP_REG(GOP_4G_OFST, 0x10) 454 #define GOP_4G_BRI GOP_REG(GOP_4G_OFST, 0x11) 455 #define GOP_4G_CON GOP_REG(GOP_4G_OFST, 0x12) 456 #define GOP_4G_BW GOP_REG(GOP_4G_OFST, 0x19) 457 #define GOP_4G_NEW_BW GOP_REG(GOP_4G_OFST, 0x1C) 458 #define GOP_4G_SRAM_BORROW GOP_REG(GOP_4G_OFST, 0x1D) 459 #define GOP_4G_3D_MIDDLE GOP_REG(GOP_4G_OFST, 0x1E) 460 #define GOP_4G_MIU_SEL GOP_REG(GOP_4G_OFST, 0x1F) 461 #define GOP_4G_PRI0 GOP_REG(GOP_4G_OFST, 0x20) 462 #define GOP_4G_BOT_HS GOP_REG(GOP_4G_OFST, 0x23) 463 #define GOP_4G_TRSCLR_L GOP_REG(GOP_4G_OFST, 0x24) 464 #define GOP_4G_TRSCLR_H GOP_REG(GOP_4G_OFST, 0x25) 465 #define GOP_4G_TRSCLR_TUV_L GOP_REG(GOP_4G_OFST, 0x26) 466 #define GOP_4G_TRSCLR_TUV_H GOP_REG(GOP_4G_OFST, 0x27) 467 #define GOP_4G_YUV_SWAP GOP_REG(GOP_4G_OFST, 0x28) 468 #define GOP_4G_OP_MUX_DBF GOP_REG(GOP_4G_OFST, 0x29) 469 #define GOP_4G_CROP_HSTART GOP_REG(GOP_4G_OFST, 0x2A) 470 #define GOP_4G_CROP_HEND GOP_REG(GOP_4G_OFST, 0x2B) 471 #define GOP_4G_CROP_VSTART GOP_REG(GOP_4G_OFST, 0x2C) 472 #define GOP_4G_CROP_VEND GOP_REG(GOP_4G_OFST, 0x2D) 473 #define GOP_4G_STRCH_HSZ GOP_REG(GOP_4G_OFST, 0x30) 474 #define GOP_4G_STRCH_VSZ GOP_REG(GOP_4G_OFST, 0x31) 475 #define GOP_4G_STRCH_HSTR GOP_REG(GOP_4G_OFST, 0x32) 476 #define GOP_4G_STRCH_VSTR GOP_REG(GOP_4G_OFST, 0x34) 477 #define GOP_4G_HSTRCH GOP_REG(GOP_4G_OFST, 0x35) 478 #define GOP_4G_VSTRCH GOP_REG(GOP_4G_OFST, 0x36) 479 #define GOP_4G_HSTRCH_INI GOP_REG(GOP_4G_OFST, 0x38) 480 #define GOP_4G_VSTRCH_INI GOP_REG(GOP_4G_OFST, 0x39) 481 #define GOP_4G_HVSTRCHMD GOP_REG(GOP_4G_OFST, 0x3a) 482 #define GOP_4G_OLDADDR GOP_REG(GOP_4G_OFST, 0x3b) 483 #define GOP_4G_MULTI_ALPHA GOP_REG(GOP_4G_OFST, 0x3c) 484 #define GOP_4G_TWO_LINEBUFFER GOP_4G_MULTI_ALPHA 485 #define GOP_4G_VIP_VOP_TIMING_SEL GOP_4G_MULTI_ALPHA 486 #define GOP_4G_SPLIT_LRSZ GOP_REG(GOP_4G_OFST, 0x3E) 487 #define GOP_4G_HW_USAGE GOP_REG(GOP_4G_OFST, 0x40) 488 #define GOP_4G_BANK_FWR GOP_REG(GOP_4G_OFST, 0x50) 489 #define GOP_4G_BANK_HVAILDSIZE GOP_REG(GOP_4G_OFST, 0x52) 490 #define GOP_4G_BANK_VVAILDSIZE GOP_REG(GOP_4G_OFST, 0x53) 491 #define GOP_4G_SCALING_H_OUTPUTSIZE GOP_REG(GOP_4G_OFST, 0x56) 492 #define GOP_4G_SCALING_HRATIO_L GOP_REG(GOP_4G_OFST, 0x59) //GOP scaling down ratio dst / out * 2^20 493 #define GOP_4G_SCALING_HRATIO_H GOP_REG(GOP_4G_OFST, 0x5A) 494 #define GOP_4G_SCALING_CFG GOP_REG(GOP_4G_OFST, 0x5B) 495 #define GOP_4G_SCALING_VRATIO_L GOP_REG(GOP_4G_OFST, 0x5C) //GOP scaling down ratio dst / out * 2^20 496 #define GOP_4G_SCALING_VRATIO_H GOP_REG(GOP_4G_OFST, 0x5D) 497 498 499 #define GOP_4G_RBLK0_VOFFL GOP_REG(GOP_4G_OFST, 0x60) 500 #define GOP_4G_RBLK0_VOFFH GOP_REG(GOP_4G_OFST, 0x61) 501 #define GOP_4G_RBLK1_VOFFL GOP_REG(GOP_4G_OFST, 0x62) 502 #define GOP_4G_RBLK1_VOFFH GOP_REG(GOP_4G_OFST, 0x63) 503 #define GOP_4G_RBLK2_VOFFL GOP_REG(GOP_4G_OFST, 0x64) 504 #define GOP_4G_RBLK2_VOFFH GOP_REG(GOP_4G_OFST, 0x65) 505 #define GOP_4G_RBLK3_VOFFL GOP_REG(GOP_4G_OFST, 0x66) 506 #define GOP_4G_RBLK3_VOFFH GOP_REG(GOP_4G_OFST, 0x67) 507 #define GOP_4G_SLPIT_GUARDBAND GOP_REG(GOP_4G_OFST, 0x6C) 508 #define GOP_4G_SLPIT_SHIFT_PIPE GOP_REG(GOP_4G_OFST, 0x6D) 509 #define GOP_4G_RBLK0_HOFF GOP_REG(GOP_4G_OFST, 0x70) 510 #define GOP_4G_RBLK1_HOFF GOP_REG(GOP_4G_OFST, 0x71) 511 #define GOP_4G_RBLK2_HOFF GOP_REG(GOP_4G_OFST, 0x72) 512 #define GOP_4G_RBLK3_HOFF GOP_REG(GOP_4G_OFST, 0x73) 513 #define GOP_4G_REGDMA_EN GOP_REG(GOP_4G_OFST, 0x78) 514 #define GOP_4G_SPLIT_LRSZ GOP_REG(GOP_4G_OFST, 0x3E) 515 #define GOP_MUX_IPVOP __GOP_REG(0x77) 516 #define GOP_MUX4_4K120 __GOP_REG(0x7A) 517 #define GOP_MUX4_MIX_VE __GOP_REG(0x7B) 518 #define GOP_BAK_SEL_EX __GOP_REG(0x7C) 519 #define GOP_MUX_4K2K __GOP_REG(0x7D) 520 #define GOP_MUX __GOP_REG(0x7e) 521 #define GOP_BAK_SEL __GOP_REG(0x7f) 522 523 #define GOP_4G_GWIN0_CTRL(id) GOP_REG(GOP_4G_OFST+1, 0x00 + (0x20*((id)%MAX_GOP0_GWIN))) 524 #define GOP_4G_DRAM_RBLK_L(id) GOP_REG(GOP_4G_OFST+1, 0x01 + (0x20*((id)%MAX_GOP0_GWIN))) 525 #define GOP_4G_DRAM_RBLK_H(id) GOP_REG(GOP_4G_OFST+1, 0x02 + (0x20*((id)%MAX_GOP0_GWIN))) 526 #define GOP_4G_DEL_PIXEL(id) GOP_REG(GOP_4G_OFST+1, 0x03 + (0x20*((id)%MAX_GOP1_GWIN))) 527 #define GOP_4G_HSTR(id) GOP_REG(GOP_4G_OFST+1, 0x04 + (0x20*((id)%MAX_GOP0_GWIN))) 528 #define GOP_4G_HEND(id) GOP_REG(GOP_4G_OFST+1, 0x05 + (0x20*((id)%MAX_GOP0_GWIN))) 529 #define GOP_4G_VSTR(id) GOP_REG(GOP_4G_OFST+1, 0x06 + (0x20*((id)%MAX_GOP0_GWIN))) 530 #define GOP_4G_GWIN_MIDDLE(id) GOP_REG(GOP_4G_OFST+1, 0x07 + (0x20*((id)%MAX_GOP0_GWIN))) 531 #define GOP_4G_VEND(id) GOP_REG(GOP_4G_OFST+1, 0x08 + (0x20*((id)%MAX_GOP0_GWIN))) 532 #define GOP_4G_DRAM_RBLK_HSIZE(id) GOP_REG(GOP_4G_OFST+1, 0x09 + (0x20*((id)%MAX_GOP0_GWIN))) 533 #define GOP_4G_GWIN_ALPHA01(id) GOP_REG(GOP_4G_OFST+1, 0x0A + (0x20*((id)%MAX_GOP0_GWIN))) 534 #define GOP_4G_DRAM_VSTR_L(id) GOP_REG(GOP_4G_OFST+1, 0x0C + (0x20*((id)%MAX_GOP0_GWIN))) 535 #define GOP_4G_DRAM_VSTR_H(id) GOP_REG(GOP_4G_OFST+1, 0x0D + (0x20*((id)%MAX_GOP0_GWIN))) 536 #define GOP_4G_DRAM_HSTR(id) GOP_REG(GOP_4G_OFST+1, 0x0E + (0x20*((id)%MAX_GOP0_GWIN))) 537 #define GOP_4G_DRAM_RBLK_SIZE_L(id) GOP_REG(GOP_4G_OFST+1, 0x10 + (0x20*((id)%MAX_GOP0_GWIN))) 538 #define GOP_4G_DRAM_RBLK_SIZE_H(id) GOP_REG(GOP_4G_OFST+1, 0x11 + (0x20*((id)%MAX_GOP0_GWIN))) 539 #define GOP_4G_DRAM_RLEN_L(id) GOP_REG(GOP_4G_OFST+1, 0x12 + (0x20*((id)%MAX_GOP0_GWIN))) 540 #define GOP_4G_DRAM_RLEN_H(id) GOP_REG(GOP_4G_OFST+1, 0x13 + (0x20*((id)%MAX_GOP0_GWIN))) 541 #define GOP_4G_DRAM_HVSTOP_L(id) GOP_REG(GOP_4G_OFST+1, 0x14 + (0x20*((id)%MAX_GOP0_GWIN))) 542 #define GOP_4G_DRAM_HVSTOP_H(id) GOP_REG(GOP_4G_OFST+1, 0x15 + (0x20*((id)%MAX_GOP0_GWIN))) 543 #define GOP_4G_DRAM_FADE(id) GOP_REG(GOP_4G_OFST+1, 0x16 + (0x20*((id)%MAX_GOP0_GWIN))) 544 #define GOP_4G_BG_CLR(id) GOP_REG(GOP_4G_OFST+1, 0x18 + (0x20*((id)%MAX_GOP0_GWIN))) 545 #define GOP_4G_BG_HSTR(id) GOP_REG(GOP_4G_OFST+1, 0x19 + (0x20*((id)%MAX_GOP0_GWIN))) 546 #define GOP_4G_BG_HEND(id) GOP_REG(GOP_4G_OFST+1, 0x1a + (0x20*((id)%MAX_GOP0_GWIN))) 547 #define GOP_4G_BG_VSTR(id) GOP_REG(GOP_4G_OFST+1, 0x1C + (0x20*((id)%MAX_GOP0_GWIN))) 548 #define GOP_4G_BG_VEND(id) GOP_REG(GOP_4G_OFST+1, 0x1D + (0x20*((id)%MAX_GOP0_GWIN))) 549 #define GOP_4G_3DOSD_SUB_RBLK_L(id) GOP_REG(GOP_4G_OFST+1, 0x1E + (0x20*((id)%MAX_GOP0_GWIN))) 550 #define GOP_4G_3DOSD_SUB_RBLK_H(id) GOP_REG(GOP_4G_OFST+1, 0x1F + (0x20*((id)%MAX_GOP0_GWIN))) 551 552 553 #define GOP_2G_CTRL0 GOP_REG(GOP_2G_OFST, 0x00) 554 #define GOP_2G_CTRL1 GOP_REG(GOP_2G_OFST, 0x01) 555 #define GOP_2G_RATE GOP_REG(GOP_2G_OFST, 0x02) 556 #define GOP_2G_PALDATA_L GOP_REG(GOP_2G_OFST, 0x03) 557 #define GOP_2G_PALDATA_H GOP_REG(GOP_2G_OFST, 0x04) 558 #define GOP_2G_PALCTRL GOP_REG(GOP_2G_OFST, 0x05) 559 #define GOP_2G_REGDMA_END GOP_REG(GOP_2G_OFST, 0x06) 560 #define GOP_2G_REGDMA_STR GOP_REG(GOP_2G_OFST, 0x07) 561 #define GOP_2G_INT GOP_REG(GOP_2G_OFST, 0x08) 562 #define GOP_2G_HWSTATE GOP_REG(GOP_2G_OFST, 0x09) 563 #define GOP_2G_RDMA_HT GOP_REG(GOP_2G_OFST, 0x0e) 564 #define GOP_2G_HS_PIPE GOP_REG(GOP_2G_OFST, 0x0f) 565 #define GOP_2G_SLOW GOP_REG(GOP_2G_OFST, 0x10) 566 #define GOP_2G_BRI GOP_REG(GOP_2G_OFST, 0x11) 567 #define GOP_2G_CON GOP_REG(GOP_2G_OFST, 0x12) 568 #define GOP_2G_BW GOP_REG(GOP_2G_OFST, 0x19) 569 #define GOP_2G_3D_MIDDLE GOP_REG(GOP_2G_OFST, 0x1E) 570 #define GOP_2G_PRI0 GOP_REG(GOP_2G_OFST, 0x20) 571 #define GOP_2G_TRSCLR_L GOP_REG(GOP_2G_OFST, 0x24) 572 #define GOP_2G_TRSCLR_H GOP_REG(GOP_2G_OFST, 0x25) 573 #define GOP_2G_STRCH_HSZ GOP_REG(GOP_2G_OFST, 0x30) 574 #define GOP_2G_STRCH_VSZ GOP_REG(GOP_2G_OFST, 0x31) 575 #define GOP_2G_STRCH_HSTR GOP_REG(GOP_2G_OFST, 0x32) 576 #define GOP_2G_STRCH_VSTR GOP_REG(GOP_2G_OFST, 0x34) 577 #define GOP_2G_HSTRCH GOP_REG(GOP_2G_OFST, 0x35) 578 #define GOP_2G_VSTRCH GOP_REG(GOP_2G_OFST, 0x36) 579 #define GOP_2G_HSTRCH_INI GOP_REG(GOP_2G_OFST, 0x38) 580 #define GOP_2G_VSTRCH_INI GOP_REG(GOP_2G_OFST, 0x39) 581 #define GOP_2G_HVStrch_MD GOP_REG(GOP_2G_OFST, 0x3a) 582 #define GOP_2G_OLDADDR GOP_REG(GOP_2G_OFST, 0x3b) 583 #define GOP_2G_MULTI_ALPHA GOP_REG(GOP_2G_OFST, 0x3c) 584 #define GOP_2G_REGDMA_EN GOP_REG(GOP_2G_OFST, 0x78) 585 586 587 #define GOP_2G_GWIN0_CTRL(id) GOP_REG(GOP_2G_OFST+1, 0x00 + (0x20*((id)%MAX_GOP1_GWIN))) 588 #define GOP_2G_GWIN_CTRL(id) GOP_REG(GOP_2G_OFST+1, 0x00 + (0x20*((id)%MAX_GOP1_GWIN))) 589 #define GOP_2G_DRAM_RBLK_L(id) GOP_REG(GOP_2G_OFST+1, 0x01 + (0x20*((id)%MAX_GOP1_GWIN))) 590 #define GOP_2G_DRAM_RBLK_H(id) GOP_REG(GOP_2G_OFST+1, 0x02 + (0x20*((id)%MAX_GOP1_GWIN))) 591 #define GOP_2G_DEL_PIXEL(id) GOP_REG(GOP_2G_OFST+1, 0x03 + (0x20*((id)%MAX_GOP1_GWIN))) 592 #define GOP_2G_HSTR(id) GOP_REG(GOP_2G_OFST+1, 0x04 + (0x20*((id)%MAX_GOP1_GWIN))) 593 #define GOP_2G_HEND(id) GOP_REG(GOP_2G_OFST+1, 0x05 + (0x20*((id)%MAX_GOP1_GWIN))) 594 #define GOP_2G_VSTR(id) GOP_REG(GOP_2G_OFST+1, 0x06 + (0x20*((id)%MAX_GOP1_GWIN))) 595 #define GOP_2G_VEND(id) GOP_REG(GOP_2G_OFST+1, 0x08 + (0x20*((id)%MAX_GOP1_GWIN))) 596 #define GOP_2G_DRAM_RBLK_HSIZE(id) GOP_REG(GOP_2G_OFST+1, 0x09 + (0x20*((id)%MAX_GOP1_GWIN))) 597 #define GOP_2G_GWIN_ALPHA01(id) GOP_REG(GOP_2G_OFST+1, 0x0A + (0x20*((id)%MAX_GOP1_GWIN))) 598 #define GOP_2G_DRAM_VSTR_L(id) GOP_REG(GOP_2G_OFST+1, 0x0C + (0x20*((id)%MAX_GOP1_GWIN))) 599 #define GOP_2G_DRAM_VSTR_H(id) GOP_REG(GOP_2G_OFST+1, 0x0D + (0x20*((id)%MAX_GOP1_GWIN))) 600 #define GOP_2G_DRAM_FADE(id) GOP_REG(GOP_2G_OFST+1, 0x16 + (0x20*((id)%MAX_GOP1_GWIN))) 601 #define GOP_2G_3DOSD_SUB_RBLK_L(id) GOP_REG(GOP_2G_OFST+1, 0x1E + (0x20*((id)%MAX_GOP1_GWIN))) 602 #define GOP_2G_3DOSD_SUB_RBLK_H(id) GOP_REG(GOP_2G_OFST+1, 0x1F + (0x20*((id)%MAX_GOP1_GWIN))) 603 604 // DWIN reg 605 #define GOP_DW_CTL0_EN GOP_REG(GOP_DW_OFST, 0x00) 606 #define GOP_DWIN_EN (0x00) 607 #define GOP_DWIN_EN_VAL GOP_REG_VAL(GOP_DWIN_EN) 608 #define GOP_DWIN_SHOT (0x07) 609 #define GOP_DWIN_SHOT_VAL GOP_REG_VAL(GOP_DWIN_SHOT) 610 611 #define GOP_DW_LSTR_WBE GOP_REG(GOP_DW_OFST, 0x01) 612 #define GOP_DW_INT_MASK GOP_REG(GOP_DW_OFST, 0x02) 613 #define GOP_DW_DEBUG GOP_REG(GOP_DW_OFST, 0x03) 614 #define GOP_DW_ALPHA GOP_REG(GOP_DW_OFST, 0x04) 615 #define GOP_DW_BW GOP_REG(GOP_DW_OFST, 0x05) 616 #define GOP_DW_VSTR GOP_REG(GOP_DW_OFST, 0x10) 617 #define GOP_DW_HSTR GOP_REG(GOP_DW_OFST, 0x11) 618 #define GOP_DW_VEND GOP_REG(GOP_DW_OFST, 0x12) 619 #define GOP_DW_HEND GOP_REG(GOP_DW_OFST, 0x13) 620 #define GOP_DW_HSIZE GOP_REG(GOP_DW_OFST, 0x14) 621 #define GOP_DW_JMPLEN GOP_REG(GOP_DW_OFST, 0x15) 622 #define GOP_DW_DSTR_L GOP_REG(GOP_DW_OFST, 0x16) 623 #define GOP_DW_DSTR_H GOP_REG(GOP_DW_OFST, 0x17) 624 #define GOP_DW_UB_L GOP_REG(GOP_DW_OFST, 0x18) 625 #define GOP_DW_UB_H GOP_REG(GOP_DW_OFST, 0x19) 626 627 #define GOP_DW_PON_DSTR_L GOP_REG(GOP_DW_OFST, 0x1a) 628 #define GOP_DW_PON_DSTR_H GOP_REG(GOP_DW_OFST, 0x1b) 629 #define GOP_DW_PON_UB_L GOP_REG(GOP_DW_OFST, 0x1c) 630 #define GOP_DW_PON_UB_H GOP_REG(GOP_DW_OFST, 0x1d) 631 #define GOP_DW_FRAME_CTRL GOP_REG(GOP_DW_OFST, 0x30) 632 633 #define GOP_1G_CTRL0 GOP_REG(GOP_1G_OFST, 0x00) 634 #define GOP_1G_CTRL1 GOP_REG(GOP_1G_OFST, 0x01) 635 #define GOP_1G_RATE GOP_REG(GOP_1G_OFST, 0x02) 636 #define GOP_1G_PALDATA_L GOP_REG(GOP_1G_OFST, 0x03) 637 #define GOP_1G_PALDATA_H GOP_REG(GOP_1G_OFST, 0x04) 638 #define GOP_1G_PALCTRL GOP_REG(GOP_1G_OFST, 0x05) 639 #define GOP_1G_REGDMA_END GOP_REG(GOP_1G_OFST, 0x06) 640 #define GOP_1G_REGDMA_STR GOP_REG(GOP_1G_OFST, 0x07) 641 #define GOP_1G_INT GOP_REG(GOP_1G_OFST, 0x08) 642 #define GOP_1G_HWSTATE GOP_REG(GOP_1G_OFST, 0x09) 643 #define GOP_1G_RDMA_HT GOP_REG(GOP_1G_OFST, 0x0e) 644 #define GOP_1G_HS_PIPE GOP_REG(GOP_1G_OFST, 0x0f) 645 #define GOP_1G_BRI GOP_REG(GOP_1G_OFST, 0x11) 646 #define GOP_1G_CON GOP_REG(GOP_1G_OFST, 0x12) 647 #define GOP_1G_BW GOP_REG(GOP_1G_OFST, 0x19) 648 #define GOP_1G_3D_MIDDLE GOP_REG(GOP_1G_OFST, 0x1E) 649 #define GOP_1G_TRSCLR_L GOP_REG(GOP_1G_OFST, 0x24) 650 #define GOP_1G_TRSCLR_H GOP_REG(GOP_1G_OFST, 0x25) 651 #define GOP_1G_STRCH_HSZ GOP_REG(GOP_1G_OFST, 0x30) 652 #define GOP_1G_STRCH_VSZ GOP_REG(GOP_1G_OFST, 0x31) 653 #define GOP_1G_STRCH_HSTR GOP_REG(GOP_1G_OFST, 0x32) 654 #define GOP_1G_STRCH_VSTR GOP_REG(GOP_1G_OFST, 0x34) 655 #define GOP_1G_HSTRCH GOP_REG(GOP_1G_OFST, 0x35) 656 #define GOP_1G_HSTRCH_INI GOP_REG(GOP_1G_OFST, 0x38) 657 #define GOP_1G_VSTRCH_INI GOP_REG(GOP_1G_OFST, 0x39) 658 #define GOP_1G_HStrch_MD GOP_REG(GOP_1G_OFST, 0x3a) 659 #define GOP_1G_OLDADDR GOP_REG(GOP_1G_OFST, 0x3b) 660 #define GOP_1G_MULTI_ALPHA GOP_REG(GOP_1G_OFST, 0x3c) 661 662 #define GOP_1G_GWIN0_CTRL GOP_REG(GOP_1G_OFST+1, 0x0) 663 #define GOP_1G_DRAM_RBLK_L GOP_REG(GOP_1G_OFST+1, 0x1) 664 #define GOP_1G_DRAM_RBLK_H GOP_REG(GOP_1G_OFST+1, 0x2) 665 #define GOP_1G_DEL_PIXEL GOP_REG(GOP_1G_OFST+1, 0x3) 666 #define GOP_1G_HSTR GOP_REG(GOP_1G_OFST+1, 0x4) 667 #define GOP_1G_HEND GOP_REG(GOP_1G_OFST+1, 0x5) 668 #define GOP_1G_VSTR GOP_REG(GOP_1G_OFST+1, 0x6) 669 #define GOP_1G_VEND GOP_REG(GOP_1G_OFST+1, 0x8) 670 #define GOP_1G_DRAM_RBLK_HSIZE GOP_REG(GOP_1G_OFST+1, 0x9) 671 #define GOP_1G_GWIN_ALPHA01 GOP_REG(GOP_1G_OFST+1, 0xA) 672 #define GOP_1G_DRAM_VSTR_L GOP_REG(GOP_1G_OFST+1, 0x0C) 673 #define GOP_1G_DRAM_VSTR_H GOP_REG(GOP_1G_OFST+1, 0x0D) 674 #define GOP_1G_DRAM_FADE GOP_REG(GOP_1G_OFST+1, 0x16) 675 #define GOP_1G_3DOSD_SUB_RBLK_L GOP_REG(GOP_1G_OFST+1, 0x1E) 676 #define GOP_1G_3DOSD_SUB_RBLK_H GOP_REG(GOP_1G_OFST+1, 0x1F) 677 678 #define GOP_1GX_CTRL0 GOP_REG(GOP_1GX_OFST, 0x00) 679 #define GOP_1GX_CTRL1 GOP_REG(GOP_1GX_OFST, 0x01) 680 #define GOP_1GX_RATE GOP_REG(GOP_1GX_OFST, 0x02) 681 #define GOP_1GX_PALDATA_L GOP_REG(GOP_1GX_OFST, 0x03) 682 #define GOP_1GX_PALDATA_H GOP_REG(GOP_1GX_OFST, 0x04) 683 #define GOP_1GX_PALCTRL GOP_REG(GOP_1GX_OFST, 0x05) 684 #define GOP_1GX_REGDMA_END GOP_REG(GOP_1GX_OFST, 0x06) 685 #define GOP_1GX_REGDMA_STR GOP_REG(GOP_1GX_OFST, 0x07) 686 #define GOP_1GX_INT GOP_REG(GOP_1GX_OFST, 0x08) 687 #define GOP_1GX_HWSTATE GOP_REG(GOP_1GX_OFST, 0x09) 688 #define GOP_1GX_RDMA_HT GOP_REG(GOP_1GX_OFST, 0x0e) 689 #define GOP_1GX_HS_PIPE GOP_REG(GOP_1GX_OFST, 0x0f) 690 #define GOP_1GX_BRI GOP_REG(GOP_1GX_OFST, 0x11) 691 #define GOP_1GX_CON GOP_REG(GOP_1GX_OFST, 0x12) 692 #define GOP_1GX_BW GOP_REG(GOP_1GX_OFST, 0x19) 693 #define GOP_1GX_3D_MIDDLE GOP_REG(GOP_1GX_OFST, 0x1E) 694 #define GOP_1GX_TRSCLR_L GOP_REG(GOP_1GX_OFST, 0x24) 695 #define GOP_1GX_TRSCLR_H GOP_REG(GOP_1GX_OFST, 0x25) 696 #define GOP_1GX_STRCH_HSZ GOP_REG(GOP_1GX_OFST, 0x30) 697 #define GOP_1GX_STRCH_VSZ GOP_REG(GOP_1GX_OFST, 0x31) 698 #define GOP_1GX_STRCH_HSTR GOP_REG(GOP_1GX_OFST, 0x32) 699 #define GOP_1GX_STRCH_VSTR GOP_REG(GOP_1GX_OFST, 0x34) 700 #define GOP_1GX_HSTRCH GOP_REG(GOP_1GX_OFST, 0x35) 701 #define GOP_1GX_HSTRCH_INI GOP_REG(GOP_1GX_OFST, 0x38) 702 #define GOP_1GX_VSTRCH_INI GOP_REG(GOP_1GX_OFST, 0x39) 703 #define GOP_1GX_HStrch_MD GOP_REG(GOP_1GX_OFST, 0x3a) 704 #define GOP_1GX_OLDADDR GOP_REG(GOP_1GX_OFST, 0x3b) 705 #define GOP_1GX_MULTI_ALPHA GOP_REG(GOP_1GX_OFST, 0x3c) 706 707 #define GOP_1GX_GWIN0_CTRL GOP_REG(GOP_1GX_OFST+1, 0x00) 708 #define GOP_1GX_DRAM_RBLK_L GOP_REG(GOP_1GX_OFST+1, 0x01) 709 #define GOP_1GX_DRAM_RBLK_H GOP_REG(GOP_1GX_OFST+1, 0x02) 710 #define GOP_1GX_DEL_PIXEL GOP_REG(GOP_1GX_OFST+1, 0x03) 711 #define GOP_1GX_HSTR GOP_REG(GOP_1GX_OFST+1, 0x04) 712 #define GOP_1GX_HEND GOP_REG(GOP_1GX_OFST+1, 0x05) 713 #define GOP_1GX_VSTR GOP_REG(GOP_1GX_OFST+1, 0x06) 714 #define GOP_1GX_VEND GOP_REG(GOP_1GX_OFST+1, 0x08) 715 #define GOP_1GX_DRAM_RBLK_HSIZE GOP_REG(GOP_1GX_OFST+1, 0x09) 716 #define GOP_1GX_GWIN_ALPHA01 GOP_REG(GOP_1GX_OFST+1, 0x0A) 717 #define GOP_1GX_DRAM_VSTR_L GOP_REG(GOP_1GX_OFST+1, 0x0C) 718 #define GOP_1GX_DRAM_VSTR_H GOP_REG(GOP_1GX_OFST+1, 0x0D) 719 #define GOP_1GX_DRAM_FADE GOP_REG(GOP_1GX_OFST+1, 0x16) 720 #define GOP_1GX_3DOSD_SUB_RBLK_L GOP_REG(GOP_1GX_OFST+1, 0x1E) 721 #define GOP_1GX_3DOSD_SUB_RBLK_H GOP_REG(GOP_1GX_OFST+1, 0x1F) 722 723 #define GOP_1GS0_CTRL0 GOP_REG(GOP_1GS0_OFST, 0x00) 724 #define GOP_1GS0_CTRL1 GOP_REG(GOP_1GS0_OFST, 0x01) 725 #define GOP_1GS0_RATE GOP_REG(GOP_1GS0_OFST, 0x02) 726 #define GOP_1GS0_PALDATA_L GOP_REG(GOP_1GS0_OFST, 0x03) 727 #define GOP_1GS0_PALDATA_H GOP_REG(GOP_1GS0_OFST, 0x04) 728 #define GOP_1GS0_PALCTRL GOP_REG(GOP_1GS0_OFST, 0x05) 729 #define GOP_1GS0_REGDMA_END GOP_REG(GOP_1GS0_OFST, 0x06) 730 #define GOP_1GS0_REGDMA_STR GOP_REG(GOP_1GS0_OFST, 0x07) 731 #define GOP_1GS0_INT GOP_REG(GOP_1GS0_OFST, 0x08) 732 #define GOP_1GS0_HWSTATE GOP_REG(GOP_1GS0_OFST, 0x09) 733 #define GOP_1GS0_RDMA_HT GOP_REG(GOP_1GS0_OFST, 0x0e) 734 #define GOP_1GS0_HS_PIPE GOP_REG(GOP_1GS0_OFST, 0x0f) 735 #define GOP_1GS0_BRI GOP_REG(GOP_1GS0_OFST, 0x11) 736 #define GOP_1GS0_CON GOP_REG(GOP_1GS0_OFST, 0x12) 737 #define GOP_1GS0_BW GOP_REG(GOP_1GS0_OFST, 0x19) 738 #define GOP_1GS0_TRSCLR_L GOP_REG(GOP_1GS0_OFST, 0x24) 739 #define GOP_1GS0_TRSCLR_H GOP_REG(GOP_1GS0_OFST, 0x25) 740 #define GOP_1GS0_STRCH_HSZ GOP_REG(GOP_1GS0_OFST, 0x30) 741 #define GOP_1GS0_STRCH_VSZ GOP_REG(GOP_1GS0_OFST, 0x31) 742 #define GOP_1GS0_STRCH_HSTR GOP_REG(GOP_1GS0_OFST, 0x32) 743 #define GOP_1GS0_STRCH_VSTR GOP_REG(GOP_1GS0_OFST, 0x34) 744 #define GOP_1GS0_HSTRCH GOP_REG(GOP_1GS0_OFST, 0x35) 745 #define GOP_1GS0_HSTRCH_INI GOP_REG(GOP_1GS0_OFST, 0x38) 746 #define GOP_1GS0_VSTRCH_INI GOP_REG(GOP_1GS0_OFST, 0x39) 747 #define GOP_1GS0_HVStrch_MD GOP_REG(GOP_1GS0_OFST, 0x3a) 748 #define GOP_1GS0_OLDADDR GOP_REG(GOP_1GS0_OFST, 0x3b) 749 #define GOP_1GS0_MULTI_ALPHA GOP_REG(GOP_1GS0_OFST, 0x3c) 750 751 #define GOP_1GS0_GWIN0_CTRL GOP_REG(GOP_1GS0_OFST+1, 0x00) 752 #define GOP_1GS0_DRAM_RBLK_L GOP_REG(GOP_1GS0_OFST+1, 0x01) 753 #define GOP_1GS0_DRAM_RBLK_H GOP_REG(GOP_1GS0_OFST+1, 0x02) 754 #define GOP_1GS0_DEL_PIXEL GOP_REG(GOP_1GS0_OFST+1, 0x03) 755 #define GOP_1GS0_HSTR GOP_REG(GOP_1GS0_OFST+1, 0x04) 756 #define GOP_1GS0_HEND GOP_REG(GOP_1GS0_OFST+1, 0x05) 757 #define GOP_1GS0_VSTR GOP_REG(GOP_1GS0_OFST+1, 0x06) 758 #define GOP_1GS0_VEND GOP_REG(GOP_1GS0_OFST+1, 0x08) 759 #define GOP_1GS0_DRAM_RBLK_HSIZE GOP_REG(GOP_1GS0_OFST+1, 0x09) 760 #define GOP_1GS0_GWIN_ALPHA01 GOP_REG(GOP_1GS0_OFST+1, 0x0A) 761 #define GOP_1GS0_DRAM_VSTR_L GOP_REG(GOP_1GS0_OFST+1, 0x0C) 762 #define GOP_1GS0_DRAM_VSTR_H GOP_REG(GOP_1GS0_OFST+1, 0x0D) 763 #define GOP_1GS0_DRAM_FADE GOP_REG(GOP_1GS0_OFST+1, 0x16) 764 #define GOP_1GS0_3DOSD_SUB_RBLK_L GOP_REG(GOP_1GS0_OFST+1, 0x1E) 765 #define GOP_1GS0_3DOSD_SUB_RBLK_H GOP_REG(GOP_1GS0_OFST+1, 0x1F) 766 767 #define GOP_1GS1_CTRL0 GOP_REG(GOP_1GS1_OFST, 0x00) 768 #define GOP_1GS1_CTRL1 GOP_REG(GOP_1GS1_OFST, 0x01) 769 #define GOP_1GS1_RATE GOP_REG(GOP_1GS1_OFST, 0x02) 770 #define GOP_1GS1_PALDATA_L GOP_REG(GOP_1GS1_OFST, 0x03) 771 #define GOP_1GS1_PALDATA_H GOP_REG(GOP_1GS1_OFST, 0x04) 772 #define GOP_1GS1_PALCTRL GOP_REG(GOP_1GS1_OFST, 0x05) 773 #define GOP_1GS1_REGDMA_END GOP_REG(GOP_1GS1_OFST, 0x06) 774 #define GOP_1GS1_REGDMA_STR GOP_REG(GOP_1GS1_OFST, 0x07) 775 #define GOP_1GS1_INT GOP_REG(GOP_1GS1_OFST, 0x08) 776 #define GOP_1GS1_HWSTATE GOP_REG(GOP_1GS1_OFST, 0x09) 777 #define GOP_1GS1_RDMA_HT GOP_REG(GOP_1GS1_OFST, 0x0e) 778 #define GOP_1GS1_HS_PIPE GOP_REG(GOP_1GS1_OFST, 0x0f) 779 #define GOP_1GS1_BRI GOP_REG(GOP_1GS1_OFST, 0x11) 780 #define GOP_1GS1_CON GOP_REG(GOP_1GS1_OFST, 0x12) 781 #define GOP_1GS1_BW GOP_REG(GOP_1GS1_OFST, 0x19) 782 #define GOP_1GS1_TRSCLR_L GOP_REG(GOP_1GS1_OFST, 0x24) 783 #define GOP_1GS1_TRSCLR_H GOP_REG(GOP_1GS1_OFST, 0x25) 784 #define GOP_1GS1_STRCH_HSZ GOP_REG(GOP_1GS1_OFST, 0x30) 785 #define GOP_1GS1_STRCH_VSZ GOP_REG(GOP_1GS1_OFST, 0x31) 786 #define GOP_1GS1_STRCH_HSTR GOP_REG(GOP_1GS1_OFST, 0x32) 787 #define GOP_1GS1_STRCH_VSTR GOP_REG(GOP_1GS1_OFST, 0x34) 788 #define GOP_1GS1_HSTRCH GOP_REG(GOP_1GS1_OFST, 0x35) 789 #define GOP_1GS1_HSTRCH_INI GOP_REG(GOP_1GS1_OFST, 0x38) 790 #define GOP_1GS1_VSTRCH_INI GOP_REG(GOP_1GS1_OFST, 0x39) 791 #define GOP_1GS1_HVStrch_MD GOP_REG(GOP_1GS1_OFST, 0x3a) 792 #define GOP_1GS1_OLDADDR GOP_REG(GOP_1GS1_OFST, 0x3b) 793 #define GOP_1GS1_MULTI_ALPHA GOP_REG(GOP_1GS1_OFST, 0x3c) 794 795 #define GOP_1GS1_GWIN0_CTRL GOP_REG(GOP_1GS1_OFST+1, 0x00) 796 #define GOP_1GS1_DRAM_RBLK_L GOP_REG(GOP_1GS1_OFST+1, 0x01) 797 #define GOP_1GS1_DRAM_RBLK_H GOP_REG(GOP_1GS1_OFST+1, 0x02) 798 #define GOP_1GS1_DEL_PIXEL GOP_REG(GOP_1GS1_OFST+1, 0x03) 799 #define GOP_1GS1_HSTR GOP_REG(GOP_1GS1_OFST+1, 0x04) 800 #define GOP_1GS1_HEND GOP_REG(GOP_1GS1_OFST+1, 0x05) 801 #define GOP_1GS1_VSTR GOP_REG(GOP_1GS1_OFST+1, 0x06) 802 #define GOP_1GS1_VEND GOP_REG(GOP_1GS1_OFST+1, 0x08) 803 #define GOP_1GS1_DRAM_RBLK_HSIZE GOP_REG(GOP_1GS1_OFST+1, 0x09) 804 #define GOP_1GS1_GWIN_ALPHA01 GOP_REG(GOP_1GS1_OFST+1, 0x0A) 805 #define GOP_1GS1_DRAM_VSTR_L GOP_REG(GOP_1GS1_OFST+1, 0x0C) 806 #define GOP_1GS1_DRAM_VSTR_H GOP_REG(GOP_1GS1_OFST+1, 0x0D) 807 #define GOP_1GS1_DRAM_FADE GOP_REG(GOP_1GS1_OFST+1, 0x16) 808 #define GOP_1GS1_3DOSD_SUB_RBLK_L GOP_REG(GOP_1GS1_OFST+1, 0x1E) 809 #define GOP_1GS1_3DOSD_SUB_RBLK_H GOP_REG(GOP_1GS1_OFST+1, 0x1F) 810 //------------------------------------------------------------------------------------------------- 811 // Type and Structure 812 //------------------------------------------------------------------------------------------------- 813 814 //---------------------------------------------------------------------------- 815 // GOP Test Pattern Reg 816 //---------------------------------------------------------------------------- 817 #define REG_TSTCLR_EN GOP_REG(GOP_4G_OFST, 0x00) 818 #define REG_TSTCLR_ALPHA_EN GOP_REG(GOP_4G_OFST+2, 0x00) 819 #define REG_TLB_TAG_ADDR_L GOP_REG(GOP_4G_OFST+2, 0x2C) 820 #define REG_TLB_TAG_ADDR_H GOP_REG(GOP_4G_OFST+2, 0x2D) 821 #define REG_TLB_TAG_ADDR_RVIEW_L GOP_REG(GOP_4G_OFST+2, 0x2E) 822 #define REG_TLB_TAG_ADDR_RVIEW_H GOP_REG(GOP_4G_OFST+2, 0x2F) 823 #define REG_TSTCLR_ALPHA GOP_REG(GOP_4G_OFST+2, 0x40) 824 #define REG_R_STC GOP_REG(GOP_4G_OFST+2, 0x41) 825 #define REG_G_STC GOP_REG(GOP_4G_OFST+2, 0x48) 826 #define REG_B_STC GOP_REG(GOP_4G_OFST+2, 0x49) 827 #define REG_TSTCLR_HDUP GOP_REG(GOP_4G_OFST+2, 0x01) 828 #define REG_TSTCLR_VDUP GOP_REG(GOP_4G_OFST+2, 0x01) 829 #define REG_HR_INC GOP_REG(GOP_4G_OFST+2, 0x42) 830 #define REG_HR_INC_SIGNZ GOP_REG(GOP_4G_OFST+2, 0x42) 831 #define REG_HG_INC GOP_REG(GOP_4G_OFST+2, 0x43) 832 #define REG_HG_INC_SIGNZ GOP_REG(GOP_4G_OFST+2, 0x43) 833 #define REG_HB_INC GOP_REG(GOP_4G_OFST+2, 0x44) 834 #define REG_HB_INC_SIGNZ GOP_REG(GOP_4G_OFST+2, 0x44) 835 #define REG_HR_STEP GOP_REG(GOP_4G_OFST+2, 0x4A) 836 #define REG_HG_STEP GOP_REG(GOP_4G_OFST+2, 0x4B) 837 #define REG_HB_STEP GOP_REG(GOP_4G_OFST+2, 0x4C) 838 #define REG_VR_INC GOP_REG(GOP_4G_OFST+2, 0x45) 839 #define REG_VR_INC_SIGNZ GOP_REG(GOP_4G_OFST+2, 0x45) 840 #define REG_VG_INC GOP_REG(GOP_4G_OFST+2, 0x46) 841 #define REG_VG_INC_SIGNZ GOP_REG(GOP_4G_OFST+2, 0x46) 842 #define REG_VB_INC GOP_REG(GOP_4G_OFST+2, 0x47) 843 #define REG_VB_INC_SIGNZ GOP_REG(GOP_4G_OFST+2, 0x47) 844 #define REG_VR_STEP GOP_REG(GOP_4G_OFST+2, 0x4D) 845 #define REG_VG_STEP GOP_REG(GOP_4G_OFST+2, 0x4E) 846 #define REG_VB_STEP GOP_REG(GOP_4G_OFST+2, 0x4F) 847 #define REG_TLB_BASE_ADDR_L GOP_REG(GOP_4G_OFST+2, 0x58) 848 #define REG_TLB_BASE_ADDR_H GOP_REG(GOP_4G_OFST+2, 0x59) 849 #define REG_TLB_BASE_ADDR_RVIEW_L GOP_REG(GOP_4G_OFST+2, 0x5A) 850 #define REG_TLB_BASE_ADDR_RVIEW_H GOP_REG(GOP_4G_OFST+2, 0x5B) 851 852 #define MASK_TSTCLR_EN GOP_BIT6 853 #define MASK_TSTCLR_ALPHA_EN GOP_BIT1 854 #define MASK_TSTCLR_ALPHA BMASK(11:8)|BMASK(3:0) 855 #define MASK_RGB_STC_VALID BMASK(7:0) 856 #define MASK_R_STC BMASK(11:8)|BMASK(3:0) 857 #define MASK_G_STC BMASK(11:8)|BMASK(3:0) 858 #define MASK_B_STC BMASK(11:8)|BMASK(3:0) 859 #define MASK_INI_TSTCLR_EN GOP_BIT0 860 #define MASK_TSTCLR_HDUP BMASK(3:2) 861 #define MASK_TSTCLR_VDUP BMASK(1:0) 862 #define MASK_HR_INC BMASK(10:8)|BMASK(3:0) 863 #define MASK_HR_INC_SIGNZ GOP_BIT11 864 #define MASK_HG_INC BMASK(10:8)|BMASK(3:0) 865 #define MASK_HG_INC_SIGNZ GOP_BIT11 866 #define MASK_HB_INC BMASK(10:8)|BMASK(3:0) 867 #define MASK_HB_INC_SIGNZ GOP_BIT11 868 #define MASK_HR_STEP BMASK(11:8)|BMASK(3:0) 869 #define MASK_HG_STEP BMASK(11:8)|BMASK(3:0) 870 #define MASK_HB_STEP BMASK(11:8)|BMASK(3:0) 871 #define MASK_VR_INC BMASK(10:8)|BMASK(3:0) 872 #define MASK_VR_INC_SIGNZ GOP_BIT11 873 #define MASK_VG_INC BMASK(10:8)|BMASK(3:0) 874 #define MASK_VG_INC_SIGNZ GOP_BIT11 875 #define MASK_VB_INC BMASK(10:8)|BMASK(3:0) 876 #define MASK_VB_INC_SIGNZ GOP_BIT11 877 #define MASK_VR_STEP BMASK(11:8)|BMASK(3:0) 878 #define MASK_VG_STEP BMASK(11:8)|BMASK(3:0) 879 #define MASK_VB_STEP BMASK(11:8)|BMASK(3:0) 880 881 #define SHIFT_TSTCLR_EN 6 882 #define SHIFT_TSTCLR_ALPHA_EN 1 883 #define SHIFT_TSTCLR_ALPHA 8 884 #define SHIFT_R_STC 0 885 #define SHIFT_G_STC 0 886 #define SHIFT_B_STC 0 887 #define SHIFT_INI_TSTCLR_EN 0 888 #define SHIFT_TSTCLR_HDUP 2 889 #define SHIFT_TSTCLR_VDUP 0 890 #define SHIFT_HR_INC 0 891 #define SHIFT_HR_INC_SIGNZ 11 892 #define SHIFT_HG_INC 0 893 #define SHIFT_HG_INC_SIGNZ 11 894 #define SHIFT_HB_INC 0 895 #define SHIFT_HB_INC_SIGNZ 11 896 #define SHIFT_HR_STEP 0 897 #define SHIFT_HG_STEP 0 898 #define SHIFT_HB_STEP 0 899 #define SHIFT_VR_INC 0 900 #define SHIFT_VR_INC_SIGNZ 11 901 #define SHIFT_VG_INC 0 902 #define SHIFT_VG_INC_SIGNZ 11 903 #define SHIFT_VB_INC 0 904 #define SHIFT_VB_INC_SIGNZ 11 905 #define SHIFT_VR_STEP 0 906 #define SHIFT_VG_STEP 0 907 #define SHIFT_VB_STEP 0 908 909 //---------------------------------------------------------------------------- 910 // GOP AFBC Reg 911 //---------------------------------------------------------------------------- 912 #define REG_AFBC_CORE_EN(id) GOP_REG(GOP_4G_OFST+GOP_AFBC_OFST, 0x00+(0x20*id)) 913 #define REG_AFBC_ADDR_L(id) GOP_REG(GOP_4G_OFST+GOP_AFBC_OFST, 0x01+(0x20*id)) 914 #define REG_AFBC_ADDR_H(id) GOP_REG(GOP_4G_OFST+GOP_AFBC_OFST, 0x02+(0x20*id)) 915 #define REG_AFBC_FMT(id) GOP_REG(GOP_4G_OFST+GOP_AFBC_OFST, 0x0C+(0x20*id)) 916 #define REG_AFBC_WIDTH(id) GOP_REG(GOP_4G_OFST+GOP_AFBC_OFST, 0x0A+(0x20*id)) 917 #define REG_AFBC_HEIGHT(id) GOP_REG(GOP_4G_OFST+GOP_AFBC_OFST, 0x0B+(0x20*id)) 918 #define REG_AFBC_RESP(id) GOP_REG(GOP_4G_OFST+GOP_AFBC_OFST, 0x0F+(0x20*id)) 919 #define REG_AFBC_MIU GOP_REG(GOP_4G_OFST+GOP_AFBC_OFST, 0x43) 920 #define REG_AFBC_DEBUG(id) GOP_REG(GOP_4G_OFST+GOP_AFBC_OFST, 0x44+(0x20*id)) 921 #define REG_AFBC_READCNT(id) GOP_REG(GOP_4G_OFST+GOP_AFBC_OFST, 0x4C+(0x20*id)) 922 #define REG_AFBC_TRIGGER GOP_REG(GOP_4G_OFST+GOP_AFBC_OFST, 0x50) 923 924 #endif // _REG_GOP_H_ 925