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MStar hereby reserves the // rights to any and all damages, losses, costs and expenses resulting therefrom. // //////////////////////////////////////////////////////////////////////////////// #ifndef _REG_GOP_H_ #define _REG_GOP_H_ //------------------------------------------------------------------------------------------------- // Hardware Capability //------------------------------------------------------------------------------------------------- //------------------------------------------------------------------------------------------------- // Macro and Define //------------------------------------------------------------------------------------------------- //---------------------------------------------------------------------------- // HW IP Reg Base Adr //---------------------------------------------------------------------------- #define GOP_REG_BASE 0x1F00UL #define GE_REG_BASE 0x2800UL #define SC1_REG_BASE 0x2F00UL #define CKG_REG_BASE 0x0B00UL #define MIU0_REG_BASE 0x0600UL #define MIU_REG_BASE 0x1200UL #define MIU2_REG_BASE 0x162000 #define MVOP_REG_BASE 0x1400UL #define SC1_DIRREG_BASE 0x130000UL #define AFBC_REG_BASE 0x113100 //---------------------------------------------------------------------------- // Scaler Reg //---------------------------------------------------------------------------- #define XC_REG(bk, reg) (SC1_REG_BASE+((MS_U32)(bk)<<16) + (reg) * 2) #define REG_SC_BK00_00_L XC_REG(0x00, 0x00) #define REG_SC_BK00_05_L XC_REG(0x00, 0x05) #define REG_SC_BK00_06_L XC_REG(0x00, 0x06) #define REG_SC_BK01_02_L XC_REG(0x01, 0x02) #define REG_SC_BK01_05_L XC_REG(0x01, 0x05) #define REG_SC_BK01_1E_L XC_REG(0x01, 0x1E) #define REG_SC_BK01_21_L XC_REG(0x01, 0x21) #define REG_SC_BK02_5F_L XC_REG(0x02, 0x5F) #define REG_SC_BK0F_2B_L XC_REG(0x0F, 0x2B) #define REG_SC_BK10_23_L XC_REG(0x10, 0x23) #define REG_SC_BK10_5B_L XC_REG(0x10, 0x5B) #define REG_SC_BK12_03_L XC_REG(0x12, 0x03) #define REG_SC_BK37_22_L XC_REG(0x37, 0x22) #define REG_SC_BK37_24_L XC_REG(0x37, 0x24) #define REG_SC_BK37_28_L XC_REG(0x37, 0x28) #define REG_SC_BK3D_0D_L XC_REG(0x3D, 0x0D) #define REG_SC_BK40_22_L XC_REG(0x40, 0x22) #define REG_SC_BK40_23_L XC_REG(0x40, 0x23) #define REG_SC_BK40_24_L XC_REG(0x40, 0x24) #define REG_SC_BK40_25_L XC_REG(0x40, 0x25) #define REG_SC_BK7F_10_L XC_REG(0x7F, 0x10) #define REG_SC_BK7F_11_L XC_REG(0x7F, 0x11) #define REG_SC_BK7F_18_L XC_REG(0x7F, 0x18) #define REG_SC_BKC9_50_L XC_REG(0xC9, 0x50) #define REG_SC_BKC9_51_L XC_REG(0xC9, 0x51) #define REG_SC_BKC9_52_L XC_REG(0xC9, 0x52) #define REG_SC_BKCB_48_L XC_REG(0xCB, 0x48) #define REG_SC_BK80_05_L XC_REG(0x80, 0x05) #define GOP_SC_BANKSEL REG_SC_BK00_00_L #define GOP_SC_CHANNELSYNC REG_SC_BK00_05_L #define GOP_SC1_CHANNELSYNC REG_SC_BK80_05_L #define IPMUX0_BLENDING_ENABLE GOP_BIT13 #define IPMUX1_BLENDING_ENABLE GOP_BIT12 #define GOP_SC_GOPEN REG_SC_BK00_06_L #define GOP_SC_IP_SYNC REG_SC_BK01_02_L #define GOP_SC_IP_MAIN_HSTART REG_SC_BK01_05_L #define GOP_SC_IP_MAIN_INTERLACE REG_SC_BK01_1E_L #define GOP_SC_IP_MAIN_USR_INTERLACE REG_SC_BK01_21_L #define GOP_SC_IP2GOP_SRCSEL REG_SC_BK02_5F_L #define GOP_SC_OSD_CHECK_ALPHA REG_SC_BK0F_2B_L #define GOP_SC_VOPNBL REG_SC_BK10_23_L #define GOP_SC_GOPENMODE1 REG_SC_BK10_5B_L #define GOP_SC_MIRRORCFG REG_SC_BK12_03_L #define GOP_SC_OCMIXER REG_SC_BK37_22_L #define GOP_SC_OCMISC REG_SC_BK37_24_L #define GOP_SC_OCALPHA REG_SC_BK37_28_L #define GOP_SC_FRC_LAYER1_L_EN REG_SC_BK40_22_L #define GOP_SC_FRC_LAYER1_R_EN REG_SC_BK40_23_L #define GOP_SC_FRC_LAYER2_L_EN REG_SC_BK40_24_L #define GOP_SC_FRC_LAYER2_R_EN REG_SC_BK40_25_L #define GOP_SC_MIU_SEL REG_SC_BK7F_10_L #define GOP_SC_MIU_IP_SEL REG_SC_BK7F_11_L #define GOP_SC_4K120_EN0 REG_SC_BKC9_50_L #define GOP_SC_4K120_EN1 REG_SC_BKC9_51_L #define GOP_SC_4K120_EN2 REG_SC_BKC9_52_L #define GOP_SC_GOP_HSYNC_START REG_SC_BKCB_48_L //---------------------------------------------------------------------------- // MVOP Reg //---------------------------------------------------------------------------- #define GOP_MVOP_MIRRORCFG (MVOP_REG_BASE+0x76) //---------------------------------------------------------------------------- // GE Reg //---------------------------------------------------------------------------- #define GOP_GE_FMT_BLT (GE_REG_BASE+(0x01*2)) #define GOP_GE_EN_CMDQ BIT(0) #define GOP_GE_EN_VCMDQ BIT(1) #define GOP_GE_VQ_FIFO_STATUS_L (GE_REG_BASE+(0x04*2)) #define GOP_GE_VQ_FIFO_STATUS_H (GE_REG_BASE+(0x05*2)) #define GOP_GE_STATUS (GE_REG_BASE+(0x07*2)) #define GOP_GE_BUSY BIT(0) #define GOP_GE_CMDQ1_STATUS BMASK(7:3) #define GOP_GE_CMDQ2_STATUS BMASK(15:11) #define GOP_GE_TAG (GE_REG_BASE+(0x2C*2)) #define GOP_GE_DBBASE0 (GE_REG_BASE+(0x26*2)) #define GOP_GE_DBBASE1 (GE_REG_BASE+(0x27*2)) #define GOP_GE_DBPIT (GE_REG_BASE+(0x33*2)) #define GOP_GE_FBFMT (GE_REG_BASE+(0x34*2)) #define GOP_GE_SRCW (GE_REG_BASE+(0x6e*2)) #define GOP_GE_SRCH (GE_REG_BASE+(0x6f*2)) //---------------------------------------------------------------------------- // ChipTop Reg //---------------------------------------------------------------------------- /* GOP0 and GOP1 CLK */ #define GOP_GOPCLK (CKG_REG_BASE+(0x40<<1)) #define CKG_GOPG0_DISABLE_CLK ~(GOP_BIT0) #define CKG_GOPG0_ODCLK (0<<2) #define CKG_GOPG0_IDCLK2 (1 << 2) #define CKG_GOPG0_IDCLK1 (2 << 2) #define CKG_GOPG0_OCC_FRCCLK (3 << 2) #define CKG_GOPG0_MIXERCLK_VE (4 << 2) #define CKG_GOPG0_FCLK (8 << 2) #define CKG_GOPG0_DISABLE_CLK_MASK (GOP_BIT0) #define CKG_GOPG0_MASK (GOP_BIT5 | GOP_BIT4 | GOP_BIT3 | GOP_BIT2) #define CKG_GOPG1_DISABLE_CLK ~(GOP_BIT8) #define CKG_GOPG1_ODCLK (0 << 10) #define CKG_GOPG1_IDCLK2 (1 << 10) #define CKG_GOPG1_IDCLK1 (2 << 10) #define CKG_GOPG1_OCC_FRCCLK (3 << 10) #define CKG_GOPG1_MIXERCLK_VE (4 << 10) #define CKG_GOPG1_FCLK (8 << 10) #define CKG_GOPG1_DISABLE_CLK_MASK (GOP_BIT8) #define CKG_GOPG1_MASK (GOP_BIT13 | GOP_BIT12 | GOP_BIT11 | GOP_BIT10) #define CKG_GOPG0_SCALING (CKG_REG_BASE+0x88) #define CKG_GOPG0_MG (CKG_REG_BASE+0xFE) #define CKG_GOPG0_MG_MASK (GOP_BIT3 | GOP_BIT2) #define CKG_GOPG2_MG_MASK (GOP_BIT7 | GOP_BIT6) /* GOP2 and GOPDWIN CLK */ #define GOP_GOP2CLK (CKG_REG_BASE+(0x41<<1)) #define CKG_GOPG2_DISABLE_CLK ~(GOP_BIT0) #define CKG_GOPG2_ODCLK (0<<2) #define CKG_GOPG2_IDCLK2 (1 << 2) #define CKG_GOPG2_IDCLK1 (2 << 2) #define CKG_GOPG2_OCC_FRCCLK (3 << 2) #define CKG_GOPG2_MIXERCLK_VE (4 << 2) #define CKG_GOPG2_FCLK (8 << 2) #define CKG_GOPG2_DISABLE_CLK_MASK (GOP_BIT0) #define CKG_GOPG2_MASK (GOP_BIT5 |GOP_BIT4 | GOP_BIT3 | GOP_BIT2) #define CKG_GOPD_CLK_IDCLK2 (0 << 10) #define CKG_GOPD_CLK_ODCLK (1 << 10) #define CKG_GOPD_CLK_DC0CLK (2 << 10) #define CKG_GOPD_CLK_SUBDC0CLK (3 << 10) #define CKG_GOPD_CLK_MIXERCLK_VE (4 << 10) #define CKG_GOPD_MASK (GOP_BIT12 | GOP_BIT11 | GOP_BIT10) /* GOP3 CLK*/ #define GOP_GOP3CLK (CKG_REG_BASE+(0x42<<1)) #define CKG_GOPG3_ODCLK (0<<2) #define CKG_GOPG3_IDCLK2 (1 << 2) #define CKG_GOPG3_IDCLK1 (2 << 2) #define CKG_GOPG3_OCC_FRCCLK (3 << 2) #define CKG_GOPG3_MIXERCLK_VE (4 << 2) #define CKG_GOPG3_FCLK (8 << 2) #define CKG_GOPG3_DISABLE_CLK_MASK (GOP_BIT0) #define CKG_GOPG3_MASK (GOP_BIT5 | GOP_BIT4 | GOP_BIT3 | GOP_BIT2) #define CKG_GOPD_DISABLE_CLK ~(GOP_BIT8) /* GOP4 CLK*/ #define GOP_GOP4CLK (CKG_REG_BASE+(0x7E<<1)) #define CKG_GOPG4_ODCLK (0 << 10) #define CKG_GOPG4_IDCLK2 (1 << 10) #define CKG_GOPG4_IDCLK1 (2 << 10) #define CKG_GOPG4_OCC_FRCCLK (3 << 10) #define CKG_GOPG4_MIXERCLK_VE (4 << 10) #define CKG_GOPG4_FCLK (9 << 10) #define CKG_GOPG4_DISABLE_CLK_MASK (GOP_BIT8) #define CKG_GOPG4_MASK (GOP_BIT13 |GOP_BIT12 | GOP_BIT11 | GOP_BIT10) /* SRAM CLK */ #define GOP_SRAMCLK (CKG_REG_BASE+(0x43<<1)) #define CKG_SRAM0_DISABLE_CLK (GOP_BIT0) #define CKG_SRAM1_DISABLE_CLK (GOP_BIT8) #define CKG_SRAM0_MASK (GOP_BIT0|GOP_BIT1) #define CKG_SRAM1_MASK (GOP_BIT8|GOP_BIT9) /* LINE BUFFER SRAM CLK */ #define GOP_LB_SRAMCLK (CKG_REG_BASE+(0x45<<1)) #define CKG_LB_SRAM1_DISABLE_CLK (GOP_BIT0) /*GOP1*/ #define CKG_LB_SRAM2_DISABLE_CLK (GOP_BIT4) /*GOP2*/ #define CKG_LB_SRAM1_MASK (GOP_BIT2|GOP_BIT3) #define CKG_LB_SRAM2_MASK (GOP_BIT6|GOP_BIT7) /*AFBC CLK*/ #define GOP_AFBCCLK (CKG_REG_BASE+(0x46<<1)) #define CKG_AFBCCLK_DISABLE_CLK (GOP_BIT0) #define CKG_AFBCCLK_432 (0 << 2) #define CKG_AFBCCLK_216 (1 << 2) #define CKG_AFBCCLK_DISABLE_CLK_MASK (GOP_BIT0|GOP_BIT1|GOP_BIT2|GOP_BIT3) //---------------------------------------------------------------------------- // MIU Reg //---------------------------------------------------------------------------- #define GOP_CLIENT_REG 0x7E #define GOP_MIU_GROUP (MIU0_REG_BASE+(GOP_CLIENT_REG*2)) #define USE_XCBANK_MIU_SELECT 1 #if USE_XCBANK_MIU_SELECT==1 #define GOP_MIU_GROUP1 REG_SC_BK7F_10_L #define GOP_MIU_GROUP2 REG_SC_BK7F_18_L #else #define GOP_MIU_GROUP1 (MIU_REG_BASE+(GOP_CLIENT_REG*2)) #define GOP_MIU_GROUP2 (MIU2_REG_BASE+(GOP_CLIENT_REG*2)) #endif /*Define each gop miu clint bit*/ #define GOP_MIU_CLIENT_DWIN 0xFF #define GOP_MIU_CLIENT_GOP0 0x5 #define GOP_MIU_CLIENT_GOP1 0x6 #define GOP_MIU_CLIENT_GOP2 0x7 #define GOP_MIU_CLIENT_GOP3 0x8 #define GOP_MIU_CLIENT_GOP4 0x6 #define GOP_MIU_CLIENT_GOP5 0xff //---------------------------------------------------------------------------- // VE Reg //---------------------------------------------------------------------------- #define GOP_VE_TVS_OSD_EN 0x60 #define GOP_VE_TVS_OSD1_EN 0x61 //---------------------------------------------------------------------------- // GOP Reg //---------------------------------------------------------------------------- #define GOP_REG(bk, reg) (GOP_REG_BASE+((MS_U32)(bk)<<16) + (reg) * 2) #define __GOP_REG(reg) (GOP_REG_BASE+(reg) * 2) #define GOP_REG_DIRECT_BASE (0x120200) #define GOP_REG_GOP4_BK_OFFSET 0x1900 #define GOP_REG_GOP4_GW_OFFSET 0x1C00 #define GOP_REG_GOP4_ST_OFFSET 0x1D00 #define GOP_REG_VAL(x) (1<