xref: /utopia/UTPA2-700.0.x/modules/flash/hal/mainz/flash/nor/regPARFLASH.h (revision 53ee8cc121a030b8d368113ac3e966b4705770ef)
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94 
95 ///////////////////////////////////////////////////////////////////////////////////////////////////
96 ///
97 /// file    regPARFLASH.h
98 /// @brief  Parallel Flash Register Definition
99 /// @author MStar Semiconductor Inc.
100 ///////////////////////////////////////////////////////////////////////////////////////////////////
101 
102 #ifndef _REG_PARFLASH_H_
103 #define _REG_PARFLASH_H_
104 
105 
106 //-------------------------------------------------------------------------------------------------
107 //  Hardware Capability
108 //-------------------------------------------------------------------------------------------------
109 
110 
111 //-------------------------------------------------------------------------------------------------
112 //  Macro and Define
113 //-------------------------------------------------------------------------------------------------
114 
115 // BASEADDR & BK
116 #define BASEADDR_RIU                    0xBF000000  // TODO: <-@@@ CHIP SPECIFIC
117 
118 #define BK_CHIPTOP                      0x3C00
119 #define BK_PFSH                         0xB00
120 #define BK_PIU							0x7800
121 
122 //-------- PIU register ------------------------
123 #define REG_PIU_SPI_CLK_SRC         0x26
124 	#define PSCS_CLK_SRC_SEL_MASK       	BMASK(5:5)
125     #define PSCS_CLK_SRC_SEL_XTAL           BITS(5:5, 0)
126     #define PSCS_CLK_SRC_SEL_CLK            BITS(5:5, 1)
127 	#define PSCS_CLK_SEL_MASK           	BMASK(4:2)
128     #define PSCS_CLK_SEL_XTAL               BITS(4:2, 0)
129     #define PSCS_CLK_SEL_27MHZ              BITS(4:2, 1)
130     #define PSCS_CLK_SEL_36MHZ              BITS(4:2, 2)
131     #define PSCS_CLK_SEL_43MHZ              BITS(4:2, 3)
132     #define PSCS_CLK_SEL_54MHZ              BITS(4:2, 4)
133     #define PSCS_CLK_SEL_72MHZ              BITS(4:2, 5)
134     #define PSCS_CLK_SEL_86MHZ              BITS(4:2, 6)
135     #define PSCS_CLK_SEL_108MHZ             BITS(4:2, 7)
136     #define PSCS_CLK_SRC_SEL_MASK       	BMASK(5:5)
137     #define PSCS_CLK_SRC_SEL_XTAL           BITS(5:5, 0)
138     #define PSCS_CLK_SRC_SEL_CLK            BITS(5:5, 1)
139 
140 //-------------------------------------------
141 
142 //----- Chip top -------------------------
143 #define REG_ALLPAD_IN                   0x50
144 #define REG_PCMCONFIG                   0x6E
145 #define REG_PF_MODE                     0x6F
146 #define REG_PCMISGPIO					0x70
147 
148 //---- Nor flash register ------------------
149 #define REG_NORPF_CLOCK_LENGTH          0x00
150 #define REG_NORPF_FLASH_DATA_WIDTH8     0x00
151 #define REG_NORPF_WRITE_RUN             0x01
152 #define REG_NORPF_DIRECT_READ_MODE      0x01
153 #define REG_NORPF_CEB_START             0x02
154 #define REG_NORPF_CEB_END               0x02
155 #define REG_NORPF_OEB_START             0x02
156 #define REG_NORPF_OEB_END               0x02
157 #define REG_NORPF_WEB_START             0x03
158 #define REG_NORPF_WEB_END               0x03
159 #define REG_NORPF_DATAOEN_START         0x03
160 #define REG_NORPF_DATAOEN_END           0x03
161 #define REG_NORPF_DATA_LATCH_CNT        0x04
162 #define REG_NORPF_CTRL                  0x06
163 #define REG_NORPF_BRIDGE_CTRL           0x07
164 #define REG_NORPF_XIU_CTRL              0x08
165 #define REG_NORPF_XIU_ADDR_L            0x09
166 #define REG_NORPF_XIU_ADDR_H            0x0A
167 #define REG_NORPF_XIU_WDATA             0x0B
168 #define REG_NORPF_XIU_STATUS            0x0C
169 #define REG_NORPF_XIU_RDATA_L           0x0D
170 #define REG_NORPF_XIU_RDATA_H           0x0E
171 #define REG_NORPF_WRITE_ADDR0_L         0x10
172 #define REG_NORPF_WRITE_ADDR0_H         0x11
173 #define REG_NORPF_WRITE_ADDR1_L         0x12
174 #define REG_NORPF_WRITE_ADDR1_H         0x13
175 #define REG_NORPF_WRITE_ADDR2_L         0x14
176 #define REG_NORPF_WRITE_ADDR2_H         0x15
177 #define REG_NORPF_WRITE_ADDR3_L         0x16
178 #define REG_NORPF_WRITE_ADDR3_H         0x17
179 #define REG_NORPF_WRITE_ADDR4_L         0x18
180 #define REG_NORPF_WRITE_ADDR4_H         0x19
181 #define REG_NORPF_WRITE_ADDR5_L         0x1A
182 #define REG_NORPF_WRITE_ADDR5_H         0x1B
183 #define REG_NORPF_WRITE_ADDR6_L         0x1C
184 #define REG_NORPF_WRITE_ADDR6_H         0x1D
185 #define REG_NORPF_WRITE_ADDR7_L         0x1E
186 #define REG_NORPF_WRITE_ADDR7_H         0x1F
187 #define REG_NORPF_WRITE_DATA0           0x20
188 #define REG_NORPF_WRITE_DATA1           0x21
189 #define REG_NORPF_WRITE_DATA2           0x22
190 #define REG_NORPF_WRITE_DATA3           0x23
191 #define REG_NORPF_WRITE_DATA4           0x24
192 #define REG_NORPF_WRITE_DATA5           0x25
193 #define REG_NORPF_WRITE_DATA6           0x26
194 #define REG_NORPF_WRITE_DATA7           0x27
195 
196 
197 //-------------------------------------------------------------------------------------------------
198 //  Type and Structure
199 //-------------------------------------------------------------------------------------------------
200 
201 
202 #endif // _REG_PARFLASH_H_
203