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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 //////////////////////////////////////////////////////////////////////////////////////////////////// 96 /// 97 /// file drvDscmb.h 98 /// @brief Descrambler (Dscmb) Driver Interface 99 /// @author MStar Semiconductor,Inc. 100 /// @attention 101 //////////////////////////////////////////////////////////////////////////////////////////////////// 102 103 #ifndef __REG_DSCMB_H__ 104 #define __REG_DSCMB_H__ 105 106 #define DSCMB_SHAREFLT_ENABLE 0 107 108 #define ENG_NUM 1UL 109 #define ENG0_MAP_PID_START 16UL 110 #define ENG0_MAP_PID_LENGTH 16UL 111 112 #define MAX_NUM 17UL 113 #define MAX_DSCMB_PIDFLT_NUM 8UL 114 #define DSCMB_SHARE_SLOT_REV_IDX (MAX_NUM-1UL) 115 #define REG_DSCMB_MAX_SLOT (MAX_NUM*2UL) 116 #define REG_DSCMB_MAX_PIDFLT 16UL 117 118 #define TSP_PID_FLT_NUM 32UL 119 120 /* 121 typedef enum 122 { 123 HAL_DSCMB_KEY_TYPE_CLEAR = 0, 124 HAL_DSCMB_KEY_TYPE_EVEN = 1, 125 HAL_DSCMB_KEY_TYPE_ODD = 2, 126 } HAL_DscmbKeyType; 127 */ 128 129 // #define REG_DSCMB_KEY_TYPE_CLEAR 0UL 130 #define REG_DSCMB_KEY_TYPE_ODD 3UL 131 #define REG_DSCMB_KEY_TYPE_EVEN 2UL 132 #define REG_DSCMB_POS_SWITCH2 13UL 133 134 //////////////////////////////////////////////////////////////////////////////////////////////// 135 // TSP bank 1 136 //////////////////////////////////////////////////////////////////////////////////////////////// 137 #define REG_TSP1_BANK 0x0B00UL 138 139 #define REG_TSP1_CACTRL (REG_TSP1_BANK+ 0x0040UL) 140 #define REG_TSP1_CACTRL_MASK 0x00FFUL 141 #define REG_TSP1_CACTRL_INPUT_TS0LIVE 0x0001UL 142 #define REG_TSP1_CACTRL_INPUT_TS0FILE 0x0002UL 143 #define REG_TSP1_CACTRL_INPUT_TS1 0x0004UL 144 145 //////////////////////////////////////////////////////////////////////////////////////////////// 146 // Descambler bank 0 147 //////////////////////////////////////////////////////////////////////////////////////////////// 148 #define REG_DSCMB_BANK 0x0600UL 149 150 #define REG_DSCMB_CTRL (REG_DSCMB_BANK+ 0x0000UL) 151 #define REG_DSCMB_CTRL_CSA_ENABLE 0x0001UL 152 #define REG_DSCMB_CTRL_CONFORMANCE_MECH 0x0020UL 153 #define REG_DSCMB_CTRL_CORRECT_SCRMBFLAG 0x0040UL 154 #define REG_DSCMB_CTRL_OLD_TSC 0x0080UL 155 #define REG_DSCMB_CTRL_SW_RST 0x8000UL 156 157 #define REG_DSCMB_CTRL1 (REG_DSCMB_BANK+ 0x0001UL) 158 #define REG_DSCMB_CTRL1_NEW_TSC_MASK 0x0003UL 159 #define REG_DSCMB_CTRL1_NEW_TSC_EVEN 0x0002UL 160 #define REG_DSCMB_CTRL1_NEW_TSC_ODD 0x0003UL 161 162 #define REG_DSCMB_SCMB_TS (REG_DSCMB_BANK+ 0x0002UL) 163 // #define REG_DSCMB_SCMB_PES (REG_DSCMB_BANK+ 0x0004UL) 164 165 166 #define REG_DSCMB_CIPHER_CONNECT_L (REG_DSCMB_BANK+ 0x000aUL) 167 #define REG_DSCMB_CSA_CIP 0x1045UL 168 #define REG_DSCMB_CSA_CIP_ENCRYPT 0x1044UL // HDCP2 169 #define REG_DSCMB_CIP_CSA 0x0511UL 170 #define REG_DSCMB_CSA 0x0109UL 171 #define REG_DSCMB_CIP 0x0030UL 172 173 /* 174 175 #define REG_DSCMB_CIPHER_CONNECT_H (REG_DSCMB_BANK+ 0x000bUL) 176 #define REG_DSCMB_KT_TO_PASER 0x0001UL 177 #define REG_DSCMB_IV_ENABLE 0x0100UL 178 */ 179 180 #define REG_DSCMB_KL_CTRL1 (REG_DSCMB_BANK+ 0x000cUL) 181 #define REG_KL_START 0x0001UL 182 #define REG_KL_DECRYPT 0x0002UL // 1: decrypt. 0: encrypt 183 #define REG_KL_BYTE_INV 0x0008UL 184 #define REG_KL_KEEP_ROUNDS 0x0010UL 185 #define REG_KL_SWRST 0x0080UL 186 #define REG_KL_KEY_SRC_MASK 0x0700UL 187 #define REG_KL_KEY_SRC_SHFT 8UL 188 #define REG_KL_KEY_SRC_ACPU 0UL 189 #define REG_KL_KEY_SRC_SECRET1 1UL 190 #define REG_KL_KEY_SRC_SECRET2 2UL 191 #define REG_KL_KEY_SRC_SECRET3 3UL 192 #define REG_KL_KEY_SRC_SECRET4 4UL 193 #define REG_KL_KEY_SRC_VGK 7UL 194 #define REG_KL_ROUNDS_MASK 0xf000UL 195 #define REG_KL_ROUNDS_SHFT 12UL 196 197 #define REG_DSCMB_KL_CTRL2 (REG_DSCMB_BANK+ 0x000dUL) 198 #define REG_KL_ENG_MODE_MASK 0x003fUL 199 #define REG_KL_ENG_MODE_SHFT 0UL 200 #define REG_LK_ENG_MODE_TDES 0UL 201 #define REG_KL_KEY_DST_MASK 0x3f00UL 202 #define REG_KL_KEY_DST_SHFT 8UL 203 #define REG_KL_KEY_DST_KTAB_ESA 0x4UL 204 #define REG_KL_KEY_DST_KTAB_NSK 0x2UL 205 #define REG_KL_KEY_DST_AESDMA_AES 0x8UL 206 #define REG_KL_KEY_DST_AESDMA_TDES 0x10UL 207 #define REG_KL_KEY_DST_ACPU 0x1UL 208 209 #define REG_DSCMB_KL_CTRL3 (REG_DSCMB_BANK+ 0x000eUL) 210 #define REG_KL_ACPU_ACK 0x0001UL 211 #define REG_KL_FORCE_ACK 0x0008UL 212 213 #define REG_DSCMB_KL_STATUS (REG_DSCMB_BANK+ 0x000fUL) 214 #define REG_KL_KTE_STATUS_DONE 0x0001UL 215 #define REG_KL_STATUS_CW_RDY_MASK 0x007cUL 216 #define REG_KL_STATUS_CW_RDY_SHFT 2UL 217 218 #define REG_DSCMB_CIPHER0_HDCP2_RIV0 (REG_DSCMB_BANK + 0x0010UL) 219 #define REG_DSCMB_CIPHER0_HDCP2_RIV1 (REG_DSCMB_BANK + 0x0011UL) 220 #define REG_DSCMB_CIPHER0_HDCP2_RIV2 (REG_DSCMB_BANK + 0x0012UL) 221 #define REG_DSCMB_CIPHER0_HDCP2_RIV3 (REG_DSCMB_BANK + 0x0013UL) 222 223 224 #define REG_DSCMB_KL_KEY (REG_DSCMB_BANK+ 0x0018UL) 225 226 #define REG_DSCMB_ACPU_START (REG_DSCMB_BANK+ 0x0020UL) 227 #define REG_ACPU_CMD_START 0x0001UL 228 /* 229 #define REG_ACPU_CMD_WEN_SHFT 4UL 230 #define REG_ACPU_CMD_WEN_MASK 0x00F0UL 231 #define REG_ACPU_CMD_WEN_ACPU 0x0010UL 232 #define REG_ACPU_CMD_WEN_KLADDER 0x0020UL 233 #define REG_ACPU_CMD_WEN_NSK 0x0040UL 234 #define REG_ACPU_CMD_WEN_SWITCH2 0x0080UL 235 */ 236 237 #define REG_DSCMB_ACPU_CMD (REG_DSCMB_BANK+ 0x0022UL) 238 #define REG_ACPU_CMD_READ 0x0000UL 239 #define REG_ACPU_CMD_WRITE 0x0001UL 240 #define REG_ACPU_CMD_POS_SHFT 4UL 241 #define REG_ACPU_CMD_POS_MASK 0x00F0UL 242 #define REG_ACPU_PIDFLTID_SHFT 8UL 243 #define REG_ACPU_PIDFLTID_MASK 0x0F00UL 244 #define REG_ACPU_DSCMB_TYPE_SHFT 12UL 245 #define REG_ACPU_DSCMB_TYPE_MASK 0x3000UL 246 #define REG_ACPU_DSCMB_TYPE_CLEAR HAL_DSCMB_KEY_TYPE_CLEAR 247 #define REG_ACPU_DSCMB_TYPE_EVEN HAL_DSCMB_KEY_TYPE_EVEN 248 #define REG_ACPU_DSCMB_TYPE_ODD HAL_DSCMB_KEY_TYPE_ODD 249 #define REG_ACPU_DSCMB_VALID 14UL 250 251 #define REG_DSCMB_WRITE (REG_DSCMB_BANK+ 0x0024UL) 252 #define REG_DSCMB_READ (REG_DSCMB_BANK+ 0x0026UL) 253 254 #define REG_DSCMB_ESA_MODE_EXT (REG_DSCMB_BANK+ 0x002fUL) 255 #define REG_DSCMB_ESA_OC_MODE 0x0001UL 256 #define REG_DSCMB_ESA_CLR_START_MODE 0x0002UL 257 #define REG_DSCMB_ESA_TSC_PUSI_MODE 0x0004UL 258 259 #define REG_DSCMB_KT_CTRL (REG_DSCMB_BANK+ 0x0030UL) 260 #define REG_DSCMB_CIP_ESA_DES_MODE 0x0001UL 261 #define REG_DSCMB_CIP_ESA_AES_MODE 0x0008UL 262 #define REG_DSCMB_CIP_ESA_ECB_MODE 0x0010UL 263 #define REG_DSCMB_CIP_ESA_CBC_MODE 0x0020UL //T8 new 264 #define REG_DSCMB_CIP_ESA_CBC_CLR_MODE 0x0040UL 265 #define REG_DSCMB_CIP_ESA_DECRYPT 0x0080UL 266 #define REG_DSCMB_CIP_ESA_PES_MODE 0x0800UL 267 #define REG_DSCMB_CIP_ESA_MULTI2_MODE 0x1000UL 268 #define REG_DSCMB_CIP_ESA_CTR_MODE 0x2000UL 269 #define REG_DSCMB_CIP_ESA_CTR_CLR_MODE 0x4000UL 270 #define REG_DSCMB_CIP_ESA_HDCP2_MODE 0x8000UL 271 272 /* 273 #define REG_DSCMB_NSAD2KT_VALID 0x0001UL 274 #define REG_DSCMB_ESA2KT_VALID 0x0002UL 275 #define REG_DSCMB_NSAS2KT_VALID 0x0004UL 276 #define REG_DSCMB_SWITCH2KT_VALID 0x0008UL 277 #define REG_DSCMB_NSAD2KT_WEN 0x0010UL 278 #define REG_DSCMB_ESA2KT_WEN 0x0020UL 279 #define REG_DSCMB_NSAS2KT_WEN 0x0040UL 280 #define REG_DSCMB_SWITCH2KT_WEN 0x0080UL 281 #define REG_DSCMB_SWITCH2WNASK 0x0F00UL 282 */ 283 #define REG_DSCMB_MULTI2_ROUND (REG_DSCMB_BANK+ 0x0031UL) 284 #define REG_DSCMB_CW_LEVEL0 (REG_DSCMB_BANK+ 0x0034UL) 285 #define REG_DSCMB_CW_LEVEL1 (REG_DSCMB_BANK+ 0x003cUL) 286 #define REG_DSCMB_CW_LEVEL2 (REG_DSCMB_BANK+ 0x0044UL) 287 #define REG_DSCMB_ENG2_CTRL (REG_DSCMB_BANK+ 0x005FUL) 288 #define REG_DSCMB_MULTI2_ROUNDS_MASK 0x00FFUL 289 //////////////////////////////////////////////////////////////////////////////////////////////// 290 // Descambler bank 2 291 //////////////////////////////////////////////////////////////////////////////////////////////// 292 #define REG_DSCMB2_BANK 0x9E00UL 293 294 #define REG_DSCMB2_CIPHERENG_CTRL (REG_DSCMB2_BANK+ 0x000CUL) 295 #define REG_BLK_AF 0x0008UL // DSCMB status don't care packet which full of AF data 296 297 #define REG_DSCMB2_MULTI2_SYSKEY_L0_0 (REG_DSCMB2_BANK+ 0x0020UL) // systemkey 0 298 #define REG_DSCMB2_MULTI2_SYSKEY_H0_0 (REG_DSCMB2_BANK+ 0x0022UL) 299 #define REG_DSCMB2_MULTI2_SYSKEY_L1_0 (REG_DSCMB2_BANK+ 0x0024UL) // systemkey 1 300 #define REG_DSCMB2_MULTI2_SYSKEY_H1_0 (REG_DSCMB2_BANK+ 0x0026UL) 301 #define REG_DSCMB2_MULTI2_SYSKEY_L2_0 (REG_DSCMB2_BANK+ 0x0028UL) // systemkey 2 302 #define REG_DSCMB2_MULTI2_SYSKEY_H2_0 (REG_DSCMB2_BANK+ 0x002AUL) 303 #define REG_DSCMB2_MULTI2_SYSKEY_L3_0 (REG_DSCMB2_BANK+ 0x002CUL) // systemkey 3 304 #define REG_DSCMB2_MULTI2_SYSKEY_H3_0 (REG_DSCMB2_BANK+ 0x002EUL) 305 306 #define REG_DSCMB2_PIDSLOT0 (REG_DSCMB2_BANK+ 0x0040UL) 307 #define REG_PIDSLOT_SLOTID_CLEAR_MASK 0x001FUL 308 #define REG_PIDSLOT_SLOTID_CLEAR_SHFT 0UL 309 #define REG_PIDSLOT_SLOTID_EVEN_MASK 0x03E0UL 310 #define REG_PIDSLOT_SLOTID_EVEN_SHFT 5UL 311 #define REG_PIDSLOT_SLOTID_ODD_MASK 0x7C00UL 312 #define REG_PIDSLOT_SLOTID_ODD_SHFT 10UL 313 314 // Slot/switch 315 316 #endif // #ifndef __REG_DSCMB_H__ 317