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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 //////////////////////////////////////////////////////////////////////////////////////////////////// 96 // 97 // File name: regTCF.h 98 // Description: CF, CFKE Register Definition 99 // 100 //////////////////////////////////////////////////////////////////////////////////////////////////// 101 102 #ifndef _REG_TCF_H_ 103 #define _REG_TCF_H_ 104 105 106 //-------------------------------------------------------------------------------------------------- 107 // Abbreviation 108 //-------------------------------------------------------------------------------------------------- 109 // TCF Transport Crypto Firewall 110 // CFKE Crypto Firewall Key Engine 111 112 113 //-------------------------------------------------------------------------------------------------- 114 // Global Definition 115 //-------------------------------------------------------------------------------------------------- 116 //#define TEST_PM_BASE // temporary solution-- calculate from PM Base 117 #ifdef TEST_PM_BASE 118 #define CLKGEN0_BASE (0x100B00*2) // h100B 119 #define X32_CRI_BASE (0x1D0200*2) // h1D02 120 #define CRI_KL_BASE (0x173E00*2) // h173E 121 #else 122 #define CLKGEN0_BASE (0x00B00*2) // h100B 123 #define X32_CRI_BASE (0xD0200*2) // h1D02 124 #define CRI_KL_BASE (0x73E00*2) // h173E 125 #endif 126 127 /// CLK 128 #define REG_CLK_TCF_SEL (0x09*4) 129 #define TCF_CLK_54_MHZ (0x00000001) // [0] 0: XTAL 12Mhz (default); 1: 54Mhz 130 131 /// X32_CRI 132 #define CF_BASE (X32_CRI_BASE) 133 #define CFKE_BASE ((X32_CRI_BASE)+(0x40*4)) 134 135 136 //-------------------------------------------------------------------------------------------------- 137 // Compliation Option 138 //-------------------------------------------------------------------------------------------------- 139 140 141 //------------------------------------------------------------------------------------------------- 142 // Harware Capability 143 //------------------------------------------------------------------------------------------------- 144 145 146 //------------------------------------------------------------------------------------------------- 147 // Type and Structure 148 //------------------------------------------------------------------------------------------------- 149 typedef struct _REG32 150 { 151 volatile MS_U32 u32Reg; 152 } REG32; 153 154 155 typedef struct _REG_CFCtrl 156 { 157 REG32 Cf_Status; // (REG_CF_BASE + 0x00*4) 158 #define CF_TRANS_STATUS_MASK 0xF0000000 // 159 #define CF_NVM_STATUS_MASK 0x0C000000 // 160 #define CF_DIFF_STATUS_MASK 0x02000000 // 161 #define CF_RESERVED_MASK 0x01FE0000 // 162 #define CF_USE_NVMKEY_MASK 0x00010000 // 163 #define CF_OPERATION_TYPE_MASK 0x0000E000 // 164 #define CF_DECM_SOURCE_MASK 0x00001800 // 165 #define CF_OUTPUT_USAGE_MASK 0x00000600 // 166 #define CF_PRODUCT_RANGE_MASK 0x00000100 // 167 #define CF_PRODUCT_OFFSET_MASK 0x000000FF // 168 #define CF_TRANS_STATUS_POS 28 169 #define CF_NVM_STATUS_POS 26 170 #define CF_DIFF_STATUS_POS 25 171 #define CF_RESERVED_POS 17 172 #define CF_USE_NVMKEY_POS 16 173 #define CF_OPERATION_TYPE_POS 13 174 #define CF_DECM_SOURCE_POS 11 175 #define CF_OUTPUT_USAGE_POS 9 176 #define CF_PRODUCT_RANGE_POS 8 177 #define CF_PRODUCT_OFFSET_POS 0 178 REG32 Cf_Reserve01_03[3]; 179 //REG32 Cf_Reserve02; 180 //REG32 Cf_Reserve03; 181 REG32 Cf_Input; // (REG_CF_BASE + 0x04*4) 182 // 183 REG32 Cf_Reserve05_07[3]; 184 //REG32 Cf_Reserve06; 185 //REG32 Cf_Reserve07; 186 REG32 Cf_Output; // (REG_CF_BASE + 0x08*4) 187 // 188 REG32 Cf_Reserve09_0B[3]; 189 //REG32 Cf_Reserve0A; 190 //REG32 Cf_Reserve0B; 191 REG32 Cf_Platform; // (REG_CF_BASE + 0x0C*4) 192 #define CF_PLATFORM_RECENT_RESET_MASK 0x80000000 // 193 #define CF_PLATFORM_TRANSACTION_DONE_MASK 0x40000000 // 194 #define CF_PLATFORM_CF_ALERT_MASK 0x02000000 // 195 #define CF_PLATFORM_HW_DECM_ERROR_MASK 0x01000000 // 196 #define CF_PLATFORM_CWC_VALID_MASK 0x00800000 // 197 #define CF_PLATFORM_HW_DECM_VALID_MASK 0x00400000 // 198 #define CF_PLATFORM_HW_DECM_FLUSH_MASK 0x00200000 // 199 #define CF_PLATFORM_CF_ACTIVATED_MASK 0x00020000 // 200 #define CF_PLATFORM_DEVELOPMENT_MODE_MASK 0x00010000 //~ Note: 15 in Spec. ~// // 201 #define CF_PLATFORM_RECENT_RESET_POS 31 202 #define CF_PLATFORM_TRANSACTION_DONE_POS 30 203 #define CF_PLATFORM_CF_ALERT_POS 25 204 #define CF_PLATFORM_HW_DECM_ERROR_POS 24 205 #define CF_PLATFORM_CWC_VALID_POS 23 206 #define CF_PLATFORM_HW_DECM_VALID_POS 22 207 #define CF_PLATFORM_HW_DECM_FLUSH_POS 21 208 #define CF_PLATFORM_CF_ACTIVATED_POS 17 209 #define CF_PLATFORM_DEVELOPMENT_MODE_POS 16 //~ Note: 15 in Spec. ~// 210 REG32 Cf_Reserve0D_0F[3]; 211 //REG32 Cf_Reserve0E; 212 //REG32 Cf_Reserve0F; 213 REG32 Cf_Feature; // (REG_CF_BASE + 0x10*4) 214 // 215 REG32 Cf_Reserve11_13[3]; 216 //REG32 Cf_Reserve12; 217 //REG32 Cf_Reserve13; 218 REG32 Cf_Version; // (REG_CF_BASE + 0x14*4) 219 #define CF_VERSION_MANUFACTURER_ID_MASK 0x07000000 // 220 #define CF_VERSION_NETLIST_VERSION_MASK 0x003F0000 // 221 #define CF_VERSION_VERSION_EPOCH_MASK 0x00000F00 // 222 #define CF_VERSION_BUILD_ID_MASK 0x000000FF // 223 #define CF_VERSION_MANUFACTURER_ID_POS 24 224 #define CF_VERSION_NETLIST_VERSION_POS 16 225 #define CF_VERSION_VERSION_EPOCH_POS 8 226 #define CF_VERSION_BUILD_ID_POS 0 227 REG32 Cf_Reserve15_17[3]; 228 //REG32 Cf_Reserve16; 229 //REG32 Cf_Reserve17; 230 REG32 Cf_Perso_Config; // (REG_CF_BASE + 0x18*4) 231 // 232 }REG_CFCtrl; 233 234 235 typedef struct _REG_CFKECtrl 236 { 237 REG32 Cfke_Command; // (REG_CFB_BASE + 0x40*4) 238 #define CFKE_CMD_OP_MASK 0x0000F000 // cfkeCmdOp 239 #define CFKE_CMD_DEST_MASK 0x00000F00 // cfkeCmdDest 240 #define CFKE_CMD_SRC1_MASK 0x000000F0 // cfkeCmdSrc1 241 #define CFKE_CMD_SRC2_MASK 0x0000000F // cfkeCmdSrc2 242 #define CFKE_CMD_OP_POS 12 243 #define CFKE_CMD_DEST_POS 8 244 #define CFKE_CMD_SRC1_POS 4 245 #define CFKE_CMD_SRC2_POS 0 246 REG32 Cfke_Reserve41_43[3]; 247 //REG32 Cf_Reserve42; 248 //REG32 Cf_Reserve43; 249 REG32 Cfke_Status; // (REG_CFB_BASE + 0x44*4) 250 #define CFKE_OPERATION_STATUS_MASK 0xF0000000 // cfkeOperationStatus 251 #define CFKE_OPERATION_COUNT_MASK 0x0FF00000 // cfkeOperationCount 252 #define CFKE_ERROR_CODE_MASK 0x000F0000 // cfkeErrorCode 253 #define CFKE_OPERATION_TYPE_MASK 0x0000E000 // cfkeOperationType 254 #define CFKR_RESERVED_MASK 0x00001FF0 // reserved 255 #define CFKE_DIFF_ALLOW_NON_UNW_MASK 0x00000008 // cfkeDiffAllowNonUnw 256 #define CFKE_DIFF_ALLOW_CK_MASK 0x00000004 // cfkeDiffAllowCk 257 #define CFKE_DIFF_CONTENT_OUTPUT_ALLOWED_MASK 0x00000003 // cfkeDiffContentOutputAllowed 258 #define CFKE_OPERATION_STATUS_POS 28 259 #define CFKE_OPERATION_COUNT_POS 20 260 #define CFKE_ERROR_CODE_POS 16 261 #define CFKE_OPERATION_TYPE_POS 13 262 #define CFKE_RESERVED_POS 4 263 #define CFKE_DIFF_ALLOW_NON_UNW_POS 3 264 #define CFKE_DIFF_ALLOW_CK_POS 2 265 #define CFKE_DIFF_CONTENT_OUTPUT_ALLOWED_POS 0 266 REG32 Cfke_Reserve45_47[3]; 267 //REG32 Cf_Reserve46; 268 //REG32 Cf_Reserve47; 269 REG32 Cfke_Platform; // (REG_CFB_BASE + 0x48*4) 270 #define CFKE_TRANSACTION_DONE_MASK 0x40000000 // cfkeTransactionDone 271 #define CK_OUTPUT_ALLOWED_MASK 0x00000600 // ckOutputAllowed 272 #define CK_VALID_MASK 0x00000100 // ckValid 273 #define CW_OUTPUT_ALLOWED_MASK 0x00000006 // ckOutputAllowed 274 #define CW_VALID_MASK 0x00000001 // ckValid 275 #define CFKE_TRANSACTION_DONE_POS 30 276 #define CK_OUTPUT_ALLOWED_POS 9 277 #define CK_VALID_POS 8 278 #define CW_OUTPUT_ALLOWED_POS 1 279 #define CW_VALID_POS 0 280 REG32 Cfke_Reserve49_4B[3]; 281 //REG32 Cf_Reserve4A; 282 //REG32 Cf_Reserve4B; 283 REG32 Cfke_Unw_Path; // (REG_CFB_BASE + 0x4C*4) 284 // 285 REG32 Cfke_Reserve4D_4F[3]; 286 //REG32 Cf_Reserve4E; 287 //REG32 Cf_Reserve4F; 288 289 REG32 Cfke_Validator_0; // (REG_CFB_BASE + 0x50*4) 290 // 291 REG32 Cfke_Reserve51_53[3]; 292 //REG32 Cf_Reserve52; 293 //REG32 Cf_Reserve53; 294 REG32 Cfke_Validator_1; // (REG_CFB_BASE + 0x54*4) 295 // 296 REG32 Cfke_Reserve55_57[3]; 297 //REG32 Cf_Reserve56; 298 //REG32 Cf_Reserve57; 299 300 REG32 Cfke_Slot_A; // (REG_CFB_BASE + 0x58*4) 301 // 302 REG32 Cfke_Reserve59_5B[3]; 303 //REG32 Cf_Reserve5A; 304 //REG32 Cf_Reserve5B; 305 REG32 Cfke_Slot_B; // (REG_CFB_BASE + 0x5C*4) 306 // 307 REG32 Cfke_Reserve5D_5F[3]; 308 //REG32 Cf_Reserve5E; 309 //REG32 Cf_Reserve5F; 310 REG32 Cfke_Slot_C; // (REG_CFB_BASE + 0x60*4) 311 // 312 REG32 Cfke_Reserve61_63[3]; 313 //REG32 Cf_Reserve62; 314 //REG32 Cf_Reserve63; 315 REG32 Cfke_Slot_D; // (REG_CFB_BASE + 0x64*4) 316 // 317 REG32 Cfke_Reserve65_67[3]; 318 //REG32 Cf_Reserve66; 319 //REG32 Cf_Reserve67; 320 321 REG32 Cfke_User_Hash; // (REG_CFB_BASE + 0x68*4) 322 // 323 }REG_CFKECtrl; 324 325 326 typedef struct _REG_CRIKLCtrl 327 { 328 REG32 reg_cfstatusout_l; // 0x00 329 REG32 reg_cfstatusout_h; // 0x01 330 331 REG32 reg_cfkestatusout_l; // 0x02 332 REG32 reg_cfkestatusout_h; // 0x03 333 334 REG32 reg_cfplatformout_l; // 0x04 335 REG32 reg_cfplatformout_h; // 0x05 336 337 REG32 reg_cffeatureout_l; // 0x06 338 REG32 reg_cffeatureout_h; // 0x07 339 340 REG32 reg_transaction; // 0x08 341 #define CRI_KT_CF_TRANSACTION_DONE 0x0001 342 #define CRI_KT_CFKE_TRANSACTION_DONE 0x0002 343 #define CRI_KT_CF_TRAN_INT 0x0004 344 #define CRI_KT_CFKE_TRAN_INT 0x0008 345 #define CRI_KT_CF_TRAN_INT_MASK 0x0010 346 #define CRI_KT_CFKE_TRAN_INT_MASK 0x0020 347 #define CRI_KT_PROCTION_MODE 0x0100 348 // 349 REG32 reg_cri_kt; // 0x09 350 #define CRI_KT_INT 0x0001 351 #define CRI_KT_INT_NONSEC 0x0002 352 #define CRI_KT_INT_MASK 0x0010 353 #define CRI_KT_INT_MASK_NONSEC 0x0020 354 #define CRI_KT_CLR_ERR 0x0100 355 #define CRI_KT_ERR_FLAG 0xF000 356 REG32 reg_cri_kt_index; // 0x0a 357 #define CRI_KT_SCMB_CTL_POS 4 358 359 REG32 reg_cri_kt_para_15_00; // 0x0b 360 #define CRI_KT_DEST_AESDMA_POS 12 361 #define CRI_KT_DEST_PVR_POS 11 362 #define CRI_KT_DEST_CIPHER_POS 10 363 #define CRI_KT_ENCRYPT_POS 9 364 #define CRI_KT_DECRYPT_POS 8 365 #define CRI_KT_KTE_3 7 366 #define CRI_KT_KTE_2 6 367 #define CRI_KT_KTE_1 5 368 #define CRI_KT_KTE_0 4 369 #define CRI_KT_LOCK 3 370 #define CRI_KT_PARA_VLA 2 371 #define CRI_KT_KL_EN 0 372 REG32 reg_cri_kt_para_31_16; // 0x0c 373 #define CRI_KT_DROP_MASK 0x00F0 374 #define CRI_KT_CNT_MASK 0x000F 375 #define CRI_KT_ENG_NPD_POS 15 376 #define CRI_KT_ENG_MULTI2_POS 14 377 #define CRI_KT_ENG_CSAV2_POS 13 378 #define CRI_KT_ENG_CSAV3_POS 12 379 #define CRI_KT_ENG_ASA_POS 11 380 #define CRI_KT_ENG_DES_POS 10 381 #define CRI_KT_ENG_TDES_POS 9 382 #define CRI_KT_ENG_AES_POS 8 383 #define CRI_KT_DROP_POS 4 384 #define CRI_KT_CNT_POS 0 385 REG32 reg_cri_kt_para_47_32; // 0x0d 386 #define CRI_KT_VENDOR_ATT_L_POS 14 387 #define CRI_KT_OUTPUT_ALLOWED_POS 12 388 #define CRI_KT_MULTI_ENG_POS 5 389 #define CRI_KT_LSB64_POS 4 390 #define CRI_KT_KEY_SIZE_256_POS 3 391 #define CRI_KT_KEY_SIZE_192_POS 2 392 #define CRI_KT_KEY_SIZE_128_POS 1 393 #define CRI_KT_KEY_SIZE_64_POS 0 394 // VendorAtt 395 #define CRI_KT_VENDOR_ATT_L_VAL_MASK 0x0003 396 REG32 reg_cri_kt_para_63_48; // 0x0e 397 #define CRI_KT_VENDOR_NO_POS 12 398 #define CRI_KT_VENDOR_ATT_H_POS 0 399 // VendorAtt 400 #define CRI_KT_VENDOR_ATT_H_VAL_MASK 0xFFFC 401 #define CRI_KT_VENDOR_ATT_L_OFFSET 2 402 403 REG32 reg_reserve_1d_0f[15]; // 0x1d~0xf 404 405 REG32 reg_cri_kt_dbg; // 0x1e 406 #define CRI_KT_DBG_SEL 0x00FF 407 #define CRI_KT_BRIDGE_DBG_L 0xFF00 408 REG32 reg_cri_kt_bridge_debug; // 0x1f 409 #define CRI_KT_BRIDGE_DBG_H 0xFFFF 410 // 411 REG32 reg_cri_ks; // 0x20 412 #define CRI_KS_INT 0x0001 413 #define CRI_KS_INT_NONSEC 0x0002 414 #define CRI_KS_INT_MASK 0x0010 415 #define CRI_KS_INT_MASK_NONSEC 0x0020 416 #define CRI_KS_CLR_ERR 0x0100 417 #define CRI_KS_ERR_FLAG 0xF000 418 REG32 reg_cri_ks_index; // 0x21 419 #define CRI_KS_IDX_VAL_MASK 0x001F 420 421 REG32 reg_cri_ks_para_15_00; // 0x22 422 #define CRI_KS_DEST_AESDMA_POS 12 423 #define CRI_KS_DEST_PVR_POS 11 424 #define CRI_KS_DEST_CIPHER_POS 10 425 #define CRI_KS_ENCRYPT_POS 9 426 #define CRI_KS_DECRYPT_POS 8 427 #define CRI_KS_KTE_3 7 428 #define CRI_KS_KTE_2 6 429 #define CRI_KS_KTE_1 5 430 #define CRI_KS_KTE_0 4 431 #define CRI_KS_LOCK 3 432 #define CRI_KS_PARA_VLA 2 433 #define CRI_KS_KL_EN 0 434 REG32 reg_cri_ks_para_31_16; // 0x23 435 #define CRI_KS_DROP_MASK 0x00F0 436 #define CRI_KS_CNT_MASK 0x000F 437 #define CRI_KS_ENG_NPD_POS 15 438 #define CRI_KS_ENG_MULTI2_POS 14 439 #define CRI_KS_ENG_CSAV2_POS 13 440 #define CRI_KS_ENG_CSAV3_POS 12 441 #define CRI_KS_ENG_ASA_POS 11 442 #define CRI_KS_ENG_DES_POS 10 443 #define CRI_KS_ENG_TDES_POS 9 444 #define CRI_KS_ENG_AES_POS 8 445 #define CRI_KS_DROP_POS 4 446 #define CRI_KS_CNT_POS 0 447 REG32 reg_cri_ks_para_47_32; // 0x24 448 #define CRI_KS_VENDOR_ATT_L_POS 14 449 #define CRI_KS_OUTPUT_ALLOWED_POS 12 450 #define CRI_KS_MULTI_ENG_POS 5 451 #define CRI_KS_LSB64_POS 4 452 #define CRI_KS_KEY_SIZE_256_POS 3 453 #define CRI_KS_KEY_SIZE_192_POS 2 454 #define CRI_KS_KEY_SIZE_128_POS 1 455 #define CRI_KS_KEY_SIZE_64_POS 0 456 // VendorAtt 457 #define CRI_KS_VENDOR_ATT_L_VAL_MASK 0x0003 458 REG32 reg_cri_ks_para_63_48; // 0x25 459 #define CRI_KS_VENDOR_NO_POS 12 460 #define CRI_KS_VENDOR_ATT_H_POS 0 461 // VendorAtt 462 #define CRI_KS_VENDOR_ATT_H_VAL_MASK 0xFFFC 463 #define CRI_KS_VENDOR_ATT_L_OFFSET 2 464 465 REG32 reg_cri_ks_dbg; // 0x26 466 #define CRI_KS_DBG_SEL 0x00FF 467 #define CRI_KS_BRIDGE_DBG_L 0xFF00 468 REG32 reg_cri_ks_bridge_debug; // 0x27 469 #define CRI_KS_BRIDGE_DBG_H 0xFFFF 470 }REG_CRIKLCtrl; 471 472 #endif // #ifndef _REG_TCF_H_ 473