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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 //////////////////////////////////////////////////////////////////////////////////////////////////// 96 // 97 // File name: regTCF.h 98 // Description: TCF Register Definition 99 // 100 //////////////////////////////////////////////////////////////////////////////////////////////////// 101 102 #ifndef _REG_TCF_H_ 103 #define _REG_TCF_H_ 104 105 106 //-------------------------------------------------------------------------------------------------- 107 // Abbreviation 108 //-------------------------------------------------------------------------------------------------- 109 // TCF Transport Crypto Firewall 110 111 112 //-------------------------------------------------------------------------------------------------- 113 // Global Definition 114 //-------------------------------------------------------------------------------------------------- 115 116 117 //-------------------------------------------------------------------------------------------------- 118 // Compliation Option 119 //-------------------------------------------------------------------------------------------------- 120 121 122 //------------------------------------------------------------------------------------------------- 123 // Harware Capability 124 //------------------------------------------------------------------------------------------------- 125 126 127 //------------------------------------------------------------------------------------------------- 128 // Type and Structure 129 //------------------------------------------------------------------------------------------------- 130 #define REG_CLK_CF_BASE (0x03300*2) // h1033 131 //#define REG_CLK_TSP_BASE (0x00b00*2) // h100b 132 #define REG_CLK_GEN0_BASE (0x00B00*2) //h100B 133 #define REG_CFB_BASE (0xA0E00*2) // h1A0E 134 #define REG_CF_BASE (0xA0F00*2) // h1A0F 135 136 #define REG_CLK_CF (0x24*4) 137 #define ENABLE_48_MHZ_CF_CLK_MASK 0x00000010 //[4] 0: enable 48MHz TCG clock 138 #define ENABLE_48_MHZ_CF_CLK 0x00000000 139 140 #define REG_CLK_CFTOP_P_SEL (0x31*4) 141 #define ENABLE_CFTOP_P_SEL_MASK 0x00000300 //[9:8] 00: xtail 12M clock, 01: 54M clock, others: N/A 142 #define ENABLE_CFTOP_P_12M_CLK 0x00000000 143 #define ENABLE_CFTOP_P_54M_CLK 0x00000100 144 145 //#define REG_CLK_TSP (0x2a*4) 146 //#define SET_192_MHZ_TSP_CLK_MASK 0x0000001F //[4;0] 8: set 192MHz TSP clock 147 //#define SET_192_MHZ_TSP_CLK 0x00000008 148 149 150 typedef struct _REG32 151 { 152 volatile MS_U32 u32Reg; 153 } REG32; 154 155 156 typedef struct _REG_CFCtrl 157 { 158 REG32 Cf_Status; // (REG_CF_BASE + 0x00*4) 159 #define CF_TRANS_STATUS_MASK 0xF0000000 // 160 #define CF_NVM_STATUS_MASK 0x0C000000 // 161 #define CF_DIFF_STATUS_MASK 0x02000000 // 162 #define CF_RESERVED_MASK 0x01FE0000 // 163 #define CF_USE_NVMKEY_MASK 0x00010000 // 164 #define CF_OPERATION_TYPE_MASK 0x0000E000 // 165 #define CF_DECM_SOURCE_MASK 0x00001800 // 166 #define CF_OUTPUT_USAGE_MASK 0x00000600 // 167 #define CF_PRODUCT_RANGE_MASK 0x00000100 // 168 #define CF_PRODUCT_OFFSET_MASK 0x000000FF // 169 #define CF_TRANS_STATUS_POS 28 170 #define CF_NVM_STATUS_POS 26 171 #define CF_DIFF_STATUS_POS 25 172 #define CF_RESERVED_POS 17 173 #define CF_USE_NVMKEY_POS 16 174 #define CF_OPERATION_TYPE_POS 13 175 #define CF_DECM_SOURCE_POS 11 176 #define CF_OUTPUT_USAGE_POS 9 177 #define CF_PRODUCT_RANGE_POS 8 178 #define CF_PRODUCT_OFFSET_POS 0 179 REG32 Cf_Reserve01_03[3]; 180 //REG32 Cf_Reserve02; 181 //REG32 Cf_Reserve03; 182 REG32 Cf_Input; // (REG_CF_BASE + 0x04*4) 183 // 184 REG32 Cf_Reserve05_07[3]; 185 //REG32 Cf_Reserve06; 186 //REG32 Cf_Reserve07; 187 REG32 Cf_Output; // (REG_CF_BASE + 0x08*4) 188 // 189 REG32 Cf_Reserve09_0B[3]; 190 //REG32 Cf_Reserve0A; 191 //REG32 Cf_Reserve0B; 192 REG32 Cf_Platform; // (REG_CF_BASE + 0x0C*4) 193 #define CF_PLATFORM_RECENT_RESET_MASK 0x80000000 // 194 #define CF_PLATFORM_TRANSACTION_DONE_MASK 0x40000000 // 195 #define CF_PLATFORM_CF_ALERT_MASK 0x02000000 // 196 #define CF_PLATFORM_HW_DECM_ERROR_MASK 0x01000000 // 197 #define CF_PLATFORM_CWC_VALID_MASK 0x00800000 // 198 #define CF_PLATFORM_HW_DECM_VALID_MASK 0x00400000 // 199 #define CF_PLATFORM_HW_DECM_FLUSH_MASK 0x00200000 // 200 #define CF_PLATFORM_CF_ACTIVATED_MASK 0x00020000 // 201 #define CF_PLATFORM_DEVELOPMENT_MODE_MASK 0x00010000 //~ Note: 15 in Spec. ~// // 202 #define CF_PLATFORM_RECENT_RESET_POS 31 203 #define CF_PLATFORM_TRANSACTION_DONE_POS 30 204 #define CF_PLATFORM_CF_ALERT_POS 25 205 #define CF_PLATFORM_HW_DECM_ERROR_POS 24 206 #define CF_PLATFORM_CWC_VALID_POS 23 207 #define CF_PLATFORM_HW_DECM_VALID_POS 22 208 #define CF_PLATFORM_HW_DECM_FLUSH_POS 21 209 #define CF_PLATFORM_CF_ACTIVATED_POS 17 210 #define CF_PLATFORM_DEVELOPMENT_MODE_POS 16 //~ Note: 15 in Spec. ~// 211 REG32 Cf_Reserve0D_0F[3]; 212 //REG32 Cf_Reserve0E; 213 //REG32 Cf_Reserve0F; 214 REG32 Cf_Feature; // (REG_CF_BASE + 0x10*4) 215 // 216 REG32 Cf_Reserve11_13[3]; 217 //REG32 Cf_Reserve12; 218 //REG32 Cf_Reserve13; 219 REG32 Cf_Version; // (REG_CF_BASE + 0x14*4) 220 #define CF_VERSION_MANUFACTURER_ID_MASK 0x07000000 // 221 #define CF_VERSION_NETLIST_VERSION_MASK 0x003F0000 // 222 #define CF_VERSION_VERSION_EPOCH_MASK 0x00000F00 // 223 #define CF_VERSION_BUILD_ID_MASK 0x000000FF // 224 #define CF_VERSION_MANUFACTURER_ID_POS 24 225 #define CF_VERSION_NETLIST_VERSION_POS 16 226 #define CF_VERSION_VERSION_EPOCH_POS 8 227 #define CF_VERSION_BUILD_ID_POS 0 228 REG32 Cf_Reserve15_17[3]; 229 //REG32 Cf_Reserve16; 230 //REG32 Cf_Reserve17; 231 REG32 Cf_Perso_Config; // (REG_CF_BASE + 0x18*4) 232 // 233 }REG_CFCtrl; 234 235 236 typedef struct _REG_CFBCtrl 237 { 238 REG32 Cfb_Use_Case; // (REG_CFB_BASE + 0x00*4) 239 #define REG_USE_CASE_MASK 0x0000000F 240 #define REG_RESET_CFB 0x00000010 241 #define REG_INITIAL_SM 0x00000020 242 #define REG_CFB_INT_CLR 0x00000040 243 #define REG_TCF_KEY_SEL_MASK 0x00000F00 244 #define REG_CFB_CACWC_SEL 0x00010000 245 REG32 Cfb_Status; // (REG_CFB_BASE + 0x01*4) 246 #define REG_CFB_DONE 0x00000002 247 #define REG_CFB_READY 0x00000004 248 #define REG_AES_DONE 0x00000008 249 //... 250 #define REG_FORBID_TCF_KEY_OP 0x00000020 251 #define REG_TCF_CWC_WR_DONE_LTH 0x00000040 252 #define REG_TCF_CWC_WR_RESP_LTH 0x00001F00 253 REG32 Cfb_State; // (REG_CFB_BASE + 0x02*4) 254 #define REG_CF_STATE 0x000000FF 255 256 REG32 Cfb_Reserve; 257 258 REG32 Cfb_Cacwc0; // (REG_CFB_BASE + 0x04*4) 259 REG32 Cfb_Cacwc1; // (REG_CFB_BASE + 0x05*4) 260 REG32 Cfb_Cacwc2; // (REG_CFB_BASE + 0x06*4) 261 REG32 Cfb_Cacwc3; // (REG_CFB_BASE + 0x07*4) 262 REG32 Cfb_Epk0; // (REG_CFB_BASE + 0x08*4) 263 REG32 Cfb_Epk1; // (REG_CFB_BASE + 0x09*4) 264 REG32 Cfb_Epk2; // (REG_CFB_BASE + 0x0A*4) 265 REG32 Cfb_Epk3; // (REG_CFB_BASE + 0x0B*4) 266 REG32 Cfb_Efuv0; // (REG_CFB_BASE + 0x0C*4) 267 REG32 Cfb_Efuv1; // (REG_CFB_BASE + 0x0D*4) 268 REG32 Cfb_Efuv2; // (REG_CFB_BASE + 0x0E*4) 269 REG32 Cfb_Efuv3; // (REG_CFB_BASE + 0x0F*4) 270 271 REG32 Cfb_Tcf_Key_Otp; // (REG_CFB_BASE + 0x10*4) 272 #define REG_TCF_CWC_TSID 0x00000F00 273 #define REG_TCF_CWC_SCB 0x00030000 274 #define REG_TCF_CWC_FSCB 0x000C0000 275 #define REG_TCF_CWC_FLD 0x00300000 276 #define REG_TCF_CWC_PID 0xFF000000 277 REG32 Cfb_Key_Dst; // (REG_CFB_BASE + 0x11*4) 278 REG32 Cfb_Reserve11_5F[0x4E]; // (REG_CFB_BASE + (0x12~0x5F)*4) 279 REG32 Cfb_Btw[0x7]; // (REG_CFB_BASE + 0x60*4) 280 REG32 Cfb_Reserve67_6F[0x9]; // (REG_CFB_BASE + (0x67~0x6F)*4) 281 REG32 Cfb_TcfProductionMode; // (REG_CFB_BASE + 0x70*4) 282 #define REG_TCF_PRODUCTION_MODE 0x00000001 283 }REG_CFBCtrl; 284 285 #endif // #ifndef _REG_TCF_H_ 286