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77 //<MStar Software>
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93 ////////////////////////////////////////////////////////////////////////////////////////////////////
94
95 ////////////////////////////////////////////////////////////////////////////////////////////////////
96 //
97 // file drvTCF.c
98 // @brief TCF Driver
99 // @author MStar Semiconductor,Inc.
100 //
101 ////////////////////////////////////////////////////////////////////////////////////////////////////
102
103 #include <string.h>
104
105 #include "MsCommon.h"
106 #include "MsIRQ.h"
107 #include "MsOS.h"
108 #include "MsVersion.h"
109
110 #include "drvMMIO.h"
111 #include "drvTCF.h"
112 #include "halTCF.h"
113 #include "regTCF.h"
114
115 //--------------------------------------------------------------------------------------------------
116 // Driver Compiler Option
117 //--------------------------------------------------------------------------------------------------
118
119
120 //--------------------------------------------------------------------------------------------------
121 // Local Defines
122 //--------------------------------------------------------------------------------------------------
123
124
125 //--------------------------------------------------------------------------------------------------
126 // Global Variable
127 //--------------------------------------------------------------------------------------------------
128
129
130 //--------------------------------------------------------------------------------------------------
131 // Internal Variable
132 //--------------------------------------------------------------------------------------------------
133 static MS_BOOL _bTCF_Init = FALSE;
134 static MS_S32 _s32TCFMutexId = -1;
135 static MS_BOOL _bActivateCFB = TRUE;
136
137 #define TCF_TIMEOUT_VALUE (500)
138
139
140 //--------------------------------------------------------------------------------------------------
141 // Debug Function
142 //--------------------------------------------------------------------------------------------------
143 #define _TCF_DBG(fmt, args...) //printf("\033[32m""[DBG]"fmt"\033[m", ## args)
144 #define _TCF_ERR(fmt, args...) printf("\033[31m""[ERR]"fmt"\033[m", ## args)
145
146 //--------------------------------------------------------------------------------------------------
147 // Internal Function
148 //--------------------------------------------------------------------------------------------------
_MDrv_CF_Ready(void)149 static MS_BOOL _MDrv_CF_Ready(void)
150 {
151 _TCF_DBG("[%s][%d] Tracing...........\n", __FUNCTION__, __LINE__);
152 CF_TRANS_STATUS_VALUES eTransStatus = E_CF_TRANS_STATUS_BUSY_INIT;
153 MS_U32 u32Retries = 0;
154 MS_U8 u8Ret = DRV_TCF_OK;
155
156 eTransStatus = HAL_CF_Get_Trans_Status();
157 switch(eTransStatus)
158 {
159 case E_CF_TRANS_STATUS_INPUT:
160 u32Retries = CF_CMD_WORDS;
161 do {
162 HAL_CF_Write_Input( 0);
163 eTransStatus = HAL_CF_Get_Trans_Status();
164
165 if( 0>=u32Retries-- )
166 {
167 _TCF_ERR("[%s][%d] Busy!!\n", __FUNCTION__, __LINE__);
168 u8Ret = DRV_TCF_FAIL;
169 break;
170 }
171 } while( E_CF_TRANS_STATUS_INPUT==eTransStatus );
172 case E_CF_TRANS_STATUS_BUSY_OP:
173 u32Retries = 30;
174 while( E_CF_TRANS_STATUS_BUSY_OP==eTransStatus )
175 {
176 MsOS_DelayTask(1);
177 eTransStatus = HAL_CF_Get_Trans_Status();
178
179 if( 0>=u32Retries-- )
180 {
181 _TCF_ERR("[%s][%d] Busy!!\n", __FUNCTION__, __LINE__);
182 u8Ret = DRV_TCF_FAIL;
183 break;
184 }
185 }
186 case E_CF_TRANS_STATUS_DONE_OK:
187 case E_CF_TRANS_STATUS_DONE_ERROR:
188 case E_CF_TRANS_STATUS_DONE_MFR_TEST:
189 u32Retries = CF_CWC_WORDS;
190 do {
191 HAL_CF_Read_Output();
192 HAL_CF_Write_Output( 0);
193 eTransStatus = HAL_CF_Get_Trans_Status();
194
195 if( 0>=u32Retries-- )
196 {
197 _TCF_ERR("[%s][%d] Busy!!\n", __FUNCTION__, __LINE__);
198 u8Ret = DRV_TCF_FAIL;
199 break;
200 }
201 } while( (E_CF_TRANS_STATUS_DONE_OK==eTransStatus) ||
202 (E_CF_TRANS_STATUS_DONE_ERROR==eTransStatus) ||
203 (E_CF_TRANS_STATUS_DONE_MFR_TEST==eTransStatus) );
204 case E_CF_TRANS_STATUS_BUSY_INIT:
205 case E_CF_TRANS_STATUS_BUSY_SETUP:
206 u32Retries = 30;
207 while( E_CF_TRANS_STATUS_READY > eTransStatus )
208 {
209 MsOS_DelayTask(1);
210 eTransStatus = HAL_CF_Get_Trans_Status();
211
212 if( 0>=u32Retries-- )
213 {
214 _TCF_ERR("[%s][%d] Invalid state!!\n", __FUNCTION__, __LINE__);
215 u8Ret = DRV_TCF_FAIL;
216 break;
217 }
218 }
219 default:
220 break;
221 }
222
223 return u8Ret;
224 }
225
226 #ifdef TCF_CFKE
_MDrv_CFKE_Ready(void)227 static MS_BOOL _MDrv_CFKE_Ready(void)
228 {
229 _TCF_DBG("[%s][%d] Tracing...........\n", __FUNCTION__, __LINE__);
230 CFKE_TRANS_STATUS_VALUES eTransStatus = E_CFKE_TRANS_STATUS_BUSY_INIT;
231 MS_U32 u32Retries = 0;
232 MS_U8 u8Ret = DRV_TCF_OK;
233
234
235 eTransStatus = HAL_CFKE_Get_OperationStatus();
236 switch(eTransStatus){
237 case E_CFKE_TRANS_STATUS_DONE_ERROR:
238 case E_CFKE_TRANS_STATUS_DONE_TEST:
239 _TCF_DBG("[%s][%d] Perform hard-coded \"CFKE_OP_CLRKE_CMD\"\n", __FUNCTION__, __LINE__);
240 HAL_CFKE_Write_Command( CFKE_OP_CLRKE_CMD);
241 eTransStatus = HAL_CFKE_Get_OperationStatus();
242 case E_CFKE_TRANS_STATUS_BUSY_OP:
243 u32Retries = 30;
244 while( E_CFKE_TRANS_STATUS_BUSY_OP==eTransStatus ){
245 MsOS_DelayTask(1);
246 eTransStatus = HAL_CFKE_Get_OperationStatus();
247
248 if( 0>=u32Retries-- )
249 {
250 _TCF_ERR("[%s][%d] Busy!!\n", __FUNCTION__, __LINE__);
251 u8Ret = DRV_TCF_FAIL;
252 break;
253 }
254 }
255 case E_CFKE_TRANS_STATUS_BUSY_INIT:
256 u32Retries = 30;
257 while( (CFKE_TRANS_STATUS_VALUES)E_CF_TRANS_STATUS_READY>eTransStatus ){
258 MsOS_DelayTask(1);
259 eTransStatus = HAL_CFKE_Get_OperationStatus();
260
261 if( 0>=u32Retries-- ){
262 _TCF_ERR("[%s][%d] Invalid state!!\n", __FUNCTION__, __LINE__);
263 u8Ret = DRV_TCF_FAIL;
264 break;
265 }
266 }
267 default:
268 break;
269 }
270
271 return u8Ret;
272 }
273
_MDrv_CFKE_WriteSlots(DRV_CFKE_SOURCE * pSrc)274 static void _MDrv_CFKE_WriteSlots(DRV_CFKE_SOURCE *pSrc)
275 {
276 MS_U8 u8i = 0;
277
278 switch(pSrc->eSrcType){
279 case E_CFKE_SRC_SLOTA:
280 for( u8i=0 ; u8i<CFKE_INPUT_WORDS ; u8i++ ){
281 HAL_CFKE_Write_SlotA( pSrc->pu32KeySlotData[u8i]);
282 }
283 break;
284 case E_CFKE_SRC_SLOTB:
285 for( u8i=0 ; u8i<CFKE_INPUT_WORDS ; u8i++ ){
286 HAL_CFKE_Write_SlotB( pSrc->pu32KeySlotData[u8i]);
287 }
288 break;
289 case E_CFKE_SRC_SLOTC:
290 for( u8i=0 ; u8i<CFKE_INPUT_WORDS ; u8i++ ){
291 HAL_CFKE_Write_SlotC( pSrc->pu32KeySlotData[u8i]);
292 }
293 break;
294 case E_CFKE_SRC_SLOTD:
295 for( u8i=0 ; u8i<CFKE_INPUT_WORDS ; u8i++ ){
296 HAL_CFKE_Write_SlotD( pSrc->pu32KeySlotData[u8i]);
297 }
298 break;
299 default:
300 break;
301 }
302
303 }
304 #endif
305
306
307 //--------------------------------------------------------------------------------------------------
308 // Global Function
309 //--------------------------------------------------------------------------------------------------
MDrv_TCF_Init(void)310 DLL_PUBLIC DRV_TCF_RET MDrv_TCF_Init(void)
311 {
312 MS_VIRT u32Bank = 0;
313 MS_PHY u32BankSize = 0;
314
315 if( !_bTCF_Init ){
316 if (FALSE == MDrv_MMIO_GetBASE( (MS_VIRT*)&u32Bank, (MS_PHY*)&u32BankSize, MS_MODULE_HW)){
317 _TCF_ERR("[%s][%d] Get MMIO base fail\n", __FUNCTION__, __LINE__);
318 return DRV_TCF_FAIL;
319 }
320 //printf("[%s] >>>>>> u32Bank= 0x%08lx\n", __FUNCTION__, u32Bank);
321
322 HAL_CF_SetBank( u32Bank);
323 HAL_CF_Clk(TRUE);
324 do
325 {
326 if(HAL_CF_Get_Trans_Status() != 0)
327 {
328 break;
329 }
330 }while(1);
331 _s32TCFMutexId = MsOS_CreateMutex(E_MSOS_FIFO, (char*)"TCF mutex", MSOS_PROCESS_SHARED);
332 _bTCF_Init = TRUE;
333 _TCF_DBG("[%s][%d] MDrv_TCF_Init Done!\n", __FUNCTION__, __LINE__);
334 }
335 else{
336 _TCF_DBG("[%s][%d] TCF was already inited!\n", __FUNCTION__, __LINE__);
337 }
338
339 return DRV_TCF_OK;
340 }
341
342
343 // CF
344 //
MDrv_CF_Version_Info(DRV_CF_VERSION * pstVersion)345 DLL_PUBLIC DRV_TCF_RET MDrv_CF_Version_Info(DRV_CF_VERSION *pstVersion)
346 {
347 if( !_bTCF_Init ){
348 _TCF_ERR("[%s][%d] TCF is NOT inited\n", __FUNCTION__, __LINE__);
349 return DRV_TCF_FAIL;
350 }
351 MsOS_ObtainMutex(_s32TCFMutexId, MSOS_WAIT_FOREVER);
352
353 HAL_CF_VERSION_INFO *_pstVersion= (HAL_CF_VERSION_INFO *) pstVersion;
354
355 HAL_CF_Version_Info( _pstVersion);
356
357 MsOS_ReleaseMutex(_s32TCFMutexId);
358 return DRV_TCF_OK;
359 }
360
MDrv_CF_Trans_Status(DRV_CF_TRANS_STATUS * pstTransStatus)361 DLL_PUBLIC DRV_TCF_RET MDrv_CF_Trans_Status(DRV_CF_TRANS_STATUS *pstTransStatus)
362 {
363 if( !_bTCF_Init ){
364 _TCF_ERR("[%s][%d] TCF is NOT inited\n", __FUNCTION__, __LINE__);
365 return DRV_TCF_FAIL;
366 }
367 MsOS_ObtainMutex(_s32TCFMutexId, MSOS_WAIT_FOREVER);
368
369 HAL_CF_TRANS_STATUS *_pstTransStatus= (HAL_CF_TRANS_STATUS *) pstTransStatus;
370
371 HAL_CF_Trans_Status( _pstTransStatus);
372
373 MsOS_ReleaseMutex(_s32TCFMutexId);
374 return DRV_TCF_OK;
375 }
376
MDrv_CF_Cf_Status(DRV_CF_CF_STATUS * pstCfStatus)377 DLL_PUBLIC DRV_TCF_RET MDrv_CF_Cf_Status(DRV_CF_CF_STATUS *pstCfStatus)
378 {
379 if( !_bTCF_Init ){
380 _TCF_ERR("[%s][%d] TCF is NOT inited\n", __FUNCTION__, __LINE__);
381 return DRV_TCF_FAIL;
382 }
383 MsOS_ObtainMutex(_s32TCFMutexId, MSOS_WAIT_FOREVER);
384
385 HAL_CF_CF_STATUS *_pstCfStatus= (HAL_CF_CF_STATUS *) pstCfStatus;
386
387 HAL_CF_Cf_Status( _pstCfStatus);
388
389 MsOS_ReleaseMutex(_s32TCFMutexId);
390 return DRV_TCF_OK;
391 }
392
MDrv_CF_FeatureVector(DRV_CF_FEATURE_VECTOR * pstCfFeature)393 DLL_PUBLIC DRV_TCF_RET MDrv_CF_FeatureVector(DRV_CF_FEATURE_VECTOR *pstCfFeature)
394 {
395 if( !_bTCF_Init ){
396 _TCF_ERR("[%s][%d] TCF is NOT inited\n", __FUNCTION__, __LINE__);
397 return DRV_TCF_FAIL;
398 }
399 MsOS_ObtainMutex(_s32TCFMutexId, MSOS_WAIT_FOREVER);
400
401 HAL_CF_FEATURE_VECTOR *_pstCfFeature= (HAL_CF_FEATURE_VECTOR *) pstCfFeature;
402
403 HAL_CF_Cf_FeatureVector( _pstCfFeature);
404
405 MsOS_ReleaseMutex(_s32TCFMutexId);
406 return DRV_TCF_OK;
407 }
408
MDrv_CF_Issue_Op(DRV_CF_OPERATION * pCfOperations)409 DLL_PUBLIC DRV_TCF_RET MDrv_CF_Issue_Op(DRV_CF_OPERATION *pCfOperations)
410 {
411 CF_TRANS_STATUS_VALUES eTransStatus = E_CF_TRANS_STATUS_BUSY_INIT;
412 CF_OPERATION_TYPE eOpType = E_CF_OP_TYPE_OP_CWC;
413 MS_U32 u32Cmd = 0;
414 MS_U32 u32WaitCnt = 0;
415 MS_U8 u8Ret = DRV_TCF_OK;
416 MS_U32 u32i = 0;
417
418 if( !_bTCF_Init ){
419 _TCF_ERR("[%s][%d] TCF is NOT inited\n", __FUNCTION__, __LINE__);
420 return DRV_TCF_FAIL;
421 }
422 MsOS_ObtainMutex(_s32TCFMutexId, MSOS_WAIT_FOREVER);
423
424 eTransStatus = HAL_CF_Get_Trans_Status();
425 switch(eTransStatus)
426 {
427 case E_CF_TRANS_STATUS_BUSY_INIT:
428 case E_CF_TRANS_STATUS_BUSY_SETUP:
429 case E_CF_TRANS_STATUS_INPUT: // note: same as vendor
430 case E_CF_TRANS_STATUS_BUSY_OP:
431 case E_CF_TRANS_STATUS_DONE_OK:
432 if( DRV_TCF_OK!=(u8Ret= _MDrv_CF_Ready()) )
433 {
434 _TCF_ERR("[%s][%d] Set CF to E_CF_TRANS_STATUS_READY fail!!\n", __FUNCTION__, __LINE__);
435 goto CF_ISSUE_OP_FINISH;
436 }
437 case E_CF_TRANS_STATUS_READY:
438 #if 1 // patch of K3S HW bug
439 eOpType = (pCfOperations->Op[0]&CF_OP_TYPE_MASK)>>CF_OP_TYPE_POS;
440 _TCF_DBG("[%s] _bActivateCFB = %s\n", __FUNCTION__, _bActivateCFB? "True":"Flase");
441 _TCF_DBG("[%s] Operation Type= %u\n", __FUNCTION__, eOpType);
442 if( _bActivateCFB && (eOpType==E_CF_OP_TYPE_OP_CWC) )
443 {
444 _TCF_DBG("[%s] E_CF_OP_TYPE_OP_CWC => MDrv_CFB_Enable()\n", __FUNCTION__);
445 MDrv_CFB_Enable();
446
447 // Wait reg_cgb_ready
448 while( MDrv_CFB_Is_Ready()!=DRV_TCF_OK )
449 ;
450 }
451 #endif
452
453 for( u32i=0 ; u32i<CF_CMD_WORDS ; u32i++ )
454 {
455 HAL_CF_Write_Input( pCfOperations->Op[u32i]);
456 u32Cmd = HAL_CF_Read_Input();
457 if( u32Cmd!=pCfOperations->Op[u32i] )
458 {
459 _TCF_ERR("[%s][%d] Write cmd fail!!\n", __FUNCTION__, __LINE__);
460 u8Ret = DRV_TCF_FAIL;
461 }
462 }
463
464 #if 1 // patch of K3S HW bug
465 if( _bActivateCFB && (eOpType==E_CF_OP_TYPE_OP_CWC) )
466 {
467 // Wait reg_cfb_done
468 u32WaitCnt = 0;
469 while( (MDrv_CFB_Is_Done()!=DRV_TCF_OK) && (u32WaitCnt<TCF_TIMEOUT_VALUE) )
470 {
471 MsOS_DelayTask(10);
472 u32WaitCnt++;
473 }
474 if( u32WaitCnt>=TCF_TIMEOUT_VALUE )
475 {
476 _TCF_ERR("[%s] CFB timeout!!\n", __FUNCTION__);
477 u8Ret = DRV_TCF_FAIL;
478 }
479
480 _TCF_DBG("[%s] E_CF_OP_TYPE_OP_CWC => MDrv_CFB_Reset()\n", __FUNCTION__);
481 MDrv_CFB_Reset();
482 }
483
484 if( (_bActivateCFB==FALSE) && (eOpType==E_CF_OP_TYPE_OP_CWC) )
485 {
486 _TCF_DBG("[%s] Activate CFB when Next OP_CWC comes()\n", __FUNCTION__);
487 _bActivateCFB = TRUE;
488 }
489 #endif
490 break;
491 default:
492 _TCF_ERR("[%s][%d] CF is busy!!\n", __FUNCTION__, __LINE__);
493 u8Ret = DRV_TCF_FAIL;
494 break;
495 }
496
497 CF_ISSUE_OP_FINISH:
498 MsOS_ReleaseMutex(_s32TCFMutexId);
499 return u8Ret;
500 }
501
MDrv_CF_IsFinished(void)502 DLL_PUBLIC DRV_TCF_RET MDrv_CF_IsFinished(void)
503 {
504 MS_U8 u8Ret = DRV_TCF_OK;
505
506 if( !_bTCF_Init ){
507 _TCF_ERR("[%s][%d] TCF is NOT inited\n", __FUNCTION__, __LINE__);
508 return DRV_TCF_FAIL;
509 }
510 MsOS_ObtainMutex(_s32TCFMutexId, MSOS_WAIT_FOREVER);
511
512 if( HAL_CF_Get_CF_IsFinished()==TRUE )
513 {
514 u8Ret = DRV_TCF_OK;
515 }
516 else
517 {
518 u8Ret = DRV_TCF_FAIL;
519 }
520
521 MsOS_ReleaseMutex(_s32TCFMutexId);
522 return u8Ret;
523 }
524
MDrv_CF_Read_Op_Result(DRV_CF_RESULT * pCfResult)525 DLL_PUBLIC DRV_TCF_RET MDrv_CF_Read_Op_Result(DRV_CF_RESULT *pCfResult)
526 {
527 MS_U32 u32i = 0;
528 MS_U8 u8Ret = DRV_TCF_OK;
529
530 if( !_bTCF_Init ){
531 _TCF_ERR("[%s][%d] TCF is NOT inited\n", __FUNCTION__, __LINE__);
532 return DRV_TCF_FAIL;
533 }
534 MsOS_ObtainMutex(_s32TCFMutexId, MSOS_WAIT_FOREVER);
535
536 memset( pCfResult, 0x00, sizeof(DRV_CF_RESULT));
537 pCfResult->eTransStatus = HAL_CF_Get_Trans_Status();
538 pCfResult->eOperationType = HAL_CF_Get_Operation_Type();
539 pCfResult->u8CwcValid = HAL_CF_Get_CwcValid();
540
541 if( E_CF_TRANS_STATUS_BUSY_OP < pCfResult->eTransStatus ) // E_CF_TRANS_STATUS_DONE_*
542 {
543 for( u32i=0 ; u32i<CF_CWC_WORDS ; u32i++ )
544 {
545 pCfResult->Shv[u32i] = HAL_CF_Read_Output();
546 HAL_CF_Write_Output( 0);
547 }
548 }
549 else
550 {
551 switch(pCfResult->eTransStatus)
552 {
553 case E_CF_TRANS_STATUS_BUSY_INIT:
554 case E_CF_TRANS_STATUS_BUSY_SETUP:
555 case E_CF_TRANS_STATUS_READY:
556 case E_CF_TRANS_STATUS_INPUT:
557 _TCF_ERR("[%s][%d] Invalid state!!\n", __FUNCTION__, __LINE__);
558 u8Ret = DRV_TCF_FAIL;
559 break;
560 default:
561 _TCF_ERR("[%s][%d] Timed out!!\n", __FUNCTION__, __LINE__);
562 u8Ret = DRV_TCF_FAIL;
563 break;
564 }
565 }
566
567 MsOS_ReleaseMutex(_s32TCFMutexId);
568 return u8Ret;
569 }
570
571
572 // CFB
573 //
MDrv_CFB_Init(void)574 DLL_PUBLIC DRV_TCF_RET MDrv_CFB_Init(void)
575 {
576 #ifdef TCF_CFKE
577 _TCF_ERR("[%s][%d] NOT Supported!!\n", __FUNCTION__, __LINE__);
578 return DRV_TCF_FAIL;
579 #else
580 MS_BOOL bRet = DRV_TCF_FAIL;
581
582 if( MDrv_TCF_Init()==DRV_TCF_FAIL )
583 {
584 _TCF_ERR("[%s][%d] MDrv_TCF_Init fail\n", __FUNCTION__, __LINE__);
585 return DRV_TCF_FAIL;
586 }
587 MsOS_ObtainMutex(_s32TCFMutexId, MSOS_WAIT_FOREVER);
588
589 bRet = HAL_CFB_Init();
590
591 MsOS_ReleaseMutex(_s32TCFMutexId);
592 if( bRet!=TRUE ){
593 return DRV_TCF_FAIL;
594 }
595 else{
596 return DRV_TCF_OK;
597 }
598 #endif
599 }
600
MDrv_CFB_Enable(void)601 DLL_PUBLIC DRV_TCF_RET MDrv_CFB_Enable(void)
602 {
603 #ifdef TCF_CFKE
604 _TCF_ERR("[%s][%d] NOT Supported!!\n", __FUNCTION__, __LINE__);
605 return DRV_TCF_FAIL;
606 #else
607 MS_BOOL bRet = DRV_TCF_FAIL;
608
609 if( MDrv_TCF_Init()==DRV_TCF_FAIL )
610 {
611 _TCF_ERR("[%s][%d] MDrv_TCF_Init fail\n", __FUNCTION__, __LINE__);
612 return DRV_TCF_FAIL;
613 }
614
615 bRet = HAL_CFB_Enable();
616
617 if( bRet!=TRUE ){
618 return DRV_TCF_FAIL;
619 }
620 else{
621 return DRV_TCF_OK;
622 }
623 #endif
624 }
625
MDrv_CFB_Reset(void)626 DLL_PUBLIC DRV_TCF_RET MDrv_CFB_Reset(void)
627 {
628 #ifdef TCF_CFKE
629 _TCF_ERR("[%s][%d] NOT Supported!!\n", __FUNCTION__, __LINE__);
630 return DRV_TCF_FAIL;
631 #else
632 MS_BOOL bRet = DRV_TCF_FAIL;
633
634 if( MDrv_TCF_Init()==DRV_TCF_FAIL )
635 {
636 _TCF_ERR("[%s][%d] MDrv_TCF_Init fail\n", __FUNCTION__, __LINE__);
637 return DRV_TCF_FAIL;
638 }
639
640 _bActivateCFB = TRUE;
641 bRet = HAL_CFB_Reset();
642
643 if( bRet!=TRUE ){
644 return DRV_TCF_FAIL;
645 }
646 else{
647 return DRV_TCF_OK;
648 }
649 #endif
650 }
651
MDrv_CFB_Setup(DRV_CFB_CFBCFG * pstCFBCfg)652 DLL_PUBLIC DRV_TCF_RET MDrv_CFB_Setup(DRV_CFB_CFBCFG *pstCFBCfg)
653 {
654 #ifdef TCF_CFKE
655 _TCF_ERR("[%s][%d] NOT Supported!!\n", __FUNCTION__, __LINE__);
656 return DRV_TCF_FAIL;
657 #else
658 HAL_CFB_CWCCFG *_pstCwcCfg = (HAL_CFB_CWCCFG *)&(pstCFBCfg->stCwcCfg);
659
660 if( MDrv_TCF_Init()==DRV_TCF_FAIL )
661 {
662 _TCF_ERR("[%s][%d] MDrv_TCF_Init fail\n", __FUNCTION__, __LINE__);
663 return DRV_TCF_FAIL;
664 }
665 MsOS_ObtainMutex(_s32TCFMutexId, MSOS_WAIT_FOREVER);
666
667 if( (pstCFBCfg->u8UseCase==E_CFB_USE_CASE_3_1_2) || (pstCFBCfg->u8UseCase==E_CFB_USE_CASE_3_5_1) )
668 {
669 _TCF_DBG("[%s]] It's AES_KEY Use_Case!!!\n", __FUNCTION__);
670 _bActivateCFB = FALSE; // obmit CFB_enable when first OP_AES comes
671 }
672
673 HAL_CFB_Set_Use_Case( pstCFBCfg->u8UseCase);
674 HAL_CFB_Set_Otp_Key( pstCFBCfg->u8OtpKeyIdx);
675 HAL_CFB_Set_CACWC_Src( pstCFBCfg->u8CAcwcSrc);
676
677 if( NULL!=pstCFBCfg->CACWC )
678 HAL_CFB_SET_CACWC( pstCFBCfg->CACWC);
679 if( NULL!=pstCFBCfg->EPK )
680 HAL_CFB_SET_EPK( pstCFBCfg->EPK);
681 if( NULL!=pstCFBCfg->EFUV )
682 HAL_CFB_SET_EFUV( pstCFBCfg->EFUV);
683
684 HAL_CFB_Set_Cwc_Cfg( _pstCwcCfg);
685
686 MsOS_ReleaseMutex(_s32TCFMutexId);
687 return DRV_TCF_OK;
688 #endif
689 }
690
MDrv_CFB_Is_Ready(void)691 DLL_PUBLIC DRV_TCF_RET MDrv_CFB_Is_Ready(void)
692 {
693 #ifdef TCF_CFKE
694 _TCF_ERR("[%s][%d] NOT Supported!!\n", __FUNCTION__, __LINE__);
695 return DRV_TCF_FAIL;
696 #else
697 MS_BOOL bRet = DRV_TCF_FAIL;
698
699 if( MDrv_TCF_Init()==DRV_TCF_FAIL )
700 {
701 _TCF_ERR("[%s][%d] MDrv_TCF_Init fail\n", __FUNCTION__, __LINE__);
702 return DRV_TCF_FAIL;
703 }
704
705 bRet = HAL_CFB_Is_Ready();
706
707 if( bRet!=TRUE ){
708 return DRV_TCF_FAIL;
709 }
710 else{
711 return DRV_TCF_OK; // ready
712 }
713 #endif
714 }
715
MDrv_CFB_Is_Done(void)716 DLL_PUBLIC DRV_TCF_RET MDrv_CFB_Is_Done(void)
717 {
718 #ifdef TCF_CFKE
719 _TCF_ERR("[%s][%d] NOT Supported!!\n", __FUNCTION__, __LINE__);
720 return DRV_TCF_FAIL;
721 #else
722 MS_BOOL bRet = DRV_TCF_FAIL;
723
724 if( MDrv_TCF_Init()==DRV_TCF_FAIL )
725 {
726 _TCF_ERR("[%s][%d] MDrv_TCF_Init fail\n", __FUNCTION__, __LINE__);
727 return DRV_TCF_FAIL;
728 }
729
730 bRet = HAL_CFB_Is_Done();
731
732 if( bRet!=TRUE ){
733 return DRV_TCF_FAIL;
734 }
735 else{
736 return DRV_TCF_OK; // done
737 }
738 #endif
739 }
740
MDrv_CFB_DBG_KT_Response(void)741 DLL_PUBLIC void MDrv_CFB_DBG_KT_Response(void)
742 {
743 #ifdef TCF_CFKE
744 _TCF_ERR("[%s][%d] NOT Supported!!\n", __FUNCTION__, __LINE__);
745 #else
746 HAL_CFB_DBG_KT_Response();
747 #endif
748 }
749
MDrv_CFB_DBG_CFB_FSM(void)750 DLL_PUBLIC MS_U8 MDrv_CFB_DBG_CFB_FSM(void)
751 {
752 #ifdef TCF_CFKE
753 _TCF_ERR("[%s][%d] NOT Supported!!\n", __FUNCTION__, __LINE__);
754 return 0;
755 #else
756 return HAL_CFB_DBG_CFB_FSM();
757 #endif
758 }
759
760
761 // CFKE
762 //
MDrv_CFKE_Cmd_Exe(DRV_CFKE_OPERATION * pCfkeOp)763 DLL_PUBLIC DRV_TCF_RET MDrv_CFKE_Cmd_Exe(DRV_CFKE_OPERATION *pCfkeOp)
764 {
765 #ifdef TCF_CFKE
766 CFKE_TRANS_STATUS_VALUES eTransStatus = E_CFKE_TRANS_STATUS_BUSY_INIT;
767 MS_U32 u32Cmd = 0;
768 // MS_U8 uDesireStatus = CFKE_STATUS_DONE;
769 // MS_U8 u8i = 0;
770 MS_U8 u8Ret = DRV_TCF_OK;
771
772
773 if( !_bTCF_Init ){
774 _TCF_ERR("[%s][%d] TCF is NOT inited\n", __FUNCTION__, __LINE__);
775 return DRV_TCF_FAIL;
776 }
777 MsOS_ObtainMutex(_s32TCFMutexId, MSOS_WAIT_FOREVER);
778
779
780 // check CFKE_STATUS
781 eTransStatus = HAL_CFKE_Get_OperationStatus();
782 switch(eTransStatus){
783 case E_CFKE_TRANS_STATUS_BUSY_INIT:
784 case E_CFKE_TRANS_STATUS_DONE_ERROR:
785 case E_CFKE_TRANS_STATUS_DONE_TEST:
786 if( DRV_TCF_OK!=(u8Ret= _MDrv_CFKE_Ready()) ){
787 _TCF_ERR("[%s][%d] Set CF to E_CF_TRANS_STATUS_READY fail!!\n", __FUNCTION__, __LINE__);
788 goto CFKE_CMD_EXE_FINISH;
789 }
790 case E_CFKE_TRANS_STATUS_READY:
791 case E_CFKE_TRANS_STATUS_DONE_OK:
792 // write the input data based on operation request
793 switch(pCfkeOp->eOpType){
794 case E_CFKE_OP_DCF:
795 _TCF_DBG("[%s][%d] Direct CF operation.\n", __FUNCTION__, __LINE__);
796
797 //~ Conditions to check ~//
798 // i) operation type field is valid
799 // ii) src1 and src2 should be null. dest should not be null.
800 if( E_CFKE_OP_DCF!=pCfkeOp->eOpType){
801 _TCF_ERR("[%s][%d] <OP_DCF> Operation type requested is not correct\n", __FUNCTION__, __LINE__);
802 u8Ret = DRV_TCF_INVALID_INPUT;
803 goto CFKE_CMD_EXE_FINISH;
804 }
805 if( E_CFKE_SRC_NULL!=pCfkeOp->eOpSrc1.eSrcType || E_CFKE_SRC_NULL!=pCfkeOp->eOpSrc2.eSrcType || E_CFKE_DEST_NULL==pCfkeOp->eOpDest ){
806 _TCF_ERR("[%s][%d] <OP_DCF> SRC1 & SRC2 values should be NULL, DEST should not be NULL.\n", __FUNCTION__, __LINE__);
807 u8Ret = DRV_TCF_INVALID_INPUT;
808 goto CFKE_CMD_EXE_FINISH;
809 }
810
811 //~ Populate the command data ~//
812 u32Cmd = 0;
813 u32Cmd |= pCfkeOp->eOpType << CFKE_CMD_OP_POS;
814 u32Cmd |= pCfkeOp->eOpDest << CFKE_CMD_DEST_POS;
815 u32Cmd |= pCfkeOp->eOpSrc1.eSrcType << CFKE_CMD_SRC1_POS;
816 u32Cmd |= pCfkeOp->eOpSrc2.eSrcType << CFKE_CMD_SRC2_POS;
817 break;
818
819 case E_CFKE_OP_XOR:
820 _TCF_DBG("[%s][%d] XOR operation.\n", __FUNCTION__, __LINE__);
821
822 //~ Conditions to check ~//
823 // i) operation type field is valid
824 // ii) src1, src2 and dest are not null
825 if( E_CFKE_OP_XOR!=pCfkeOp->eOpType){
826 _TCF_ERR("[%s][%d] <OP_XOR> Operation type requested is not correct\n", __FUNCTION__, __LINE__);
827 u8Ret = DRV_TCF_INVALID_INPUT;
828 goto CFKE_CMD_EXE_FINISH;
829 }
830 if( E_CFKE_SRC_NULL==pCfkeOp->eOpSrc1.eSrcType || E_CFKE_SRC_NULL==pCfkeOp->eOpSrc2.eSrcType || E_CFKE_DEST_NULL==pCfkeOp->eOpDest ){
831 _TCF_ERR("[%s][%d] <OP_XOR> SRC1, SRC2 and DEST values should not be NULL.\n", __FUNCTION__, __LINE__);
832 u8Ret = DRV_TCF_INVALID_INPUT;
833 goto CFKE_CMD_EXE_FINISH;
834 }
835
836 //~ Write the data to the key registers for both sources ~//
837 // Src1
838 switch(pCfkeOp->eOpSrc1.eSrcType){
839 case E_CFKE_SRC_CF:
840 break;
841 case E_CFKE_SRC_SLOTAL:
842 case E_CFKE_SRC_SLOTBL:
843 case E_CFKE_SRC_SLOTCL:
844 case E_CFKE_SRC_SLOTDL:
845 pCfkeOp->eOpSrc1.eSrcType = (pCfkeOp->eOpSrc1.eSrcType) - (E_CFKE_SRC_SLOTAL-E_CFKE_SRC_SLOTA);
846 _MDrv_CFKE_WriteSlots( (DRV_CFKE_SOURCE*)&pCfkeOp->eOpSrc1);
847 break;
848 case E_CFKE_SRC_SLOTA:
849 case E_CFKE_SRC_SLOTB:
850 case E_CFKE_SRC_SLOTC:
851 case E_CFKE_SRC_SLOTD:
852 // Don't load the key slots. Use previously loaded values as sources.
853 break;
854 default:
855 _TCF_ERR("[%s][%d] <OP_XOR> Invalid Src1 type requested!\n", __FUNCTION__, __LINE__);
856 u8Ret = DRV_TCF_INVALID_INPUT;
857 break;
858 }
859
860 // Do the same for Src2
861 switch(pCfkeOp->eOpSrc2.eSrcType){
862 case E_CFKE_SRC_CF:
863 break;
864 case E_CFKE_SRC_SLOTAL:
865 case E_CFKE_SRC_SLOTBL:
866 case E_CFKE_SRC_SLOTCL:
867 case E_CFKE_SRC_SLOTDL:
868 pCfkeOp->eOpSrc2.eSrcType = (pCfkeOp->eOpSrc2.eSrcType) - (E_CFKE_SRC_SLOTAL-E_CFKE_SRC_SLOTA);
869 _MDrv_CFKE_WriteSlots( (DRV_CFKE_SOURCE*)&pCfkeOp->eOpSrc2);
870 break;
871 case E_CFKE_SRC_SLOTA:
872 case E_CFKE_SRC_SLOTB:
873 case E_CFKE_SRC_SLOTC:
874 case E_CFKE_SRC_SLOTD:
875 // Don't load the key slots. Use previously loaded values as sources.
876 break;
877 default:
878 _TCF_ERR("[%s][%d] <OP_XOR> Invalid Src2 type requested!\n", __FUNCTION__, __LINE__);
879 u8Ret = DRV_TCF_INVALID_INPUT;
880 break;
881 }
882
883 //~ Populate the command data ~//
884 u32Cmd = 0;
885 u32Cmd |= pCfkeOp->eOpType << CFKE_CMD_OP_POS;
886 u32Cmd |= pCfkeOp->eOpDest << CFKE_CMD_DEST_POS;
887 u32Cmd |= pCfkeOp->eOpSrc1.eSrcType << CFKE_CMD_SRC1_POS;
888 u32Cmd |= pCfkeOp->eOpSrc2.eSrcType << CFKE_CMD_SRC2_POS;
889 break;
890
891 case E_CFKE_OP_AES:
892 _TCF_DBG("[%s][%d] AES operation.\n", __FUNCTION__, __LINE__);
893
894 //~ Conditions to check ~//
895 // i) operation type field is valid
896 // ii) src1, src2 and dest are not null
897 if( E_CFKE_OP_AES!=pCfkeOp->eOpType){
898 _TCF_ERR("[%s][%d] <OP_AES> Operation type requested is not correct\n", __FUNCTION__, __LINE__);
899 u8Ret = DRV_TCF_INVALID_INPUT;
900 goto CFKE_CMD_EXE_FINISH;
901 }
902 if( E_CFKE_SRC_NULL==pCfkeOp->eOpSrc1.eSrcType || E_CFKE_SRC_NULL==pCfkeOp->eOpSrc2.eSrcType || E_CFKE_DEST_NULL==pCfkeOp->eOpDest ){
903 _TCF_ERR("[%s][%d] <OP_AES> SRC1, SRC2 and DEST values should not be NULL.\n", __FUNCTION__, __LINE__);
904 u8Ret = DRV_TCF_INVALID_INPUT;
905 goto CFKE_CMD_EXE_FINISH;
906 }
907
908 //~ Write the data to the key registers for both sources ~//
909 // Src1
910 switch(pCfkeOp->eOpSrc1.eSrcType){
911 case E_CFKE_SRC_CF:
912 break;
913 case E_CFKE_SRC_SLOTAL:
914 case E_CFKE_SRC_SLOTBL:
915 case E_CFKE_SRC_SLOTCL:
916 case E_CFKE_SRC_SLOTDL:
917 pCfkeOp->eOpSrc1.eSrcType = (pCfkeOp->eOpSrc1.eSrcType) - (E_CFKE_SRC_SLOTAL-E_CFKE_SRC_SLOTA);
918 _MDrv_CFKE_WriteSlots( (DRV_CFKE_SOURCE*)&pCfkeOp->eOpSrc1);
919 break;
920 case E_CFKE_SRC_SLOTA:
921 case E_CFKE_SRC_SLOTB:
922 case E_CFKE_SRC_SLOTC:
923 case E_CFKE_SRC_SLOTD:
924 // Don't load the key slots. Use previously loaded values as sources.
925 break;
926 default:
927 _TCF_ERR("[%s][%d] <OP_AES> Invalid Src1 type requested!\n", __FUNCTION__, __LINE__);
928 u8Ret = DRV_TCF_INVALID_INPUT;
929 break;
930 }
931
932 // Do the same for Src2
933 switch(pCfkeOp->eOpSrc2.eSrcType){
934 case E_CFKE_SRC_CF:
935 break;
936 case E_CFKE_SRC_SLOTAL:
937 case E_CFKE_SRC_SLOTBL:
938 case E_CFKE_SRC_SLOTCL:
939 case E_CFKE_SRC_SLOTDL:
940 pCfkeOp->eOpSrc2.eSrcType = (pCfkeOp->eOpSrc2.eSrcType) - (E_CFKE_SRC_SLOTAL-E_CFKE_SRC_SLOTA);
941 _MDrv_CFKE_WriteSlots( (DRV_CFKE_SOURCE*)&pCfkeOp->eOpSrc2);
942 break;
943 case E_CFKE_SRC_SLOTA:
944 case E_CFKE_SRC_SLOTB:
945 case E_CFKE_SRC_SLOTC:
946 case E_CFKE_SRC_SLOTD:
947 // Don't load the key slots. Use previously loaded values as sources.
948 break;
949 default:
950 _TCF_ERR("[%s][%d] <OP_AES> Invalid Src2 type requested!\n", __FUNCTION__, __LINE__);
951 u8Ret = DRV_TCF_INVALID_INPUT;
952 break;
953 }
954
955 //~ Populate the command data ~//
956 u32Cmd = 0;
957 u32Cmd |= pCfkeOp->eOpType << CFKE_CMD_OP_POS;
958 u32Cmd |= pCfkeOp->eOpDest << CFKE_CMD_DEST_POS;
959 u32Cmd |= pCfkeOp->eOpSrc1.eSrcType << CFKE_CMD_SRC1_POS;
960 u32Cmd |= pCfkeOp->eOpSrc2.eSrcType << CFKE_CMD_SRC2_POS;
961 break;
962
963 case E_CFKE_OP_UNW:
964 _TCF_DBG("[%s][%d] UNW operation.\n", __FUNCTION__, __LINE__);
965
966 //~ Conditions to check ~//
967 // i) operation type field is valid
968 // ii) src1, src2 and dest are not null
969 if( E_CFKE_OP_UNW!=pCfkeOp->eOpType){
970 _TCF_ERR("[%s][%d] <OP_UNW> Operation type requested is not correct\n", __FUNCTION__, __LINE__);
971 u8Ret = DRV_TCF_INVALID_INPUT;
972 goto CFKE_CMD_EXE_FINISH;
973 }
974 if( E_CFKE_SRC_NULL==pCfkeOp->eOpSrc1.eSrcType || E_CFKE_SRC_NULL==pCfkeOp->eOpSrc2.eSrcType || E_CFKE_DEST_NULL==pCfkeOp->eOpDest ){
975 _TCF_ERR("[%s][%d] <OP_UNW> SRC1, SRC2 and DEST values should not be NULL.\n", __FUNCTION__, __LINE__);
976 u8Ret = DRV_TCF_INVALID_INPUT;
977 goto CFKE_CMD_EXE_FINISH;
978 }
979
980 //~ Write the data to the key registers for both sources ~//
981 // Src1
982 switch(pCfkeOp->eOpSrc1.eSrcType){
983 case E_CFKE_SRC_CF:
984 break;
985 case E_CFKE_SRC_SLOTAL:
986 case E_CFKE_SRC_SLOTBL:
987 case E_CFKE_SRC_SLOTCL:
988 case E_CFKE_SRC_SLOTDL:
989 pCfkeOp->eOpSrc1.eSrcType = (pCfkeOp->eOpSrc1.eSrcType) - (E_CFKE_SRC_SLOTAL-E_CFKE_SRC_SLOTA);
990 _MDrv_CFKE_WriteSlots( (DRV_CFKE_SOURCE*)&pCfkeOp->eOpSrc1);
991 break;
992 case E_CFKE_SRC_SLOTA:
993 case E_CFKE_SRC_SLOTB:
994 case E_CFKE_SRC_SLOTC:
995 case E_CFKE_SRC_SLOTD:
996 // Don't load the key slots. Use previously loaded values as sources.
997 break;
998 default:
999 _TCF_ERR("[%s][%d] <OP_UNW> Invalid Src1 type requested!\n", __FUNCTION__, __LINE__);
1000 u8Ret = DRV_TCF_INVALID_INPUT;
1001 break;
1002 }
1003
1004 // Do the same for Src2
1005 switch(pCfkeOp->eOpSrc2.eSrcType){
1006 case E_CFKE_SRC_CF:
1007 break;
1008 case E_CFKE_SRC_SLOTAL:
1009 case E_CFKE_SRC_SLOTBL:
1010 case E_CFKE_SRC_SLOTCL:
1011 case E_CFKE_SRC_SLOTDL:
1012 pCfkeOp->eOpSrc2.eSrcType = (pCfkeOp->eOpSrc2.eSrcType) - (E_CFKE_SRC_SLOTAL-E_CFKE_SRC_SLOTA);
1013 _MDrv_CFKE_WriteSlots( (DRV_CFKE_SOURCE*)&pCfkeOp->eOpSrc2);
1014 break;
1015 case E_CFKE_SRC_SLOTA:
1016 case E_CFKE_SRC_SLOTB:
1017 case E_CFKE_SRC_SLOTC:
1018 case E_CFKE_SRC_SLOTD:
1019 // Don't load the key slots. Use previously loaded values as sources.
1020 break;
1021 default:
1022 _TCF_ERR("[%s][%d] <OP_UNW> Invalid Src2 type requested!\n", __FUNCTION__, __LINE__);
1023 u8Ret = DRV_TCF_INVALID_INPUT;
1024 break;
1025 }
1026
1027 //~ Write unwrap data to the registers ~//
1028 // (unwrap data) Write the value to the unwrap path register
1029 HAL_CFKE_Write_UnwPath( pCfkeOp->UnwData.u32UnwPathData);
1030 // Read back the data to verify whether the data is written successfully
1031 if( pCfkeOp->UnwData.u32UnwPathData!=HAL_CFKE_Read_UnwPath() ){
1032 _TCF_ERR("[%s][%d] <OP_UNW> CFKE Write UNW Path Register Error!!\n", __FUNCTION__, __LINE__);
1033 u8Ret = DRV_TCF_FAIL;
1034 goto CFKE_CMD_EXE_FINISH;
1035 }
1036
1037 // Write the value [31:0] to the validator register
1038 HAL_CFKE_Write_Validator0( pCfkeOp->UnwData.pu832ValidatorData[0]);
1039 if( pCfkeOp->UnwData.pu832ValidatorData[0]!=HAL_CFKE_Read_Validator0() ){
1040 _TCF_ERR("[%s][%d] <OP_UNW> CFKE Write Validator 0 Register Error!!\n", __FUNCTION__, __LINE__);
1041 u8Ret = DRV_TCF_FAIL;
1042 goto CFKE_CMD_EXE_FINISH;
1043 }
1044
1045 // Write the value [63:32]to the validator1 register
1046 HAL_CFKE_Write_Validator1( pCfkeOp->UnwData.pu832ValidatorData[1]);
1047 if( pCfkeOp->UnwData.pu832ValidatorData[1]!=HAL_CFKE_Read_Validator1() ){
1048 _TCF_ERR("[%s][%d] <OP_UNW> CFKE Write Validator 1 Register Error!!\n", __FUNCTION__, __LINE__);
1049 u8Ret = DRV_TCF_FAIL;
1050 goto CFKE_CMD_EXE_FINISH;
1051 }
1052
1053 //~ Populate the command data ~//
1054 u32Cmd = 0;
1055 u32Cmd |= pCfkeOp->eOpType << CFKE_CMD_OP_POS;
1056 u32Cmd |= pCfkeOp->eOpDest << CFKE_CMD_DEST_POS;
1057 u32Cmd |= pCfkeOp->eOpSrc1.eSrcType << CFKE_CMD_SRC1_POS;
1058 u32Cmd |= pCfkeOp->eOpSrc2.eSrcType << CFKE_CMD_SRC2_POS;
1059 break;
1060
1061 case E_CFKE_OP_HWDECM:
1062 _TCF_DBG("[%s][%d] HWDECM operation.\n", __FUNCTION__, __LINE__);
1063
1064 //~ Conditions to check ~//
1065 // i) operation type field is valid
1066 // ii) src1 should not be null. dest and src2 must be null
1067 if( E_CFKE_OP_HWDECM!=pCfkeOp->eOpType){
1068 _TCF_ERR("[%s][%d] <OP_HWDECM> Operation type requested is not correct\n", __FUNCTION__, __LINE__);
1069 u8Ret = DRV_TCF_INVALID_INPUT;
1070 goto CFKE_CMD_EXE_FINISH;
1071 }
1072 if( E_CFKE_SRC_NULL==pCfkeOp->eOpSrc1.eSrcType || E_CFKE_SRC_NULL!=pCfkeOp->eOpSrc2.eSrcType || E_CFKE_DEST_NULL!=pCfkeOp->eOpDest ){
1073 _TCF_ERR("[%s][%d] <OP_HWDECM> SRC1/SRC2/Dest values are not valid.\n", __FUNCTION__, __LINE__);
1074 u8Ret = DRV_TCF_INVALID_INPUT;
1075 goto CFKE_CMD_EXE_FINISH;
1076 }
1077
1078 // Write the data to the key registers for src1
1079 switch(pCfkeOp->eOpSrc1.eSrcType){
1080 case E_CFKE_SRC_CF:
1081 break;
1082 case E_CFKE_SRC_SLOTAL:
1083 case E_CFKE_SRC_SLOTBL:
1084 case E_CFKE_SRC_SLOTCL:
1085 case E_CFKE_SRC_SLOTDL:
1086 pCfkeOp->eOpSrc1.eSrcType = (pCfkeOp->eOpSrc1.eSrcType) - (E_CFKE_SRC_SLOTAL-E_CFKE_SRC_SLOTA);
1087 _MDrv_CFKE_WriteSlots( (DRV_CFKE_SOURCE*)&pCfkeOp->eOpSrc1);
1088 break;
1089 case E_CFKE_SRC_SLOTA:
1090 case E_CFKE_SRC_SLOTB:
1091 case E_CFKE_SRC_SLOTC:
1092 case E_CFKE_SRC_SLOTD:
1093 // Don't load the key slots. Use previously loaded values as sources.
1094 break;
1095 default:
1096 _TCF_ERR("[%s][%d] <OP_HWDECM> Invalid Src1 type requested!\n", __FUNCTION__, __LINE__);
1097 u8Ret = DRV_TCF_INVALID_INPUT;
1098 break;
1099 }
1100
1101 //~ Populate the command data ~//
1102 u32Cmd = 0;
1103 u32Cmd |= pCfkeOp->eOpType << CFKE_CMD_OP_POS;
1104 u32Cmd |= pCfkeOp->eOpDest << CFKE_CMD_DEST_POS;
1105 u32Cmd |= pCfkeOp->eOpSrc1.eSrcType << CFKE_CMD_SRC1_POS;
1106 u32Cmd |= pCfkeOp->eOpSrc2.eSrcType << CFKE_CMD_SRC2_POS;
1107 break;
1108
1109 case E_CFKE_OP_TEST:
1110 _TCF_DBG("[%s][%d] TEST operation.\n", __FUNCTION__, __LINE__);
1111
1112 //~ Conditions to check ~//
1113 // i) operation type field is valid
1114 // ii) src1 src2 and dest must be null
1115 if( E_CFKE_OP_TEST!=pCfkeOp->eOpType){
1116 _TCF_ERR("[%s][%d] <OP_TEST> Operation type requested is not correct\n", __FUNCTION__, __LINE__);
1117 u8Ret = DRV_TCF_INVALID_INPUT;
1118 goto CFKE_CMD_EXE_FINISH;
1119 }
1120 if( E_CFKE_SRC_NULL!=pCfkeOp->eOpSrc1.eSrcType || E_CFKE_SRC_NULL!=pCfkeOp->eOpSrc2.eSrcType || E_CFKE_DEST_NULL!=pCfkeOp->eOpDest ){
1121 _TCF_ERR("[%s][%d] <OP_TEST> SRC1/SRC2/Dest values should be NULL.\n", __FUNCTION__, __LINE__);
1122 u8Ret = DRV_TCF_INVALID_INPUT;
1123 goto CFKE_CMD_EXE_FINISH;
1124 }
1125
1126 //~ Populate the command data ~//
1127 u32Cmd = 0;
1128 u32Cmd |= pCfkeOp->eOpType << CFKE_CMD_OP_POS;
1129 u32Cmd |= pCfkeOp->eOpDest << CFKE_CMD_DEST_POS;
1130 u32Cmd |= pCfkeOp->eOpSrc1.eSrcType << CFKE_CMD_SRC1_POS;
1131 u32Cmd |= pCfkeOp->eOpSrc2.eSrcType << CFKE_CMD_SRC2_POS;
1132 break;
1133
1134 case E_CFKE_OP_CLRKE:
1135 _TCF_DBG("[%s][%d] CLRKE operation.\n", __FUNCTION__, __LINE__);
1136
1137 //~ Conditions to check ~//
1138 // i) operation type field is valid
1139 // ii) src1 src2 and dest are ignored
1140 if( E_CFKE_OP_CLRKE!=pCfkeOp->eOpType){
1141 _TCF_ERR("[%s][%d] <OP_CLRKE> Operation type requested is not correct\n", __FUNCTION__, __LINE__);
1142 u8Ret = DRV_TCF_INVALID_INPUT;
1143 goto CFKE_CMD_EXE_FINISH;
1144 }
1145
1146 //~ Populate the command data ~//
1147 u32Cmd = 0;
1148 u32Cmd |= pCfkeOp->eOpType << CFKE_CMD_OP_POS;
1149 u32Cmd |= pCfkeOp->eOpDest << CFKE_CMD_DEST_POS;
1150 break;
1151
1152 default: // default of 'switch(pCfkeOp->eOpType)'
1153 _TCF_ERR("[%s][%d] Invalid operation type requested!!\n", __FUNCTION__, __LINE__);
1154 u8Ret = DRV_TCF_INVALID_INPUT;
1155 break;
1156 }// end of 'switch(pCfkeOp->eOpType)'
1157
1158
1159 // Write the command data to the command register, Read back the data to verify whether the command is written successfully
1160 HAL_CFKE_Write_Command( u32Cmd);
1161 if( u32Cmd!=HAL_CFKE_Read_Command() ){
1162 _TCF_ERR("[%s][%d] CFKE Write Command Error!!\n", __FUNCTION__, __LINE__);
1163 u8Ret = DRV_TCF_FAIL;
1164 goto CFKE_CMD_EXE_FINISH;
1165 }
1166 _TCF_DBG("[%s][%d] CFKE Write Command OK-- 0x%08lx\n\n", __FUNCTION__, __LINE__, u32Cmd);
1167 break;
1168
1169 default: // default of 'switch(eTransStatus)'
1170 _TCF_ERR("[%s][%d] Busy..\n", __FUNCTION__, __LINE__);
1171 u8Ret = DRV_TCF_BUSY;
1172 break;
1173 }// end of 'switch(eTransStatus)'
1174
1175
1176 CFKE_CMD_EXE_FINISH:
1177 MsOS_ReleaseMutex(_s32TCFMutexId);
1178 return u8Ret;
1179 #else
1180 _TCF_ERR("[%s][%d] NOT Supported!!\n", __FUNCTION__, __LINE__);
1181 return DRV_TCF_FAIL;
1182 #endif
1183 }
1184
MDrv_CFKE_IsDone(CFKE_ERROR_CODE * eCfkeErr)1185 DLL_PUBLIC DRV_TCF_RET MDrv_CFKE_IsDone(CFKE_ERROR_CODE *eCfkeErr)
1186 {
1187 #ifdef TCF_CFKE
1188 CFKE_TRANS_STATUS_VALUES eTransStatus = E_CFKE_TRANS_STATUS_BUSY_INIT;
1189 MS_U8 u8Ret = DRV_TCF_OK;
1190
1191 if( !_bTCF_Init ){
1192 _TCF_ERR("[%s][%d] TCF is NOT inited\n", __FUNCTION__, __LINE__);
1193 return DRV_TCF_FAIL;
1194 }
1195 MsOS_ObtainMutex(_s32TCFMutexId, MSOS_WAIT_FOREVER);
1196
1197 if( CFKE_STATUS_DONE&(eTransStatus= HAL_CFKE_Get_OperationStatus()) ){
1198 *eCfkeErr = HAL_CFKE_Get_ErrorCode();
1199 if( *eCfkeErr ){
1200 _TCF_ERR("[%s] CFKE Error!! (ErrorCode= 0x%x)\n", __FUNCTION__, *eCfkeErr);
1201 }
1202 u8Ret = DRV_TCF_OK;
1203 }
1204 else{
1205 u8Ret = DRV_TCF_FAIL;
1206 }
1207
1208 MsOS_ReleaseMutex(_s32TCFMutexId);
1209 return u8Ret;
1210 #else
1211 _TCF_ERR("[%s][%d] NOT Supported!!\n", __FUNCTION__, __LINE__);
1212 return DRV_TCF_FAIL;
1213 #endif
1214 }
1215
MDrv_CFKE_IsReady(void)1216 DLL_PUBLIC DRV_TCF_RET MDrv_CFKE_IsReady(void)
1217 {
1218 #ifdef TCF_CFKE
1219 MS_U8 u8Ret = DRV_TCF_OK;
1220
1221 if( !_bTCF_Init ){
1222 _TCF_ERR("[%s][%d] TCF is NOT inited\n", __FUNCTION__, __LINE__);
1223 return DRV_TCF_FAIL;
1224 }
1225 MsOS_ObtainMutex(_s32TCFMutexId, MSOS_WAIT_FOREVER);
1226
1227 if( E_CFKE_TRANS_STATUS_READY==HAL_CFKE_Get_OperationStatus() ){
1228 u8Ret = DRV_TCF_OK;
1229 }
1230 else{
1231 u8Ret = DRV_TCF_FAIL;
1232 }
1233
1234 MsOS_ReleaseMutex(_s32TCFMutexId);
1235 return u8Ret;
1236 #else
1237 _TCF_ERR("[%s][%d] NOT Supported!!\n", __FUNCTION__, __LINE__);
1238 return DRV_TCF_FAIL;
1239 #endif
1240 }
1241
MDrv_CFKE_UserHash_Setup(DRV_CFKE_USER_HASH_DATA * pUserHash)1242 DLL_PUBLIC DRV_TCF_RET MDrv_CFKE_UserHash_Setup(DRV_CFKE_USER_HASH_DATA *pUserHash)
1243 {
1244 #ifdef TCF_CFKE
1245 MS_U8 u8i = 0;
1246
1247 if( !_bTCF_Init ){
1248 _TCF_ERR("[%s][%d] TCF is NOT inited\n", __FUNCTION__, __LINE__);
1249 return DRV_TCF_FAIL;
1250 }
1251 MsOS_ObtainMutex(_s32TCFMutexId, MSOS_WAIT_FOREVER);
1252
1253 // Write the value to the user hash register
1254 for( u8i=0 ; u8i<CFKE_INPUT_WORDS ; u8i++ ){
1255 HAL_CFKE_Write_UserHash( pUserHash->pu32UsrHashData[u8i]);
1256 }
1257
1258 MsOS_ReleaseMutex(_s32TCFMutexId);
1259
1260 return DRV_TCF_OK;
1261 #else
1262 _TCF_ERR("[%s][%d] NOT Supported!!\n", __FUNCTION__, __LINE__);
1263 return DRV_TCF_FAIL;
1264 #endif
1265 }
1266
1267 // CRIKL
1268 //
MDrv_CRIKL_Mirror(CRIKL_MIRROR_MEM eCandidate)1269 DLL_PUBLIC MS_U32 MDrv_CRIKL_Mirror(CRIKL_MIRROR_MEM eCandidate)
1270 {
1271 #ifdef TCF_CFKE
1272 MS_U32 u32Value = 0;
1273
1274 switch(eCandidate){
1275 case E_CRIKL_MIRROR_CF_STATUS:
1276 u32Value = HAL_CRIKL_Read_CfStatus();
1277 break;
1278 case E_CRIKL_MIRROR_CFKE_STATUS:
1279 u32Value = HAL_CRIKL_Read_CfkeStatus();
1280 break;
1281 case E_CRIKL_MIRROR_CF_PLATFORM:
1282 u32Value = HAL_CRIKL_Read_CfPlatform();
1283 break;
1284 case E_CRIKL_MIRROR_CF_FEATURE:
1285 u32Value = HAL_CRIKL_Read_CfFeature();
1286 break;
1287 default:
1288 _TCF_ERR("[%s][%d] Invalid Mirror Member\n", __FUNCTION__, __LINE__);
1289 break;
1290 }
1291
1292 return u32Value;
1293 #else
1294 _TCF_ERR("[%s][%d] NOT Supported!!\n", __FUNCTION__, __LINE__);
1295 return 0;
1296 #endif
1297 }
1298
MDrv_CRIKL_Set_KeyConfig(DRV_CRIKL_KEY_CONFIG * stKeyCfg)1299 DLL_PUBLIC DRV_TCF_RET MDrv_CRIKL_Set_KeyConfig(DRV_CRIKL_KEY_CONFIG *stKeyCfg)
1300 {
1301 #ifdef TCF_CFKE
1302 MS_BOOL _bDscmbKey = stKeyCfg->bDscmbKey;
1303
1304
1305 /// kt_index | ks_index
1306 if(_bDscmbKey){
1307 HAL_CRIKL_Set_KTIndex( stKeyCfg->eScmbCtl, stKeyCfg->u8DscmbId);
1308 }
1309 else{
1310 HAL_CRIKL_Set_KSIndex( stKeyCfg->u8KeySlotIdx);
1311 }
1312
1313 /// kt_para | ks_para
1314 HAL_CRIKL_Reset_KeyPara();
1315
1316 // High_HalfWord
1317 HAL_CRIKL_Setup_VendorNo( _bDscmbKey, stKeyCfg->u8VendorNo);
1318 HAL_CRIKL_Setup_VendorAtt( _bDscmbKey, stKeyCfg->u16VendorAtt);
1319
1320 // 2nd_HalfWord
1321 HAL_CRIKL_Setup_OutputAllowed( _bDscmbKey, stKeyCfg->u8OutputAllowed);
1322 HAL_CRIKL_Setup_bMultiEng( _bDscmbKey, stKeyCfg->bMultiEng);
1323 HAL_CRIKL_Setup_bLsb64( _bDscmbKey, stKeyCfg->bLsb64);
1324 HAL_CRIKL_Setup_KeySize( _bDscmbKey, stKeyCfg->eKeySize);
1325
1326 // 3rd_HalfWord
1327 HAL_CRIKL_Setup_KeyEngine( _bDscmbKey, stKeyCfg->u8KlEng);
1328 HAL_CRIKL_Setup_Drop( _bDscmbKey, stKeyCfg->u8Drop);
1329 HAL_CRIKL_Setup_Cnt( _bDscmbKey, stKeyCfg->u8Cnt);
1330
1331 // Low_HalfWord
1332 HAL_CRIKL_Setup_KeyDest( _bDscmbKey, stKeyCfg->u8KlDest);
1333 HAL_CRIKL_Setup_OpType( _bDscmbKey, stKeyCfg->eOpSel);
1334 if(_bDscmbKey){
1335 HAL_CRIKL_Setup_KteSel( _bDscmbKey, stKeyCfg->eKteSel);
1336 }
1337 HAL_CRIKL_Setup_bLock( _bDscmbKey, stKeyCfg->bLock);
1338 HAL_CRIKL_Setup_bParaValid( _bDscmbKey, stKeyCfg->bParaVld);
1339 HAL_CRIKL_Setup_bKlEn( _bDscmbKey, stKeyCfg->bKlEn);
1340
1341 HAL_CRIKL_Write_KeyPara( _bDscmbKey);
1342
1343 return DRV_TCF_OK;
1344 #else
1345 _TCF_ERR("[%s][%d] NOT Supported!!\n", __FUNCTION__, __LINE__);
1346 return DRV_TCF_FAIL;
1347 #endif
1348 }
1349
1350