1
2
3 #include "MsCommon.h"
4
5 #ifdef MSOS_TYPE_LINUX
6 #include "string.h"
7 #endif
8
9
10 #include "asmCPU.h"
11 #include "regNDSRASP.h"
12 #include "halNDSRASP.h"
13 #include "drvNDSRASP.h"
14 #include "XtvTypes.h"
15 #include "ndstypes.h"
16 #include "drvMMIO.h"
17 #include "drvEMMFlt.h"
18 #include "halEMMflt.h"
19 //--------------------------------------------------------------------------------------------------
20 // Debug Macro
21 //--------------------------------------------------------------------------------------------------
22 static MS_U32 _g32RASPDrvDbgLv = RASP_DBGLV_DEBUG;
23
24 #define DRVRASP_DBG(lv, x, args...) if (lv <= _g32RASPDrvDbgLv ) \
25 { printf("%s, ",__FUNCTION__); \
26 printf(x, ##args); }
27
28 //------------------------------------------------------------------------//
29 // Macro Definition
30 //------------------------------------------------------------------------//
31
32 #define RASP_INT_EVENT_ALL (RASP_INT_EFRAME_RD_OVF | RASP_INT_EFRAME_WT_OVF| \
33 RASP_INT_STR2MIU | RASP_INT_PAYLD2MIU | RASP_INT_ECM2MIU|\
34 RASP_INT_TIME_WATER_MARK|RASP_INT_EVENT_WATER_MARK |\
35 RASP_INT_ECM_PKT_RDY )
36
37
38 #define NDS_RASP_TASK_STACK_SIZE (1024 * 16 )
39
40
41 #define NDS_RASP_TIME_WATER_MARK 0x00000200
42 #define NDS_RASP_EVENT_WATER_MARK 0x00000400
43 #define NDS_RASP_ECM_OVERFLOW_SHIFT 0x00000016
44
45 #define NDS_RASP_EVENT_ALL 0xFFFFFFFF
46
47
48
49 #define NDS_CAM_FLT_BUF_SIZE (256)
50 #define NDS_CAM_FLT_BUF_ALIGN (8)
51 #define NDS_CAM_ECM_FLT_NUM (6)
52 #define NDS_CAM_EMM_BUF_NUM (10)
53
54 #define NDS_RASP_PAYLOAD_PKT_NUM (1000)
55
56 #define NDS_RASP_ECM_BUF_SIZE (NDS_CAM_FLT_BUF_SIZE * (NDS_CAM_ECM_FLT_NUM+2) )
57 #define NDS_RASP_PAYLOAD_BUF_SIZE (192 * NDS_RASP_PAYLOAD_PKT_NUM )
58
59 #define NDS_RASP_ALL_BUF_SIZE (NDS_RASP_ECM_BUF_SIZE + NDS_RASP_PAYLOAD_BUF_SIZE)
60 #define CA_OK 0
61 #define CA_REQUEST_NOT_SUPPORTED_BY_DRIVER 1
62 #define CA_DRIVER_CAN_NOT_PERFORM_FUNCTION_NOW 2
63 #define CA_GLOBAL_HARDWARE_FAILURE 3
64 #define CA_ECM_PID_FILTER_ALREADY_DEFINED 4
65 #define CA_DRIVER_INVALID_DATA_STREAM 5
66 #define CA_DRIVER_INVALID_LOGICAL_STREAM_ID 6
67 // #define CA_INSUFICIENT_BUFFER 7
68 #define CA_INFO_NOT_AVAILABLE 7
69 #define CA_INSUFFICIENT_BUFFER 8
70 #define CA_SCHEME_NOT_SUPPORTED 9
71 #define CA_FUNCTIONALITY_NOT_AVAILABLE_UNTIL_RESTART 10
72 #define CA_FUNCTIONALITY_PERMANENTLY_NOT_AVAILABLE 11
73 #define CA_FEATURE_NOT_SUPPORTED 12
74
75 #if 1
76 #define MAX_PIDS 8
77
78 /* HDICA_ECM_FILTER_CONTROL_ODD_RECEPTION_MASK */
79 #define HDICA_ECM_FILTER_CONTROL_DISABLE_ODD_RECEPTION 0x00
80 #define HDICA_ECM_FILTER_CONTROL_ENABLE_ODD_RECEPTION 0x20
81
82 /* HDICA_ECM_FILTER_CONTROL_EVEN_RECEPTION_MASK */
83 #define HDICA_ECM_FILTER_CONTROL_DISABLE_EVEN_RECEPTION 0x00
84 #define HDICA_ECM_FILTER_CONTROL_ENABLE_EVEN_RECEPTION 0x40
85
86 #define REG_RASP_ECM03_PID(n) (0x0012+n*1)
87 #define RASP_ECM_PID_MASK BMASK(12:0)
88 #define RASP_ECM_PID_TID_MASK BMASK(14:13)
89 #define RASP_ECM_PID_TID_ODD BIT(13)
90 #define RASP_ECM_PID_TID_EVEN BIT(14)
91 #define RASP_ECM_PID_ENABLE BIT(15)
92 //#define REG_RASP_ECM_TID 0x0016
93 // #define RASP_ECM_TID_EVEN_MASK BMASK(7:0)
94 // #define RASP_ECM_TID_ODD_MASK BMASK(15:8)
95 #define REG_RASP_ECM03_LOCK_CTRL 0x0017
96 #define RASP_ECM_LOCK_BITS 4
97 //#define REG_RASP_CA_INT 0x0018
98 #define RASP_CA_INT_ECM BIT(0)
99 #define RASP_CA_INT_MASK_RESET_MODE BIT(7) // set 1 to reset interrupt status
100 #define REG_RASP_ECM_INT_STAT 0x0019
101 #define RASP_ECM_INT_FLT_MASK BMASK(7:0)
102
103 #define REG_RASP_ECM45_PID(n) (0x0030+(n-4)*1)
104
105 #define REG_RASP_ECM45_LOCK_CTRL_ 0x0032
106
107 /* HDICA_ECM_RECEPTION_MASK */
108 #define HDICA_ECM_RECEPTION_DISABLE 0x00
109 #define HDICA_ECM_RECEPTION_ENABLE 0x80
110
111 #define HDICA_ECM_DISABLE_RECEPTION 0x00 /* it's multiply because of mismatch in the document */
112 #define HDICA_ECM_ENABLE_RECEPTION 0x80
113
114 //#define HW_RASP_REGBASE 0xBF223800
115 //#define RASP_REG(addr) (*((volatile MS_U16*)(HW_RASP_REGBASE + ((addr)<<2))))
116
117 // Macros
118 #define REG_RASP_ECM_PID(n) ( (n<4) ? (REG_RASP_ECM03_PID(n)) : (REG_RASP_ECM45_PID(n)) )
119 #define REG_RASP_ECM_LOCK(n) ( (n<4) ? (REG_RASP_ECM03_LOCK_CTRL) : (REG_RASP_ECM45_LOCK_CTRL_) )
120 #define RASP_ECM_LOCK_MASK(n) ( (n<4) ? (BMASK(2:0)<<(RASP_ECM_LOCK_BITS*n)) : (BMASK(2:0)<<(RASP_ECM_LOCK_BITS*(n-4))) )
121 #define RASP_ECM_LOCK_AUTO(n) ( (n<4) ? (BIT(0) <<(RASP_ECM_LOCK_BITS*n)) : (BIT(0) <<(RASP_ECM_LOCK_BITS*(n-4))) )
122 #define RASP_ECM_LOCK_EVEN(n) ( (n<4) ? (BIT(1) <<(RASP_ECM_LOCK_BITS*n)) : (BIT(1) <<(RASP_ECM_LOCK_BITS*(n-4))) )
123 #define RASP_ECM_LOCK_ODD(n) ( (n<4) ? (BIT(2) <<(RASP_ECM_LOCK_BITS*n)) : (BIT(2) <<(RASP_ECM_LOCK_BITS*(n-4))) )
124 #endif
125
126 //------------------------------------------------------------------------//
127 // Local Structure definition
128 //------------------------------------------------------------------------//
129
130 typedef struct
131 {
132
133 MS_U16 pid ;
134 MS_U16 ecmid;
135 MS_U8 ecm_ctrl;
136 MS_U32 Xconn;
137 MS_BOOL b_defined;
138
139 } NDS_RASP_ECM_FLT;
140
141 typedef struct
142 {
143 MS_U16 u16FltId;
144 XUSHORT Pid;
145 F_RASP_EV_MASK EventMask;
146 F_RASP_EV_MASK PayloadMask;
147 DrvRASP_FltState RASP_FltState;
148 } EventMask_s;
149
150 //------------------------------------------------------------------------//
151 // Variable declaration
152 //------------------------------------------------------------------------//
153
154 //static MS_U8 *_rasp_ecm_addr[RASP_NUM] ;//{[0 ... (RASP_NUM)] = NULL } ;
155 static MS_S32 _nds_rasp_eventid = -1 , _nds_rasp_taskid = -1 ;
156
157 //static MS_U32 _u32LastErr;
158 //static MS_BOOL _bSuspend = FALSE;
159
160 MS_U8 _u8RaspEcmBuf[RASP_NUM][NDS_CAM_ECM_FLT_NUM][2][NDS_CAM_FLT_BUF_SIZE];
161
162 NDS_RASP_ECM_FLT _rasp_ecm_flt[RASP_NUM][NDS_CAM_ECM_FLT_NUM];
163
164 static MS_U32 _nds_rasp_stack[NDS_RASP_TASK_STACK_SIZE/sizeof(MS_U32)];
165
166 //static EventMask_s _tEventMask[RASP_EVENT_NUM];
167 //static MS_U32 _u32PidIndEventMask = 0;
168
169 //static XUSHORT EcmPid[RASP_NUM][NDS_CAM_ECM_FLT_NUM];
170 static MS_U32 EcmPktNumer,EcmWritePtr,EcmTimeStamp;
171 static MS_U16 EcmIntStatus;
172 static MS_BOOL _bRASPIsInit = FALSE;
173
174 //#ifdef MSOS_TYPE_LINUX_KERNEL
175 //static irqreturn_t _NDS_RASP_Isr(int irq, void *dev_id);
176 //#else
177 //static void _NDS_RASP_Isr(InterruptNum eIntNum);
178 //#endif
179
180 static void _NDS_RASP_IsrTask(void);
181 RASP_EVENT_NOTIFY_FOUNCTION *_RaspEventCB;
182 RASP_OVERFLOW_NOTIFY_FUNCTION *_RaspOvfCB;
183 MS_PHYADDR _pPayloadBuf0;
184 MS_PHYADDR _pPayloadBuf1;
185 MS_U32 _PayloadSize0;
186 MS_U32 _PayloadSize1;
187 MS_U8 _u8pingpong;
188
189 //static MS_U8 *_rasp_payload_addr[RASP_NUM] ;//{[0 ... (RASP_NUM)] = NULL } ;
190 //RASP_EVENT _RaspEvents[NDS_RASP_PAYLOAD_PKT_NUM]; //egi
191
192 static MS_U32 _u32RaspEventFlag;
193 static MS_U32 _u32RaspOvfEventFlag;
194 static MS_U16 _RaspEventIdx;
195 //static MS_U16 _RaspNumEvents = 0;
196 static MS_U16 _RaspNumEventsTotal=0;
197 static MS_U16 _RaspReadIdx = 0;
198 MS_U16 _RaspEventHighMark;
199 MS_U32 _RaspTriggerExecutor;
200
201
202 //static MS_U16 EventLog = 0;
203 //static MS_U32 EventDescr = 0;
204 static MS_U16 EventNumber = 0;
205 static MS_U16 EventCurIndex[RASP_NUM];
206 static MS_U16 EventReadIndex[RASP_NUM];
207 static MS_U16 EventTmpIndex[RASP_NUM];
208
209 //static MS_U16 EventWriteIndex = 0;
210
211 static NDS_RASP_EVENT _EventDataArray[RASP_NUM][RASP_EVENT_FIFO_DEPTH];
212
213 //static MS_U16 EventNumber2 = 0;
214 //static MS_U32 _EventDataArray2[6];
215
216 //--------------------------------------------------------------------------------------------------
217 // Driver Compiler Option
218 //--------------------------------------------------------------------------------------------------
219
220 // Safe Mode Configuration
221 // ============================================
222 // ISR_SAFE TASK_SAFE
223 // ISR_SAFE Int,Reg Int,Reg,Task
224 // TASK_SAFE Int,Reg,Task Mutex,Reg,Task
225 //
226 #define _RASP_SetEvent(flag) MsOS_SetEvent(_s32RASPEventId, (flag))
227 #define _RASP_SetSecRdyId(eng, flag) MsOS_SetEvent(_s32RASPSecRdyId[(eng)], (flag))
228 #define _RASP_SetSecOvfId(eng, flag) MsOS_SetEvent(_s32RASPSecOvfId[(eng)], (flag))
229
230 #define _RASP_GetEvent(events, flag, opt, timeout) MsOS_WaitEvent(_s32RASPEventId, (flag), &(events), (opt), (timeout))
231 #define _RASP_GetSecRdyId(eng, flag, events, opt) MsOS_WaitEvent(_s32RASPSecRdyId[(eng)], (flag), &(events), (opt), 0)
232 #define _RASP_GetSecOvfId(eng, flag, events, opt) MsOS_WaitEvent(_s32RASPSecOvfId[(eng)], (flag), &(events), (opt), 0)
233
234 #define _RASP_SetSecCrcId(eng, flag) MsOS_SetEvent(_s32RASPSecCrcId[(eng)], (flag))
235 #define _RASP_GetSecCrcId(eng, flag, events, opt) MsOS_WaitEvent(_s32RASPSecCrcId[(eng)], (flag), &(events), (opt), 0)
236
237 #define _RASP_SetFltDisableId(eng, flag) MsOS_SetEvent(_s32RASPFltDisableId[(eng)], (flag))
238 #define _RASP_GetFltDisableId(eng, flag, events, opt) MsOS_WaitEvent(_s32RASPFltDisableId[(eng)], (flag), &(events), (opt), 0)
239
240 //--------------------------------------------------------------------------------------------------
241 // Local Defines
242 //--------------------------------------------------------------------------------------------------
243
244 #if defined (MSOS_TYPE_NOS)
245 #define _RASP_ENTRY()
246 #define _RASP_RETURN(_ret) {return _ret;}
247 #define _RASP_CHECK(idx)
248 #else
249 #define _RASP_ENTRY() if (!MsOS_ObtainMutex(_prasp_res->_s32RASPMutexId, MSOS_WAIT_FOREVER)) \
250 { \
251 _prasp_res->_u32LastErr = DRVRASP_FUNC_ERROR; \
252 printf("_RASP_ENTRY return ERROR\n"); \
253 return DRVRASP_FUNC_ERROR; \
254 } \
255 if (_prasp_res->_bSuspend) \
256 { \
257 _RASP_RETURN(FALSE); \
258 }
259
260 #define _RASP_RETURN(_ret) if(MsOS_ReleaseMutex(_prasp_res->_s32RASPMutexId)) {return _ret;} \
261 else \
262 { \
263 _prasp_res->_u32LastErr = DRVRASP_FUNC_ERROR; \
264 return DRVRASP_FUNC_ERROR; \
265 }
266
267 #define _RASP_CHECK(idx) if( (MS_U32)idx >= (MS_U32)RASP_NUM ) \
268 { printf("[RASP][ERR] Rasp Engine [%d] not exist ! \n",idx); \
269 _RASP_RETURN(FALSE); }
270 #endif
271
272 //--------------------------------------------------------------------------------------------------
273 // Local variable
274 //--------------------------------------------------------------------------------------------------
275
276 typedef struct _DrvRASP_State
277 {
278 MS_U32 _RASP_init;
279 DrvRASP_FltState _RASP_FltState;
280 DrvRASP_FltState _RASP_ECMFltState;
281 } DrvRASP_State;
282
283 typedef struct _RASP_RESOURCE_PRIVATE
284 {
285 MS_S32 _s32RASPMutexId;
286 MS_U32 _u32LastErr;
287 MS_BOOL _bSuspend;
288
289 DrvRASP_State _RASPState[RASP_NUM][RASP_PIDFLT_NUM_ALL];
290
291 DrvRASP_Event _RASPEvtNotify[RASP_NUM];
292 P_DrvRASP_EvtCallback _RASPCallback[RASP_NUM];
293 P_DrvRASP_EventCB _RASPEventCB[RASP_NUM]; //event array callback
294
295 MS_BOOL _bRASPInitReady;
296 }RASP_RESOURCE_PRIVATE;
297
298
299 //static MSIF_Version _drv_RASP_version = {
300 // .DDI = { RASP_DRV_VERSION, },
301 //};
302
303
304 static RASP_RESOURCE_PRIVATE _rasp_res = {
305 ._s32RASPMutexId = -1,
306 ._u32LastErr = TRUE,
307 ._bSuspend = FALSE,
308 ._bRASPInitReady = FALSE,
309 };
310
311 static RASP_RESOURCE_PRIVATE* _prasp_res = &_rasp_res;
312 static P_NDSRASP_Callback _ndsrasp_cb = NULL;
313
314 static MS_PHYADDR _rasp_writeptr = 0;
315 static MS_PHYADDR _rasp_payloadptr = 0;
316
317 //--------------------------------------------------------------------------------------------------
318 // Forward declaration
319 //--------------------------------------------------------------------------------------------------
320
321 #ifdef MSOS_TYPE_LINUX_KERNEL
_NDS_RASP_Isr(int irq,void * dev_id)322 irqreturn_t _NDS_RASP_Isr(int irq, void *dev_id)
323 #else
324 void _NDS_RASP_Isr(InterruptNum eIntNum)
325 #endif
326 {
327 #if 0
328 MS_U8 u8EcmReg;
329 MS_U8 ecm_polarity;
330 MS_U32 i;
331 MS_U32 u32OvfEvents = 0;
332 #endif
333 MS_U32 IntStatus[RASP_NUM];
334 MS_U16 i;
335 MS_U32 RaspID;
336
337 //MsOS_DisableInterrupt(E_INT_IRQ_RASP);
338 //printf("____NDS_RASP_Isr____\n");
339
340 for( RaspID=0; RaspID<RASP_NUM; RaspID++)
341 {
342 IntStatus[RaspID] = (MS_U32)HAL_NDSRASP_INT_GetHW(RaspID);
343
344 if(IntStatus[RaspID] == 0)
345 continue;
346
347 if(IntStatus[RaspID] & RASP_INT_STR2MIU)
348 {
349 _rasp_writeptr = HAL_NDSRASP_GetWritePtr(RaspID);
350 }
351
352 if( IntStatus[RaspID] & (RASP_INT_TIME_WATER_MARK | RASP_INT_EVENT_WATER_MARK) )
353 {
354 EventNumber = HAL_NDSRASP_EVENT_GetEventNum(RaspID);//reg_RASP0_event_log_ctrl_status
355
356 //Ring queue push
357 if(EventCurIndex[RaspID] + EventNumber < RASP_EVENT_FIFO_DEPTH)
358 {
359 for(i = EventCurIndex[RaspID] + 1; i <= (EventCurIndex[RaspID] + EventNumber); i++)
360 {HAL_NDSRASP_EVENT_GetEventDescriptor(RaspID, (MS_U32*)&_EventDataArray[RaspID][i], 5);}
361 EventCurIndex[RaspID] = EventCurIndex[RaspID] + EventNumber;
362 }
363 else
364 {
365 for(i = EventCurIndex[RaspID] + 1; i < RASP_EVENT_FIFO_DEPTH; i++)
366 {HAL_NDSRASP_EVENT_GetEventDescriptor(RaspID, (MS_U32*)&_EventDataArray[RaspID][i], 5);}
367 for(i = 0; i <= (EventCurIndex[RaspID] + EventNumber - RASP_EVENT_FIFO_DEPTH); i++)
368 {HAL_NDSRASP_EVENT_GetEventDescriptor(RaspID, (MS_U32*)&_EventDataArray[RaspID][i], 5);}
369 EventCurIndex[RaspID] = (EventCurIndex[RaspID] + EventNumber - RASP_EVENT_FIFO_DEPTH);
370 }
371
372 EventTmpIndex[RaspID] = EventCurIndex[RaspID];
373 printf("EventCurIndex=%x EventNumber=%x\n", (MS_U32)EventCurIndex[RaspID], (MS_U32)EventNumber);
374
375 }
376
377 if(IntStatus[RaspID] & RASP_INT_EFRAME_RD_OVF)
378 {
379 }
380
381 if(IntStatus[RaspID] & RASP_INT_EFRAME_WT_OVF)
382 {
383 }
384
385 if(IntStatus[RaspID] & RASP_INT_PAYLD2MIU)
386 {
387 _rasp_payloadptr = HAL_NDSRASP_GetPayloadWritePtr(RaspID);
388 }
389
390 if (IntStatus[RaspID] & RASP_INT_ECM_PKT_RDY) // ECM Packet Ready
391 {
392 EcmPktNumer = HAL_NDSRASP_GetEcmPktNum(RaspID);
393 printf("ECM Packet Number is [0x%x]\n", EcmPktNumer);
394
395 //printf("ECM Interrupt state = %X\n", HAL_NDSRASP_SetECM_GetHW(RaspID));
396 HAL_NDSRASP_SetECM_ResetHW(RaspID, 0xFFFF);
397
398 EcmWritePtr = HAL_NDSRASP_GetECMWritePtr(RaspID);
399 printf("ECM EcmWritePtr is [0x%x]\n", EcmWritePtr);
400
401 #if 0 //TODO
402 EcmWritePtr = HAL_NDSRASP_GetECMWritePtr(EngId);
403 EcmTimeStamp= HAL_NDSRASP_GetECMTimeStamp(EngId);
404 //NDS_RASP_DBG("HAL_NDSRASP_SetECM_GetHW = %X\n", HAL_NDSRASP_SetECM_GetHW(0));
405
406 EcmIntStatus = HAL_NDSRASP_SetECM_GetHW(EngId);
407 //HAL_NDSRASP_SetECM_ResetHW(EngId, EcmIntStatus);
408
409
410 if (pEcmData[0] != 0x47)
411 {
412 continue; //_NDS_ASSERT_;
413 }
414 if (pEcmData[5] == 0x80)
415 {
416 ecm_polarity = 0; // EVEN
417 }
418 else if (pEcmData[5] == 0x81)
419 {
420 ecm_polarity = 1; // ODD
421 }
422 else
423 {
424 NDS_ASSERT(FALSE, , "[%s]-[%d]\n", __FUNCTION__, __LINE__);
425 }
426
427
428 //need to copy to ecm buffer to keep buffer for future usage.....
429 //memcpy(_u8RaspEcmBuf,
430 #endif
431 }
432
433 HAL_NDSRASP_INT_ClrHW(RaspID , IntStatus[RaspID]);
434 //HAL_NDSRASP_INT_ClrHW(RaspID , 0x0);
435 //printf("int status after clear = %x",(MS_U32)HAL_NDSRASP_INT_GetHW(RaspID));
436 //HAL_NDSRASP_INT_Enable(RaspID , 0xffff);
437
438 MsOS_SetEvent(_nds_rasp_eventid, RaspID<<16 | (IntStatus[RaspID] ) );
439 }
440
441
442 if(FALSE == HAL_EMMFLT_GetIntMode())
443 {
444 MsOS_EnableInterrupt(E_INT_IRQ_RASP);
445 }
446
447 }
448
_NDS_RASP_IsrTask(void)449 static void _NDS_RASP_IsrTask(void)
450 {
451 //MS_U32 i ,p ,hi_count ,lo_count;;
452 MS_U32 u32Events;
453 //MS_U32 DataArray[5];
454 MS_U8 RaspID;
455 NDSRaspCallBack_t cb_info;
456 P_DrvRASP_EventCB _Event_CallBackFun;
457 MS_U16 u16EventQueued=0;
458
459 printf("ISR task\n");
460
461 while(1)
462 {
463 MsOS_WaitEvent(_nds_rasp_eventid, NDS_RASP_EVENT_ALL, &u32Events, E_OR_CLEAR, MSOS_WAIT_FOREVER);
464
465 RaspID = ((u32Events>>16) & 0xff);
466 printf("[RASP]_NDS_RASP_IsrTask!!----- u32Events = 0x%x, ID = %x \n",u32Events, RaspID);
467 //printf("EventLog = %x, EventDescr = %x, EventNumber = %x\n",EventLog, EventDescr, EventNumber);
468
469 if(RaspID >= RASP_NUM)
470 {
471 DRVRASP_DBG(RASP_DBGLV_ERR,"invalid Rasp ID\n");
472 continue;
473 }
474
475 _Event_CallBackFun = _prasp_res->_RASPEventCB[RaspID];
476
477 memset(&cb_info, 0x0, sizeof(cb_info));
478
479 if(u32Events & RASP_INT_STR2MIU)
480 {
481 printf("Str2MIU INT, _rasp_writeptr = %x\n",_rasp_writeptr);
482 cb_info.eEvent = NDSRASP_CB_STR2RAM;
483 cb_info.index = 1;
484 cb_info.write_ptr = _rasp_writeptr;
485 if(_ndsrasp_cb != NULL)
486 {
487 _ndsrasp_cb(RaspID, &cb_info);
488 }
489 }
490
491 if(u32Events & RASP_INT_PVR2MIU)
492 {
493 printf("PVR2MIU INT\n");
494 }
495
496 if(u32Events & RASP_INT_PAYLD2MIU)
497 {
498 printf("Payload INT, _rasp_payloadptr = %x\n",_rasp_payloadptr);
499 cb_info.eEvent = NDSRASP_CB_PAYLOAD2RAM;
500 cb_info.index = 1;
501 cb_info.write_ptr = _rasp_payloadptr;
502 if(_ndsrasp_cb != NULL)
503 {
504 _ndsrasp_cb(RaspID, &cb_info);
505 }
506 }
507
508 if( u32Events & (RASP_INT_TIME_WATER_MARK | RASP_INT_EVENT_WATER_MARK) )
509 {
510 printf("Event TIME/EVENT WATER MARK Int\n");
511 printf("EventReadIndex now [0x%x]\n", (MS_U32)EventReadIndex[RaspID]);
512
513 if (EventReadIndex[RaspID] < EventTmpIndex[RaspID])
514 {
515 u16EventQueued = (MS_U16)(EventTmpIndex[RaspID] - EventReadIndex[RaspID]);
516 }
517 else if (EventReadIndex[RaspID] > EventTmpIndex[RaspID])
518 {
519 u16EventQueued = (MS_U16)(RASP_EVENT_FIFO_DEPTH - EventReadIndex[RaspID] + EventTmpIndex[RaspID]);
520 }
521 else
522 { printf("Event SW FIFO is not updated\n"); }
523 printf("u16EventQueued [0x%x]\n", (MS_U32)u16EventQueued);
524
525 EventReadIndex[RaspID] ++;
526 if(NULL != _Event_CallBackFun)
527 {
528 _Event_CallBackFun(RaspID, _EventDataArray[RaspID], u16EventQueued, EventReadIndex[RaspID]);
529 }
530 EventReadIndex[RaspID] += (u16EventQueued-1);
531
532 printf("EventReadIndex then [0x%x]\n", (MS_U32)EventReadIndex[RaspID]);
533 #if 0 //TODO
534 for(i=0;i<EventNumber;i++)
535 {
536 printf("EventNumber = %x\n",i);
537 printf("EventDescr = %x, PktPID = %x, PktNum = %x, PktTimer = %x, PktPCR = %x) \n",_EventDataArray[RaspID][i].Event_Descriptor, \
538 _EventDataArray[RaspID][i].Pid, _EventDataArray[RaspID][i].PacketNum,_EventDataArray[RaspID][i].Timer,_EventDataArray[RaspID][i].PCR);
539 }
540 #endif
541
542 }
543
544 if(u32Events & RASP_INT_ECM2MIU)
545 {
546 printf("ECM 2 MIU Int\n");
547 }
548
549 if(u32Events & RASP_INT_ECM_PKT_RDY)
550 {
551 printf("ECM Packet Ready, EcmPktNumer = %x, EcmWritePtr = %x, EcmTimeStamp = %x, EcmIntStatus = %x\n",EcmPktNumer, EcmWritePtr, EcmTimeStamp, EcmIntStatus);
552 }
553
554 if(u32Events & RASP_INT_EFRAME_RD_OVF)
555 {
556 printf("RASP_INT_EFRAME_RD_OVF \n");
557 }
558
559 if(u32Events & RASP_INT_EFRAME_WT_OVF)
560 {
561 printf("RASP_INT_EFRAME_WT_OVF \n");
562 }
563
564 MsOS_DelayTask(1);
565
566 }// while(1)
567 }
568
569 #if 0 //TEST
570 #ifdef MSOS_TYPE_LINUX_KERNEL
571 static irqreturn_t _NDS_RASP_Isr2(int irq, void *dev_id)
572 #else
573 static void _NDS_RASP_Isr2(InterruptNum eIntNum)
574 #endif
575
576 {
577 #if 0
578 MS_U8 u8EcmReg;
579 MS_U8 ecm_polarity;
580 MS_U32 i;
581 MS_U32 u32OvfEvents = 0;
582 #endif
583 MS_U32 IntStatus;
584 MS_U32 i;
585 MS_U32 RaspID=0;
586
587 MsOS_DisableInterrupt(E_INT_IRQ_RASP);
588
589
590
591 IntStatus = (MS_U32)HAL_NDSRASP_INT_GetHW(RaspID);
592 printf("____Isr #2____[%08X]\n", IntStatus);
593
594 if (IntStatus & RASP_INT_ECM_PKT_RDY)
595 {
596 //NDS_RASP_DBG("RASP_INT_ECM_PKT_RDY\n");
597 EcmPktNumer = HAL_NDSRASP_GetEcmPktNum(RaspID);
598 printf("ECM Packet Number is [0x%x]\n", EcmPktNumer);
599 //printf("ECM Interrupt state = %X\n", HAL_NDSRASP_SetECM_GetHW(RaspID));
600 HAL_NDSRASP_SetECM_ResetHW(RaspID, 0xFFFF);
601 //EcmWritePtr = HAL_NDSRASP_GetECMWritePtr(RaspID);
602 //printf("ECM EcmWritePtr is [0x%x]\n", EcmWritePtr);
603
604 MsOS_ReleaseSemaphore(_nds_rasp_eventid);
605 #if 0
606 EcmWritePtr = HAL_NDSRASP_GetECMWritePtr(EngId);
607 EcmTimeStamp= HAL_NDSRASP_GetECMTimeStamp(EngId);
608 //NDS_RASP_DBG("HAL_NDSRASP_SetECM_GetHW = %X\n", HAL_NDSRASP_SetECM_GetHW(0));
609
610 EcmIntStatus = HAL_NDSRASP_SetECM_GetHW(EngId);
611 //HAL_NDSRASP_SetECM_ResetHW(EngId, EcmIntStatus);
612
613
614 if (pEcmData[0] != 0x47)
615 {
616 continue; //_NDS_ASSERT_;
617 }
618 if (pEcmData[5] == 0x80)
619 {
620 ecm_polarity = 0; // EVEN
621 }
622 else if (pEcmData[5] == 0x81)
623 {
624 ecm_polarity = 1; // ODD
625 }
626 else
627 {
628 NDS_ASSERT(FALSE, , "[%s]-[%d]\n", __FUNCTION__, __LINE__);
629 }
630
631
632 //need to copy to ecm buffer to keep buffer for future usage.....
633 //memcpy(_u8RaspEcmBuf,
634 #endif
635 }
636
637 if(IntStatus & RASP_INT_EFRAME_RD_OVF)
638 {
639 }
640
641 if(IntStatus & RASP_INT_EFRAME_WT_OVF)
642 {
643 }
644
645 if(IntStatus & RASP_INT_PAYLD2MIU)
646 {
647 _rasp_payloadptr = HAL_NDSRASP_GetPayloadWritePtr(RaspID);
648 }
649 if(IntStatus & RASP_INT_EVENT_WATER_MARK)
650 ;
651 if(IntStatus & RASP_INT_TIME_WATER_MARK)
652 ;
653 if(IntStatus & RASP_INT_STR2MIU)
654 {
655 _rasp_writeptr = HAL_NDSRASP_GetWritePtr(RaspID);
656 }
657 if(IntStatus & RASP_INT_PAYLD2MIU)
658 {
659 _rasp_payloadptr = HAL_NDSRASP_GetPayloadWritePtr(RaspID);
660 }
661
662 //HAL_NDSRASP_INT_ClrHW(RaspID , IntStatus[RaspID]);
663 HAL_NDSRASP_INT_ClrHW(RaspID , 0xFFFF);
664
665 //MsOS_SetEvent(_nds_rasp_eventid, RaspID<<16 | (IntStatus[RaspID] ) );
666
667
668
669
670 MsOS_EnableInterrupt(E_INT_IRQ_RASP);
671 }
672 #endif
673 #if 0
674 static void _NDS_RASP_IsrTask2(void)
675 {
676
677 MS_U32 u32Events=0;
678 MS_U32 RaspID;
679
680
681 printf("ISR task222\n");
682
683 while(1)
684 {
685 //MsOS_WaitEvent(_nds_rasp_eventid, NDS_RASP_EVENT_ALL, &u32Events, E_OR_CLEAR, MSOS_WAIT_FOREVER);
686 MsOS_ObtainSemaphore(_nds_rasp_eventid, MSOS_WAIT_FOREVER);
687
688 printf("[RASP]_NDS_RASP_IsrTask2222!!----- u32Events = %x \n",u32Events);
689 //printf("EventLog = %x, EventDescr = %x, EventNumber = %x\n",EventLog, EventDescr, EventNumber);
690
691 #if 0
692 RaspID = (u32Events>>16);
693 if(RaspID >= RASP_NUM)
694 {
695 DRVRASP_DBG(RASP_DBGLV_ERR,"invalid Rasp ID\n");
696 continue;
697 }
698
699 printf("Rasp ID = %x\n",RaspID);
700
701 if(u32Events & RASP_INT_ECM_PKT_RDY)
702 {
703 printf("ECM Packet Ready, EcmPktNumer = %x, EcmWritePtr = %x, EcmTimeStamp = %x, EcmIntStatus = %x\n",EcmPktNumer, EcmWritePtr, EcmTimeStamp, EcmIntStatus);
704 }
705 #endif
706 }
707 }
708 #endif
709
_RASP_InitResource(RASP_RESOURCE_PRIVATE * presource)710 static MS_BOOL _RASP_InitResource(RASP_RESOURCE_PRIVATE* presource)
711 {
712 if(presource == NULL)
713 return FALSE;
714
715 presource->_s32RASPMutexId = -1;
716 presource->_bSuspend = FALSE;
717 presource->_bRASPInitReady = FALSE;
718 presource->_u32LastErr = TRUE;
719
720 return TRUE;
721 }
722
_NDS_RASP_SwStateReset(void)723 static void _NDS_RASP_SwStateReset(void)
724 {
725 MS_U32 _u32RASPnum = 0;
726 MS_U32 i = 0;
727 printf("%s\n",__FUNCTION__);
728
729 for (_u32RASPnum = 0 ; _u32RASPnum < RASP_NUM ; _u32RASPnum++)
730 {
731 for (i = RASP_PIDFLT_START_NUM; i < RASP_PIDFLT_END_NUM; i++)
732 {
733 _prasp_res->_RASPState[_u32RASPnum][i]._RASP_init = 0;
734 _prasp_res->_RASPState[_u32RASPnum][i]._RASP_FltState = E_DRVRASP_FLT_STATE_FREE;
735 _prasp_res->_RASPState[_u32RASPnum][i]._RASP_ECMFltState = E_DRVRASP_FLT_STATE_FREE;
736 }
737 }
738 }
739
_NDS_RASP_RegStateReset(void)740 static void _NDS_RASP_RegStateReset(void)
741 {
742 printf("%s\n",__FUNCTION__);
743
744 MS_U16 _u16fltnum = 0;
745 MS_U32 _u32RASPnum = 0;
746 for (_u32RASPnum = 0 ; _u32RASPnum < RASP_NUM ; _u32RASPnum++)
747 {
748 HAL_RASP_SetPVRDstBuf(_u32RASPnum,0,0,0,0);
749 for (_u16fltnum = 0 ; _u16fltnum < RASP_PIDFLT_NUM ; _u16fltnum++)
750 {
751 HAL_NDSRASP_SetPidflt(_u32RASPnum, _u16fltnum, RASP_PIDFLT_DEF);
752 }
753
754 for (_u16fltnum = 0 ; _u16fltnum < RASP_EVENT_NUM ; _u16fltnum++)
755 {
756 HAL_NDSRASP_SetEventMask(_u32RASPnum, _u16fltnum, ~RASP_BYPASS_MASK);
757 HAL_NDSRASP_SetPayloadMask(_u32RASPnum, _u16fltnum, ~RASP_BYPASS_MASK);
758 }
759 }
760 }
761
_RASP_Close(void)762 static void _RASP_Close(void)
763 {
764 MS_U8 u8ii;
765
766 for(u8ii = 0; u8ii < RASP_NUM; u8ii++)
767 {
768 HAL_NDSRASP_Exit(u8ii);
769 }
770
771 }
772
773 // General API
774 //-------------------------------------------------------------------------------------------------
775 /// Initialize lib resource API
776 /// @param pResMemAddr \b IN: Pointer to store resource memory address
777 /// @return MMFI_Result
778 /// @note
779 //-------------------------------------------------------------------------------------------------
NDS_RASP_InitLibResource(void * pResMemAddr)780 MS_U32 NDS_RASP_InitLibResource(void* pResMemAddr)
781 {
782 if(pResMemAddr == 0)
783 return FALSE;
784
785 _prasp_res = (RASP_RESOURCE_PRIVATE*)pResMemAddr;
786
787 if(_prasp_res->_bRASPInitReady != TRUE)
788 {
789 if(_RASP_InitResource(_prasp_res) == FALSE)
790 {
791 _prasp_res->_u32LastErr = FALSE;
792 }
793 else
794 _prasp_res->_u32LastErr = TRUE;
795 }
796
797 return (_prasp_res->_u32LastErr);
798 }
799
800 //--------------------------------------------------------------------------------------------------
801 /// Initialize RASP driver and RASP engine
802 /// @return MS_U32
803 /// @note
804 /// It should be called before calling any other RASP DDI functions.
805 /// Driver task is in @ref E_TASK_PRI_SYS level.
806 //--------------------------------------------------------------------------------------------------
NDS_RASP_Init(void)807 MS_U32 NDS_RASP_Init(void)
808 {
809 MS_U32 bRet = TRUE;
810 MS_U8 u8ii;
811
812 DRVRASP_DBG(RASP_DBGLV_INFO, "\n");
813
814 if(_bRASPIsInit == FALSE)
815 {
816 MS_VIRT u32Bank;
817 MS_PHY u32BankSize;
818 printf("%s\n",__FUNCTION__);
819 if (FALSE == MDrv_MMIO_GetBASE(&u32Bank, &u32BankSize, MS_MODULE_PM))
820 {
821 DRVRASP_DBG(RASP_DBGLV_ERR,"MDrv_MMIO_GetBASE fail\n");
822 MS_ASSERT(0);
823 }
824
825 printf("u32Bank = %X\n",u32Bank);
826 HAL_NDSRASP_SetBank(u32Bank);
827
828 for(u8ii = 0; u8ii < RASP_NUM; u8ii++)
829 {
830 _prasp_res->_RASPEvtNotify[u8ii] = E_DRVRASP_EVENT_DATA_INIT;
831 _prasp_res->_RASPCallback[u8ii] = NULL;
832
833 HAL_NDSRASP_PowerCtrl(u8ii, ENABLE);
834 HAL_NDSRASP_Init(u8ii);
835 }
836 _NDS_RASP_SwStateReset();
837
838 if (-1 == _prasp_res->_s32RASPMutexId)
839 {
840 _prasp_res->_s32RASPMutexId = MsOS_CreateMutex(E_MSOS_FIFO , "RASP_Mutex" , MSOS_PROCESS_SHARED);
841 }
842 else
843 {
844 DRVRASP_DBG(RASP_DBGLV_ERR,"Create _s32RASPMutexId more than once\n");
845 }
846
847 _u32RaspEventFlag = 0;
848 _u32RaspOvfEventFlag = 0;
849 _RaspEventIdx = 0;
850 _RaspReadIdx = 0;
851 _RaspNumEventsTotal=0;
852
853
854 if (-1 == _nds_rasp_eventid)
855 {
856 _nds_rasp_eventid = MsOS_CreateEventGroup("NDS_RASP_Event");
857 }
858
859 if (-1 == _nds_rasp_taskid)
860 {
861 _nds_rasp_taskid = MsOS_CreateTask( (TaskEntry) _NDS_RASP_IsrTask,
862 (MS_U32)NULL,
863 (TaskPriority) E_TASK_PRI_HIGHEST,
864 TRUE,
865 _nds_rasp_stack,
866 NDS_RASP_TASK_STACK_SIZE,
867 "NDS_RASP_IsrTask");
868 }
869
870 EMMRASP_IntAttach(RASP_ENGINE, TRUE);
871 HAL_NDSRASP_INT_Enable(0 ,0xffff);
872 _bRASPIsInit = TRUE;
873
874 _RASP_ENTRY();
875 _prasp_res->_bRASPInitReady = TRUE;
876 _RASP_RETURN(bRet);
877 }
878
879
880 return bRet;
881 }
882
883 //--------------------------------------------------------------------------------------------------
884 /// Poweroff RASP driver and RASP engine
885 /// @return MS_U32
886 /// @note
887 //--------------------------------------------------------------------------------------------------
NDS_RASP_Reset(void)888 MS_U32 NDS_RASP_Reset(void)
889 {
890 _RASP_ENTRY();
891 _NDS_RASP_SwStateReset();
892 _NDS_RASP_RegStateReset();
893 _RASP_RETURN(TRUE);
894 }
895
896 //--------------------------------------------------------------------------------------------------
897 /// Close RASP driver and reset software/register state
898 /// @return MS_U32
899 /// @note
900 //--------------------------------------------------------------------------------------------------
NDS_RASP_Exit(void)901 MS_U32 NDS_RASP_Exit(void)
902 {
903 if (_prasp_res->_s32RASPMutexId != -1)
904 {
905 _RASP_ENTRY();
906 }
907
908 if(_prasp_res->_bRASPInitReady == TRUE)
909 {
910 _NDS_RASP_SwStateReset();
911 _NDS_RASP_RegStateReset();
912 _RASP_Close();
913 _prasp_res->_bRASPInitReady = FALSE;
914 }
915
916 if (_prasp_res->_s32RASPMutexId != -1)
917 {
918 MsOS_ReleaseMutex(_prasp_res->_s32RASPMutexId);
919 MsOS_DeleteMutex(_prasp_res->_s32RASPMutexId);
920 _prasp_res->_s32RASPMutexId = -1;
921 }
922
923 return TRUE ;
924 }
925
926 #if 0
927 MS_U32 NDS_RASP_SetBuffer(MS_U32 u32RASPEng, MS_PHYADDR u32BufStart0, MS_PHYADDR u32BufStart1, MS_U32 u32BufSize0, MS_U32 u32BufSize1)
928 {
929 DRVRASP_DBG(RASP_DBGLV_INFO, "RaspEng = %x, StartAddr0 = %x, BufSize0 = %x, StartAddr1 = %x, BufSize1 = %x\n", u32RASPEng,u32BufStart0,u32BufSize0,u32BufStart1,u32BufSize1);
930
931 _NDS_RASP_ENTRY();
932 _NDS_RASP_CHECK(u32RASPEng);
933
934 //check buffer size.....
935 HAL_RASP_SetPVRDstBuf(u32RASPEng, u32BufStart0,(u32BufStart0 + u32BufSize0), u32BufStart1, (u32BufStart1 + u32BufSize1));
936 _NDS_RASP_RETURN(TRUE);
937 }
938 #endif
939
940
NDS_RASP_RaspEngStart(MS_U32 u32RASPEng,DrvRASP_CtrlMode eCtrlMode,MS_BOOL bEnable)941 MS_U32 NDS_RASP_RaspEngStart(MS_U32 u32RASPEng, DrvRASP_CtrlMode eCtrlMode, MS_BOOL bEnable)
942 {
943 DRVRASP_DBG(RASP_DBGLV_INFO, "RaspEng = %x, eCtrlMode = %d, bEnable = %d\n",u32RASPEng, eCtrlMode, bEnable);
944
945 _RASP_ENTRY();
946 _RASP_CHECK(u32RASPEng);
947
948 if (!bEnable)
949 {
950 switch (eCtrlMode)
951 {
952 case E_DRVRASP_MODE_PAYLOAD:
953 {
954 HAL_NDSRASP_Payload_Enable(u32RASPEng , FALSE);
955 break;
956 }
957 case E_DRVRASP_MODE_ECM:
958 {
959 HAL_NDSRASP_ECM_Enable(u32RASPEng , FALSE);
960 break;
961 }
962 default :
963 break;
964 }
965
966 }
967 else
968 {
969 switch (eCtrlMode)
970 {
971 case E_DRVRASP_MODE_PAYLOAD:
972 {
973 HAL_NDSRASP_Payload_Enable(u32RASPEng , TRUE);
974 break;
975 }
976 case E_DRVRASP_MODE_ECM:
977 {
978 HAL_NDSRASP_ECM_Enable(u32RASPEng , TRUE);
979 break;
980 }
981 default :
982 break;
983 }
984
985 }
986 _RASP_RETURN(TRUE);
987 }
988
NDS_RASP_PvrEngStart(MS_U32 u32RASPEng,DrvRASP_RecMode eRecMode,MS_BOOL bEnable)989 MS_U32 NDS_RASP_PvrEngStart(MS_U32 u32RASPEng, DrvRASP_RecMode eRecMode, MS_BOOL bEnable)
990 {
991 DRVRASP_DBG(RASP_DBGLV_INFO, "RaspEng = %x, eRecMode = %d, bEnable = %d\n",u32RASPEng, eRecMode, bEnable);
992
993 _RASP_ENTRY();
994 _RASP_CHECK(u32RASPEng);
995
996 if (!bEnable)
997 {
998 switch (eRecMode)
999 {
1000 case E_DRVRASP_REC_MODE_PID:
1001 {
1002 HAL_NDSRASP_Stop(u32RASPEng);
1003 break;
1004 }
1005 case E_DRVRASP_REC_MODE_ALL:
1006 {
1007 HAL_NDSRASP_Stop(u32RASPEng);
1008 break;
1009 }
1010
1011 default :
1012 break;
1013 }
1014
1015 }
1016 else
1017 {
1018 switch (eRecMode)
1019 {
1020 case E_DRVRASP_REC_MODE_PID:
1021 {
1022 HAL_NDSRASP_Rec_PID(u32RASPEng, TRUE);
1023 HAL_NDSRASP_Pvr_Enable(u32RASPEng);
1024 break;
1025 }
1026 case E_DRVRASP_REC_MODE_ALL:
1027 {
1028 HAL_NDSRASP_Rec_PID(u32RASPEng, FALSE);
1029 HAL_NDSRASP_Pvr_Enable(u32RASPEng);
1030 break;
1031 }
1032
1033 default :
1034 break;
1035 }
1036
1037 }
1038 _RASP_RETURN(TRUE);
1039 }
1040
NDS_RASP_AdvEnable(MS_U32 u32RASPEng,DrvRASP_RecMode eRecMode,MS_BOOL bEn)1041 MS_U32 NDS_RASP_AdvEnable(MS_U32 u32RASPEng, DrvRASP_RecMode eRecMode, MS_BOOL bEn)
1042 {
1043 DRVRASP_DBG(RASP_DBGLV_INFO, "RaspEng = %x, eRecMode = %d, bEn = %d\n",u32RASPEng, eRecMode, bEn);
1044
1045 _RASP_ENTRY();
1046 _RASP_CHECK(u32RASPEng);
1047
1048 if (!bEn)
1049 {
1050 switch (eRecMode)
1051 {
1052 case E_DRVRASP_MODE_PAYLOAD:
1053 {
1054 HAL_NDSRASP_Payload_Enable(u32RASPEng , FALSE);
1055 break;
1056 }
1057 case E_DRVRASP_MODE_ECM:
1058 {
1059 HAL_NDSRASP_ECM_Enable(u32RASPEng , FALSE);
1060 break;
1061 }
1062 default :
1063 break;
1064 }
1065
1066 }
1067 else
1068 {
1069 switch (eRecMode)
1070 {
1071 case E_DRVRASP_MODE_PAYLOAD:
1072 {
1073 HAL_NDSRASP_Payload_Enable(u32RASPEng , TRUE);
1074 break;
1075 }
1076 case E_DRVRASP_MODE_ECM:
1077 {
1078 HAL_NDSRASP_ECM_Enable(u32RASPEng , TRUE);
1079 break;
1080 }
1081 default :
1082 break;
1083 }
1084
1085 }
1086 _RASP_RETURN(TRUE);
1087 }
1088
1089
1090
NDS_RASP_Pause(MS_U32 u32RASPEng,MS_BOOL bPause)1091 MS_U32 NDS_RASP_Pause(MS_U32 u32RASPEng, MS_BOOL bPause)
1092 {
1093 DRVRASP_DBG(RASP_DBGLV_INFO, "RaspEng = %x, bPause = %d\n",u32RASPEng, bPause);
1094
1095 _RASP_ENTRY();
1096 _RASP_CHECK(u32RASPEng);
1097
1098 HAL_NDSRASP_Pause(u32RASPEng,bPause);
1099
1100
1101 _RASP_RETURN(TRUE);
1102 }
1103
1104
NDS_RASP_GetWriteAddr(MS_U32 u32RASPEng,MS_PHYADDR * pu32WriteAddr)1105 MS_U32 NDS_RASP_GetWriteAddr(MS_U32 u32RASPEng, MS_PHYADDR *pu32WriteAddr)
1106 {
1107 DRVRASP_DBG(RASP_DBGLV_INFO, "RaspEng = %x\n",u32RASPEng);
1108 _RASP_ENTRY();
1109 _RASP_CHECK(u32RASPEng);
1110 *pu32WriteAddr = HAL_NDSRASP_GetWritePtr(u32RASPEng);
1111 _RASP_RETURN(TRUE);
1112 }
1113
NDS_RASP_GetPayloadWriteAddr(MS_U32 u32RASPEng,MS_PHYADDR * pu32WriteAddr)1114 MS_U32 NDS_RASP_GetPayloadWriteAddr(MS_U32 u32RASPEng, MS_PHYADDR *pu32WriteAddr)
1115 {
1116 DRVRASP_DBG(RASP_DBGLV_INFO, "RaspEng = %x\n",u32RASPEng);
1117 _RASP_ENTRY();
1118 _RASP_CHECK(u32RASPEng);
1119 *pu32WriteAddr = HAL_NDSRASP_GetPayloadWritePtr(u32RASPEng);
1120 _RASP_RETURN(TRUE);
1121 }
1122
1123
NDS_RASP_SetNotify(MS_U32 u32RASPEng,DrvRASP_Event eEvents,P_DrvRASP_EvtCallback pfCallback)1124 MS_U32 NDS_RASP_SetNotify(MS_U32 u32RASPEng, DrvRASP_Event eEvents, P_DrvRASP_EvtCallback pfCallback)
1125 {
1126 DRVRASP_DBG(RASP_DBGLV_INFO, "eEvents = %x\n",eEvents);
1127 _RASP_ENTRY();
1128 _RASP_CHECK(u32RASPEng);
1129
1130 if (pfCallback)
1131 {
1132 _prasp_res->_RASPEvtNotify[u32RASPEng] = eEvents;
1133 _prasp_res->_RASPCallback[u32RASPEng] = pfCallback;
1134 }
1135 else
1136 {
1137 _prasp_res->_RASPEvtNotify[u32RASPEng] = E_DRVRASP_EVENT_DATA_INIT;
1138 _prasp_res->_RASPCallback[u32RASPEng] = NULL;
1139 }
1140 _RASP_RETURN(TRUE);
1141 }
1142
NDS_RASP_Set_EventNotify(MS_U32 u32RASPEng,P_DrvRASP_EventCB CallBackFun)1143 MS_U32 NDS_RASP_Set_EventNotify(MS_U32 u32RASPEng, P_DrvRASP_EventCB CallBackFun)
1144 {
1145
1146 //DRVRASP_DBG(RASP_DBGLV_INFO, "eEvents = %x\n",eEvents);
1147 DRVRASP_DBG(RASP_DBGLV_INFO, "\n");
1148 _RASP_ENTRY();
1149 _RASP_CHECK(u32RASPEng);
1150
1151 if (CallBackFun)
1152 {
1153 _prasp_res->_RASPEventCB[u32RASPEng] = CallBackFun;
1154 }
1155
1156 _RASP_RETURN(TRUE);
1157 }
1158
1159
NDS_RASP_SetCallBack(MS_U32 u32RASPEng,P_NDSRASP_Callback pfCallback)1160 MS_U32 NDS_RASP_SetCallBack(MS_U32 u32RASPEng, P_NDSRASP_Callback pfCallback)
1161 {
1162 DRVRASP_DBG(RASP_DBGLV_INFO, "RASPEng = %x\n",u32RASPEng);
1163 _RASP_ENTRY();
1164 _RASP_CHECK(u32RASPEng);
1165
1166 if(pfCallback == NULL)
1167 {
1168 _RASP_RETURN(FALSE);
1169 }
1170 _ndsrasp_cb = pfCallback;
1171 _RASP_RETURN(TRUE);
1172 }
1173
1174
NDS_RASP_SetPacketMode(MS_U32 u32RASPEng,NDSRASP_RecType eRecType,RASP_OUTSIZE_e eOutSize)1175 MS_U32 NDS_RASP_SetPacketMode(MS_U32 u32RASPEng, NDSRASP_RecType eRecType, RASP_OUTSIZE_e eOutSize)
1176 {
1177 DRVRASP_DBG(RASP_DBGLV_INFO, "RaspEng = %x, eRecType = %d, eOutSize = %d\n",u32RASPEng, eRecType, eOutSize);
1178
1179 _RASP_ENTRY();
1180 _RASP_CHECK(u32RASPEng);
1181
1182 MS_BOOL b192 = TRUE;
1183
1184 if(eOutSize == RASP_OUT_188)
1185 b192 = FALSE;
1186
1187 switch (eRecType)
1188 {
1189 case STR2MIU:
1190 HAL_NDSRASP_SetStrPacketMode(u32RASPEng, b192);
1191 break;
1192 case PAYLOAD2MIU:
1193 HAL_NDSRASP_SetPayloadPacketMode(u32RASPEng, !b192);
1194 break;
1195 case ECM2MIU:
1196 HAL_NDSRASP_SetECMPacketMode(u32RASPEng, !b192);
1197 break;
1198
1199 default:
1200 DRVRASP_DBG(RASP_DBGLV_ERR, "Wrong eRecType\n");
1201 break;
1202 }
1203 _RASP_RETURN(TRUE);
1204 }
1205
NDS_RASP_SetBufInfo(MS_U32 u32RASPEng,NDSRASP_RecType eRecType,MS_PHYADDR u32BufStart0,MS_PHYADDR u32BufStart1,MS_U32 u32BufSize0,MS_U32 u32BufSize1)1206 MS_U32 NDS_RASP_SetBufInfo(MS_U32 u32RASPEng, NDSRASP_RecType eRecType, MS_PHYADDR u32BufStart0, MS_PHYADDR u32BufStart1, MS_U32 u32BufSize0, MS_U32 u32BufSize1)
1207 {
1208 DRVRASP_DBG(RASP_DBGLV_INFO, "RaspEng = %x, eRecType = %d, StartAddr0 = %x, BufSize0 = %x, StartAddr1 = %x, BufSize1 = %x\n",u32RASPEng,eRecType,u32BufStart0,u32BufSize0,u32BufStart1,u32BufSize1);
1209 _RASP_ENTRY();
1210 _RASP_CHECK(u32RASPEng);
1211
1212 switch (eRecType)
1213 {
1214 case STR2MIU:
1215 HAL_RASP_SetPVRDstBuf(u32RASPEng, u32BufStart0,(u32BufStart0 + u32BufSize0), u32BufStart1, (u32BufStart1 + u32BufSize1));
1216 break;
1217
1218 case PAYLOAD2MIU:
1219 HAL_RASP_SetPayloadDstBuf(u32RASPEng, u32BufStart0,
1220 (u32BufStart0 + u32BufSize0),
1221 (u32BufStart0 + 2*u32BufSize0),
1222 u32BufStart1,
1223 (u32BufStart1 + u32BufSize1),
1224 (u32BufStart1 + 2*u32BufSize1)
1225 );
1226 break;
1227
1228 case ECM2MIU:
1229 HAL_RASP_SetECMDstBuf(u32RASPEng, (u32BufStart0) ,
1230 (u32BufStart0 + u32BufSize0),
1231 (u32BufStart0 + 2*u32BufSize0)
1232 );
1233 break;
1234 default:
1235 break;
1236 }
1237
1238 _RASP_RETURN(TRUE);
1239 }
1240
1241
1242 //this function needs to check pid filter does open this pid or not....
NDS_RASP_SetECMPid(MS_U32 u32RASPEng,MS_U16 u16Fltid,MS_U16 u16Pid)1243 MS_U32 NDS_RASP_SetECMPid(MS_U32 u32RASPEng, MS_U16 u16Fltid, MS_U16 u16Pid)
1244 {
1245 DRVRASP_DBG(RASP_DBGLV_INFO, "RaspEng = %x, u16Fltid = %x, u16Pid = %x\n",u32RASPEng, u16Fltid, u16Pid);
1246
1247 _RASP_ENTRY();
1248 _RASP_CHECK(u32RASPEng);
1249
1250 HAL_NDSRASP_SetEcmPidflt(u32RASPEng,u16Fltid,u16Pid);
1251
1252 //MS_U16 ReadBackPid;
1253 //HAL_NDSRASP_ReadEcmPidflt(u32RASPEng,u16Fltid,&ReadBackPid);
1254 //DRVRASP_DBG(RASP_DBGLV_INFO, "Read Back ECM Pid = %x\n",ReadBackPid);
1255 _RASP_RETURN(TRUE);
1256 }
1257
NDS_RASP_SetRecordTimeStamp(MS_U32 u32RASPEng,MS_U32 u32Stamp)1258 MS_U32 NDS_RASP_SetRecordTimeStamp(MS_U32 u32RASPEng, MS_U32 u32Stamp)
1259 {
1260 DRVRASP_DBG(RASP_DBGLV_INFO, "RaspEng = %x, u32Stamp = %x\n",u32RASPEng, u32Stamp);
1261
1262 _RASP_ENTRY();
1263 _RASP_CHECK(u32RASPEng);
1264
1265 HAL_NDSRASP_SetPVRTimeStamp(u32RASPEng, u32Stamp);
1266
1267 _RASP_RETURN(TRUE);
1268 }
1269
NDS_RASP_GetRecordTimeStamp(MS_U32 u32RASPEng,MS_U32 * u32Stamp)1270 MS_U32 NDS_RASP_GetRecordTimeStamp(MS_U32 u32RASPEng, MS_U32* u32Stamp)
1271 {
1272 //_RASP_CHECK(u32RASPEng);
1273 *u32Stamp = HAL_NDSRASP_GetPVRTimeStamp(u32RASPEng);
1274 return TRUE;
1275 }
1276
NDS_RASP_SetECMTimeStamp(MS_U32 u32RASPEng,MS_U32 u32Stamp)1277 MS_U32 NDS_RASP_SetECMTimeStamp(MS_U32 u32RASPEng, MS_U32 u32Stamp)
1278 {
1279 DRVRASP_DBG(RASP_DBGLV_INFO, "RaspEng = %x, u32Stamp = %x\n",u32RASPEng, u32Stamp);
1280
1281 _RASP_ENTRY();
1282 _RASP_CHECK(u32RASPEng);
1283
1284 HAL_NDSRASP_SetECMTimeStamp(u32RASPEng, u32Stamp);
1285
1286 _RASP_RETURN(TRUE);
1287 }
1288
NDS_RASP_GetECMTimeStamp(MS_U32 u32RASPEng,MS_U32 * u32Stamp)1289 MS_U32 NDS_RASP_GetECMTimeStamp(MS_U32 u32RASPEng, MS_U32* u32Stamp)
1290 {
1291 //_RASP_CHECK(u32RASPEng);
1292 *u32Stamp = HAL_NDSRASP_GetECMTimeStamp(u32RASPEng);
1293 return TRUE;
1294 }
1295
NDS_RASP_TimeStampSelRecordStampSrc(MS_U32 u32RASPEng,MS_BOOL bLocal)1296 MS_U32 NDS_RASP_TimeStampSelRecordStampSrc(MS_U32 u32RASPEng, MS_BOOL bLocal)
1297 {
1298 //not implement
1299 return TRUE;
1300 }
1301
NDS_RASP_GetCurrentPktStatus(MS_U32 u32RASPEng,MS_U32 * u32PktStamp,MS_U32 * u32PktNumber)1302 MS_U32 NDS_RASP_GetCurrentPktStatus(MS_U32 u32RASPEng, MS_U32* u32PktStamp, MS_U32* u32PktNumber)
1303 {
1304 *u32PktStamp = HAL_NDSRASP_GetPktTimer(u32RASPEng);
1305 *u32PktNumber = HAL_NDSRASP_GetPktNum(u32RASPEng);
1306 return TRUE;
1307 }
1308
1309 #if 0 //Migrate to RASP_FlowSet
1310 MS_U32 NDS_RASP_SetTSIF(MS_U32 u32RASPEng, MS_BOOL bPara, MS_BOOL bExtSync, MS_BOOL bDataSWP)
1311 {
1312 _RASP_ENTRY();
1313
1314 _RASP_CHECK(u32RASPEng);
1315 HAL_NDSRASP_SetTSIF(u32RASPEng, bPara, bExtSync, bDataSWP);
1316 _RASP_RETURN(TRUE);
1317 }
1318 #endif
1319
NDS_RASP_GetTSIFStatus(MS_U32 u32RASPEng,MS_BOOL * pbExtSyc,MS_BOOL * pbParl,MS_BOOL * pbDataSWP)1320 MS_U32 NDS_RASP_GetTSIFStatus(MS_U32 u32RASPEng, MS_BOOL* pbExtSyc, MS_BOOL* pbParl, MS_BOOL *pbDataSWP)
1321 {
1322 _RASP_ENTRY();
1323 _RASP_CHECK(u32RASPEng);
1324 // HAL_NDSRASP_GetTSIF(u32RASPEng, pbParl, pbExtSyc, pbDataSWP);
1325 _RASP_RETURN(TRUE);
1326 }
1327
NDS_RASP_LiveSrcConvert(RASP_FLOW_INPUT eSource)1328 RASP_LIVEIN_SRC_e NDS_RASP_LiveSrcConvert(RASP_FLOW_INPUT eSource)
1329 {
1330 RASP_LIVEIN_SRC_e eSrc = RASP_SRC_TS0;
1331
1332 switch(eSource)
1333 {
1334 case RASP_FLOW_INPUT_DEMOD0:
1335 eSrc = RASP_SRC_DEMOD0;
1336 break;
1337
1338 case RASP_FLOW_INPUT_DEMOD1:
1339 eSrc = RASP_SRC_DEMOD1;
1340 break;
1341
1342 case RASP_FLOW_INPUT_TS0:
1343 eSrc = RASP_SRC_TS0;
1344 break;
1345
1346 case RASP_FLOW_INPUT_TS1:
1347 eSrc = RASP_SRC_TS1;
1348 break;
1349
1350 case RASP_FLOW_INPUT_TS2:
1351 eSrc = RASP_SRC_TS2;
1352 break;
1353
1354 case RASP_FLOW_INPUT_TS3:
1355 eSrc = RASP_SRC_TS3;
1356 break;
1357
1358 case RASP_FLOW_INPUT_TS4:
1359 eSrc = RASP_SRC_TS4;
1360 break;
1361
1362 case RASP_FLOW_INPUT_TS5:
1363 eSrc = RASP_SRC_TS5;
1364 break;
1365
1366 case RASP_FLOW_INPUT_TS6:
1367 eSrc = RASP_SRC_TS6;
1368 break;
1369
1370 default:
1371 eSrc = RASP_SRC_TS0;
1372 break;
1373 }
1374
1375
1376 return eSrc;
1377 }
1378
NDS_RASP_FlowSet(MS_U32 rasp_eng,RASP_FLOW_INPUT eSource,RASP_FLOW_OUTPUT eDest,MS_BOOL bPara,MS_BOOL bExtSync,MS_BOOL bDataSWP,RASP_INPUTSIZE_e eMode)1379 MS_BOOL NDS_RASP_FlowSet(MS_U32 rasp_eng, RASP_FLOW_INPUT eSource, RASP_FLOW_OUTPUT eDest, MS_BOOL bPara, MS_BOOL bExtSync, MS_BOOL bDataSWP, RASP_INPUTSIZE_e eMode )
1380 {
1381 MS_U8 u8pLen=188;
1382
1383
1384 if (eMode==RASP_IN_188){
1385 u8pLen = 188;
1386 }
1387 else if (eMode==RASP_IN_192){
1388 u8pLen = 192;
1389 }
1390
1391 DRVRASP_DBG(RASP_DBGLV_INFO, "Input packet Size = %x\n", u8pLen);
1392 DRVRASP_DBG(RASP_DBGLV_DEBUG, "rasp_eng = %x, eSource = %d, bPara = %d, eMode = %d\n", rasp_eng, eSource, bPara, eMode );
1393
1394 if (eSource==RASP_FLOW_INPUT_MEM)
1395 {
1396 HAL_NDSRASP_SetFileinConfig(rasp_eng, TRUE, 6); // filein en, blocklevel
1397 HAL_NDSRASP_FileIn_Init(rasp_eng, u8pLen); //filein bank. reset, chunk_size, auto flush
1398 }
1399 else //LIVEIN
1400 {
1401 HAL_NDSRASP_SetTSIF(rasp_eng, bPara, bExtSync, bDataSWP); // rasp_ctrl0, TSIF
1402 HAL_NDSRASP_SetFileinConfig(rasp_eng, FALSE, 0); // filein dis, blocklevel
1403 HAL_NDSRASP_LiveIn_Init(rasp_eng, u8pLen); //filein bank. reset, chunk_size, auto flush
1404
1405 HAL_NDSRASP_Livein_Config(rasp_eng, NDS_RASP_LiveSrcConvert(eSource));
1406 }
1407 return TRUE;
1408 }
1409
1410
1411
NDS_RASP_AllocFlt(MS_U32 u32RASPEng,MS_U32 * pu16PidFltId)1412 MS_U32 NDS_RASP_AllocFlt(MS_U32 u32RASPEng, MS_U32 *pu16PidFltId)
1413 {
1414 DRVRASP_DBG(RASP_DBGLV_INFO, "RaspEng = %x\n",u32RASPEng);
1415
1416 _RASP_ENTRY();
1417 _RASP_CHECK(u32RASPEng);
1418 MS_U16 i = 0;
1419
1420 for (i = RASP_PIDFLT_START_NUM ; i < RASP_PIDFLT_END_NUM ; i++)
1421 {
1422 if (_prasp_res->_RASPState[u32RASPEng][i]._RASP_FltState == E_DRVRASP_FLT_STATE_FREE)
1423 {
1424 _prasp_res->_RASPState[u32RASPEng][i]._RASP_FltState = E_DRVRASP_FLT_STATE_ALLOC;
1425 *pu16PidFltId = i;
1426 break;
1427 }
1428 }
1429
1430 if (i == RASP_PIDFLT_END_NUM)
1431 {
1432 //RASP_ASSERT(0, OSAL_TSP_Print("[TSP_ERROR][%06d] No free fitler found 0x%02lx\n", __LINE__, i));
1433 _RASP_RETURN(FALSE);
1434 }
1435
1436 _RASP_RETURN(TRUE);
1437 }
1438
NDS_RASP_FreeFlt(MS_U32 u32RASPEng,MS_U32 u32PidFltId)1439 MS_U32 NDS_RASP_FreeFlt(MS_U32 u32RASPEng, MS_U32 u32PidFltId)
1440 {
1441 DRVRASP_DBG(RASP_DBGLV_INFO, "RaspEng = %x, u32PidFltId = %x\n",u32RASPEng,u32PidFltId);
1442
1443 _RASP_ENTRY();
1444 _RASP_CHECK(u32RASPEng);
1445
1446 if(u32PidFltId >= RASP_PIDFLT_END_NUM)
1447 {
1448 _RASP_RETURN(FALSE);
1449 }
1450
1451 HAL_NDSRASP_SetPidflt(u32RASPEng, u32PidFltId, DRVRASP_PID_NULL);
1452 _prasp_res->_RASPState[u32RASPEng][u32PidFltId]._RASP_FltState = E_DRVRASP_FLT_STATE_FREE;
1453 _RASP_RETURN(TRUE);
1454 }
1455
1456
NDS_RASP_AllocECMFlt(MS_U32 u32RASPEng,MS_U16 * pu16ECMFltId)1457 MS_U32 NDS_RASP_AllocECMFlt(MS_U32 u32RASPEng, MS_U16 *pu16ECMFltId)
1458 {
1459 DRVRASP_DBG(RASP_DBGLV_INFO, "RaspEng = %x\n",u32RASPEng);
1460
1461 _RASP_ENTRY();
1462 _RASP_CHECK(u32RASPEng);
1463 MS_U16 i = 0;
1464
1465 for (i = RASP_ECMFLT_START_NUM ; i < RASP_ECMFLT_END_NUM ; i++)
1466 {
1467 if (_prasp_res->_RASPState[u32RASPEng][i]._RASP_ECMFltState == E_DRVRASP_FLT_STATE_FREE)
1468 {
1469 _prasp_res->_RASPState[u32RASPEng][i]._RASP_ECMFltState = E_DRVRASP_FLT_STATE_ALLOC;
1470 *pu16ECMFltId = i;
1471 break;
1472 }
1473 }
1474
1475 if (i == RASP_ECMFLT_END_NUM)
1476 {
1477 DRVRASP_DBG(RASP_DBGLV_ERR, "[ERROR][%d] No free fitler found 0x%x\n", __LINE__, (MS_U32)i);
1478 _RASP_RETURN(FALSE);
1479 }
1480
1481 DRVRASP_DBG(RASP_DBGLV_INFO, "ECM Flt ID = %x\n",(MS_U32)*pu16ECMFltId);
1482
1483 _RASP_RETURN(TRUE);
1484 }
1485
NDS_RASP_FreeECMFlt(MS_U32 u32RASPEng,MS_U16 u16ECMFltId)1486 MS_U32 NDS_RASP_FreeECMFlt(MS_U32 u32RASPEng, MS_U16 u16ECMFltId)
1487 {
1488 DRVRASP_DBG(RASP_DBGLV_INFO, "RaspEng = %x, u32ECMFltId = %x\n",u32RASPEng,(MS_U32)u16ECMFltId);
1489
1490 _RASP_ENTRY();
1491 _RASP_CHECK(u32RASPEng);
1492
1493 if(u16ECMFltId >= RASP_ECMFLT_END_NUM)
1494 {
1495 _RASP_RETURN(FALSE);
1496 }
1497
1498 HAL_NDSRASP_SetPidflt(u32RASPEng, u16ECMFltId, DRVRASP_PID_NULL);
1499 _prasp_res->_RASPState[u32RASPEng][u16ECMFltId]._RASP_ECMFltState = E_DRVRASP_FLT_STATE_FREE;
1500 _RASP_RETURN(TRUE);
1501 }
1502
NDS_RASP_SetPid(MS_U32 u32RASPEng,MS_U16 u16Fltid,MS_U16 u16Pid)1503 MS_U32 NDS_RASP_SetPid(MS_U32 u32RASPEng, MS_U16 u16Fltid, MS_U16 u16Pid)
1504 {
1505 DRVRASP_DBG(RASP_DBGLV_INFO, "RaspEng = %x, u16Fltid = %x, u16Pid = %x\n",u32RASPEng,u16Fltid,u16Pid);
1506
1507 _RASP_ENTRY();
1508 _RASP_CHECK(u32RASPEng);
1509
1510 HAL_NDSRASP_SetPidflt(u32RASPEng, u16Fltid, u16Pid);
1511 _RASP_RETURN(TRUE);
1512 }
1513
NDS_RASP_GetPid(MS_U32 u32RASPEng,MS_U16 u16Fltid,MS_U16 * pu16Pid)1514 MS_U32 NDS_RASP_GetPid(MS_U32 u32RASPEng, MS_U16 u16Fltid, MS_U16 *pu16Pid)
1515 {
1516 DRVRASP_DBG(RASP_DBGLV_INFO, "RaspEng = %x, u16Fltid = %x\n",u32RASPEng,u16Fltid);
1517
1518 _RASP_ENTRY();
1519 _RASP_CHECK(u32RASPEng);
1520
1521 HAL_NDSRASP_GetPidflt(u32RASPEng, u16Fltid, pu16Pid);
1522
1523 DRVRASP_DBG(RASP_DBGLV_INFO, "Pid = %x\n",*pu16Pid);
1524 _RASP_RETURN(TRUE);
1525 }
1526
NDS_RASP_GetFileinEnable(MS_U32 u32RASPEng,MS_BOOL * bEn)1527 MS_U32 NDS_RASP_GetFileinEnable(MS_U32 u32RASPEng, MS_BOOL* bEn)
1528 {
1529 _RASP_ENTRY();
1530 _RASP_CHECK(u32RASPEng);
1531
1532 *bEn = HAL_NDSRASP_GetFileinStart(u32RASPEng);
1533
1534 _RASP_RETURN(TRUE);
1535 }
1536
NDS_RASP_GetCap(NDSRASP_Cap eCap,void * pOutput)1537 MS_U32 NDS_RASP_GetCap(NDSRASP_Cap eCap, void* pOutput)
1538 {
1539 *((MS_U32*)pOutput) = 0;
1540
1541 switch (eCap)
1542 {
1543 case E_NDSRASP_CAP_RESOURCE_SIZE:
1544 *((MS_U32*)pOutput) = sizeof(RASP_RESOURCE_PRIVATE);
1545 return TRUE;
1546 case E_NDSRASP_CAP_FILTER_NUM:
1547 case E_NDSRASP_CAP_FILTER_PVR_NUM:
1548 *((MS_U32*)pOutput) = RASP_PIDFLT_NUM_ALL;
1549 return TRUE;
1550 case E_NDSRASP_CAP_PVR_ALIGN:
1551 *((MS_U32*)pOutput) = 16;
1552 return TRUE;
1553 case E_NDSRASP_CAP_RASP_NUM:
1554 *((MS_U32*)pOutput) = RASP_NUM;
1555 return TRUE;
1556 case E_NDSRASP_CAP_EVENT_FIFO_DEPTH:
1557 return RASP_EVENT_FIFO_DEPTH;
1558 case E_NDSRASP_CAP_EVENT_NUM:
1559 return RASP_EVENT_NUM;
1560 default:
1561 return DRVRASP_INVALID_PARAM;
1562 }
1563 }
1564
1565
NDS_RASP_SetEventMask(MS_U32 u32RASPEng,MS_U16 u16Flt,MS_U32 u32Event)1566 MS_U32 NDS_RASP_SetEventMask(MS_U32 u32RASPEng, MS_U16 u16Flt, MS_U32 u32Event)
1567 {
1568 DRVRASP_DBG(RASP_DBGLV_INFO, "RaspEng = %x, u16Flt = %x, u32Event = %x\n",u32RASPEng, u16Flt, u32Event);
1569
1570 _RASP_ENTRY();
1571 _RASP_CHECK(u32RASPEng);
1572
1573 HAL_NDSRASP_SetEventMask(u32RASPEng, u16Flt, u32Event);
1574
1575 _RASP_RETURN(TRUE);
1576 }
1577
NDS_RASP_SetWatermark(MS_U32 u32RASPEng,WATERMARK_TYPE WType,MS_BOOL bEnable)1578 MS_U32 NDS_RASP_SetWatermark(MS_U32 u32RASPEng, WATERMARK_TYPE WType, MS_BOOL bEnable)
1579 {
1580 DRVRASP_DBG(RASP_DBGLV_INFO, "RaspEng = %x, WType = %d, bEnable = %d\n",u32RASPEng, WType, bEnable);
1581
1582 _RASP_ENTRY();
1583 _RASP_CHECK(u32RASPEng);
1584
1585 if(WType == EVENT_WATERMARK)
1586 {
1587 //HAL_NDSRASP_SetEventWaterMark(u32RASPEng, 0xf); //TPE team request, separate API
1588 HAL_NDSRASP_EVENT_EventWM_Enable(u32RASPEng, bEnable);
1589 }
1590 else if(WType == TIMER_WATERMARK)
1591 {
1592 //HAL_NDSRASP_SetTimerWaterMark(u32RASPEng, 2); //TPE team request, separate API
1593 HAL_NDSRASP_EVENT_TimeWM_Enable(u32RASPEng, bEnable);
1594 }
1595
1596 //HAL_NDSRASP_SetEventMask(u32RASPEng, u16Flt, u32Event);
1597
1598 _RASP_RETURN(TRUE);
1599 }
1600
NDS_RASP_SetEvent_Threshold(MS_U32 u32RASPEng,MS_U8 u8Threshold)1601 MS_BOOL NDS_RASP_SetEvent_Threshold(MS_U32 u32RASPEng, MS_U8 u8Threshold /*Maximum value is 31*/)
1602 {
1603 DRVRASP_DBG(RASP_DBGLV_INFO, "RaspEng [%x], Event Threshold [%x]\n", u32RASPEng, u8Threshold);
1604
1605 if (u8Threshold <= 31 )
1606 {
1607 return HAL_NDSRASP_EVENT_SetEventThreshold(u32RASPEng, (MS_U32)u8Threshold);
1608 }
1609
1610 DRVRASP_DBG(RASP_DBGLV_ERR, "Threshold exceeds\n");
1611 return FALSE;
1612
1613 }
1614
NDS_RASP_SetTime_Timeout(MS_U32 u32RASPEng,TIME_WATERMARK_e timeout)1615 MS_BOOL NDS_RASP_SetTime_Timeout(MS_U32 u32RASPEng, TIME_WATERMARK_e timeout)
1616 {
1617 DRVRASP_DBG(RASP_DBGLV_INFO, "RaspEng [%x], Event Threshold [%x]\n", u32RASPEng, timeout);
1618 return HAL_NDSRASP_EVENT_SetTimerThreshold(u32RASPEng, (MS_U16)timeout );
1619 }
1620
NDS_RASP_SetPayloadMask(MS_U32 u32RASPEng,MS_U16 u16Flt,MS_U32 u32Payload)1621 MS_U32 NDS_RASP_SetPayloadMask(MS_U32 u32RASPEng, MS_U16 u16Flt, MS_U32 u32Payload)
1622 {
1623 _RASP_ENTRY();
1624 _RASP_CHECK(u32RASPEng);
1625
1626 HAL_NDSRASP_SetPayloadMask(u32RASPEng, u16Flt, u32Payload);
1627
1628 _RASP_RETURN(TRUE);
1629 }
1630
NDS_RASP_SetPayloadTimeStamp(MS_U32 u32RASPEng,MS_U32 u32TimeStamp)1631 MS_U32 NDS_RASP_SetPayloadTimeStamp(MS_U32 u32RASPEng , MS_U32 u32TimeStamp)
1632 {
1633 DRVRASP_DBG(RASP_DBGLV_INFO, "RaspEng = %x, u32TimeStamp = %x\n",u32RASPEng, u32TimeStamp);
1634
1635 _RASP_ENTRY();
1636 _RASP_CHECK(u32RASPEng);
1637
1638 HAL_NDSRASP_SetPayloadTimeStamp(u32RASPEng,u32TimeStamp);
1639 _RASP_RETURN(TRUE);
1640 }
1641
NDS_RASP_GetPayloadTimeStamp(MS_U32 u32RASPEng,MS_U32 * pu32TimeStamp)1642 MS_U32 NDS_RASP_GetPayloadTimeStamp(MS_U32 u32RASPEng , MS_U32 *pu32TimeStamp)
1643 {
1644 DRVRASP_DBG(RASP_DBGLV_INFO, "RaspEng = %x\n",u32RASPEng);
1645
1646 _RASP_ENTRY();
1647 _RASP_CHECK(u32RASPEng);
1648
1649 *pu32TimeStamp = HAL_NDSRASP_GetPayloadTimeStamp(u32RASPEng);
1650 DRVRASP_DBG(RASP_DBGLV_INFO, "TimeStamp = %x\n",*pu32TimeStamp);
1651 _RASP_RETURN(TRUE);
1652 }
1653
1654 #if 0 //move to NDS_RASP_SetPacketMode
1655 MS_U32 NDS_RASP_SetPayloadPacketMode(MS_U32 u32RASPEng, MS_BOOL bDisable192)
1656 {
1657 DRVRASP_DBG(RASP_DBGLV_INFO, "RaspEng = %x\n",u32RASPEng);
1658
1659 _RASP_ENTRY();
1660 _RASP_CHECK(u32RASPEng);
1661
1662 //If want to disable 192 mode--> TRUE
1663 //If want to enable 192 mode--> FALSE
1664 HAL_NDSRASP_SetPayloadPacketMode(u32RASPEng, bDisable192);
1665
1666 _RASP_RETURN(TRUE);
1667 }
1668 #endif
1669
NDS_RASP_SetDataSwap(MS_U32 u32RASPEng,MS_BOOL bEn)1670 MS_U32 NDS_RASP_SetDataSwap(MS_U32 u32RASPEng, MS_BOOL bEn)
1671 {
1672 _RASP_ENTRY();
1673 _RASP_CHECK(u32RASPEng);
1674 HAL_NDSRASP_SetDataSwap(u32RASPEng, bEn);
1675 _RASP_RETURN(TRUE);
1676 }
1677
NDS_RASP_CallbackSize(MS_U32 u32RASPEng,MS_U32 * pu32CallbackSize,MS_BOOL bSet)1678 MS_U32 NDS_RASP_CallbackSize(MS_U32 u32RASPEng, MS_U32* pu32CallbackSize, MS_BOOL bSet)
1679 {
1680 _RASP_ENTRY();
1681 _RASP_CHECK(u32RASPEng);
1682 #ifdef PVR_CALLBACK_BY_SIZE_ENABLE
1683 if(bSet)
1684 {
1685 HAL_NDSRASP_SetCallbackSize(u32RASPEng, *pu32CallbackSize);
1686 if(*pu32CallbackSize < CALLBACK_SIZE_MIN)
1687 {
1688 HAL_NDSRASP_INT_Disable(u32RASPEng, RASP_INT_CALLBACK_BY_SIZE);
1689 }
1690 else
1691 {
1692 if(_prasp_res->_RASPCallback[u32RASPEng])
1693 HAL_NDSRASP_INT_Enable(u32RASPEng, RASP_INT_CALLBACK_BY_SIZE);
1694 }
1695 }
1696 else
1697 *pu32CallbackSize = HAL_NDSRASP_GetCallbackSize(u32RASPEng);
1698 #endif
1699
1700 _RASP_RETURN(TRUE);
1701 }
1702
NDS_PROC_RASP_PVR_SizeMet(MS_U32 u32RASPEng)1703 MS_U32 NDS_PROC_RASP_PVR_SizeMet(MS_U32 u32RASPEng)
1704 {
1705 static DrvRASP_Msg stMsg;
1706 _RASP_CHECK(u32RASPEng);
1707 if(_prasp_res->_RASPEvtNotify[u32RASPEng] && _prasp_res->_RASPCallback[u32RASPEng])
1708 {
1709 if(_prasp_res->_RASPEvtNotify[u32RASPEng] & E_DRVRASP_EVENT_CALLBACK_SIZE_MET)
1710 {
1711 stMsg.u8PVREngNum = u32RASPEng;
1712 _prasp_res->_RASPCallback[u32RASPEng](E_DRVRASP_EVENT_CALLBACK_SIZE_MET, &stMsg);
1713 }
1714 }
1715 return TRUE;
1716 }
1717
NDS_RASP_CallbackIntCheck(MS_U32 u32RASPEng,MS_BOOL * bInterrupted)1718 MS_U32 NDS_RASP_CallbackIntCheck(MS_U32 u32RASPEng, MS_BOOL* bInterrupted)
1719 {//this func may be used in interrupt context , so watch out!!! Here's no synchronization mechanism.
1720 #ifdef PVR_CALLBACK_BY_SIZE_ENABLE
1721 if(!bInterrupted)
1722 return FALSE;
1723 _RASP_CHECK(u32RASPEng);
1724 if(HAL_NDSRASP_INT_GetHW(u32RASPEng) & RASP_INT_CALLBACK_BY_SIZE)
1725 *bInterrupted = TRUE;
1726 else
1727 *bInterrupted = FALSE;
1728 #endif
1729 return TRUE;
1730 }
1731
NDS_RASP_CallbackIntClr(MS_U32 u32RASPEng)1732 MS_U32 NDS_RASP_CallbackIntClr(MS_U32 u32RASPEng)
1733 {//this func may be used in interrupt context , so watch out!!! Here's no synchronization mechanism.
1734 #ifdef PVR_CALLBACK_BY_SIZE_ENABLE
1735 _RASP_CHECK(u32RASPEng);
1736 HAL_NDSRASP_INT_ClrHW(u32RASPEng, RASP_INT_CALLBACK_BY_SIZE);
1737 #endif
1738 return TRUE;
1739 }
1740
1741
NDS_RASP_SetFileIn_Config(MS_U32 RaspEng,MS_U32 StartAddr,MS_U32 FileInSize)1742 MS_U32 NDS_RASP_SetFileIn_Config(MS_U32 RaspEng, MS_U32 StartAddr, MS_U32 FileInSize)
1743 {
1744 DRVRASP_DBG(RASP_DBGLV_INFO,"RaspEng = %x, StartAddr = %x, FileInSize = %x\n",RaspEng,StartAddr,FileInSize);
1745 return HAL_RASP_SetFileIn_Config(RaspEng, StartAddr, FileInSize);
1746 }
1747
NDS_RASP_FileIn_Start(MS_U32 RaspEng)1748 MS_U32 NDS_RASP_FileIn_Start(MS_U32 RaspEng)
1749 {
1750 DRVRASP_DBG(RASP_DBGLV_INFO, "RaspEng = %x\n",RaspEng);
1751
1752 _RASP_ENTRY();
1753 _RASP_CHECK(RaspEng);
1754
1755 _RASP_RETURN(HAL_RASP_FileIn_Start(RaspEng));
1756 }
1757
NDS_RASP_SetFileIn_Timer(MS_U32 RaspEng,MS_U16 u16Timer)1758 MS_U32 NDS_RASP_SetFileIn_Timer(MS_U32 RaspEng, MS_U16 u16Timer)
1759 {
1760 DRVRASP_DBG(RASP_DBGLV_INFO,"RaspEng = %x, u16Timer = %x\n",RaspEng,u16Timer);
1761 return HAL_RASP_SetFileIn_Timer(RaspEng, u16Timer);
1762 }
1763
NDS_RASP_SetFileIn_PktSize(MS_U32 RaspEng,MS_U16 PktSize)1764 MS_U32 NDS_RASP_SetFileIn_PktSize(MS_U32 RaspEng, MS_U16 PktSize)
1765 {
1766 //(Packet Size �V 1) for sync detection in TSIF1
1767 DRVRASP_DBG(RASP_DBGLV_INFO, "RaspEng = %x, PktSize = %x\n", RaspEng,PktSize);
1768 _RASP_ENTRY();
1769 _RASP_CHECK(RaspEng);
1770
1771 _RASP_RETURN(HAL_RASP_SetFileIn_PktSize(RaspEng, PktSize));
1772 }
1773
NDS_RASP_IsFileIn_Done(MS_U32 RaspEng)1774 MS_BOOL NDS_RASP_IsFileIn_Done(MS_U32 RaspEng)
1775 {
1776 DRVRASP_DBG(RASP_DBGLV_INFO, "RaspEng = %x\n", RaspEng);
1777 _RASP_ENTRY();
1778 _RASP_CHECK(RaspEng);
1779 _RASP_RETURN(HAL_RASP_IsFileIn_Done(RaspEng));
1780 }
1781
NDS_RASP_FileIn_Flush(MS_U32 RaspEng)1782 MS_U32 NDS_RASP_FileIn_Flush(MS_U32 RaspEng)
1783 {
1784 DRVRASP_DBG(RASP_DBGLV_INFO, "RaspEng = %x\n", RaspEng);
1785
1786 _RASP_ENTRY();
1787 _RASP_CHECK(RaspEng);
1788
1789 _RASP_RETURN(HAL_RASP_FileIn_Flush(RaspEng));
1790 }
1791
1792 #if 0 //Migrate to RASP_FlowSet
1793 MS_U32 NDS_RASP_FileinInit(MS_U32 u32RASPEng)
1794 {
1795 DRVRASP_DBG(RASP_DBGLV_INFO, "RaspEng = %x\n",u32RASPEng);
1796
1797 _RASP_ENTRY();
1798 _RASP_CHECK(u32RASPEng);
1799
1800 HAL_RASP_FileIn_Init(u32RASPEng);
1801
1802 _RASP_RETURN(TRUE);
1803 }
1804 #endif
1805
1806 //--------------------------------------------------------------------------------------------------
1807 /// FileIn mode bypass timestamp.
1808 /// If 192 byte Filein mode --> bypass=FALSE
1809 /// If 188 byte Filein mode --> NO NEED CALL THIS API
1810 /// @return
1811 //--------------------------------------------------------------------------------------------------
NDS_RASP_FileIn_BypassTimeStamp(MS_U32 u32RASPEng,MS_BOOL bypass)1812 MS_U32 NDS_RASP_FileIn_BypassTimeStamp (MS_U32 u32RASPEng, MS_BOOL bypass)
1813 {
1814 DRVRASP_DBG(RASP_DBGLV_INFO, "RaspEng = %x\n",u32RASPEng);
1815
1816 _RASP_ENTRY();
1817 _RASP_CHECK(u32RASPEng);
1818
1819 HAL_RASP_FileIn_BlockTimeStamp(u32RASPEng, !bypass);
1820
1821 _RASP_RETURN(TRUE);
1822 }
1823
1824 //--------------------------------------------------------------------------------------------------
1825 /// FileIn mode bypass timestamp.
1826 /// If lpcr2 (system 90k counter) is higher than stream timestamp, then packet can output. Otherwise no packet will output.
1827 /// So, the one should set lpcr2 time initial value according to FileIn packet initial timestamp value
1828 /// @return
1829 //--------------------------------------------------------------------------------------------------
NDS_RASP_FileIn_SetPlaybackTimeStamp(MS_U32 u32RASPEng,MS_U32 u32Stamp)1830 MS_U32 NDS_RASP_FileIn_SetPlaybackTimeStamp (MS_U32 u32RASPEng, MS_U32 u32Stamp)
1831 {
1832 DRVRASP_DBG(RASP_DBGLV_INFO, "RaspEng = %x\n",u32RASPEng);
1833
1834 _RASP_ENTRY();
1835 _RASP_CHECK(u32RASPEng);
1836
1837 HAL_RASP_FileIn_SetPlaybackTimeStamp(u32RASPEng, u32Stamp);
1838
1839 _RASP_RETURN(TRUE);
1840 }
1841
NDS_RASP_FileIn_GetPlaybackTimeStamp(MS_U32 u32RASPEng)1842 MS_U32 NDS_RASP_FileIn_GetPlaybackTimeStamp (MS_U32 u32RASPEng)
1843 {
1844 DRVRASP_DBG(RASP_DBGLV_INFO, "RaspEng = %x\n",u32RASPEng);
1845
1846 _RASP_ENTRY();
1847 _RASP_CHECK(u32RASPEng);
1848
1849 _RASP_RETURN( HAL_RASP_FileIn_GetPlaybackTimeStamp(u32RASPEng) );
1850 }
1851
NDS_RASP_FileIn_IsCMDQ_Full(MS_U32 RaspEng)1852 MS_BOOL NDS_RASP_FileIn_IsCMDQ_Full(MS_U32 RaspEng)
1853 {
1854 DRVRASP_DBG(RASP_DBGLV_INFO, "RaspEng = %x\n",RaspEng);
1855
1856 _RASP_ENTRY();
1857 _RASP_CHECK(RaspEng);
1858 _RASP_RETURN( HAL_RASP_FileIn_IsCMDQ_Full(RaspEng) );
1859 }
1860
NDS_RASP_FileIn_IsCMDQ_Empty(MS_U32 RaspEng)1861 MS_BOOL NDS_RASP_FileIn_IsCMDQ_Empty(MS_U32 RaspEng)
1862 {
1863 DRVRASP_DBG(RASP_DBGLV_INFO, "RaspEng = %x\n",RaspEng);
1864
1865 _RASP_ENTRY();
1866 _RASP_CHECK(RaspEng);
1867
1868 _RASP_RETURN( HAL_RASP_FileIn_IsCMDQ_Empty(RaspEng) );
1869 }
1870
NDS_RASP_FileIn_GetCmdQueueLevel(MS_U32 RaspEng,FILEIN_CMDQ_LEVEL * peCMDQLvl)1871 MS_BOOL NDS_RASP_FileIn_GetCmdQueueLevel(MS_U32 RaspEng, FILEIN_CMDQ_LEVEL* peCMDQLvl)
1872 {
1873 DRVRASP_DBG(RASP_DBGLV_INFO, "RaspEng = %x\n",RaspEng);
1874
1875 _RASP_ENTRY();
1876 _RASP_CHECK(RaspEng);
1877 MS_U8 CmdQLevel=0xFF;
1878
1879 /*
1880 cmd_wr_level = 2'b00 //empty
1881 cmd_wr_level = 2'b01 // 25% full
1882 cmd_wr_level = 2'b10 // 50% full
1883 cmd_wr_level = 2'b11 // 75% full
1884 */
1885 HAL_RASP_FileIn_GetCmdQueueLevel( RaspEng, &CmdQLevel);
1886
1887 if (CmdQLevel!=0xFF)
1888 {
1889 *peCMDQLvl = (FILEIN_CMDQ_LEVEL)CmdQLevel;
1890 _RASP_RETURN( TRUE );
1891 }
1892
1893 DRVRASP_DBG(RASP_DBGLV_ERR, "CmdQLevel value ERROR\n");
1894 _RASP_RETURN( FALSE );
1895
1896 }
1897
1898
NDS_RASP_FileIn_GetEmptyNum(MS_U32 RaspEng,MS_U8 * peCMDQCnt)1899 MS_BOOL NDS_RASP_FileIn_GetEmptyNum(MS_U32 RaspEng, MS_U8* peCMDQCnt)
1900 {
1901 DRVRASP_DBG(RASP_DBGLV_INFO, "RaspEng = %x\n",RaspEng);
1902
1903 _RASP_ENTRY();
1904 _RASP_CHECK(RaspEng);
1905 MS_U8 CmdQCnt=0xFF;
1906
1907 /* empty cmd_wr_count */
1908 HAL_RASP_FileIn_GetEmptyNum( RaspEng, &CmdQCnt);
1909
1910 if (CmdQCnt!=0xFF)
1911 {
1912 *peCMDQCnt = CmdQCnt;
1913 _RASP_RETURN( TRUE );
1914 }
1915
1916 DRVRASP_DBG(RASP_DBGLV_ERR, "peCMDQCnt value ERROR\n");
1917 _RASP_RETURN( FALSE );
1918
1919 }
1920
NDS_RASP_FileIn_Timer(MS_U32 RaspEng,MS_BOOL bEnFileInTimer,MS_U16 u16Timer)1921 MS_U32 NDS_RASP_FileIn_Timer(MS_U32 RaspEng, MS_BOOL bEnFileInTimer, MS_U16 u16Timer)
1922 {
1923 DRVRASP_DBG(RASP_DBGLV_INFO, "RaspEng = %x\n",RaspEng);
1924
1925 _RASP_ENTRY();
1926 _RASP_CHECK(RaspEng);
1927
1928 HAL_RASP_FileIn_Timer(RaspEng, bEnFileInTimer, u16Timer);
1929
1930 _RASP_RETURN( TRUE );
1931 }
1932
NDS_RASP_FileIn_Init_TimeStamp(MS_U32 RaspEng,MS_BOOL bResetPacketTimeStamp)1933 MS_BOOL NDS_RASP_FileIn_Init_TimeStamp(MS_U32 RaspEng, MS_BOOL bResetPacketTimeStamp)
1934 {
1935 DRVRASP_DBG(RASP_DBGLV_INFO, "RaspEng = %x\n",RaspEng);
1936
1937 _RASP_ENTRY();
1938 _RASP_CHECK(RaspEng);
1939
1940 HAL_RASP_FileIn_Reset_TStamp(RaspEng, bResetPacketTimeStamp);
1941
1942 _RASP_RETURN( TRUE );
1943 }
1944
NDS_RASP_Reset_EventPktCounter(MS_U32 RaspEng)1945 MS_BOOL NDS_RASP_Reset_EventPktCounter(MS_U32 RaspEng)
1946 {
1947 DRVRASP_DBG(RASP_DBGLV_INFO, "RaspEng = %x\n",RaspEng);
1948
1949 _RASP_ENTRY();
1950 _RASP_CHECK(RaspEng);
1951
1952 HAL_NDSRASP_EVENT_RstCounter(RaspEng);
1953
1954 _RASP_RETURN( TRUE );
1955 }
1956
NDS_RASP_Reset_EventPktTimer(MS_U32 RaspEng)1957 MS_BOOL NDS_RASP_Reset_EventPktTimer(MS_U32 RaspEng)
1958 {
1959 DRVRASP_DBG(RASP_DBGLV_INFO, "RaspEng = %x\n",RaspEng);
1960
1961 _RASP_ENTRY();
1962 _RASP_CHECK(RaspEng);
1963
1964 HAL_NDSRASP_EVENT_RstTimer(RaspEng);
1965
1966 _RASP_RETURN( TRUE );
1967 }
1968
1969 //--------------------------------------------------------------------------------------------------
1970 /// Get Event descriptor from FIFO, intended for polling mode
1971 /// Otherwise use interrupt callback method
1972 /// @return
1973 //--------------------------------------------------------------------------------------------------
NDS_RASP_GetEventDescriptor(MS_U32 RaspEng,NDS_RASP_EVENT * pEventDesc,MS_U32 u32ArraySize)1974 MS_BOOL NDS_RASP_GetEventDescriptor(MS_U32 RaspEng, NDS_RASP_EVENT *pEventDesc, MS_U32 u32ArraySize)
1975 {
1976 DRVRASP_DBG(RASP_DBGLV_INFO, "RaspEng = %x\n",RaspEng);
1977
1978 _RASP_ENTRY();
1979 _RASP_CHECK(RaspEng);
1980
1981 if (pEventDesc)
1982 {
1983 HAL_NDSRASP_EVENT_GetEventDescriptor(RaspEng, (MS_U32 *)pEventDesc, u32ArraySize);
1984 _RASP_RETURN( TRUE );
1985 }
1986 else
1987 {
1988 DRVRASP_DBG(RASP_DBGLV_INFO, "NULL descriptor pointer\n");
1989
1990 }
1991
1992 _RASP_RETURN( FALSE );
1993 }
1994
1995 //--------------------------------------------------------------------------------------------------
1996 /// Get remaining event numbers in event FIFO
1997 /// @return
1998 //--------------------------------------------------------------------------------------------------
NDS_RASP_GetEventNumber(MS_U32 RaspEng)1999 MS_U16 NDS_RASP_GetEventNumber(MS_U32 RaspEng)
2000 {
2001
2002 DRVRASP_DBG(RASP_DBGLV_INFO, "RaspEng = %x\n",RaspEng);
2003
2004 return HAL_NDSRASP_EVENT_GetEventNum(RaspEng);
2005
2006 }
2007
NDS_RASP_SetDbgLevel(MS_U32 level)2008 void NDS_RASP_SetDbgLevel(MS_U32 level)
2009 {
2010 _g32RASPDrvDbgLv = level;
2011 HAL_NDSRASP_SetDbgLevel(level);
2012
2013 }
2014
RaspDemoTest(MS_U32 Addr)2015 void RaspDemoTest(MS_U32 Addr)
2016 {
2017 MS_U32 u32Size = (188 * 10);
2018 printf("enter RaspDemoTest\n");
2019 NDS_RASP_SetDbgLevel(7);
2020 NDS_RASP_Init();
2021
2022 MS_U32 rasp_eng = 0;
2023 HAL_NDSRASP_Rec_PID(0, TRUE);
2024 NDS_RASP_SetPid(0, 0, 0xc1);
2025
2026 NDS_RASP_SetBufInfo(rasp_eng, STR2MIU /*PVR*/, Addr, (Addr + u32Size), u32Size, u32Size);
2027
2028 //payload packetmode, FALSE-->188 byte mode
2029 //NDS_RASP_SetPayloadPacketMode(rasp_eng, TRUE); //payload packet 192/188
2030
2031 NDS_RASP_FlowSet(rasp_eng, RASP_FLOW_INPUT_DEMOD0, 0 /*not implement*/, TRUE, TRUE, FALSE, RASP_IN_188);
2032
2033 }
2034
NDS_RASP_SetExtendConfig(MS_U32 RaspEng,MS_U16 type,MS_U16 extendbytes,MS_U16 syncbyte)2035 MS_BOOL NDS_RASP_SetExtendConfig(MS_U32 RaspEng, MS_U16 type, MS_U16 extendbytes, MS_U16 syncbyte)
2036 {
2037
2038 printf("NDS_RASP_SetExtendConfig, RaspEng = %x\n",RaspEng);
2039 HAL_NDSRASP_SetExtendConfig(RaspEng, type, extendbytes, syncbyte);
2040
2041 return TRUE;
2042 }
2043
2044