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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 //////////////////////////////////////////////////////////////////////////////////////////////////// 96 // 97 // File name: mmfilein.h 98 // Description: Multimedia File In (MMFILEIN) Register Definition 99 // 100 //////////////////////////////////////////////////////////////////////////////////////////////////// 101 102 #ifndef _MMFILEIN_REG_H_ 103 #define _MMFILEIN_REG_H_ 104 105 //-------------------------------------------------------------------------------------------------- 106 // Abbreviation 107 //-------------------------------------------------------------------------------------------------- 108 // Addr Address 109 // Buf Buffer 110 // Clr Clear 111 // CmdQ Command queue 112 // Cnt Count 113 // Ctrl Control 114 // Flt Filter 115 // Hw Hardware 116 // Int Interrupt 117 // Len Length 118 // Ovfw Overflow 119 // Pkt Packet 120 // Rec Record 121 // Recv Receive 122 // Rmn Remain 123 // Reg Register 124 // Req Request 125 // Rst Reset 126 // Scmb Scramble 127 // Sec Section 128 // Stat Status 129 // Sw Software 130 // Ts Transport Stream 131 // MMFI Multi Media File In 132 133 //-------------------------------------------------------------------------------------------------- 134 // Global Definition 135 //-------------------------------------------------------------------------------------------------- 136 #define MMFI_ENGINE_NUM (2UL) 137 138 #define MMFI_PIDFLT_GROUP0 (4UL) // filters reside in upper half of bank MMFI 139 #define MMFI_PIDFLT_GROUP1 (2UL) // filters reside in bottom half of bank MMFI 140 141 #define MMFI_PIDFLT0_NUM (MMFI_PIDFLT_GROUP0 + MMFI_PIDFLT_GROUP1) 142 #define MMFI_PIDFLT1_NUM (MMFI_PIDFLT0_NUM) 143 144 #define MMFI_PIDFLT_NUM_ALL (MMFI_PIDFLT0_NUM+MMFI_PIDFLT1_NUM) 145 146 #define MMFI_PID_NULL 0x1FFFUL 147 148 //------------------------------------------------------------------------------------------------- 149 // Harware Capability 150 //------------------------------------------------------------------------------------------------- 151 152 //------------------------------------------------------------------------------------------------- 153 // Type and Structure 154 //------------------------------------------------------------------------------------------------- 155 156 #define REG_CTRL_BASE_MMFI0 (0x3800UL) // 0xBF800000+(1c00/2)*4 157 #define REG_CTRL_BASE_MMFI1 (0x3880UL) 158 #define REG_CTRL2 (0x3900UL) // MMFI part 2 159 160 typedef struct _REG32 161 { 162 volatile MS_U16 L; 163 volatile MS_U16 empty_L; 164 volatile MS_U16 H; 165 volatile MS_U16 empty_H; 166 } REG32; 167 168 typedef struct _REG16 169 { 170 volatile MS_U16 data; 171 volatile MS_U16 _resv; 172 } REG16; 173 174 typedef struct _REG_Ctrl_MMFI 175 { 176 //---------------------------------------------- 177 // 0xBF802A00 MIPS direct access 178 //---------------------------------------------- 179 // Index(word) CPU(byte) MIPS(0x1500/2+index)*4 180 REG32 PidFlt[4]; // 0xbf803800 0x00 181 #define MMFI_PIDFLT_PID_MASK 0x00001FFFUL 182 #define MMFI_PIDFLT_EN_MASK 0x0007E000UL 183 #define MMFI_PIDFLT_AFIFOB_EN 0x00002000UL 184 #define MMFI_PIDFLT_AFIFO_EN 0x00004000UL 185 #define MMFI_PIDFLT_VFIFO_EN 0x00008000UL 186 #define MMFI_PIDFLT_V3DFIFO_EN 0x00010000UL 187 188 REG32 FileIn_RAddr; // 0xbf803820 0x08 //byte address 189 REG32 FileIn_RNum; // 0xbf803828 0x0a 190 191 REG16 FileIn_Ctrl; // 0xbf803830 0x0c 192 #define MMFI_FILEIN_CTRL_START 0x0001UL 193 #define MMFI_FILEIN_CTRL_DONE 0x0002UL 194 #define MMFI_FILEIN_CTRL_ABORT 0x0010UL 195 #define MMFI_FILEIN_CTRL_MASK 0x0013UL 196 #define MMFI_FILEIN_TIMER_MASK 0xFF00UL 197 #define MMFI_FILEIN_TIMER_SHIFT 8UL 198 199 REG16 CmdQSts; // 0xbf803834 0x0d 200 #define MMFI_CMDQ_SIZE 8UL 201 #define MMFI_CMDQSTS_WRCNT_MASK 0x001FUL 202 #define MMFI_CMDQSTS_FIFO_FULL 0x0040UL 203 #define MMFI_CMDQSTS_FIFO_EMPTY 0x0080UL 204 #define MMFI_CMDQSTS_FIFO_WRLEVEL_MASK 0x0300UL 205 #define MMFI_CMDQSTS_FIFO_WRLEVEL_SHIFT 8UL 206 207 REG32 Cfg; // 0xbf803838 0x0e 208 #define MMFI_CFG_LPCR2_LD 0x00000001UL 209 #define MMFI_CFG_LPCR2_WLD 0x00000002UL 210 #define MMFI_CFG_TEI_SKIP 0x00000004UL 211 #define MMFI_CFG_CLR_PIDFLT_BYTE_CNT 0x00000008UL 212 #define MMFI_CFG_APID_BYPASS 0x00000010UL 213 #define MMFI_CFG_APIDB_BYPASS 0x00000020UL 214 #define MMFI_CFG_VPID_BYPASS 0x00000040UL 215 #define MMFI_CFG_VPID3D_BYPASS 0x00000080UL 216 #define MMFI_CFG_AUD_ERR_EN 0x00000100UL 217 #define MMFI_CFG_AUDB_ERR_EN 0x00000200UL 218 #define MMFI_CFG_VD_ERR_EN 0x00000400UL 219 #define MMFI_CFG_V3D_ERR_EN 0x00000800UL 220 #define MMFI_CFG_APES_ERR_RM_EN 0x00001000UL 221 #define MMFI_CFG_APESB_ERR_RM_EN 0x00002000UL 222 #define MMFI_CFG_VPES_ERR_RM_EN 0x00004000UL 223 #define MMFI_CFG_VPES3D_ERR_RM_EN 0x00008000UL 224 #define MMFI_CFG_CLR_PKT_CNT 0x00010000UL 225 #define MMFI_CFG_DIS_MIU_RQ 0x00020000UL 226 #define MMFI_CFG_RADDR_READ 0x00040000UL 227 #define MMFI_CFG_BYTETIMER_EN 0x00080000UL 228 #define MMFI_CFG_PLY_FILE_INV_EN 0x00100000UL 229 #define MMFI_CFG_DUP_PKT_SKIP 0x00200000UL 230 #define MMFI_CFG_ALT_TS_SIZE 0x00400000UL 231 #define MMFI_CFG_2MI_RPRIORITY 0x00800000UL 232 #define MMFI_CFG_PS_AUD_EN 0x01000000UL 233 #define MMFI_CFG_PS_AUDB_EN 0x02000000UL 234 #define MMFI_CFG_PS_VD_EN 0x04000000UL 235 #define MMFI_CFG_PS_V3D_EN 0x08000000UL 236 #define MMFI_CFG_MEM_TS_ORDER 0x10000000UL 237 #define MMFI_CFG_MEM_TS_DATA_ENDIAN 0x20000000UL 238 #define MMFI_CFG_PKT192_EN 0x40000000UL 239 #define MMFI_CFG_PKT192_BLK_DISABLE 0x80000000UL 240 #define MMFI_CFG_FILEIN_MODE_MASK (MMFI_CFG_APID_BYPASS|MMFI_CFG_APIDB_BYPASS|MMFI_CFG_VPID_BYPASS \ 241 |MMFI_CFG_VPID3D_BYPASS|MMFI_CFG_PS_AUD_EN|MMFI_CFG_PS_AUDB_EN \ 242 |MMFI_CFG_PS_VD_EN|MMFI_CFG_PS_V3D_EN) 243 244 REG32 TsHeader; // 0xbf803840 0x10 245 #define MMFI_HD_CCNT_MASK 0x0000000FUL 246 #define MMFI_HD_AF_MASK 0x00000030UL 247 #define MMFI_HD_AF_SHIFT 4UL 248 #define MMFI_HD_SCRAMBLE_MASK 0x000000C0UL 249 #define MMFI_HD_SCRAMBLE_SHIFT 6UL 250 #define MMFI_HD_PID 0x001FFF00UL 251 #define MMFI_HD_PID_SHIFT 8UL 252 #define MMFI_HD_TS_PRIORITY_MASK 0x00200000UL 253 #define MMFI_HD_TS_PRIORITY_SHIFT 21UL 254 #define MMFI_HD_PAYLOAD_START_FLG_MASK 0x00400000UL 255 #define MMFI_HD_PAYLOAD_START_FLG_SHIFT 22UL 256 #define MMFI_HD_ERR_FLG_MASK 0x00800000UL 257 #define MMFI_HD_ERR_FLG_SHIFT 23UL 258 259 REG16 APid_Status; // 0xbf803848 0x12 260 #define MMFI_APID_MATCHED_MASK 0x00001FFFUL 261 #define MMFI_APID_CHANGE 0x00002000UL 262 REG16 APidB_Status; // 0xbf803848 0x13 263 #define MMFI_APIDB_MATCHED_MASK 0x00001FFFUL 264 #define MMFI_APIDB_CHANGE 0x00002000UL 265 REG16 VPID_Status; // 0xbf803850 0x14 266 #define MMFI_VPID_MATCHED_MASK 0x00001FFFUL 267 #define MMFI_VPID_CHANGE 0x00002000UL 268 REG16 VPID3D_Status; // 0xbf803854 0x15 269 #define MMFI_VPID3D_MATCHED_MASK 0x00001FFFUL 270 #define MMFI_VPID3D_CHANGE 0x00002000UL 271 272 REG32 LPcr2_Buf; // 0xbf803858 0x16 273 REG32 TimeStamp_FIn; // 0xbf803860 0x18 274 275 REG16 SWRst; // 0xbf803868 0x1a 276 #define MMFI_SWRST_MASK 0x07FFUL 277 #define MMFI_SW_RSTZ_MMFILEIN_DISABLE 0x0001UL // low active 278 #define MMFI_RST_WB_DMA0 0x0002UL 279 #define MMFI_RST_CMDQ0 0x0004UL 280 #define MMFI_RST_TSIF0 0x0008UL 281 #define MMFI_RST_WB0 0x0010UL 282 #define MMFI_RST_WB_DMA1 0x0020UL 283 #define MMFI_RST_CMDQ1 0x0040UL 284 #define MMFI_RST_TSIF1 0x0080UL 285 #define MMFI_RST_WB1 0x0100UL 286 #define MMFI_RST_PATH0 0x0200UL 287 #define MMFI_RST_PATH1 0x0400UL 288 #define MMFI_RST_MOBF_MMFI0 0x0800UL 289 #define MMFI_RST_MOBF_MMFI1 0x1000UL 290 #define MMFI_RST_ALL 0x1FFEUL 291 292 REG16 HWInt; // 0xbf80386c 0x1b 293 #define MMFI_HWINT_SRC_MASK 0x00FFUL 294 #define MMFI_HWINT_SRC_FILEIN_DONE1 0x0004UL 295 #define MMFI_HWINT_SRC_FILEIN_DONE0 0x0008UL 296 #define MMFI_HWINT_SRC_VD3D_ERR1 0x0010UL 297 #define MMFI_HWINT_SRC_AUAUB_ERR1 0x0020UL 298 #define MMFI_HWINT_SRC_VD3D_ERR0 0x0040UL 299 #define MMFI_HWINT_SRC_AUAUB_ERR0 0x0080UL 300 #define MMFI_HWINT_STS_MASK 0xFF00UL 301 #define MMFI_HWINT_STS_SHIFT 8UL 302 #define MMFI_HWINT_STS_FILEIN_DONE1 0x0400UL 303 #define MMFI_HWINT_STS_FILEIN_DONE0 0x0800UL 304 #define MMFI_HWINT_STS_VD3D_ERR1 0x1000UL 305 #define MMFI_HWINT_STS_AUAUB_ERR1 0x2000UL 306 #define MMFI_HWINT_STS_VD3D_ERR0 0x4000UL 307 #define MMFI_HWINT_STS_AUAUB_ERR0 0x8000UL 308 309 REG16 PktChkSize; // 0xbf803870 0x1c 310 #define MMFI_PKTCHK_SIZE_MASK 0x00FFUL 311 #define MMFI_SYNC_BYTE_MASK 0xFF00UL 312 #define MMFI_SYNC_BYTE_SHIFT 8UL 313 314 REG16 MOBFKey; // 0xbf803874 0x1d 315 #define MMFI_MOBFKEY_MASK 0x001FUL 316 #define MMFI_FILEIN_CTRL_MOBF_EN 0 //not used 317 318 REG32 RAddr; // 0xbf803878 0x1e 319 #define MMFI_TSP2MI_RADDR_MASK 0x07FFFFFFUL 320 } REG_Ctrl_MMFI; 321 322 // MMFI part 2 323 typedef struct _REG_Ctrl_MMFI2 324 { 325 REG16 RVU_config[2]; // 0x40- 0x41 326 #define MMFI_RVU_PSI_EN 0x0001UL 327 #define MMFI_RVU_TEI_EN 0x0002UL 328 #define MMFI_RVU_ERR_CLR 0x0004UL 329 #define MMFI_RVU_EN 0x0008UL 330 #define MMFI_RVU_TIMESTAMP_EN 0x0010UL 331 REG16 dummy[14]; // 0x42 ~ 0x4F 332 REG16 Cfg2[2]; // 0x50~ 0x51 333 #define MMFI_CFG2_MMFI_27M_EN 0x0001UL 334 #define MMFI_CFG2_TSP_FILEIN_PAUSE_EN 0x0200UL 335 #define MMFI_CFG2_WB_FSRM_RST 0x0400UL 336 #define MMFI_CFG2_FILEIN_MODE_MASK 0 337 338 REG16 MMFI0_APidC_Status; // 0xbf803948 0x52 339 REG16 MMFI0_APidD_Status; // 0xbf80394C 0x53 340 REG16 MMFI1_APidC_Status; // 0xbf803950 0x54 341 REG16 MMFI1_APidD_Status; // 0xbf803954 0x55 342 REG32 PidFlt[MMFI_ENGINE_NUM][MMFI_PIDFLT_GROUP1]; // 0xbf803958 0x56 , MMFI0/1 filter 4~5 343 REG16 MMFI_ats_config[2]; // 0x66~0x67 344 #define MMFI_ATS_MODE 0x0001UL 345 #define MMFI_ATS_OFFSET_EN 0x0002UL 346 #define MMFI_ATS_OFFSET_MASK 0x1F00UL 347 #define MMFI_ATS_OFFSET_SHIFT 8UL 348 } REG_Ctrl_MMFI2; 349 #endif // _MMFILEIN_REG_H_ 350 351