1 //<MStar Software> 2 //****************************************************************************** 3 // MStar Software 4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. 5 // All software, firmware and related documentation herein ("MStar Software") are 6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by 7 // law, including, but not limited to, copyright law and international treaties. 8 // Any use, modification, reproduction, retransmission, or republication of all 9 // or part of MStar Software is expressly prohibited, unless prior written 10 // permission has been granted by MStar. 11 // 12 // By accessing, browsing and/or using MStar Software, you acknowledge that you 13 // have read, understood, and agree, to be bound by below terms ("Terms") and to 14 // comply with all applicable laws and regulations: 15 // 16 // 1. MStar shall retain any and all right, ownership and interest to MStar 17 // Software and any modification/derivatives thereof. 18 // No right, ownership, or interest to MStar Software and any 19 // modification/derivatives thereof is transferred to you under Terms. 20 // 21 // 2. You understand that MStar Software might include, incorporate or be 22 // supplied together with third party`s software and the use of MStar 23 // Software may require additional licenses from third parties. 24 // Therefore, you hereby agree it is your sole responsibility to separately 25 // obtain any and all third party right and license necessary for your use of 26 // such third party`s software. 27 // 28 // 3. MStar Software and any modification/derivatives thereof shall be deemed as 29 // MStar`s confidential information and you agree to keep MStar`s 30 // confidential information in strictest confidence and not disclose to any 31 // third party. 32 // 33 // 4. MStar Software is provided on an "AS IS" basis without warranties of any 34 // kind. Any warranties are hereby expressly disclaimed by MStar, including 35 // without limitation, any warranties of merchantability, non-infringement of 36 // intellectual property rights, fitness for a particular purpose, error free 37 // and in conformity with any international standard. You agree to waive any 38 // claim against MStar for any loss, damage, cost or expense that you may 39 // incur related to your use of MStar Software. 40 // In no event shall MStar be liable for any direct, indirect, incidental or 41 // consequential damages, including without limitation, lost of profit or 42 // revenues, lost or damage of data, and unauthorized system use. 43 // You agree that this Section 4 shall still apply without being affected 44 // even if MStar Software has been modified by MStar in accordance with your 45 // request or instruction for your use, except otherwise agreed by both 46 // parties in writing. 47 // 48 // 5. If requested, MStar may from time to time provide technical supports or 49 // services in relation with MStar Software to you for your use of 50 // MStar Software in conjunction with your or your customer`s product 51 // ("Services"). 52 // You understand and agree that, except otherwise agreed by both parties in 53 // writing, Services are provided on an "AS IS" basis and the warranty 54 // disclaimer set forth in Section 4 above shall apply. 55 // 56 // 6. Nothing contained herein shall be construed as by implication, estoppels 57 // or otherwise: 58 // (a) conferring any license or right to use MStar name, trademark, service 59 // mark, symbol or any other identification; 60 // (b) obligating MStar or any of its affiliates to furnish any person, 61 // including without limitation, you and your customers, any assistance 62 // of any kind whatsoever, or any information; or 63 // (c) conferring any license or right under any intellectual property right. 64 // 65 // 7. These terms shall be governed by and construed in accordance with the laws 66 // of Taiwan, R.O.C., excluding its conflict of law rules. 67 // Any and all dispute arising out hereof or related hereto shall be finally 68 // settled by arbitration referred to the Chinese Arbitration Association, 69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration 70 // Rules of the Association by three (3) arbitrators appointed in accordance 71 // with the said Rules. 72 // The place of arbitration shall be in Taipei, Taiwan and the language shall 73 // be English. 74 // The arbitration award shall be final and binding to both parties. 75 // 76 //****************************************************************************** 77 //<MStar Software> 78 //////////////////////////////////////////////////////////////////////////////// 79 // 80 // Copyright (c) 2010-2012 MStar Semiconductor, Inc. 81 // All rights reserved. 82 // 83 // Unless otherwise stipulated in writing, any and all information contained 84 // herein regardless in any format shall remain the sole proprietary of 85 // MStar Semiconductor Inc. and be kept in strict confidence 86 // ("MStar Confidential Information") by the recipient. 87 // Any unauthorized act including without limitation unauthorized disclosure, 88 // copying, use, reproduction, sale, distribution, modification, disassembling, 89 // reverse engineering and compiling of the contents of MStar Confidential 90 // Information is unlawful and strictly prohibited. MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 //////////////////////////////////////////////////////////////////////////////////////////////////// 96 // 97 // File name: mmfilein.h 98 // Description: Multimedia File In (MMFILEIN) Register Definition 99 // 100 //////////////////////////////////////////////////////////////////////////////////////////////////// 101 102 #ifndef _MMFILEIN_REG_H_ 103 #define _MMFILEIN_REG_H_ 104 105 //-------------------------------------------------------------------------------------------------- 106 // Abbreviation 107 //-------------------------------------------------------------------------------------------------- 108 // Addr Address 109 // Buf Buffer 110 // Clr Clear 111 // CmdQ Command queue 112 // Cnt Count 113 // Ctrl Control 114 // Flt Filter 115 // Hw Hardware 116 // Int Interrupt 117 // Len Length 118 // Ovfw Overflow 119 // Pkt Packet 120 // Rec Record 121 // Recv Receive 122 // Rmn Remain 123 // Reg Register 124 // Req Request 125 // Rst Reset 126 // Scmb Scramble 127 // Sec Section 128 // Stat Status 129 // Sw Software 130 // Ts Transport Stream 131 // MMFI Multi Media File In 132 133 //-------------------------------------------------------------------------------------------------- 134 // Global Definition 135 //-------------------------------------------------------------------------------------------------- 136 #define MMFI_AUDPIDFLT_NUM (2UL) 137 #define MMFI_V3DPIDFLT_NUM (1UL) 138 139 140 #define MMFI_PIDFLT_NUM_ALL (MMFI_AUDPIDFLT_NUM+MMFI_V3DPIDFLT_NUM) 141 142 #define MMFI_PID_NULL 0x1FFFUL 143 144 //------------------------------------------------------------------------------------------------- 145 // Harware Capability 146 //------------------------------------------------------------------------------------------------- 147 148 //------------------------------------------------------------------------------------------------- 149 // Type and Structure 150 //------------------------------------------------------------------------------------------------- 151 152 #define REG_CTRL_BASE_MMFI (0x3800UL) // 0xBF800000+(1c00/2)*4 153 #define REG_CTRL_BASE_MMFI_V3D (0x3880UL) 154 155 typedef struct _REG32_M 156 { 157 volatile MS_U16 L; 158 volatile MS_U16 empty_L; 159 volatile MS_U16 H; 160 volatile MS_U16 empty_H; 161 } REG32_M; 162 163 typedef struct _REG16_M 164 { 165 volatile MS_U16 u16data; 166 volatile MS_U16 _null; 167 } REG16_M; 168 169 170 typedef struct _REG_Ctrl_MMFI 171 { 172 //---------------------------------------------- 173 // 0xBF802A00 MIPS direct access 174 //---------------------------------------------- 175 // Index(word) CPU(byte) MIPS(0x1500/2+index)*4 176 REG32_M PidFlt; // 0xbf803800 0x00 177 #define MMFI_PIDFLT_PID_MASK 0x1FFFUL 178 #define MMFI_PIDFLT_EN_MASK 0xE000UL 179 #define MMFI_PIDFLT_AFIFO_EN 0x4000UL 180 #define MMFI_PIDFLT_VD3D_EN 0x8000UL 181 #define MMFI_PIDFLT_A_MASK 0x0000FFFFUL 182 #define MMFI_PIDFLT_B_MASK 0xFFFF0000UL 183 #define MMFI_PIDFLT_A_SHIFT 0UL 184 #define MMFI_PIDFLT_B_SHIFT 16UL 185 186 REG32_M FileIn_RAddr; // 0xbf803808 0x02 //byte address 187 REG32_M FileIn_RNum; // 0xbf803810 0x04 188 189 REG32_M Ctrl_CmdQSts; // 0xbf803818 0x06 190 #define MMFI_FILEIN_CTRL_MASK 0x000000FFUL 191 #define MMFI_FILEIN_RSTART 0x00000001UL 192 #define MMFI_FILEIN_DONE 0x00000002UL 193 #define MMFI_FILEIN_INIT_TRUST 0x00000004UL 194 #define MMFI_FILEIN_ABORT 0x00000010UL 195 #define MMFI_TIMER_MASK 0x0000FF00UL 196 #define MMFI_TIMER_SHIFT 8UL 197 198 #define MMFI_CMQ_STATUS_SHIFT 16UL 199 #define MMFI_CMDQ_SIZE 8UL 200 #define MMFI_CMQ_WR_CNT_MASK 0x001F0000UL 201 #define MMFI_CMQ_STATUS_FIFO_FULL 0x00400000UL 202 #define MMFI_CMQ_STATUS_FIFO_EMPTY 0x00800000UL 203 #define MMFI_CMQ_STATU_WR_LEVEL_MASK 0x03000000UL 204 #define MMFI_CMQ_STATU_WR_LEVEL_SHIFT 24UL 205 206 REG32_M Cfg; // 0xbf803820 0x08 207 #define MMFI_LPCR2_LOAD 0x00000001UL 208 #define MMFI_LPCR2_WLD 0x00000002UL 209 #define MMFI_TEI_SKIP_PKTF 0x00000004UL 210 #define MMFI_CLR_PIDFLT_BYTE_CNT 0x00000008UL 211 #define MMFI_PKT192_BLK_DISABLE 0x00000010UL 212 #define MMFI_PKT192_EN 0x00000020UL 213 #define MMFI_APID_BYPASS 0x00000040UL 214 #define MMFI_VPID3D_BYPASS MMFI_APID_BYPASS 215 #define MMFI_VID3D_ERR_EN 0x00000080UL 216 #define MMFI_AUD_ERR_EN 0x00000100UL 217 #define MMFI_MEM_TSDATA_ENDIAN_V3D MMFI_AUD_ERR_EN 218 #define MMFI_AUDB_ERR_EN 0x00000200UL 219 #define MMFI_MEM_TSORDER_ENDIAN_V3D MMFI_AUDB_ERR_EN 220 #define MMFI_APES_ERR_RM_EN 0x00000400UL 221 #define MMFI_MEM_TSDATA_ENDIAN_AU 0x00001000UL 222 #define MMFI_MEM_TSORDER_ENDIAN_AU 0x00002000UL 223 #define MMFI_WBDMA_ECO 0x00010000UL 224 #define MMFI_DIS_MIU_RQ 0x00020000UL 225 #define MMFI_USE_AUD_PATH 0x00040000UL 226 #define MMFI_USE_VD3D_PATH MMFI_USE_AUD_PATH 227 #define MMFI_BYTE_TIMER_EN 0x00080000UL 228 #define MMFI_BYTE_PLY_FILE_INV_EN 0x00100000UL 229 #define MMFI_DUP_PKT_SKIP 0x00200000UL 230 #define MMFI_ALT_TS_SIZE 0x00400000UL 231 #define MMFI_FILEIN2MI_RPRIORITY 0x00800000UL 232 #define MMFI_USE_AUDB_PATH MMFI_USE_AUD_PATH 233 #define MMFI_RADDR_READ_EN 0x01000000UL 234 #define MMFI_CLK27M_ENABLE 0x04000000UL 235 #define MMFI_WB_FSM_RESET 0x08000000UL 236 #define MMFI_FILEIN_PAUSE 0x10000000UL 237 238 #define MMFI_AU_MODE_MASK (MMFI_APID_BYPASS) 239 #define MMFI_AU_ERR_MASK (MMFI_AUD_ERR_EN|MMFI_AUDB_ERR_EN|MMFI_APES_ERR_RM_EN) 240 #define MMFI_AU_CFG_MASK (MMFI_AU_MODE_MASK|MMFI_AU_ERR_MASK) 241 #define MMFI_VD_MODE_MASK (MMFI_VPID3D_BYPASS) 242 #define MMFI_VD_ERR_MASK (MMFI_VID3D_ERR_EN) 243 #define MMFI_VD_CFG_MASK (MMFI_VD_MODE_MASK|MMFI_VD_ERR_MASK) 244 245 REG32_M TsHeader; // 0xbf803828 0x0a 246 #define MMFI_HD_CCNT_MASK 0x0000000FUL 247 #define MMFI_HD_AF_MASK 0x00000030UL 248 #define MMFI_HD_AF_SHIFT 4UL 249 #define MMFI_HD_SCRAMBLE_MASK 0x000000C0UL 250 #define MMFI_HD_SCRAMBLE_SHIFT 6UL 251 #define MMFI_HD_PID 0x001FFF00UL 252 #define MMFI_HD_PID_SHIFT 8UL 253 #define MMFI_HD_TS_PRIORITY_MASK 0x00200000UL 254 #define MMFI_HD_TS_PRIORITY_SHIFT 21UL 255 #define MMFI_HD_PAYLOAD_START_FLG_MASK 0x00400000UL 256 #define MMFI_HD_PAYLOAD_START_FLG_SHIFT 22UL 257 #define MMFI_HD_ERR_FLG_MASK 0x00800000UL 258 #define MMFI_HD_ERR_FLG_SHIFT 23UL 259 260 REG32_M Pid_Status; // 0xbf803830 0x0c 261 #define MMFI_PID_MATCHED_MASK 0x00001FFFUL 262 #define MMFI_PID_CHANGE 0x00002000UL 263 #define MMFI_PIFSTS_A_SHIFT 0UL 264 #define MMFI_PIFSTS_B_SHIFT 16UL 265 266 REG32_M LPcr2_Buf; // 0xbf803838 0x0e 267 REG32_M TimeStamp_FIn; // 0xbf803840 0x10 268 269 REG32_M SWRst_HWInt; // 0xbf803848 0x12 270 #define MMFI_SWRST_MASK 0x000007FFUL 271 #define MMFI_SW_RSTZ_MMFILEIN_DISABLE 0x00000001UL // low active 272 #define MMFI_RST_WB_DMA_AU 0x00000002UL 273 #define MMFI_RST_CMDQ_AU 0x00000004UL 274 #define MMFI_RST_TSIF_AU 0x00000008UL 275 #define MMFI_RST_WB_P2_AU 0x00000010UL 276 #define MMFI_RST_WB_DMA_VD 0x00000020UL 277 #define MMFI_RST_CMDQ_VD 0x00000040UL 278 #define MMFI_RST_TSIF_VD 0x00000080UL 279 #define MMFI_RST_WB_P2_VD 0x00000100UL 280 #define MMFI_RST_AU_PATH 0x00000200UL 281 #define MMFI_RST_V3D_PATH 0x00000400UL 282 #define MMFI_RST_ALL 0x000007FEUL 283 284 #define MMFI_HWINT_SRC_SHIFT 16UL 285 #define MMFI_HWINT_SRC_MASK 0x00FF0000UL 286 #define MMFI_HWINT_SRC_FILEIN_DONE_VD 0x00100000UL 287 #define MMFI_HWINT_SRC_FILEIN_DONE_AU 0x00200000UL 288 #define MMFI_HWINT_SRC_VD3D_ERR 0x00400000UL 289 #define MMFI_HWINT_SRC_AU_ERR 0x00800000UL 290 #define MMFI_HWINT_STS_MASK 0xFF000000UL 291 #define MMFI_HWINT_STS_SHIFT 24UL 292 #define MMFI_HWINT_STS_FILEIN_DONE_VD 0x10000000UL 293 #define MMFI_HWINT_STS_FILEIN_DONE_AU 0x20000000UL 294 #define MMFI_HWINT_STS_VD3D_ERR 0x40000000UL 295 #define MMFI_HWINT_STS_AU_ERR 0x80000000UL 296 297 REG32_M PktChkSize; // 0xbf803850 0x14 298 #define MMFI_PKTCHK_SIZE_MASK 0x000000FFUL 299 #define MMFI_SYNC_BYTE_MASK 0x0000FF00UL 300 #define MMFI_SYNC_BYTE_SHIFT 8UL 301 #define MMFI_MOBFKEY_MASK 0x001F0000UL 302 #define MMFI_MOBFKEY_SHIFT 16UL 303 304 REG16_M _xbf803854; // 0xbf803858 0x16 305 306 REG32_M Tsp2mi_RAddr; // 0xbf80385C 0x17 307 308 } REG_Ctrl_MMFI; 309 310 311 #endif // _MMFILEIN_REG_H_ 312