xref: /utopia/UTPA2-700.0.x/modules/dmx/hal/k7u/tsp/regTSP_SRC.h (revision 53ee8cc121a030b8d368113ac3e966b4705770ef)

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////////////////////////////////////////////////////////////////////////////////////////////////////
//
//  File name: regTSP_SRC.h
//  Description: TSP Source Mux Register Definition
//
////////////////////////////////////////////////////////////////////////////////////////////////////

#ifndef _REG_TSP_SRC_H_
#define _REG_TSP_SRC_H_

//--------------------------------------------------------------------------------------------------
//  Abbreviation
//--------------------------------------------------------------------------------------------------
// Addr                             Address
// Buf                              Buffer
// Clr                              Clear
// CmdQ                             Command queue
// Cnt                              Count
// Ctrl                             Control
// Flt                              Filter
// Hw                               Hardware
// Int                              Interrupt
// Len                              Length
// Ovfw                             Overflow
// Pkt                              Packet
// Rec                              Record
// Recv                             Receive
// Rmn                              Remain
// Reg                              Register
// Req                              Request
// Rst                              Reset
// Scmb                             Scramble
// Sec                              Section
// Stat                             Status
// Sw                               Software
// Ts                               Transport Stream
// MMFI                             Multi Media File In

//--------------------------------------------------------------------------------------------------
//  Global Definition
//--------------------------------------------------------------------------------------------------


//-------------------------------------------------------------------------------------------------
//  Harware Capability
//-------------------------------------------------------------------------------------------------


//-------------------------------------------------------------------------------------------------
//  Type and Structure
//-------------------------------------------------------------------------------------------------

typedef struct _REG_TSP_SRC_Ctrl // TSP-SRC (Bank:0x3014)
{
    REG16       CFG_TSP_SRC_00_03[0x4 - 0x0];                                   // reg_ts_mux
        #define CFG_TSP_SRC_MUX_EVEN_MASK                                       0x00FF
        #define CFG_TSP_SRC_MUX_EVEN_SHIFT                                      0
        #define CFG_TSP_SRC_MUX_ODD_MASK                                        0xFF00
        #define CFG_TSP_SRC_MUX_ODD_SHIFT                                       8

            #define CFG_TSP_SRC_MUX_PAD_TS0                                     0x0000
            #define CFG_TSP_SRC_MUX_PAD_TS1                                     0x0001
            #define CFG_TSP_SRC_MUX_PAD_TS2                                     0x0002
            #define CFG_TSP_SRC_MUX_PAD_TS3                                     0x0003
            #define CFG_TSP_SRC_MUX_PAD_TS4                                     0x0004
            #define CFG_TSP_SRC_MUX_PAD_TS5                                     0x0005
            #define CFG_TSP_SRC_MUX_PAD_TS6                                     0x0006
            #define CFG_TSP_SRC_MUX_PAD_TS7                                     0x0007
            #define CFG_TSP_SRC_MUX_PAD_TS8                                     0x0008
            #define CFG_TSP_SRC_MUX_PAD_TSO0                                    0x0009
            #define CFG_TSP_SRC_MUX_PAD_TSO1                                    0x000A
            #define CFG_TSP_SRC_MUX_PAD_TSIO                                    0x000B
            #define CFG_TSP_SRC_MUX_PAD_CILINK                                  0x000C
            #define CFG_TSP_SRC_MUX_PAD_DMD0                                    0x000E // Not support
            #define CFG_TSP_SRC_MUX_PAD_DMD1                                    0x000F // Not support

    REG16       CFG_TSP_SRC_04_06[0x7 - 0x4];                                   // reg_tso_mux (TSO #0)

    REG16       CFG_TSP_SRC_07;                                                 // reserved

    REG16       CFG_TSP_SRC_08_0A[0xB - 0x8];                                   // reg_tso_mux (TSO #1)

    REG16       CFG_TSP_SRC_0B;                                                 // reserved

    REG16       CFG_TSP_SRC_0C;                                                 // reg_s2p_mux

    REG16       CFG_TSP_SRC_0D_0F[0x10 - 0xD];                                  // reserved

    REG16       CFG_TSP_SRC_10;                                                 // reg_rasp_mux

    REG16       CFG_TSP_SRC_11;                                                 // reg_emmflt_mux

    REG16       CFG_TSP_SRC_12;                                                 // reg_cilink_mux

    REG16       CFG_TSP_SRC_13_1F[0x20 - 0x13];                                 // reserved

    REG16       CFG_TSP_SRC_20;
        #define CFG_TSP_SRC_20_REG_TS0_MUX_LOCK                                 0x0001
        #define CFG_TSP_SRC_20_REG_TS1_MUX_LOCK                                 0x0002
        #define CFG_TSP_SRC_20_REG_TS2_MUX_LOCK                                 0x0004
        #define CFG_TSP_SRC_20_REG_TS3_MUX_LOCK                                 0x0008
        #define CFG_TSP_SRC_20_REG_TS4_MUX_LOCK                                 0x0010
        #define CFG_TSP_SRC_20_REG_TS5_MUX_LOCK                                 0x0020
        #define CFG_TSP_SRC_20_REG_TS6_MUX_LOCK                                 0x0040
        #define CFG_TSP_SRC_20_REG_TSO0_MUX_LOCK                                0x0100
        #define CFG_TSP_SRC_20_REG_TSO1_MUX_LOCK                                0x0200
        #define CFG_TSP_SRC_20_REG_TSO2_MUX_LOCK                                0x0400
        #define CFG_TSP_SRC_20_REG_TSO3_MUX_LOCK                                0x0800
        #define CFG_TSP_SRC_20_REG_TSO4_MUX_LOCK                                0x1000
        #define CFG_TSP_SRC_20_REG_TSO5_MUX_LOCK                                0x2000

    REG16       CFG_TSP_SRC_21;
        #define CFG_TSP_SRC_21_REG_TSO10_MUX_LOCK                               0x0001
        #define CFG_TSP_SRC_21_REG_TSO11_MUX_LOCK                               0x0002
        #define CFG_TSP_SRC_21_REG_TSO12_MUX_LOCK                               0x0004
        #define CFG_TSP_SRC_21_REG_TSO13_MUX_LOCK                               0x0008
        #define CFG_TSP_SRC_21_REG_TSO14_MUX_LOCK                               0x0010
        #define CFG_TSP_SRC_21_REG_TSO15_MUX_LOCK                               0x0020
        #define CFG_TSP_SRC_21_REG_S2P0_MUX_LOCK                                0x0100
        #define CFG_TSP_SRC_21_REG_S2P1_MUX_LOCK                                0x0200
        #define CFG_TSP_SRC_21_REG_CILINK1_MUX_LOCK                             0x0400
        #define CFG_TSP_SRC_21_REG_CILINK2_MUX_LOCK                             0x0800

    REG16       CFG_TSP_SRC_22;
        #define CFG_TSP_SRC_22_REG_RASP0_MUX_LOCK                               0x0001
        #define CFG_TSP_SRC_22_REG_RASP1_MUX_LOCK                               0x0002
        #define CFG_TSP_SRC_22_REG_EMMFLT0_MUX_LOCK                             0x0004
        #define CFG_TSP_SRC_22_REG_EMMFLT1_MUX_LOCK                             0x0008

} REG_TSP_SRC_Ctrl;

#endif // _REG_TSP_SRC_H_