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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 //////////////////////////////////////////////////////////////////////////////////////////////////// 96 // 97 // File name: regTSP_SRC.h 98 // Description: TSP Source Mux Register Definition 99 // 100 //////////////////////////////////////////////////////////////////////////////////////////////////// 101 102 #ifndef _REG_TSP_SRC_H_ 103 #define _REG_TSP_SRC_H_ 104 105 //-------------------------------------------------------------------------------------------------- 106 // Abbreviation 107 //-------------------------------------------------------------------------------------------------- 108 // Addr Address 109 // Buf Buffer 110 // Clr Clear 111 // CmdQ Command queue 112 // Cnt Count 113 // Ctrl Control 114 // Flt Filter 115 // Hw Hardware 116 // Int Interrupt 117 // Len Length 118 // Ovfw Overflow 119 // Pkt Packet 120 // Rec Record 121 // Recv Receive 122 // Rmn Remain 123 // Reg Register 124 // Req Request 125 // Rst Reset 126 // Scmb Scramble 127 // Sec Section 128 // Stat Status 129 // Sw Software 130 // Ts Transport Stream 131 // MMFI Multi Media File In 132 133 //-------------------------------------------------------------------------------------------------- 134 // Global Definition 135 //-------------------------------------------------------------------------------------------------- 136 137 138 //------------------------------------------------------------------------------------------------- 139 // Harware Capability 140 //------------------------------------------------------------------------------------------------- 141 142 143 //------------------------------------------------------------------------------------------------- 144 // Type and Structure 145 //------------------------------------------------------------------------------------------------- 146 147 typedef struct _REG_TSP_SRC_Ctrl // TSP-SRC (Bank:0x3014) 148 { 149 REG16 CFG_TSP_SRC_00_03[0x4 - 0x0]; // reg_ts_mux 150 #define CFG_TSP_SRC_MUX_EVEN_MASK 0x00FF 151 #define CFG_TSP_SRC_MUX_EVEN_SHIFT 0 152 #define CFG_TSP_SRC_MUX_ODD_MASK 0xFF00 153 #define CFG_TSP_SRC_MUX_ODD_SHIFT 8 154 155 #define CFG_TSP_SRC_MUX_PAD_TS0 0x0000 156 #define CFG_TSP_SRC_MUX_PAD_TS1 0x0001 157 #define CFG_TSP_SRC_MUX_PAD_TS2 0x0002 158 #define CFG_TSP_SRC_MUX_PAD_TS3 0x0003 159 #define CFG_TSP_SRC_MUX_PAD_TS4 0x0004 160 #define CFG_TSP_SRC_MUX_PAD_TS5 0x0005 161 #define CFG_TSP_SRC_MUX_PAD_TS6 0x0006 162 #define CFG_TSP_SRC_MUX_PAD_TS7 0x0007 163 #define CFG_TSP_SRC_MUX_PAD_TS8 0x0008 164 #define CFG_TSP_SRC_MUX_PAD_TSO0 0x0009 165 #define CFG_TSP_SRC_MUX_PAD_TSO1 0x000A 166 #define CFG_TSP_SRC_MUX_PAD_TSIO 0x000B 167 #define CFG_TSP_SRC_MUX_PAD_CILINK 0x000C 168 #define CFG_TSP_SRC_MUX_PAD_DMD0 0x000E // Not support 169 #define CFG_TSP_SRC_MUX_PAD_DMD1 0x000F // Not support 170 171 REG16 CFG_TSP_SRC_04_06[0x7 - 0x4]; // reg_tso_mux (TSO #0) 172 173 REG16 CFG_TSP_SRC_07; // reserved 174 175 REG16 CFG_TSP_SRC_08_0A[0xB - 0x8]; // reg_tso_mux (TSO #1) 176 177 REG16 CFG_TSP_SRC_0B; // reserved 178 179 REG16 CFG_TSP_SRC_0C; // reg_s2p_mux 180 181 REG16 CFG_TSP_SRC_0D_0F[0x10 - 0xD]; // reserved 182 183 REG16 CFG_TSP_SRC_10; // reg_rasp_mux 184 185 REG16 CFG_TSP_SRC_11; // reg_emmflt_mux 186 187 REG16 CFG_TSP_SRC_12; // reg_cilink_mux 188 189 REG16 CFG_TSP_SRC_13_1F[0x20 - 0x13]; // reserved 190 191 REG16 CFG_TSP_SRC_20; 192 #define CFG_TSP_SRC_20_REG_TS0_MUX_LOCK 0x0001 193 #define CFG_TSP_SRC_20_REG_TS1_MUX_LOCK 0x0002 194 #define CFG_TSP_SRC_20_REG_TS2_MUX_LOCK 0x0004 195 #define CFG_TSP_SRC_20_REG_TS3_MUX_LOCK 0x0008 196 #define CFG_TSP_SRC_20_REG_TS4_MUX_LOCK 0x0010 197 #define CFG_TSP_SRC_20_REG_TS5_MUX_LOCK 0x0020 198 #define CFG_TSP_SRC_20_REG_TS6_MUX_LOCK 0x0040 199 #define CFG_TSP_SRC_20_REG_TSO0_MUX_LOCK 0x0100 200 #define CFG_TSP_SRC_20_REG_TSO1_MUX_LOCK 0x0200 201 #define CFG_TSP_SRC_20_REG_TSO2_MUX_LOCK 0x0400 202 #define CFG_TSP_SRC_20_REG_TSO3_MUX_LOCK 0x0800 203 #define CFG_TSP_SRC_20_REG_TSO4_MUX_LOCK 0x1000 204 #define CFG_TSP_SRC_20_REG_TSO5_MUX_LOCK 0x2000 205 206 REG16 CFG_TSP_SRC_21; 207 #define CFG_TSP_SRC_21_REG_TSO10_MUX_LOCK 0x0001 208 #define CFG_TSP_SRC_21_REG_TSO11_MUX_LOCK 0x0002 209 #define CFG_TSP_SRC_21_REG_TSO12_MUX_LOCK 0x0004 210 #define CFG_TSP_SRC_21_REG_TSO13_MUX_LOCK 0x0008 211 #define CFG_TSP_SRC_21_REG_TSO14_MUX_LOCK 0x0010 212 #define CFG_TSP_SRC_21_REG_TSO15_MUX_LOCK 0x0020 213 #define CFG_TSP_SRC_21_REG_S2P0_MUX_LOCK 0x0100 214 #define CFG_TSP_SRC_21_REG_S2P1_MUX_LOCK 0x0200 215 #define CFG_TSP_SRC_21_REG_CILINK1_MUX_LOCK 0x0400 216 #define CFG_TSP_SRC_21_REG_CILINK2_MUX_LOCK 0x0800 217 218 REG16 CFG_TSP_SRC_22; 219 #define CFG_TSP_SRC_22_REG_RASP0_MUX_LOCK 0x0001 220 #define CFG_TSP_SRC_22_REG_RASP1_MUX_LOCK 0x0002 221 #define CFG_TSP_SRC_22_REG_EMMFLT0_MUX_LOCK 0x0004 222 #define CFG_TSP_SRC_22_REG_EMMFLT1_MUX_LOCK 0x0008 223 224 } REG_TSP_SRC_Ctrl; 225 226 #endif // _REG_TSP_SRC_H_ 227