1 //<MStar Software> 2 //****************************************************************************** 3 // MStar Software 4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved. 5 // All software, firmware and related documentation herein ("MStar Software") are 6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by 7 // law, including, but not limited to, copyright law and international treaties. 8 // Any use, modification, reproduction, retransmission, or republication of all 9 // or part of MStar Software is expressly prohibited, unless prior written 10 // permission has been granted by MStar. 11 // 12 // By accessing, browsing and/or using MStar Software, you acknowledge that you 13 // have read, understood, and agree, to be bound by below terms ("Terms") and to 14 // comply with all applicable laws and regulations: 15 // 16 // 1. MStar shall retain any and all right, ownership and interest to MStar 17 // Software and any modification/derivatives thereof. 18 // No right, ownership, or interest to MStar Software and any 19 // modification/derivatives thereof is transferred to you under Terms. 20 // 21 // 2. You understand that MStar Software might include, incorporate or be 22 // supplied together with third party`s software and the use of MStar 23 // Software may require additional licenses from third parties. 24 // Therefore, you hereby agree it is your sole responsibility to separately 25 // obtain any and all third party right and license necessary for your use of 26 // such third party`s software. 27 // 28 // 3. MStar Software and any modification/derivatives thereof shall be deemed as 29 // MStar`s confidential information and you agree to keep MStar`s 30 // confidential information in strictest confidence and not disclose to any 31 // third party. 32 // 33 // 4. MStar Software is provided on an "AS IS" basis without warranties of any 34 // kind. Any warranties are hereby expressly disclaimed by MStar, including 35 // without limitation, any warranties of merchantability, non-infringement of 36 // intellectual property rights, fitness for a particular purpose, error free 37 // and in conformity with any international standard. You agree to waive any 38 // claim against MStar for any loss, damage, cost or expense that you may 39 // incur related to your use of MStar Software. 40 // In no event shall MStar be liable for any direct, indirect, incidental or 41 // consequential damages, including without limitation, lost of profit or 42 // revenues, lost or damage of data, and unauthorized system use. 43 // You agree that this Section 4 shall still apply without being affected 44 // even if MStar Software has been modified by MStar in accordance with your 45 // request or instruction for your use, except otherwise agreed by both 46 // parties in writing. 47 // 48 // 5. If requested, MStar may from time to time provide technical supports or 49 // services in relation with MStar Software to you for your use of 50 // MStar Software in conjunction with your or your customer`s product 51 // ("Services"). 52 // You understand and agree that, except otherwise agreed by both parties in 53 // writing, Services are provided on an "AS IS" basis and the warranty 54 // disclaimer set forth in Section 4 above shall apply. 55 // 56 // 6. Nothing contained herein shall be construed as by implication, estoppels 57 // or otherwise: 58 // (a) conferring any license or right to use MStar name, trademark, service 59 // mark, symbol or any other identification; 60 // (b) obligating MStar or any of its affiliates to furnish any person, 61 // including without limitation, you and your customers, any assistance 62 // of any kind whatsoever, or any information; or 63 // (c) conferring any license or right under any intellectual property right. 64 // 65 // 7. These terms shall be governed by and construed in accordance with the laws 66 // of Taiwan, R.O.C., excluding its conflict of law rules. 67 // Any and all dispute arising out hereof or related hereto shall be finally 68 // settled by arbitration referred to the Chinese Arbitration Association, 69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration 70 // Rules of the Association by three (3) arbitrators appointed in accordance 71 // with the said Rules. 72 // The place of arbitration shall be in Taipei, Taiwan and the language shall 73 // be English. 74 // The arbitration award shall be final and binding to both parties. 75 // 76 //****************************************************************************** 77 //<MStar Software> 78 //////////////////////////////////////////////////////////////////////////////// 79 // 80 // Copyright (c) 2011-2013 MStar Semiconductor, Inc. 81 // All rights reserved. 82 // 83 // Unless otherwise stipulated in writing, any and all information contained 84 // herein regardless in any format shall remain the sole proprietary of 85 // MStar Semiconductor Inc. and be kept in strict confidence 86 // ("MStar Confidential Information") by the recipient. 87 // Any unauthorized act including without limitation unauthorized disclosure, 88 // copying, use, reproduction, sale, distribution, modification, disassembling, 89 // reverse engineering and compiling of the contents of MStar Confidential 90 // Information is unlawful and strictly prohibited. MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 //////////////////////////////////////////////////////////////////////////////////////////////////// 96 // 97 // File name: regMultiPVR.h 98 // Description: TSP Multi-PVR Register Definition 99 // 100 //////////////////////////////////////////////////////////////////////////////////////////////////// 101 102 #ifndef _REG_MULTI_PVR_H_ 103 #define _REG_MULTI_PVR_H_ 104 105 //-------------------------------------------------------------------------------------------------- 106 // Global Definition 107 //-------------------------------------------------------------------------------------------------- 108 109 110 //------------------------------------------------------------------------------------------------- 111 // Harware Capability 112 //------------------------------------------------------------------------------------------------- 113 114 #define TSP_MULTI_PVR_ENG_NUM 1 115 #define TSP_MULTI_PVR_CH_NUM 8 116 117 //------------------------------------------------------------------------------------------------- 118 // Type and Structure 119 //------------------------------------------------------------------------------------------------- 120 121 typedef struct _REG32_MULTI_PVR 122 { 123 volatile MS_U16 low; 124 volatile MS_U16 _null_l; 125 volatile MS_U16 high; 126 volatile MS_U16 _null_h; 127 } REG32_MULTI_PVR; 128 129 typedef struct _REG16_MULTI_PVR 130 { 131 volatile MS_U16 data; 132 volatile MS_U16 _null; 133 } REG16_MULTI_PVR; 134 135 typedef struct _REG_MULTI_PVR_ENG_Ctrl // Multi-PVR (Bank:0x160A) 136 { 137 REG16_MULTI_PVR CFG_MULTI_PVR_00; 138 #define CFG_MULTI_PVR_00_REG_PVR_STR2MI_EN 0x0001 139 #define CFG_MULTI_PVR_00_REG_PVR_STR2MI_RST_WADR 0x0002 140 #define CFG_MULTI_PVR_00_REG_PVR_STR2MI_PAUSE 0x0004 141 #define CFG_MULTI_PVR_00_REG_PVR_BURST_LEN_MASK 0x0018 142 #define CFG_MULTI_PVR_00_REG_PVR_BURST_LEN_SHIFT 3 143 #define CFG_MULTI_PVR_00_REG_PVR_SRAM_SD_EN 0x0020 144 #define CFG_MULTI_PVR_00_REG_PVR_STR2MI_WP_LD 0x0040 145 #define CFG_MULTI_PVR_00_REG_PVR_CLR 0x0080 // clear PVR overflow flag 146 #define CFG_MULTI_PVR_00_REG_PVR_DMA_FLUSH_EN 0x0100 147 #define CFG_MULTI_PVR_00_REG_PVR_MIU_HIGHPRI 0x0200 148 #define CFG_MULTI_PVR_00_REG_PVR_WRITE_POINTER_TO_NEXT_ADDR_EN 0x0400 149 #define CFG_MULTI_PVR_00_REG_PVR_DMAW_PROTECT_EN 0x0800 150 #define CFG_MULTI_PVR_00_REG_PVR_CLR_NO_HIT_INT 0x1000 151 152 REG32_MULTI_PVR CFG_MULTI_PVR_01_02; // reg_pvr_dmaw_waddr_err 153 154 REG16_MULTI_PVR CFG_MULTI_PVR_03; // reserved 155 156 REG32_MULTI_PVR CFG_MULTI_PVR_04_05; // reg_pvr_str2mi_wadr_r 157 158 REG16_MULTI_PVR CFG_MULTI_PVR_06; 159 #define CFG_MULTI_PVR_06_REG_PVR_FIFO_STATUS_MASK 0x001F 160 #define CFG_MULTI_PVR_06_REG_PVR_FIFO_STATUS_SHIFT 0 161 162 REG32_MULTI_PVR CFG_MULTI_PVR_07_08; // reg_pvr_dmaw_lbnd 163 164 REG32_MULTI_PVR CFG_MULTI_PVR_09_0A; // reg_pvr_dmaw_ubnd 165 166 REG16_MULTI_PVR CFG_MULTI_PVR_0B_3F[0x40 - 0x0B]; // reserved 167 168 REG16_MULTI_PVR CFG_MULTI_PVR_40; 169 #define CFG_MULTI_PVR_40_REG_ACPU_ACTIVE 0x0001 170 171 REG16_MULTI_PVR CFG_MULTI_PVR_41; // reg_acpu_cmd 172 173 REG16_MULTI_PVR CFG_MULTI_PVR_42; // reg_acpu_flag 174 175 REG32_MULTI_PVR CFG_MULTI_PVR_43_44; // reg_acpu_addr_head 176 177 REG32_MULTI_PVR CFG_MULTI_PVR_45_46; // reg_acpu_addr_tail 178 179 REG32_MULTI_PVR CFG_MULTI_PVR_47_48; // reg_acpu_rdata 180 181 REG16_MULTI_PVR CFG_MULTI_PVR_49; 182 #define CFG_MULTI_PVR_49_REG_SGDMA_OUT_INT_CLR 0x0001 183 #define CFG_MULTI_PVR_49_REG_SGDMA_OUT_PAUSE 0x0002 184 #define CFG_MULTI_PVR_49_REG_SGDMA_OUT_DBG_SEL_MASK 0x00FC 185 #define CFG_MULTI_PVR_49_REG_SGDMA_OUT_DBG_SEL_SHIFT 4 186 #define CFG_MULTI_PVR_49_REG_SGDMA_OUT_INT_MASK 0x0100 187 #define CFG_MULTI_PVR_49_REG_SGDMA_OUT_VC_INT_TRIGGER 0x0400 188 189 REG16_MULTI_PVR CFG_MULTI_PVR_4A; // reg_sgdma_out_dbg 190 191 REG16_MULTI_PVR CFG_MULTI_PVR_4B; // reg_sgdma_out_vc_int (only bit[7:0]) 192 #define CFG_MULTI_PVR_4B_REG_SGDMA_OUT_VC_INT_MASK 0x00FF 193 #define CFG_MULTI_PVR_4B_REG_SGDMA_OUT_VC_INT_SHIFT 0 194 195 REG16_MULTI_PVR CFG_MULTI_PVR_4C_4E[0x4F - 0x4C]; // reg_sgdma_out_vc_int (dummy) 196 197 REG16_MULTI_PVR CFG_MULTI_PVR_4F; 198 #define CFG_MULTI_PVR_4F_REG_SGDMA_OUT_VC_INT_VC_ID_MASK 0x003F 199 #define CFG_MULTI_PVR_4F_REG_SGDMA_OUT_VC_INT_VC_ID_SHIFT 0 200 #define CFG_MULTI_PVR_4F_REG_SGDMA_OUT_VC_INT_CLR 0x0040 // clear interrupt 201 #define CFG_MULTI_PVR_4F_REG_SGDMA_OUT_VC_INT_MASK 0x0080 // mask interrupt 202 203 REG16_MULTI_PVR CFG_MULTI_PVR_50; 204 #define CFG_MULTI_PVR_50_REG_SGDMA_OUT_VC_STATUS_SEL_MASK 0x00FC 205 #define CFG_MULTI_PVR_50_REG_SGDMA_OUT_VC_STATUS_SEL_SHIFT 2 206 207 REG16_MULTI_PVR CFG_MULTI_PVR_51; // reg_sgdma_out_vc_status 208 #define CFG_MULTI_PVR_51_REG_SGDMA_OUT_VC_STATUS_ACTIVE 0x0001 209 #define CFG_MULTI_PVR_51_REG_SGDMA_OUT_VC_STATUS_PINGPONG_PTR 0x0020 210 211 REG16_MULTI_PVR CFG_MULTI_PVR_52_6F[0x70 - 0x52]; // reserved 212 213 REG16_MULTI_PVR CFG_MULTI_PVR_70; 214 #define CFG_MULTI_PVR_70_REG_START_READ_BYPASS_EN 0x0001 215 #define CFG_MULTI_PVR_70_REG_CLR_PIDFLT_BYTE_CNT 0x0002 216 #define CFG_MULTI_PVR_70_REG_PVR_ERR_RM_EN 0x0004 217 #define CFG_MULTI_PVR_70_REG_MASK_SCR_PVR_EN 0x0008 218 #define CFG_MULTI_PVR_70_REG_DIS_NULL_PKT 0x0010 219 #define CFG_MULTI_PVR_70_REG_TEI_SKIP_PKT 0x0020 220 #define CFG_MULTI_PVR_70_REG_RECORD_TS 0x0040 221 #define CFG_MULTI_PVR_70_REG_RECORD_ALL 0x0080 222 #define CFG_MULTI_PVR_70_REG_SKIP_PVR_RUSH_DATA 0x0100 223 #define CFG_MULTI_PVR_70_REG_ALT_TS_SIZE 0x0200 224 #define CFG_MULTI_PVR_70_REG_PVR_BLOCK_DISABLE 0x0400 225 #define CFG_MULTI_PVR_70_REG_PVR_PES_DIRECTV_130_MODE 0x0800 226 #define CFG_MULTI_PVR_70_REG_RESET_FILTER 0x4000 227 #define CFG_MULTI_PVR_70_REG_ONEWAY_PVR 0x8000 228 229 REG16_MULTI_PVR CFG_MULTI_PVR_71; 230 #define CFG_MULTI_PVR_71_REG_PKT_SIZE_MASK 0x00FF 231 #define CFG_MULTI_PVR_71_REG_PKT_SIZE_SHIFT 0 232 #define CFG_MULTI_PVR_71_REG_INPUT_SRC_MASK 0x0F00 233 #define CFG_MULTI_PVR_71_REG_INPUT_SRC_SHIFT 8 234 235 REG16_MULTI_PVR CFG_MULTI_PVR_72; 236 #define CFG_MULTI_PVR_72_REG_CHK_PRIVILEGE_FLAG 0x0001 237 #define CFG_MULTI_PVR_72_REG_CHK_TEE_FILEIN 0x0002 238 239 REG16_MULTI_PVR CFG_MULTI_PVR_73; 240 #define CFG_MULTI_PVR_73_REG_ONEWAY_REC_CA_UPPER_PATH 0x0001 241 #define CFG_MULTI_PVR_73_REG_REC_CA_UPPER_PATH 0x0002 242 243 REG16_MULTI_PVR CFG_MULTI_PVR_74_7E[0x7F - 0x74]; // reserved 244 245 REG16_MULTI_PVR CFG_MULTI_PVR_7F; 246 #define CFG_MULTI_PVR_7F_REG_CLK_GATING_TSP_PVR 0x0001 247 #define CFG_MULTI_PVR_7F_REG_CLK_GATING_MIU_PVR 0x0002 248 249 } REG_MULTI_PVR_ENG_Ctrl; 250 251 #endif // #ifndef _REG_MULTI_PVR_H_ 252