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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 //////////////////////////////////////////////////////////////////////////////////////////////////// 96 // file halTSO.h 97 // @brief TS I/O (TSO) HAL 98 // @author MStar Semiconductor,Inc. 99 //////////////////////////////////////////////////////////////////////////////////////////////////// 100 #ifndef __HAL_TSIO_H__ 101 #define __HAL_TSIO_H__ 102 103 #include "regTSIO.h" 104 105 //-------------------------------------------------------------------------------------------------- 106 // Driver Compiler Option 107 //-------------------------------------------------------------------------------------------------- 108 109 //-------------------------------------------------------------------------------------------------- 110 // Macro of bit operations 111 //-------------------------------------------------------------------------------------------------- 112 113 #define ANALOG_PHASE_MAX 39 114 #define ANALOG_PHASE_MIN 0 115 #define ANALOG_PHASE_NUM (ANALOG_PHASE_MAX-ANALOG_PHASE_MIN+1) 116 #define ANALOG_PHASE_GAP 7 117 #define ANALOG_PHASE_TABLE 4 //0: 200M, 1: 100M, 2:50M, 3: 25M 118 119 typedef enum 120 { 121 HAL_SGDMAOUT_DBG_INT_COM = 0, 122 HAL_SGDMAOUT_DBG_STATE = 1, 123 HAL_SGDMAOUT_DBG_CURRENT_VC_ID = 2, 124 HAL_SGDMAOUT_DBG_BUF_BASE_ADDR_L = 3, 125 HAL_SGDMAOUT_DBG_BUF_BASE_ADDR_H = 4, 126 HAL_SGDMAOUT_DBG_BUF_SIZE_L = 5, 127 HAL_SGDMAOUT_DBG_BUF_SIZE_H = 6, 128 HAL_SGDMAOUT_DBG_BUF_USED_SIZE_L = 7, 129 HAL_SGDMAOUT_DBG_BUF_USED_SIZE_H = 8, 130 HAL_SGDMAOUT_DBG_CPU_FLAG = 9, 131 HAL_SGDMAOUT_DBG_NODE_FLAG = 10, 132 HAL_SGDMAOUT_DBG_SG_FLAG = 11, 133 HAL_SGDMAOUT_DBG_BUF_EMPTY = 12, 134 HAL_SGDMAOUT_DBG_BUF_LEFT_SIZE_L = 13, 135 HAL_SGDMAOUT_DBG_BUF_LEFT_SIZE_H = 14, 136 HAL_SGDMAOUT_DBG_SGDMA_OUT_VC_INT_MASK_0 = 15, 137 HAL_SGDMAOUT_DBG_SGDMA_OUT_VC_INT_MASK_1 = 16, 138 HAL_SGDMAOUT_DBG_SGDMA_OUT_VC_INT_MASK_2 = 17, 139 HAL_SGDMAOUT_DBG_SGDMA_OUT_VC_INT_MASK_3 = 18, 140 HAL_SGDMAOUT_DBG_PACE_DBG_CLK_NUM_H = 19, 141 HAL_SGDMAOUT_DBG_PACE_DBG_CLK_NUM_L = 20, 142 HAL_SGDMAOUT_DBG_PACE_DBG_PKT_NUM = 21, 143 HAL_SGDMAOUT_DBG_MAX, 144 }HAL_SGDMAOUT_DBG; 145 146 typedef enum 147 { 148 HAL_SGDMAIN_DBG_VC_ACTIVE_0 = 0, 149 HAL_SGDMAIN_DBG_VC_ACTIVE_1 = 1, 150 HAL_SGDMAIN_DBG_VC_ACTIVE_2 = 2, 151 HAL_SGDMAIN_DBG_VC_ACTIVE_3 = 3, 152 HAL_SGDMAIN_DBG_VC_DONE_0 = 4, 153 HAL_SGDMAIN_DBG_VC_DONE_1 = 5, 154 HAL_SGDMAIN_DBG_VC_DONE_2 = 6, 155 HAL_SGDMAIN_DBG_VC_DONE_3 = 7, 156 HAL_SGDMAIN_DBG_M_PRIOR_0 = 8, 157 HAL_SGDMAIN_DBG_M_PRIOR_1 = 9, 158 HAL_SGDMAIN_DBG_M_PRIOR_2 = 10, 159 HAL_SGDMAIN_DBG_M_PRIOR_3 = 11, 160 HAL_SGDMAIN_DBG_L_PRIOR_0 = 12, 161 HAL_SGDMAIN_DBG_L_PRIOR_1 = 13, 162 HAL_SGDMAIN_DBG_L_PRIOR_2 = 14, 163 HAL_SGDMAIN_DBG_L_PRIOR_3 = 15, 164 HAL_SGDMAIN_DBG_CURRENT_STATUS = 16, 165 HAL_SGDMAIN_DBG_FIRST_NODE_ADDR_L = 17, 166 HAL_SGDMAIN_DBG_FIRST_NODE_ADDR_H = 18, 167 HAL_SGDMAIN_DBG_NEXT_NODE_ADDR_L = 19, 168 HAL_SGDMAIN_DBG_NEXT_NODE_ADDR_H = 20, 169 HAL_SGDMAIN_DBG_BUF_BASE_ADDR_L = 21, 170 HAL_SGDMAIN_DBG_BUF_BASE_ADDR_H = 22, 171 HAL_SGDMAIN_DBG_BUF_SIZE_L = 23, 172 HAL_SGDMAIN_DBG_BUF_SIZE_H = 24, 173 HAL_SGDMAIN_DBG_BUF_USED_SIZE_L = 25, 174 HAL_SGDMAIN_DBG_BUF_USED_SIZE_H = 26, 175 HAL_SGDMAIN_DBG_CPU_FLAG = 27, 176 HAL_SGDMAIN_DBG_NODE_FLAG = 28, 177 HAL_SGDMAIN_DBG_SG_FLAG = 29, 178 HAL_SGDMAIN_DBG_SG_CTRL = 30, 179 HAL_SGDMAIN_DBG_BUF_LEFT_SIZE_L = 31, 180 HAL_SGDMAIN_DBG_BUF_LEFT_SIZE_H = 32, 181 HAL_SGDMAIN_DBG_EMPTY = 33, 182 HAL_SGDMAIN_DBG_STATE = 34, 183 HAL_SGDMAIN_DBG_SGDMA_IN_VC_INT_MASK_0 = 35, 184 HAL_SGDMAIN_DBG_SGDMA_IN_VC_INT_MASK_1 = 36, 185 HAL_SGDMAIN_DBG_SGDMA_IN_VC_INT_MASK_2 = 37, 186 HAL_SGDMAIN_DBG_SGDMA_IN_VC_INT_MASK_3 = 38, 187 HAL_SGDMAIN_DBG_VC_TOUCHED_0 = 39, 188 HAL_SGDMAIN_DBG_VC_TOUCHED_1 = 40, 189 HAL_SGDMAIN_DBG_VC_TOUCHED_2 = 41, 190 HAL_SGDMAIN_DBG_VC_TOUCHED_3 = 42, 191 HAL_SGDMAIN_DBG_PACE_DBG_CLK_NUM_H = 43, 192 HAL_SGDMAIN_DBG_PACE_DBG_CLK_NUM_L = 44, 193 HAL_SGDMAIN_DBG_PACE_DBG_PKT_NUM = 45, 194 HAL_SGDMAIN_DBG_MAX, 195 }HAL_SGDMAIN_DBG; 196 197 typedef enum 198 { 199 HAL_SGDMA_SRAM_BUF_USED_SIZE = 0, 200 HAL_SGDMA_SRAM_FLAG = 1, 201 HAL_SGDMA_SRAM_BUF_SIZE = 2, 202 HAL_SGDMA_SRAM_BUF_ADDR = 3, 203 HAL_SGDMA_SRAM_NEXT_NODE_ADDR = 4, 204 HAL_SGDMA_SRAM_FIRST_NODE_ADDR = 5, 205 HAL_SGDMA_SRAM_CPU_FLAG = 6, 206 HAL_SGDMA_SRAM_MAX, 207 }HAL_SGDMA_SRAM; 208 209 typedef enum 210 { 211 HAL_TSIO_CLK_200M = 0, 212 HAL_TSIO_CLK_100M = 1, 213 HAL_TSIO_CLK_50M = 2, 214 HAL_TSIO_CLK_25M = 3, 215 }HAL_TSIO_CLK; 216 217 typedef enum 218 { 219 E_HAL_TSIO_DBG_LEVEL_NONE, // no debug message shown 220 E_HAL_TSIO_DBG_LEVEL_ERR, // only shows error message that can't be recover 221 E_HAL_TSIO_DBG_LEVEL_WARN, // error case can be recover, like retry 222 E_HAL_TSIO_DBG_LEVEL_EVENT, // event that is okay but better known, ex: timestamp ring, file circular, etc. 223 E_HAL_TSIO_DBG_LEVEL_INFO, // information for internal parameter 224 E_HAL_TSIO_DBG_LEVEL_FUNC, // Function trace and input parameter trace 225 E_HAL_TSIO_DBG_LEVEL_TRACE, // debug trace 226 } EN_HAL_TSIO_DBGMSG_LEVEL; 227 228 //////////////////////////////////////////////// 229 // HAL API 230 //////////////////////////////////////////////// 231 232 233 //======================================================= 234 // General API 235 //======================================================= 236 void HAL_TSIO_ClkOpen(MS_BOOL bEnable); 237 void HAL_TSIO_SetBank(MS_VIRT u32BankAddr); 238 void HAL_TSIO_PowerInit(void); 239 void HAL_TSIO_Reset(void); 240 void HAL_TSIO_Tx2Rx_InsertCTS(MS_BOOL bEnable); 241 void HAL_TSIO_Tx2Rx_Direct8(MS_BOOL bEnable); 242 void HAL_TSIO_Tx2Rx_Direct16(MS_BOOL bEnable); 243 void HAL_TSIO_Tx2Rx_Loopback(MS_BOOL bEnable); 244 void HAL_TSIO_StuffingSID_Set(MS_U8 u8Stuffing_sid); 245 void HAL_TSIO_Decrypt_Set(MS_BOOL bEnable); 246 void HAL_TSIO_Threshold_Set(MS_U8 u8Threshold); 247 void HAL_TSIO_BypassMerge_Set(MS_BOOL bEnable); 248 void HAL_TSIO_SIDBypassSMCMergeEnable(MS_U8 u8Sid, MS_BOOL bEnable); 249 void HAL_TSIO_CTS_En(MS_BOOL bEnable); 250 void HAL_TSIO_DbgLevel(EN_HAL_TSIO_DBGMSG_LEVEL eLevel); 251 252 //======================================================= 253 // SGDMA_IN API 254 //======================================================= 255 void HAL_TSIO_SGDMAIN_Reset(void); 256 void HAL_TSIO_SGDMAIN_LastPktBuf_Set(MS_U32 u32Head, MS_U32 u32Tail); 257 void HAL_TSIO_SGDMAIN_SGVQBuf_Set(MS_U32 u32BufAddr, MS_U32 u32BufSize); 258 void HAL_TSIO_SGDMAIN_VC_Open(MS_U32 u32Addr, MS_U8 u8Chid, MS_U8 u8Sid, MS_BOOL bTSmode, MS_BOOL bPriority, MS_BOOL bFlush, MS_BOOL bNewPkt); 259 void HAL_TSIO_SGDMAIN_VC_Close(MS_U8 u8Chid); 260 void HAL_TSIO_SGDMAIN_Global_Pacing(void); 261 void HAL_TSIO_SGDMAIN_VC_Pacing(MS_U8 u8Chid, MS_BOOL bTSmode, MS_U32 Pacing); 262 void HAL_TSIO_SGDMAIN_Start(void); 263 void HAL_TSIO_SGDMAIN_IntRead(MS_U8 u8Chid, MS_U16 *u16Status); 264 void HAL_TSIO_SGDMAIN_IntClr(MS_U8 u8Chid); 265 MS_U64 HAL_TSIO_SGDMAIN_IntAll(void); 266 void HAL_TSIO_SGDMAIN_IntClrAll(void); 267 void HAL_TSIO_SGDMAIN_PidFltEnable(MS_U8 u8Sid, MS_BOOL bEnable); 268 void HAL_TSIO_SGDMAIN_Flt_SetPid(MS_U16 u16FltId, MS_U16 u16PID); 269 void HAL_TSIO_SGDMAIN_Flt_SetSid(MS_U16 u16FltId, MS_U8 u8Sid); 270 MS_U32 HAL_TSIO_SGDMAIN_ReadSram(MS_U8 u8Chid, HAL_SGDMA_SRAM eSram); 271 272 273 //======================================================= 274 // SGDMA_OUT API 275 //======================================================= 276 void HAL_TSIO_SGDMAOUT_Init(void); 277 void HAL_TSIO_SGDMAOUT_VC_Open(MS_U32 u32Addr, MS_U8 u8Chid, MS_BOOL bSecurity); 278 void HAL_TSIO_SGDMAOUT_VC_Close(MS_U8 u8Chid); 279 void HAL_TSIO_SGDMAOUT_Start(void); 280 void HAL_TSIO_SGDMAOUT_IntRead(MS_U8 u8Chid, MS_U16 *u16Status); 281 void HAL_TSIO_SGDMAOUT_IntClr(MS_U8 u8Chid); 282 MS_U64 HAL_TSIO_SGDMAOUT_IntAll(void); 283 void HAL_TSIO_SGDMAOUT_IntClrAll(void); 284 MS_U32 HAL_TSIO_SGDMAOUT_ReadSram(MS_U8 u8Chid, HAL_SGDMA_SRAM eSram, MS_BOOL bLSB); 285 286 //======================================================= 287 // SVID table API 288 //======================================================= 289 void HAL_TSIO_SVIDTBL_Set(MS_U8 u8Tblid, MS_U8 u8Sid, MS_U8 u8Sourceid, MS_BOOL bLive); 290 291 //======================================================= 292 // CC API 293 //======================================================= 294 void HAL_TSIO_CC_RxClr(void); 295 void HAL_TSIO_CC_RxIntClr(void); 296 void HAL_TSIO_CC_RxEnable(MS_BOOL bEnable); 297 MS_BOOL HAL_TSIO_CC_RxInt(void); 298 MS_U16 HAL_TSIO_CC_RxErrStatus(void); 299 MS_U16 HAL_TSIO_CC_RxReadSize(void); 300 MS_U32 HAL_TSIO_CC_RxReadData(MS_U8 u8Addr); 301 MS_U32 HAL_TSIO_CC_RxReadData_Fast(MS_U8 u8Addr); 302 void HAL_TSIO_CC_RxReadData_FastEnable(MS_BOOL bEnable); 303 void HAL_TSIO_CC_TxClr(void); 304 void HAL_TSIO_CC_TxIntClr(void); 305 void HAL_TSIO_CC_TxEnable(MS_BOOL bEnable); 306 void HAL_TSIO_CC_TxWriteData(MS_U8 u8Addr, MS_U32 u32Data); 307 void HAL_TSIO_CC_TxWriteSize(MS_U16 u16Size); 308 MS_BOOL HAL_TSIO_CC_TxInt(void); 309 void HAL_TSIO_CC_TxWriteData_Fast(MS_U32 u32Data); 310 void HAL_TSIO_CC_TxWriteData_FastEnable(MS_BOOL bEnable); 311 312 //======================================================= 313 // Loc Decrypt API 314 //======================================================= 315 void HAL_TSIO_LOCDEC_Xiu_Lock(MS_U8 u8Xiu); 316 void HAL_TSIO_LOCDEC_Xiu_Unlock(void); 317 void HAL_TSIO_LOCDEC_ScbFixRule(MS_BOOL bEnable); 318 MS_BOOL HAL_TSIO_LOCDEC_Key_Set( MS_U8 u8Sid, MS_U8 *u8Key, MS_U16 u16KeySize, MS_BOOL bOddKey); 319 MS_BOOL HAL_TSIO_LOCDEC_KeySetDone(void); 320 void HAL_TSIO_LOCDEC_KeyEnable(MS_U8 u8Sid, MS_BOOL bEnable); 321 void HAL_TSIO_LOCDEC_PrivilegeSlotEnable(MS_U8 u8Sid, MS_BOOL bEnable); 322 void HAL_TSIO_LOCDEC_SecureSlotEnable(MS_U8 u8Sid, MS_BOOL bEnable); 323 void HAL_TSIO_LOCDEC_SetSWKeyProperty(MS_U32 keyProperty); 324 325 //======================================================= 326 // Get Infomation API 327 //======================================================= 328 MS_U16 HAL_TSIO_GetLoselockcnt(void); 329 330 //======================================================= 331 // Bit training API 332 //======================================================= 333 void HAL_TSIO_Bittraining_init(void); 334 void HAL_TSIO_Bittraining_init_dynamic(void); 335 MS_BOOL HAL_TSIO_Bittraining_Getremapstate(void); 336 void HAL_TSIO_Bittraining_Setvalue(MS_BOOL bEarly, MS_BOOL bLate); 337 MS_U32 HAL_TSIO_DBG_Read(MS_U16 u16Dbg); 338 MS_U8 HAL_TSIO_Bittraining_GetPhase(MS_U8 u8Phase); 339 void HAL_TSIO_Bittraining_GetElinfo(MS_BOOL bEarly); 340 MS_U16 HAL_TSIO_Bittraining_CheckPrbsErrcnt(void); 341 void HAL_TSIO_Bittraining_GetPhaseinfo(void); 342 343 //======================================================= 344 // Interrupt API 345 //======================================================= 346 MS_BOOL HAL_TSIO_Int_Operation_Read(void); 347 void HAL_TSIO_Int_Operation_Enable(MS_BOOL bEnable); 348 void HAL_TSIO_Int_Operation_Clear(void); 349 void HAL_TSIO_Int_Bittraining_Enable(MS_BOOL bEnable); 350 void HAL_TSIO_Int_Bittraining_Clear(void); 351 MS_BOOL HAL_TSIO_Int_Bittraining_Read(void); 352 353 //======================================================= 354 // Analog phase API 355 //======================================================= 356 void HAL_TSIO_Analogphase_Pllreset(void); 357 void HAL_TSIO_Analogphase_Init(HAL_TSIO_CLK eClk, MS_BOOL bLoopback); 358 void HAL_TSIO_Analogphase_Set(MS_BOOL bSelect, MS_U8 u8Phase, MS_U8 u8Gap); 359 MS_U16 HAL_TSIO_Analogphase_Read(MS_BOOL bEarly); 360 void HAL_TSIO_Analogphase_Start(void); 361 MS_U16 HAL_TSIO_Analogphase_GetPuhstatus(void); 362 void HAL_TSIO_Analogphase_Exit(void); 363 364 //======================================================= 365 // TSIO Filter API (use for bypass smc) 366 //======================================================= 367 void HAL_TSIO_Filter_Enable(MS_U16 u16FltId, MS_BOOL bEnable); 368 void HAL_TSIO_Filter_SetPid(MS_U16 u16FltId, MS_U16 u16Pid); 369 void HAL_TSIO_Filter_SetSid(MS_U16 u16FltId, MS_U8 u8Sid); 370 371 //======================================================= 372 // Other API 373 //======================================================= 374 void HAL_TSIO_RxRecord_Start(MS_BOOL bEnable); 375 void HAL_TSIO_RxRecord_Setbuf(MS_U32 u32Headaddr, MS_U32 u32Tailaddr); 376 void HAL_TSIO_TSP_BLK_Set(MS_BOOL bEnable); 377 void HAL_TSIO_STRLD_SET(MS_U8 u8index); 378 379 #endif // #ifndef __HAL_TSIO_H__ 380 381