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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 /////////////////////////////////////////////////////////////////////////////// 94 95 /////////////////////////////////////////////////////////////////////////////////////////////////// 96 /// 97 /// file drvTSP.h 98 /// @brief Transport Stream Processer (TSP) Driver Interface 99 /// @author MStar Semiconductor,Inc. 100 /// @attention 101 /// All TSP DDI are not allowed to use in any interrupt context other than TSP ISR and Callback 102 /////////////////////////////////////////////////////////////////////////////////////////////////// 103 104 #ifndef _DRV_TSP_H_ 105 #define _DRV_TSP_H_ 106 107 108 109 #ifdef __cplusplus 110 extern "C" 111 { 112 #endif 113 114 #define TSP_VER_1_0 0x0100UL 115 #define TSP_VER_2_0 0x0200UL 116 #define TSP_VER_3_0 0x0300UL 117 #define TSP_VER_4_0 0x0400UL 118 119 #define TSP_VERSION TSP_VER_3_0 120 121 //------------------------------------------------------------------------------------------------- 122 // Driver Capability 123 //------------------------------------------------------------------------------------------------- 124 125 #define DRVTSP_FILTER_DEPTH 16UL // TSP_FILTER_DEPTH 126 127 /// TSP byte address alignment unit 128 #define DRVTSP_ALIGN_UNIT 8UL 129 130 /// TSP byte address alignment macro 131 #define DRVTSP_ALIGN(_x) ALIGN_8((MS_U32)_x) 132 133 //------------------------------------------------------------------------------------------------- 134 // Macro and Define 135 //------------------------------------------------------------------------------------------------- 136 /// Transport stream null PID 137 #define DRVTSP_PID_NULL 0x1FFFUL 138 #define MSIF_TSP_LIB_CODE {'T','S','P','3'} // Lib code 139 #define MSIF_TSP_LIBVER {'1','3'} // LIB version 140 #define MSIF_TSP_BUILDNUM {'0','3'} // Build Number 141 #define MSIF_TSP_CHANGELIST {'0','0','6','0','7','2','6','6'} // P4 ChangeList Number 142 143 #define TSP_DRV_VERSION /* Character String for DRV/API version */ \ 144 MSIF_TAG, /* 'MSIF' */ \ 145 MSIF_CLASS, /* '00' */ \ 146 MSIF_CUS, /* 0x0000 */ \ 147 MSIF_MOD, /* 0x0000 */ \ 148 MSIF_CHIP, \ 149 MSIF_CPU, \ 150 MSIF_TSP_LIB_CODE, /* IP__ */ \ 151 MSIF_TSP_LIBVER, /* 0.0 ~ Z.Z */ \ 152 MSIF_TSP_BUILDNUM, /* 00 ~ 99 */ \ 153 MSIF_TSP_CHANGELIST, /* CL# */ \ 154 MSIF_OS 155 156 157 //------------------------------------------------------------------------------------------------- 158 // Type and Structure 159 //------------------------------------------------------------------------------------------------- 160 /// TSP DDI return value 161 162 /// @name TSP_Result 163 /// @ref TSP_Result 164 /// return value 165 /// @{ 166 typedef enum 167 { 168 DRVTSP_FAIL = 0, 169 DRVTSP_OK, 170 DRVTSP_INVALID_PARAM, 171 DRVTSP_FUNC_ERROR, 172 DRVTSP_INVALID_SECFLT, 173 DRVTSP_NOT_SUPPORTED, 174 } TSP_Result; 175 176 /// @} 177 178 #define DOUBLE_BUFFER_ENABLE TRUE 179 #define DOUBLE_BUFFER_SWITCH FALSE 180 181 #if 0 182 /// TSP channel Type 183 typedef enum //_DrvTSP_FltType 184 { 185 // get TS from Live stream 186 E_DRVTSP_FLT_TYPE_VIDEO = 0x00000000, ///<\n 187 E_DRVTSP_FLT_TYPE_AUDIO , ///<\n 188 E_DRVTSP_FLT_TYPE_AUDIO2 , ///<\n 189 E_DRVTSP_FLT_TYPE_PVR , ///<\n 190 191 // Section Filter Group 192 E_DRVTSP_FLT_TYPE_SECTION_MASK = 0x20000000, ///<\n 193 E_DRVTSP_FLT_TYPE_SECTION , ///<\n 194 E_DRVTSP_FLT_TYPE_PCR , ///<\n 195 E_DRVTSP_FLT_TYPE_PES , ///<\n 196 E_DRVTSP_FLT_TYPE_PACKET , //[Reserved] 197 E_DRVTSP_FLT_TYPE_TELETEXT , 198 E_DRVTSP_FLT_TYPE_EMM , //[Reserved] 199 E_DRVTSP_FLT_TYPE_ECM , //[Reserved] 200 201 202 E_DRVTSP_FLT_SOURCE_TYPE_MASK = 0xC0000000, 203 E_DRVTSP_FLT_SOURCE_TYPE_LIVE = 0x80000000, 204 E_DRVTSP_FLT_SOURCE_TYPE_FILE = 0x40000000, 205 206 E_DRVTSP_FLT_TYPE_LAST_ENUM 207 208 } DrvTSP_FltType; 209 #endif 210 211 #define DrvTSP_FltType MS_U32 212 // get TS from Live stream 213 #define E_DRVTSP_FLT_TYPE_VIDEO 0x00000000UL ///<\n 214 #define E_DRVTSP_FLT_TYPE_AUDIO 0x00000001UL ///<\n 215 #define E_DRVTSP_FLT_TYPE_AUDIO2 0x00000002UL ///<\n 216 #define E_DRVTSP_FLT_TYPE_PVR 0x00000003UL ///<\n 217 #define E_DRVTSP_FLT_TYPE_PVR1 0x00000004UL 218 #define E_DRVTSP_FLT_TYPE_VIDEO3D 0x00000008UL 219 #define E_DRVTSP_FLT_TYPE_CB 0x00000009UL 220 #define E_DRVTSP_FLT_TYPE_AUDIO3 0x0000000AUL 221 #define E_DRVTSP_FLT_TYPE_AUDIO4 0x0000000BUL 222 223 // Section Filter Group 224 #define E_DRVTSP_FLT_TYPE_SECTION_MASK 0x01000000UL ///<\n 225 #define E_DRVTSP_FLT_TYPE_SECTION 0x01000001UL ///<\n 226 #define E_DRVTSP_FLT_TYPE_PCR 0x01000002UL ///<\n 227 #define E_DRVTSP_FLT_TYPE_PES 0x01000003UL ///<\n 228 #define E_DRVTSP_FLT_TYPE_PACKET 0x01000004UL //[Reserved] 229 #define E_DRVTSP_FLT_TYPE_TELETEXT 0x01000005UL 230 #define E_DRVTSP_FLT_TYPE_EMM 0x01000006UL //[Reserved] 231 #define E_DRVTSP_FLT_TYPE_ECM 0x01000007UL //[Reserved] 232 #define E_DRVTSP_FLT_TYPE_SECTION_VER 0x01000008UL 233 #define E_DRVTSP_FLT_TYPE_SECTION_NO_PUSI 0x01000009UL 234 235 #define E_DRVTSP_FLT_TYPE_LAST_ENUM 0x0100000AUL 236 237 #define E_DRVTSP_FLT_MASK 0xF2FC0F00UL 238 #define E_DRVTSP_FLT_SOURCE_TYPE_MASK 0xC0FC0000UL 239 #define E_DRVTSP_FLT_SOURCE_TYPE_LIVE 0x80000000UL 240 #define E_DRVTSP_FLT_SOURCE_TYPE_FILE 0x40000000UL 241 #define E_DRVTSP_FLT_SOURCE_TYPE_TS1 0x00800000UL 242 #define E_DRVTSP_FLT_SOURCE_TYPE_TS2 0x00400000UL 243 #define E_DRVTSP_FLT_SOURCE_TYPE_TSCB 0x00200000UL 244 #define E_DRVTSP_FLT_SOURCE_TYPE_FILE1 0x00100000UL // file1 fource from TS1 245 #define E_DRVTSP_FLT_SOURCE_TYPE_FILE2 0x00080000UL // file2 fource from TS2 246 #define E_DRVTSP_FLT_SOURCE_TYPE_LIVEB E_DRVTSP_FLT_SOURCE_TYPE_FILE 247 248 // Source ID define. For merge stream 249 #define E_DRVTSP_FLT_SOURCEID_SHIFT 8UL 250 #define E_DRVTSP_FLT_SOURCEID_MASK 0x00000F00UL 251 252 #define E_DRVTSP_FLT_TYPE_DUPSEC 0x02000000UL // Only for section filter duplicate patch 253 254 #define E_DRVTSP_FLT_SCMB_MASK 0x30000000UL 255 #define E_DRVTSP_FLT_TYPE_SCMB 0x20000000UL 256 #define E_DRVTSP_FLT_TYPE_SCMB_SHAREKEY 0x10000000UL 257 258 #define DrvTSP_FltMode MS_U32 259 #define E_DRVTSP_FLT_MODE_CONTI 0x00000000UL 260 #define E_DRVTSP_FLT_MODE_ONESHOT 0x00000001UL 261 #define E_DRVTSP_FLT_MODE_PESSCMCHK 0x00000003UL //Only for PES type checking SCMB status 262 263 // optional 264 #define E_DRVTSP_FLT_MODE_CRCCHK 0x00000002UL 265 #define E_DRVTSP_FLT_MODE_AUTO_ADDR 0x00000004UL // auto move read point mode 266 267 #define DrvTSP_PKTDMXSrcType MS_U32 268 #define E_DRVTSP_PKTSRC_DEMUX0 0x00000001UL 269 #define E_DRVTSP_PKTSRC_DEMUXFILE 0x00000002UL 270 #define E_DRVTSP_PKTSRC_DEMUX1 0x00000003UL 271 #define E_DRVTSP_PKTSRC_DEMUX2 0x00000004UL 272 #define E_DRVTSP_PKTSRC_DEMUXMMFI0 0x00000006UL 273 #define E_DRVTSP_PKTSRC_DEMUXMMFI1 0x00000007UL 274 275 //-------------------------------------------------- 276 // Debug table 277 typedef enum 278 { 279 E_DRVTSP_DEBUG_CMD_NONE, 280 E_DRVTSP_DEBUG_CMD_CLEAR, 281 E_DRVTSP_DEBUG_CMD_ENABLE, 282 E_DRVTSP_DEBUG_CMD_DISABLE, 283 } DrvTSP_Debug_Cmd; 284 285 typedef enum 286 { 287 E_DRVTSP_DEBUG_SRC_TS0, 288 E_DRVTSP_DEBUG_SRC_TS1, 289 E_DRVTSP_DEBUG_SRC_TS2, 290 E_DRVTSP_DEBUG_SRC_FILE, 291 } DrvTSP_Debug_Src; 292 293 typedef enum 294 { 295 E_DRVTSP_DEBUG_TSIF_TS0, 296 E_DRVTSP_DEBUG_TSIF_TS1, 297 E_DRVTSP_DEBUG_TSIF_TSCB, 298 } DrvTSP_Debug_Tsif; 299 300 typedef enum 301 { 302 E_DRVTSP_DEBUG_FIFO_VIDEO, 303 E_DRVTSP_DEBUG_FIFO_AUDIO, 304 E_DRVTSP_DEBUG_FIFO_VIDEO3D, 305 E_DRVTSP_DEBUG_FIFO_AUDIOB, 306 E_DRVTSP_DEBUG_FIFO_AUDIOC, 307 E_DRVTSP_DEBUG_FIFO_AUDIOD, 308 } DrvTSP_Debug_Fifo; 309 310 typedef enum 311 { 312 E_DRVTSP_DEBUG_PKT_DEMUX_0, 313 E_DRVTSP_DEBUG_PKT_DEMUX_0_FILE, 314 E_DRVTSP_DEBUG_PKT_DEMUX_1, 315 E_DRVTSP_DEBUG_PKT_DEMUX_2, 316 E_DRVTSP_DEBUG_MMFI0, 317 E_DRVTSP_DEBUG_MMFI1, 318 } DrvTSP_Debug_Fifo_Src; 319 320 /// TSP channel state bit flags 321 typedef enum //_DrvTSP_FltState 322 { 323 E_DRVTSP_FLT_STATE_FREE = 0x00000000UL, ///<\n 324 E_DRVTSP_FLT_STATE_ALLOC = 0x00000001UL, ///<\n 325 E_DRVTSP_FLT_STATE_ENABLE = 0x00000002UL, ///<\n 326 E_DRVTSP_FLT_STATE_SCRAMBLED = 0x00000004UL, //[TODO] 327 E_DRVTSP_FLT_STATE_STREAM_AVAIL = 0x00000008UL, //[TODO] 328 E_DRVTSP_FLT_STATE_SCRAMBLED_ORG = 0x00000010UL, 329 E_DRVTSP_FLT_STATE_OVERFLOW = 0x00010000UL, //[Reserved] 330 E_DRVTSP_FLT_STATE_SUSPEND = 0x20000000UL, 331 E_DRVTSP_FLT_STATE_CBRUN = 0x40000000UL, // Callback processing 332 E_DRVTSP_FLT_STATE_FREEING = 0x80000000UL, // Free filter is running 333 E_DRVTSP_FLT_STATE_NA = 0xFFFFFFFFUL, 334 } DrvTSP_FltState; 335 336 337 /// TSP record mode 338 typedef enum //_DrvTSP_RecMode 339 { 340 //[TODO] rename REC_MODE to PVR_MODE 341 342 /// Record ENG0 by @ref E_DRVTSP_FLT_TYPE_PVR 343 E_DRVTSP_REC_MODE_ENG0_FLTTYPE = 0x00000000UL, // TSP_PVR_CTRL_ENG(0) 344 /// Record ENG1 by @ref E_DRVTSP_FLT_TYPE_PVR 345 E_DRVTSP_REC_MODE_ENG1_FLTTYPE = 0x00010000UL, // TSP_PVR_CTRL_ENG(1) 346 /// Record ENG0 bypass PID fliter 347 E_DRVTSP_REC_MODE_ENG0_BYPASS = 0x00000002UL, // TSP_PVR_CTRL_ENG(0) + TSP_PVR_CTRL_BYPASS 348 /// Record ENG1 bypass PID fliter 349 E_DRVTSP_REC_MODE_ENG1_BYPASS = 0x00010002UL, // TSP_PVR_CTRL_ENG(1) + TSP_PVR_CTRL_BYPASS 350 351 E_DRVTSP_REC_MODE_ENG0_FLT1CA = 0x00000004UL, 352 } DrvTSP_RecMode; 353 354 /// TSP Control Mode 355 typedef enum //_DrvTSP_CtrlMode 356 { 357 /// Input From Memory 358 E_DRVTSP_CTRL_MODE_MEM, 359 /// Input From Stream Source 0 360 E_DRVTSP_CTRL_MODE_TS0, 361 /// Input From Stream Source 1 362 E_DRVTSP_CTRL_MODE_TS1, 363 /// Input From Stream Source 2 364 E_DRVTSP_CTRL_MODE_TS2, 365 /// Input From Stream Source 3 366 E_DRVTSP_CTRL_MODE_TS3, 367 /// Enable bounding option for PVR descrambled stream 368 E_DRVTSP_CTRL_MODE_PVR_CA, 369 /// Enable bounding option for PVR1 descrambled stream 370 E_DRVTSP_CTRL_MODE_PVR1_CA, 371 /// Input TSFI and source is Live 372 E_DRVTSP_CTRL_MODE_TSFI_LIVE, 373 } DrvTSP_CtrlMode; 374 375 /// TSP input pad selection 376 typedef enum 377 { 378 E_DRVTSP_PAD_EXT_INPUT0 = 0x0, 379 E_DRVTSP_PAD_EXT_INPUT1 = 0x1, 380 E_DRVTSP_PAD_EXT_INPUT2 = 0x2, 381 E_DRVTSP_PAD_EXT_INPUT3 = 0x3, 382 E_DRVTSP_PAD_EXT_INPUT4 = 0x4, 383 E_DRVTSP_PAD_EXT_INPUT5 = 0x5, 384 E_DRVTSP_PAD_TSO = 0x6, 385 E_DRVTSP_PAD_DEMOD = 0x7, 386 E_DRVTSP_PAD_EXT_INPUT0_3WIRE = 0x80, 387 E_DRVTSP_PAD_EXT_INPUT1_3WIRE = 0x81, 388 E_DRVTSP_PAD_EXT_INPUT2_3WIRE = 0x82, 389 E_DRVTSP_PAD_EXT_INPUT3_3WIRE = 0x83, 390 E_DRVTSP_PAD_EXT_INPUT4_3WIRE = 0x84, 391 E_DRVTSP_PAD_EXT_INPUT5_3WIRE = 0x85, 392 } DrvTSP_PadIn; 393 394 #define DrvTSP_PadOut MS_U32 395 #define E_DRVTSP_OUTPAD_NONE 0x00000000UL 396 #define E_DRVTSP_OUTPAD_PAD1 0x00000001UL 397 #define E_DRVTSP_OUTPAD_PAD3 0x00000003UL 398 399 #define DrvTSP_PadOut_Mode MS_U32 400 #define E_DRVTSP_OUTPAD_MODE_MASK 0x70000000UL 401 #define E_DRVTSP_OUTPAD_FROM_DMD 0x00000000UL 402 #define E_DRVTSP_OUTPAD_FROM_S2P 0x10000000UL 403 #define E_DRVTSP_OUTPAD_FROM_TSO 0x20000000UL 404 #define E_DRVTSP_OUTPAD_FROM_S2P1 0x40000000UL 405 406 407 /// TSP interface 408 typedef enum 409 { 410 E_DRVTSP_IF_TS0 = 0x0, //TSIF0 411 E_DRVTSP_IF_TS1 = 0x1, //TSIF1 412 E_DRVTSP_IF_TS2 = 0x2, //TSIF2 413 E_DRVTSP_IF_TS3 = 0x3, //TSIF3 414 E_DRVTSP_IF_NUM = 4, 415 E_DRVTSP_IF_FI = 0x80, //TSFI (version 3.0 New) 416 417 } DrvTSP_If; 418 419 typedef struct 420 { 421 DrvTSP_PadIn ePad; 422 MS_BOOL bClkInv; 423 MS_BOOL bExtSync; 424 MS_BOOL bParallel; 425 } DrvTSP_If_Set; 426 427 /// FQ interface 428 typedef enum 429 { 430 E_DRVFQ_SRC_TSIF0 = 0x00, 431 E_DRVFQ_SRC_TSIF1 = 0x01, 432 E_DRVFQ_SRC_TSIF2 = 0x02, 433 E_DRVFQ_SRC_TSIF3 = 0x03, 434 435 E_DRVFQ_SRC_TSIFFI = 0x07, 436 E_DRVFQ_SRC_DEFAULT = 0xFF, 437 } DrvFQ_SrcIf; 438 439 //---------------------------------- 440 /// DMX debug table information structure 441 //---------------------------------- 442 typedef struct 443 { 444 DrvTSP_Debug_Cmd TspCmd; 445 DrvTSP_Debug_Src TspSrc; 446 DrvTSP_Debug_Fifo TspFifo; 447 } DrvTSP_DisContiCnt_info, DrvTSP_DropPktCnt_info; 448 449 typedef struct 450 { 451 DrvTSP_Debug_Cmd TspCmd; 452 DrvTSP_Debug_Tsif TspTsif; 453 } DrvTSP_LockPktCnt_info; 454 455 typedef struct 456 { 457 DrvTSP_Debug_Cmd TspCmd; 458 DrvTSP_Debug_Fifo TspFifo; 459 DrvTSP_Debug_Fifo_Src TspFifoSrc; 460 } DrvTSP_AVPktCnt_info; 461 462 // must alignment with TSP_TSDMA_CTRL_XXX in regTSP.h 463 typedef enum 464 { 465 /// TSP Engine 0 Transport Stream 466 E_DRVTSP_FILEIN_MODE_ENG0_TS = 0x00000000UL, //TSP_TSDMA_CTRL_ENG0 467 /// TSP Engine 0 Video PES Only 468 E_DRVTSP_FILEIN_MODE_ENG0_VPES = 0x00000004UL, //TSP_TSDMA_CTRL_VPES0 469 /// TSP Engine 0 Audio PES Only 470 E_DRVTSP_FILEIN_MODE_ENG0_APES = 0x00000008UL, //TSP_TSDMA_CTRL_APES0 471 /// TSP Engine 0 Audio2 PES Only 472 E_DRVTSP_FILEIN_MODE_ENG0_A2PES = 0x00000010UL, //TSP_TSDMA_CTRL_A2PES0 473 /// TSP Engine 0 Video3D PES Only 474 E_DRVTSP_FILEIN_MODE_ENG0_V3DPES = 0x00000020UL, //TSP_TSDMA_CTRL_V3DPES0 475 /// TSP Engine 0 Video3D PES Only 476 E_DRVTSP_FILEIN_MODE_ENG0_A3PES = 0x00000040UL, //TSP_TSDMA_CTRL_A3PES0 477 /// TSP Engine 0 Video3D PES Only 478 E_DRVTSP_FILEIN_MODE_ENG0_A4PES = 0x00000080UL, //TSP_TSDMA_CTRL_A4PES0 479 480 } DrvTSP_FileinMode; 481 482 483 typedef enum 484 { 485 /// Command Queue is Idle 486 E_DRVTSP_FILEIN_STATE_IDLE = 0000000000UL, 487 /// Command Queue is Busy 488 E_DRVTSP_FILEIN_STATE_BUSY = 0x00000001UL, 489 /// Command Queue is Paused. 490 E_DRVTSP_FILEIN_STATE_PAUSE = 0x00000002UL, 491 } DrvTSP_FileinState; 492 493 /// TSP TEI Remove Error Packet Infomation 494 typedef enum 495 { 496 E_TSP_DRV_TEI_REMOVE_AUDIO_PKT, ///< DMX TEI Remoce Audio Packet 497 E_TSP_DRV_TEI_REMOVE_VIDEO_PKT, ///< DMX TEI Remoce Video Packet 498 499 E_TSP_DRV_TEI_REMOVE_PKT0_LIVE, 500 E_TSP_DRV_TEI_REMOVE_PKT0_FILE, 501 E_TSP_DRV_TEI_REMOVE_PKT1, 502 E_TSP_DRV_TEI_REMOVE_PKT2, 503 504 }TSP_DRV_TEI_RmPktType; 505 506 #if 0 507 /// TSP notification event 508 typedef enum //_DrvTSP_Event 509 { 510 E_DRVTSP_EVENT_DATA_INIT = 0x00000000, 511 /// Section Data Ready 512 E_DRVTSP_EVENT_DATA_READY = 0x00000001, 513 /// Section Buffer Overflow 514 E_DRVTSP_EVENT_BUF_OVERFLOW = 0x00000002, 515 /// PVR Buffer is Full 516 E_DRVTSP_EVENT_PVRBUF_FULL = 0x00000010, 517 /// PVR Double Buffer Overflow 518 E_DRVTSP_EVENT_PVRBUF_OVERFLOW = 0x00000020, 519 520 521 /// TSP self task callback // optional --> default is CB by poll 522 E_DRVTSP_EVENT_CB_MASK = 0x80000000, 523 E_DRVTSP_EVENT_CB_POLL = 0x00000000, 524 E_DRVTSP_EVENT_CB_SELF = 0x80000000, 525 } DrvTSP_Event; 526 #endif 527 528 #define DrvTSP_Event MS_U32 529 #define E_DRVTSP_EVENT_DATA_INIT 0x00000000UL 530 /// Section Data Ready 531 #define E_DRVTSP_EVENT_DATA_READY 0x00000001UL 532 /// Section Buffer Overflow 533 #define E_DRVTSP_EVENT_BUF_OVERFLOW 0x00000002UL 534 /// Section Buffer CRC error 535 #define E_DRVTSP_EVENT_SEC_CRCERR 0x00000004UL 536 /// PVR Buffer is Full 537 #define E_DRVTSP_EVENT_PVRBUF_FULL 0x00000010UL 538 /// PVR Double Buffer Overflow 539 #define E_DRVTSP_EVENT_PVRBUF_OVERFLOW 0x00000020UL 540 /// Channel Browser Buffer is Full 541 #define E_DRVTSP_EVENT_CBBUF_FULL 0x00000040UL 542 #define E_DRVTSP_EVENT_CBBUF_OVERFLOW 0x00000080UL 543 ///PVR2 Buffer is Full 544 #define E_DRVTSP_EVENT_PVR2BUF_FULL 0x00000100UL 545 #define E_DRVTSP_EVENT_PVR2BUF_OVERFLOW 0x00000200UL 546 547 548 /// TSP self task callback // optional --> default is CB by poll 549 #define E_DRVTSP_EVENT_CB_MASK 0x80000000UL 550 #define E_DRVTSP_EVENT_CB_POLL 0x00000000UL 551 #define E_DRVTSP_EVENT_CB_SELF 0x80000000UL 552 553 /// TSP file in Packet mode 554 typedef enum //_DrvTSP_PacketMode 555 { 556 E_DRVTSP_PKTMODE_188 = 0x00000000UL, 557 E_DRVTSP_PKTMODE_192 = 0x00000001UL, 558 E_DRVTSP_PKTMODE_204 = 0x00000002UL, 559 E_DRVTSP_PKTMODE_130 = 0x00000003UL, // RVU 560 E_DRVTSP_PKTMODE_134 = 0x00000004UL, // RVU with timestamp 561 } DrvTSP_PacketMode; 562 563 /// TSP notification event message 564 typedef struct //_DrvTSP_Msg 565 { 566 /// Union data type of message 567 union 568 { 569 /// FltInfo message 570 /// - Byte[0] : Section filter id 571 /// - Byte[1] : TSP id 572 MS_U32 FltInfo; 573 /// PvrBufId 574 /// - Byte[0] : PVR buffer id 575 /// - Byte[1] : PVR engine id 576 MS_U32 PvrBufId; 577 }; 578 579 } DrvTSP_Msg; 580 581 typedef enum //_DrvTSP_DbgLevel 582 { 583 E_DRVTSP_DBG_Release = 0, 584 E_DRVTSP_DBG_L1, // display error msg 585 E_DRVTSP_DBG_L2, // display error msg and enter while(1) 586 } DrvTSP_DbgLevel; 587 588 /// @name DrvTSP_Msg 589 /// Macro definitions for manipulating DrvTSP_Msg 590 /// @{ 591 #define MSG_FLTINFO_SEC_ID_MASK 0x000000FFUL 592 #define MSG_FLTINFO_SEC_ID_SHFT 0UL 593 #define MSG_FLTINFO_ENG_ID_MASK 0x0000FF00UL 594 #define MSG_FLTINFO_ENG_ID_SHFT 8UL 595 #define MSG_PVRBUF_ID_MASK 0x000000FFUL 596 #define MSG_PVRBUF_ID_SHFT 0UL 597 #define MSG_PVRBUF_ID_NULL 0xFFUL 598 #define MSG_PVR_ID_MASK 0x0000FF00UL 599 #define MSG_PVR_ID_SHFT 8UL 600 601 /// @} 602 603 #define TSP_MAX_SIGFLAG_NUM 10UL 604 #define TSP_MAX_PVRSIGFLAG_NUM 10UL 605 typedef struct DLL_PACKED 606 { 607 MS_U32 u32Eng; 608 MS_U32 u32EvtWaitOpt; 609 MS_U32 u32DmxEvt; 610 MS_U32 u32TspEvt; 611 612 MS_U32 u32PvrBufFullFlag[TSP_MAX_PVRSIGFLAG_NUM]; 613 614 MS_U32 u32SecRdyFlag[TSP_MAX_SIGFLAG_NUM]; 615 MS_U32 u32SecOvfFlag[TSP_MAX_SIGFLAG_NUM]; 616 MS_U32 u32SecCrcErrFlag[TSP_MAX_SIGFLAG_NUM]; 617 618 MS_S32 s32KerModeTspEvtId; //For kernel mode, every user callback process must has itself eventid in multiple process support 619 MS_U32 u32TblIndex; 620 }DrvTSP_IoSignal; 621 622 623 typedef enum 624 { 625 E_DRVTSP_CAP_PID_FILTER_NUM = 0, // Get filter number 626 E_DRVTSP_CAP_SEC_FILTER_NUM = 1, 627 E_DRVTSP_CAP_SEC_BUF_NUM = 2, 628 629 E_DRVTSP_CAP_PVR_ENG_NUM = 3, 630 E_DRVTSP_CAP_PVR_FILTER_NUM = 4, // Get pvr filter number 631 E_DRVTSP_CAP_PVR1_FILTER_NUM = 5, // Get pvr1 filter number 632 633 E_DRVTSP_CAP_MMFI0_FILTER_NUM = 6, // Get MMFI0 filter number 634 E_DRVTSP_CAP_MMFI1_FILTER_NUM = 7, // Get MMFI1 filter number 635 636 E_DRVTSP_CAP_TSIF_NUM = 8, 637 E_DRVTSP_CAP_DEMOD_NUM = 9, 638 E_DRVTSP_CAP_TS_PAD_NUM = 10, 639 E_DRVTSP_CAP_VQ_NUM = 11, 640 641 E_DRVTSP_CAP_CA_FLT_NUM = 12, // Get dscmb filter number 642 E_DRVTSP_CAP_CA_KEY_NUM = 13, 643 644 E_DRVTSP_CAP_FW_ALIGN = 14, 645 E_DRVTSP_CAP_VQ_ALIGN = 15, 646 E_DRVTSP_CAP_VQ_PITCH = 16, 647 E_DRVTSP_CAP_SEC_BUF_ALIGN = 17, 648 649 E_DRVTSP_CAP_PVR_ALIGN = 18, 650 E_DRVTSP_CAP_PVRCA_PATH_NUM = 19, 651 E_DRVTSP_CAP_SHAREKEY_FLT_RANGE = 20, 652 E_DRVTSP_CAP_PVRCA0_FLT_RANGE = 21, 653 E_DRVTSP_CAP_PVRCA1_FLT_RANGE = 22, 654 E_DRVTSP_CAP_PVRCA2_FLT_RANGE = 23, 655 E_DRVTSP_CAP_SHAREKEY_FLT1_RANGE = 24, 656 E_DRVTSP_CAP_SHAREKEY_FLT2_RANGE = 25, 657 658 E_DRVTSP_CAP_HW_TYPE = 26, 659 660 E_DRVTSP_CAP_RESOURCE_SIZE = 27, // Get the data structure size of private resource (share resource) 661 662 E_DRVTSP_CAP_VFIFO_NUM = 28, // Get VFIFO support number 663 E_DRVTSP_CAP_AFIFO_NUM = 29, // Get AFIFO support number 664 665 E_DRVTSP_CAP_HWPCR_SUPPORT = 30, // Get HWPCR support status 666 E_DRVTSP_CAP_PCRFLT_START_IDX = 31, // Get PCR start index 667 668 E_DRVTSP_CAP_HWWP_SET_NUM = 32, // Get TSP write protect set numbers 669 670 E_DRVTSP_CAP_DSCMB_ENG_NUM = 33, // Get DSCMB engine numbers 671 672 E_DRVTSP_CAP_MAX_MERGESTR_NUM = 34, // Get Maxumum merge stream number 673 E_DRVTSP_CAP_MAX_SEC_FLT_DEPTH = 35, 674 E_DRVTSP_CAP_FW_BUF_SIZE = 36, 675 E_DRVTSP_CAP_FW_BUF_RANGE = 37, 676 E_DRVTSP_CAP_VQ_BUF_RANGE = 38, 677 E_DRVTSP_CAP_SEC_BUF_RANGE = 39, 678 E_DRVTSP_CAP_FIQ_NUM = 40, 679 E_DRVTSP_CAP_NULL, 680 } DrvTSP_Cap; 681 682 typedef enum 683 { 684 E_DRVTSP_HW_STATUS = 0, 685 E_DRVTSP_HW_INIT, 686 E_DRVTSP_HW_ALIVE, 687 E_DRVTSP_HW_DEALIVE, 688 } DrvTSP_HW_Status; 689 690 typedef enum 691 { 692 E_DRVTSP_SW_INIT = 0, 693 E_DRVTSP_SW_INIT_FAIL, 694 E_DRVTSP_SW_SUSPEND, 695 E_DRVTSP_SW_RESUME, 696 E_DRVTSP_SW_POWEROFF, 697 E_DRVTSP_SW_CLOSE, 698 E_DRVTSP_SW_EXIT, 699 } DrvTSP_SW_Status; 700 701 // legacy 702 typedef enum{ 703 E_DRVTSP_SCMB_NONE = 0x00000000UL, 704 E_DRVTSP_SCMB_TS = 0x00000001UL, 705 E_DRVTSP_SCMB_PES = 0x00000002UL, 706 E_DRVTSP_SCMB_TS_PES = (E_DRVTSP_SCMB_TS| E_DRVTSP_SCMB_PES), 707 } DrvTSP_Scmb_Level; 708 709 //---------------- 710 //For Tee 711 //---------------- 712 #ifdef SECURE_PVR_ENABLE 713 typedef enum 714 { 715 E_DRVTSP_REE_TO_TEE_CMD_NULL, 716 E_DRVTSP_REE_TO_TEE_CMD_FW_LoadCode, //None parameters 717 E_DRVTSP_REE_TO_TEE_CMD_SET_VqBuf, //None parameters 718 E_DRVTSP_REE_TO_TEE_CMD_SET_PvrBuf, //Param1: Engine id, Param2: Option 1 is reset buffer to 0 719 E_DRVTSP_REE_TO_TEE_CMD_SET_FileinBuf, //Param1: Engine id, Param2: Buf address, Param3: Buf size 720 E_DRVTSP_REE_TO_TEE_CMD_GET_PvrWPtr, //Param1: Engine id, Param2: Return Buf address 721 E_DRVTSP_REE_TO_TEE_CMD_SET_MMFIBuf //Param1: Engine id, Param2: Return Buf address 722 } TSP_REE_TO_TEE_CMD_TYPE; 723 724 typedef struct DLL_PACKED 725 { 726 MS_U32 u32BufId; 727 MS_U32 u32BufOpt; 728 MS_U32 u32BufSize; 729 MS_PHY phyBufAddr; 730 }DrvTSP_SecureBuf; 731 732 #endif //SECURE_PVR_ENABLE 733 734 // TSP event define 735 #define TSP_TASK_EVENT_SECTION_SELF 0x00000001UL 736 #define TSP_TASK_EVENT_SECTION_POLL 0x00000002UL 737 #define TSP_TASK_EVENT_PVR0_RDY_SELF 0x00000004UL //PVR1 buffer0 738 #define TSP_TASK_EVENT_PVR1_RDY_SELF 0x00000008UL //PVR1 buffer0 739 #define TSP_TASK_EVENT_PVR0_RDY_POLL 0x00000010UL //PVR1 buffer0 740 #define TSP_TASK_EVENT_PVR1_RDY_POLL 0x00000020UL //PVR1 buffer0 741 #define TSP_TASK_EVENT_FLT_FREE 0x00000040UL 742 #define TSP_TASK_EVENT_CBPVR0_RDY_SELF 0x00000080UL 743 #define TSP_TASK_EVENT_CBPVR0_RDY_POLL 0x00000100UL 744 #define TSP_TASK_EVENT_FWMSG 0x00000200UL 745 #define TSP_TASK_EVENT_PVR2PVR0_RDY_SELF 0x00000400UL //PVR2 buffer0 746 #define TSP_TASK_EVENT_PVR2PVR1_RDY_SELF 0x00000800UL //PVR2 buffer1 747 #define TSP_TASK_EVENT_PVR2PVR0_RDY_POLL 0x00001000UL //PVR2 buffer0 748 #define TSP_TASK_EVENT_PVR2PVR1_RDY_POLL 0x00002000UL //PVR2 buffer1 749 750 #define TSP_TASK_EVENT_PVR_SELF ( TSP_TASK_EVENT_PVR0_RDY_SELF | \ 751 TSP_TASK_EVENT_PVR1_RDY_SELF | \ 752 TSP_TASK_EVENT_CBPVR0_RDY_SELF | \ 753 TSP_TASK_EVENT_PVR2PVR0_RDY_SELF| \ 754 TSP_TASK_EVENT_PVR2PVR1_RDY_SELF) 755 #define TSP_TASK_EVENT_PVR_POLL ( TSP_TASK_EVENT_PVR0_RDY_POLL | \ 756 TSP_TASK_EVENT_PVR1_RDY_POLL | \ 757 TSP_TASK_EVENT_CBPVR0_RDY_POLL | \ 758 TSP_TASK_EVENT_PVR2PVR0_RDY_POLL| \ 759 TSP_TASK_EVENT_PVR2PVR1_RDY_POLL) 760 761 762 #define TSP_TASK_EVENT_GROUP_SELF ( TSP_TASK_EVENT_SECTION_SELF | \ 763 TSP_TASK_EVENT_PVR0_RDY_SELF | \ 764 TSP_TASK_EVENT_PVR1_RDY_SELF | \ 765 TSP_TASK_EVENT_CBPVR0_RDY_SELF | \ 766 TSP_TASK_EVENT_PVR2PVR0_RDY_SELF| \ 767 TSP_TASK_EVENT_PVR2PVR1_RDY_SELF) 768 #define TSP_TASK_EVENT_GROUP_POLL ( TSP_TASK_EVENT_SECTION_POLL | \ 769 TSP_TASK_EVENT_PVR0_RDY_POLL | \ 770 TSP_TASK_EVENT_PVR1_RDY_POLL | \ 771 TSP_TASK_EVENT_CBPVR0_RDY_POLL | \ 772 TSP_TASK_EVENT_PVR2PVR0_RDY_POLL| \ 773 TSP_TASK_EVENT_PVR2PVR1_RDY_POLL) 774 775 /// TSP notification function 776 typedef void (*P_DrvTSP_EvtCallback)(DrvTSP_Event eEvent, DrvTSP_Msg *pMsg); 777 778 779 //------------------------------------------------------------------------------------------------- 780 // Function and Variable 781 //------------------------------------------------------------------------------------------------- 782 783 // General API 784 TSP_Result MDrv_TSP_InitLibResource(void *pResMemAddr); 785 TSP_Result MDrv_TSP_Init(MS_PHY u32FWAddr, MS_U32 u32FWSize); // Set FW address and size 786 TSP_Result MDrv_TSP_Reinit(MS_BOOL bHK); 787 TSP_Result MDrv_TSP_PowerOff(void); 788 TSP_Result MDrv_TSP_Exit(void); 789 TSP_Result MDrv_TSP_Suspend(void); 790 TSP_Result MDrv_TSP_Resume(MS_PHY phyFWAddr, MS_U32 u32FWSize); 791 TSP_Result MDrv_TSP_Resume_Filter(void); 792 TSP_Result MDrv_TSP_Alive(MS_U32 u32EngId); 793 TSP_Result MDrv_TSP_Reset(void); 794 TSP_Result MDrv_TSP_HW_Lock_Release(void); 795 TSP_Result MDrv_TSP_RemoveDupAVPkt(MS_BOOL bEnable); 796 TSP_Result MDrv_TSP_RemoveDupAVFifoPkt(DrvTSP_FltType flttype, MS_BOOL bEnable); 797 TSP_Result MDrv_TSP_TEI_RemoveErrorPkt(TSP_DRV_TEI_RmPktType eDrvPktType, MS_BOOL bEnable); 798 TSP_Result MDrv_TSP_AU_BD_Mode_Enable(MS_BOOL bEnable); 799 TSP_Result MDrv_TSP_DropScmbPkt(DrvTSP_FltType eFilterType, MS_BOOL bEnable); 800 801 // Misc API 802 TSP_Result MDrv_TSP_SetFwDBGParam(MS_PHY phyAddr, MS_U32 u32Size, MS_U32 u32DbgWord); // for TSP f/w debug 803 TSP_Result MDrv_TSP_SetOperateMode(MS_U32 u32EngId, DrvTSP_CtrlMode eCtrlMode, MS_U8 u8DscmbEngSel); // Set TSP internal operate 804 TSP_Result MDrv_TSP_SelPad(MS_U32 u32EngId, DrvTSP_If eIf, DrvTSP_If_Set* pIfSet); // Set TSP input pad and ts0/ts1 805 TSP_Result MDrv_TSP_OutputPadCfg(DrvTSP_PadOut eOutputPad, DrvTSP_PadIn eInputPad, MS_BOOL bInParallel, MS_BOOL bEnable); 806 TSP_Result MDrv_TSP_OutputClkPhase(MS_U16 u16OutPad, MS_U16 u16Val, MS_BOOL bEnable, MS_U32 u32S2pOpt); 807 TSP_Result MDrv_TSP_AVFifo_Reset(DrvTSP_FltType eFilterType, MS_BOOL bFlush); 808 TSP_Result MDrv_TSP_AVFifo_Status(DrvTSP_FltType eFilterType, MS_U32 *u32FifoLevel); 809 TSP_Result MDrv_TSP_AVFifo_BlockEnable(DrvTSP_FltType eFilterType, MS_BOOL bEnable); 810 TSP_Result MDrv_TSP_AVFifo_SourceSelect(DrvTSP_PKTDMXSrcType ePKTSrc, MS_U32 u32FifoType); 811 TSP_Result MDrv_TSP_Parl_BitOrderSwap(MS_U32 u32EngId, DrvTSP_If eIf, MS_BOOL bInvert); 812 TSP_Result MDrv_TSP_Get_FW_VER(MS_U32* u32FWVer); 813 TSP_Result MDrv_TSP_Get_Intr_Count(MS_U32* pu32Count); 814 TSP_Result MDrv_TSP_Scmb_Status(MS_U32 u32EngId, DrvTSP_Scmb_Level* pScmbLevel); 815 TSP_Result MDrv_TSP_GetLastErr(void); 816 TSP_Result MDrv_TSP_Proc(MS_U32 u32EngId, MS_U32 u32FltId, TSP_Result* pRet, DrvTSP_Event* pEvt); // for non-OS TSP scheduling 817 TSP_Result MDrv_TSP_GetSTC(MS_U32 u32EngId, MS_U32 *pu32STC_32, MS_U32 *pu32STC); 818 TSP_Result MDrv_TSP_SetSTC(MS_U32 u32EngId, MS_U32 u32STC_32, MS_U32 u32STC); 819 TSP_Result MDrv_TSP_GetPCR(MS_U32 u32EngId, MS_U32 *pu32Pcr_32, MS_U32 *pu32Pcr); 820 TSP_Result MDrv_TSP_Flt_GetState(MS_U32 u32EngId, MS_U32 u32FltId, DrvTSP_FltState *peState); 821 TSP_Result MDrv_TSP_GetDscmbFltId_Range(MS_U32 u32EngId, MS_U32 *pu32StartId, MS_U32 *pu32EndId); 822 TSP_Result MDrv_TSP_GetDscmbEngIdx_BySource(DrvTSP_PKTDMXSrcType eInputSrc, MS_U32* pu32EngId); 823 TSP_Result MDrv_TSP_Dscmb_Source(MS_U32 u32EngId, DrvTSP_PKTDMXSrcType* peInputSrc, MS_BOOL bSet); 824 TSP_Result MDrv_TSP_STC64_Mode_Enable(MS_BOOL bEnable); 825 TSP_Result MDrv_TSP_STCClk_Adjust(MS_U32 u32EngId, MS_BOOL bUpClk, MS_U32 u32Percentage); 826 827 828 // NDS --> ECM 829 TSP_Result MDrv_TSP_SecFlt_SetEcmIdx(MS_U32 u32EngId, MS_U32 u32SecFltId, MS_U32 u32EcmIdx); 830 831 // PIDFlt API 832 TSP_Result MDrv_TSP_PidFlt_Alloc(MS_U32 u32EngId, DrvTSP_FltType eFilterType, MS_U32 *pu32PidFltId); 833 TSP_Result MDrv_TSP_PidFlt_Free(MS_U32 u32EngId, MS_U32 u32PidFltId); 834 TSP_Result MDrv_TSP_PidFlt_SetPid(MS_U32 u32EngId, MS_U32 u32PidFltId, MS_U16 u16PID); 835 TSP_Result MDrv_TSP_PidFlt_GetPid(MS_U32 u32EngId, MS_U32 u32PidFltId, MS_U32* pu32PID); 836 TSP_Result MDrv_TSP_PidFlt_SelSecFlt(MS_U32 u32EngId, MS_U32 u32PidFltId, MS_U32 u32SecFltId); 837 TSP_Result MDrv_TSP_PidFlt_SetInputSrc(MS_U32 u32EngId, MS_U32 u32PidFltId, DrvTSP_FltType eFltSrc); 838 TSP_Result MDrv_TSP_PidFlt_Enable(MS_U32 u32EngId, MS_U32 u32PidFltId, MS_BOOL bEnable); 839 TSP_Result MDrv_TSP_PidFlt_GetState(MS_U32 u32EngId, MS_U32 u32PidFltId, DrvTSP_FltState *peState); 840 TSP_Result MDrv_TSP_PidFlt_ChangeSource(MS_U32 u32EngId, MS_U32 u32PidFltId, DrvTSP_FltType eFilterType); 841 TSP_Result MDrv_TSP_PidFlt_GetScmbSts(DrvTSP_FltType FltSrc, MS_U32 u32FltGroupId, MS_U32 PidFltId, MS_U32 *pu32ScmbSts); 842 TSP_Result MDrv_TSP_FLT_LiveSrcSwitch(DrvTSP_FltType eFltSrcType); 843 TSP_Result MDrv_TSP_PidFlt_SetFltRushPass(MS_U32 u32EngId, MS_U32 u32PidFltId, MS_U8 u8Enable); 844 845 // SecFlt API 846 TSP_Result MDrv_TSP_SecFlt_Alloc(MS_U32 u32EngId, MS_U32 *pu32SecFltId); 847 TSP_Result MDrv_TSP_SecFlt_Free(MS_U32 u32EngId, MS_U32 u32SecFltId); 848 TSP_Result MDrv_TSP_SecFlt_SetMode(MS_U32 u32EngId, MS_U32 u32SecFltId, DrvTSP_FltMode eSecFltMode); 849 TSP_Result MDrv_TSP_SecFlt_SetPattern(MS_U32 u32EngId, MS_U32 u32SecFltId, MS_U8 *pu8Match, MS_U8 *pu8Mask, MS_U8 *pu8NotMask); 850 TSP_Result MDrv_TSP_SecFlt_ResetBuffer(MS_U32 u32EngId, MS_U32 u32SecFltId); 851 TSP_Result MDrv_TSP_SecFlt_SetBuffer(MS_U32 u32EngId, MS_U32 u32SecFltId, MS_PHY phyStartAddr, MS_U32 u32BufSize); 852 TSP_Result MDrv_TSP_SecFlt_SetReqCount(MS_U32 u32EngId, MS_U32 u32SecFltId, MS_U32 u32ReqCount); 853 TSP_Result MDrv_TSP_SecFlt_GetBufStart(MS_U32 u32EngId, MS_U32 u32SecFltId, MS_PHY *pphyBufStart); 854 TSP_Result MDrv_TSP_SecFlt_GetBufSize(MS_U32 u32EngId, MS_U32 u32SecFltId, MS_U32 *pu32BufSize); 855 TSP_Result MDrv_TSP_SecFlt_GetReadAddr(MS_U32 u32EngId, MS_U32 u32SecFltId, MS_PHY *pphyReadAddr); 856 TSP_Result MDrv_TSP_SecFlt_GetWriteAddr(MS_U32 u32EngId, MS_U32 u32SecFltId, MS_PHY *pphyWriteAddr); 857 858 TSP_Result MDrv_TSP_SecFlt_SetReadAddr(MS_U32 u32EngId, MS_U32 u32SecFltId, MS_PHY phyReadAddr); 859 TSP_Result MDrv_TSP_SecFlt_SetDataAddr(MS_U32 u32DataAddr); 860 TSP_Result MDrv_TSP_SecFlt_Notify(MS_U32 u32EngId, MS_U32 u32SecFltId, DrvTSP_Event eEvents, P_DrvTSP_EvtCallback pfCallback); 861 TSP_Result MDrv_TSP_SecFlt_GetState(MS_U32 u32EngId, MS_U32 u32SecFltId, DrvTSP_FltState *peState); 862 #ifdef CONFIG_UTOPIA_PROC_DBG_SUPPORT 863 TSP_Result MDrv_TSP_SecFlt_GetPattern(MS_U32 u32EngId, MS_U32 u32SecFltId, MS_U8 *pu8Match, MS_U8 *pu8Mask, MS_U8 *pu8NotMask); 864 #endif //CONFIG_UTOPIA_PROC_DBG_SUPPORT 865 866 // PVR API 867 TSP_Result MDrv_TSP_PVR_Eng_SetBuffer(MS_U8 u8PVRId, MS_PHY phyBufStart0, MS_PHY phyBufStart1, MS_U32 u32BufSize0, MS_U32 u32BufSize1); 868 TSP_Result MDrv_TSP_PVR_Eng_Start(MS_U8 u8PVRId, DrvTSP_RecMode eRecMode, MS_BOOL bStart); 869 TSP_Result MDrv_TSP_PVR_Eng_GetWriteAddr(MS_U8 u8PVRId, MS_PHY *pphy2WriteAddr); 870 TSP_Result MDrv_TSP_PVR_Eng_Notify(MS_U8 u8PVRId, DrvTSP_Event eEvents, P_DrvTSP_EvtCallback pfCallback); 871 TSP_Result MDrv_TSP_PVR_Eng_SetPacketMode(MS_U8 u8PVRId, MS_BOOL bSet); 872 TSP_Result MDrv_TSP_PVR_Eng_SelSrc(MS_U8 u8PVRId, DrvTSP_PKTDMXSrcType ePktSrc); 873 TSP_Result MDrv_TSP_PVR_BlockEnable(MS_U8 u8PVRId, MS_BOOL bEnable); 874 TSP_Result MDrv_TSP_PVR_Eng_TimeStampSetRecordStamp(MS_U8 u8PVRId, MS_U32 u32Stamp); 875 TSP_Result MDrv_TSP_PVR_Eng_TimeStampGetRecordStamp(MS_U8 u8PVRId,MS_U32* u32Stamp); 876 TSP_Result MDrv_TSP_PVR_TimeStampSetPlaybackStamp(MS_U32 u32Stamp); 877 TSP_Result MDrv_TSP_PVR_TimeStampGetPlaybackStamp(MS_U32* u32Stamp); 878 TSP_Result MDrv_TSP_PVR_TimeStamp(MS_BOOL bEnable); 879 880 TSP_Result MDrv_TSP_PVR_Eng_SetPlaybackStampClk(MS_U32 u32EngId, MS_U32 u32Clk); 881 TSP_Result MDrv_TSP_PVR_Eng_SetRecordStampClk(MS_U32 u32PvrId, MS_U32 u32Clk); 882 TSP_Result MDrv_TSP_PVR_Eng_IsStart(MS_U32 u32PvrId, MS_BOOL *pbIsStart); 883 884 TSP_Result MDrv_TSP_PVRCA_Close(MS_U8 u8PVRId); 885 886 887 #define MDrv_TSP_PVR_Notify(eEvents, pfCallback) MDrv_TSP_PVR_Eng_Notify(0, eEvents, pfCallback) 888 889 // File API 890 TSP_Result MDrv_TSP_File_SetAddr(MS_PHY phyStreamAddr); 891 TSP_Result MDrv_TSP_File_SetSize(MS_U32 u32StreamSize); 892 TSP_Result MDrv_TSP_File_Start(DrvTSP_FileinMode eFileinMode); 893 TSP_Result MDrv_TSP_File_Stop(void); 894 TSP_Result MDrv_TSP_File_Pause(void); 895 TSP_Result MDrv_TSP_File_Resume(void); 896 TSP_Result MDrv_TSP_File_GetState(DrvTSP_FileinState *peFileinState); 897 TSP_Result MDrv_TSP_File_SetRate(MS_U32 u32Div2); 898 TSP_Result MDrv_TSP_File_SetPacketMode(DrvTSP_PacketMode PKT_Mode); 899 TSP_Result MDrv_TSP_File_CMDQ_GetSlot(MS_U32 *pu32EmptySlot); 900 TSP_Result MDrv_TSP_File_CMDQ_Reset(void); 901 TSP_Result MDrv_TSP_CmdQFifo_Status(MS_U8 *pu8FifoLevel); 902 TSP_Result MDrv_TSP_ResetFileinTimestamp(void); 903 TSP_Result MDrv_TSP_File_GetReadAddr(MS_PHY *pphyReadAddr); 904 TSP_Result MDrv_TSP_File_192BlockScheme_En(MS_BOOL bEnable); 905 TSP_Result MDrv_TSP_File_PS_Path_Enable(DrvTSP_FileinMode eFileinMode); 906 TSP_Result MDrv_TSP_File_TSIFSrcSel(DrvTSP_FltType eFltSrc, MS_BOOL bFileMode); 907 908 // Capacity query 909 TSP_Result MDrv_TSP_GetCap(DrvTSP_Cap eCap, void* pOutput); 910 TSP_Result MDrv_TSP_GetStatus(DrvTSP_HW_Status *HW_Status, DrvTSP_SW_Status *SW_Status); 911 TSP_Result MDrv_TSP_GetLibVer(const MSIF_Version **ppVersion); 912 TSP_Result MDrv_TSP_SetDbgLevel(DrvTSP_DbgLevel DbgLevel); 913 TSP_Result MDrv_TSP_GetTSIFStatus(DrvTSP_If eIf, DrvTSP_If_Set* pIfSet, MS_U16* pu16Clk); 914 915 //------------------------------------------------------------------------------------------------- 916 // OBSOLETE 917 //------------------------------------------------------------------------------------------------- 918 TSP_Result MDrv_TSP_Flt_SetOwner(MS_U32 u32EngId, MS_U32 u32FltIdStart, MS_U32 u32FltIdEnd, MS_BOOL bOwner); // Set/Get the ranges of filters used, which is for AEON/MHEG5 share TSP filters resource. 919 TSP_Result MDrv_TSP_PidFlt_ChkOwner(MS_U32 u32EngId, MS_U32 u32PidFltId); 920 TSP_Result MDrv_TSP_SetHK(MS_BOOL bIsHK); 921 TSP_Result MDrv_TSP_IsAccess(MS_U32 u32Try); 922 TSP_Result MDrv_TSP_UnlockAccess(void); 923 924 TSP_Result MDrv_TSP_TTX_SecFlt_GetWriteAddr(MS_U32 u32EngId, MS_U32 u32SecFltId, MS_PHY *pphyWriteAddr); // special case for TTX 925 TSP_Result MDrv_TSP_GetDbgPortInfo(MS_U32 u32DbgSel,MS_U32* u32DbgInfo); 926 TSP_Result MDrv_TSP_BurstLen(MS_U32 u32Len); 927 TSP_Result MDrv_TSP_GetFileInTimeStamp(MS_U32* u32TSLen); 928 #if 0 929 TSP_Result MDrv_TSP_ResetFileinTimestamp(void); 930 #endif 931 932 TSP_Result MDrv_TSP_SetVQueBuf(MS_PHY phyVQBaseAddr, MS_U32 u32VQBufLen); 933 TSP_Result MDrv_TSP_VQueEnable(MS_BOOL bEnable); 934 TSP_Result MDrv_TSP_VQueReset(MS_U8 u8VQID); 935 TSP_Result MDrv_TSP_VQueue_OverflowInt_En(MS_BOOL bEnable); 936 TSP_Result MDrv_TSP_Set_VQ_Threshold(MS_U8 u8req_len); 937 TSP_Result MDrv_TSP_Get_VQStatus(MS_U32* pu32Status); 938 939 TSP_Result MDrv_TSP_Set_MOBF_Set(MS_U8 u8Model, MS_U8 u8MobfIndex0, MS_U8 u8MobfIndex1); 940 941 void MDrv_TSP_WriteProtect_Enable(MS_BOOL bEnable, MS_PHY* pphyStartAddr, MS_PHY* pphyEndAddr); 942 void MDrv_TSP_OrzWriteProtect_Enable(MS_BOOL bEnable, MS_PHY phyStartAddr, MS_PHY phyEndAddr); 943 TSP_Result MDrv_TSP_TSIF_Enable(DrvTSP_If tsif, MS_BOOL bEnable); 944 TSP_Result MDrv_TSP_ReadDropPktCnt(MS_U16* pu16ADropCnt, MS_U16* pu16VDropCnt); 945 946 #define MDrv_TSP_PVR_SetBuffer(p1, p2...) MDrv_TSP_PVR_Eng_SetBuffer(0, p1, p2) 947 #define MDrv_TSP_PVR_Start(p1, p2...) MDrv_TSP_PVR_Eng_Start(0, p1, p2) 948 #define MDrv_TSP_PVR_GetWriteAddr(p1) MDrv_TSP_PVR_Eng_GetWriteAddr(0, p1) 949 #define MDrv_TSP_PVR_SetPacketMode(p1 ) MDrv_TSP_PVR_Eng_SetPacketMode(0, p1) 950 #define MDrv_TSP_PVR_TimeStampSetRecordStamp(p1) MDrv_TSP_PVR_Eng_TimeStampSetRecordStamp(0, p1) 951 #define MDrv_TSP_PVR_TimeStampGetRecordStamp(p1 ) MDrv_TSP_PVR_Eng_TimeStampGetRecordStamp(0, p1) 952 953 //---------- Common Interface for TSP config and Api commands ------------// 954 TSP_Result MDrv_TSP_CMD_Run(MS_U32 u32Cmd, MS_U32 u32Config0, MS_U32 u32Config1 ,void *pData); 955 #define DRVTSP_CMD_SET_LIB_MODE 0x80000003UL //u32Config0: 0 -> user mode, 1 -> Kernel mode with user cb 956 #define DRVTSP_CMD_LIB_MODE_USER 0x00000000UL 957 #define DRVTSP_CMD_LIB_MODE_KRN 0x00000001UL 958 #define DRVTSP_CMD_STC_ADJUST_UNIT 0x00000020UL //u32Config0: data 959 #define TSP_CMD_PVR_PES_MODE 0x00000030UL //u32Config0: PVR EngineID, u32Config1=1, *pData = 1 is enable, pData = 0 is disable 960 961 TSP_Result MDrv_TSP_GetPesScmbSts(MS_U32 u32FltId, MS_U8 *pu8status); 962 TSP_Result MDrv_TSP_GetTsScmbSts(MS_U32 u32FltId, MS_U8 *pu8status); 963 964 TSP_Result MDrv_TSP_SetFwDataAddr(MS_PHY phyDataAddr, MS_U32 u32Size); 965 966 TSP_Result MDrv_TSP_FQ_FltNullPkt(MS_U32 u32FQEng, MS_BOOL bFltNull); 967 TSP_Result MDrv_TSP_FQ_SetMuxSwitch(MS_U32 u32FQEng, DrvFQ_SrcIf eTsSrc); 968 TSP_Result MDrv_TSP_FQ_GetMuxSwitch(MS_U32 u32FQEng, DrvFQ_SrcIf* peTsSrc); 969 970 TSP_Result MDrv_TSP_STC_Alloc(MS_U32 *pu32EngId); 971 TSP_Result MDrv_TSP_STC_Free(MS_U32 u32EngId); 972 TSP_Result MDrv_TSP_STC_UpdateCtrl(MS_U8 u8Eng, MS_U8 u8Mode); 973 TSP_Result MDrv_TSP_STC_Select(DrvTSP_FltType eFltSrc, MS_U32 u32StcEng); 974 TSP_Result MDrv_TSP_PcrId_To_StcId(MS_U32 u32PcrFltId,MS_U32 *pu32EngId); 975 TSP_Result MDrv_TSP_SetSTCOffset(MS_U32 u32EngId, MS_U32 u32Offset, MS_BOOL bAdd); 976 977 //----------- Debug table -------------- 978 TSP_Result MDrv_TSP_Get_DisContiCnt(DrvTSP_DisContiCnt_info* tspInfo, MS_U32* pu32Cnt); 979 TSP_Result MDrv_TSP_Get_DropPktCnt(DrvTSP_DropPktCnt_info* tspInfo, MS_U32* pu32Cnt); 980 TSP_Result MDrv_TSP_Get_LockPktCnt(DrvTSP_LockPktCnt_info* tspInfo, MS_U32* pu32Cnt); 981 TSP_Result MDrv_TSP_Get_AVPktCnt(DrvTSP_AVPktCnt_info* tspInfo, MS_U32* pu32Cnt); 982 983 TSP_Result MDrv_TSP_Get_SecTEI_PktCount(DrvTSP_FltType FltSrc, MS_U32* pu32PktCnt); 984 TSP_Result MDrv_TSP_Reset_SecTEI_PktCount(DrvTSP_FltType FltSrc); 985 TSP_Result MDrv_TSP_Get_SecDisCont_PktCount(MS_U32 u32FltID, MS_U32* pu32PktCnt); 986 TSP_Result MDrv_TSP_Reset_SecDisCont_PktCount(MS_U32 u32FltID); 987 988 //-------- merge stream -------------------------- 989 TSP_Result MDrv_TSP_MStr_SyncByte(DrvTSP_If eIf, MS_U8 u8StrId, MS_U8* pu8SyncByte, MS_BOOL bSet); 990 991 //------- For 2K kernel mode, user mode callback thread using events 992 TSP_Result MDrv_TSP_Create_IoSignal(DrvTSP_IoSignal *pstIoSignal); 993 TSP_Result MDrv_TSP_Close_IoSignal(DrvTSP_IoSignal *pstIoSignal); 994 TSP_Result MDrv_TSP_Wait_IoSignal(DrvTSP_IoSignal *pstIoSignal); 995 TSP_Result MDrv_TSP_Proc_IoSignal(DrvTSP_IoSignal *pstIoSignal); 996 TSP_Result MDrv_TSP_Get_SecEvents(MS_U32 u32Group, DrvTSP_IoSignal *pstIoSignal); 997 998 #ifdef SECURE_PVR_ENABLE 999 TSP_Result MDrv_TSP_Ree_TeeCmdSystem_Init(void); 1000 TSP_Result MDrv_TSP_Ree_TeeCmdSystem_Exit(void); 1001 TSP_Result MDrv_TSP_Ree_SendTeeCmd(TSP_REE_TO_TEE_CMD_TYPE cmd_type, void* param, size_t datasize); 1002 #endif //SECURE_PVR_ENABLE 1003 1004 #ifdef __cplusplus 1005 } // closing brace for extern "C" 1006 #endif 1007 1008 #endif // _DRV_TSP_H_ 1009