1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
4 // Copyright (c) 2010 - 2012 MStar Semiconductor, Inc. All rights reserved.
5 // All software, firmware and related documentation herein ("MStar Software") are
6 // intellectual property of MStar Semiconductor, Inc. ("MStar") and protected by
7 // law, including, but not limited to, copyright law and international treaties.
8 // Any use, modification, reproduction, retransmission, or republication of all
9 // or part of MStar Software is expressly prohibited, unless prior written
10 // permission has been granted by MStar.
11 //
12 // By accessing, browsing and/or using MStar Software, you acknowledge that you
13 // have read, understood, and agree, to be bound by below terms ("Terms") and to
14 // comply with all applicable laws and regulations:
15 //
16 // 1. MStar shall retain any and all right, ownership and interest to MStar
17 // Software and any modification/derivatives thereof.
18 // No right, ownership, or interest to MStar Software and any
19 // modification/derivatives thereof is transferred to you under Terms.
20 //
21 // 2. You understand that MStar Software might include, incorporate or be
22 // supplied together with third party`s software and the use of MStar
23 // Software may require additional licenses from third parties.
24 // Therefore, you hereby agree it is your sole responsibility to separately
25 // obtain any and all third party right and license necessary for your use of
26 // such third party`s software.
27 //
28 // 3. MStar Software and any modification/derivatives thereof shall be deemed as
29 // MStar`s confidential information and you agree to keep MStar`s
30 // confidential information in strictest confidence and not disclose to any
31 // third party.
32 //
33 // 4. MStar Software is provided on an "AS IS" basis without warranties of any
34 // kind. Any warranties are hereby expressly disclaimed by MStar, including
35 // without limitation, any warranties of merchantability, non-infringement of
36 // intellectual property rights, fitness for a particular purpose, error free
37 // and in conformity with any international standard. You agree to waive any
38 // claim against MStar for any loss, damage, cost or expense that you may
39 // incur related to your use of MStar Software.
40 // In no event shall MStar be liable for any direct, indirect, incidental or
41 // consequential damages, including without limitation, lost of profit or
42 // revenues, lost or damage of data, and unauthorized system use.
43 // You agree that this Section 4 shall still apply without being affected
44 // even if MStar Software has been modified by MStar in accordance with your
45 // request or instruction for your use, except otherwise agreed by both
46 // parties in writing.
47 //
48 // 5. If requested, MStar may from time to time provide technical supports or
49 // services in relation with MStar Software to you for your use of
50 // MStar Software in conjunction with your or your customer`s product
51 // ("Services").
52 // You understand and agree that, except otherwise agreed by both parties in
53 // writing, Services are provided on an "AS IS" basis and the warranty
54 // disclaimer set forth in Section 4 above shall apply.
55 //
56 // 6. Nothing contained herein shall be construed as by implication, estoppels
57 // or otherwise:
58 // (a) conferring any license or right to use MStar name, trademark, service
59 // mark, symbol or any other identification;
60 // (b) obligating MStar or any of its affiliates to furnish any person,
61 // including without limitation, you and your customers, any assistance
62 // of any kind whatsoever, or any information; or
63 // (c) conferring any license or right under any intellectual property right.
64 //
65 // 7. These terms shall be governed by and construed in accordance with the laws
66 // of Taiwan, R.O.C., excluding its conflict of law rules.
67 // Any and all dispute arising out hereof or related hereto shall be finally
68 // settled by arbitration referred to the Chinese Arbitration Association,
69 // Taipei in accordance with the ROC Arbitration Law and the Arbitration
70 // Rules of the Association by three (3) arbitrators appointed in accordance
71 // with the said Rules.
72 // The place of arbitration shall be in Taipei, Taiwan and the language shall
73 // be English.
74 // The arbitration award shall be final and binding to both parties.
75 //
76 //******************************************************************************
77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
79 //
80 // Copyright (c) 2006-2009 MStar Semiconductor, Inc.
81 // All rights reserved.
82 //
83 // Unless otherwise stipulated in writing, any and all information contained
84 // herein regardless in any format shall remain the sole proprietary of
85 // MStar Semiconductor Inc. and be kept in strict confidence
86 // (!��MStar Confidential Information!�L) by the recipient.
87 // Any unauthorized act including without limitation unauthorized disclosure,
88 // copying, use, reproduction, sale, distribution, modification, disassembling,
89 // reverse engineering and compiling of the contents of MStar Confidential
90 // Information is unlawful and strictly prohibited. MStar hereby reserves the
91 // rights to any and all damages, losses, costs and expenses resulting therefrom.
92 //
93 ////////////////////////////////////////////////////////////////////////////////
94
95
96 //-------------------------------------------------------------------------------------------------
97 // Include Files
98 //-------------------------------------------------------------------------------------------------
99
100 #ifndef MSOS_TYPE_LINUX_KERNEL
101 #include <stdio.h>
102 #include <math.h>
103 #endif
104
105 #include "drvDMD_ATSC.h"
106
107 //-------------------------------------------------------------------------------------------------
108 // Driver Compiler Options
109 //-------------------------------------------------------------------------------------------------
110
111 #define DMD_ATSC_CHIP_T3_T10 0x01
112 #define DMD_ATSC_CHIP_T7 0x02
113 #define DMD_ATSC_CHIP_T8_T9 0x03
114 #define DMD_ATSC_CHIP_A1 0x04
115 #define DMD_ATSC_CHIP_A3 0x05
116 #define DMD_ATSC_CHIP_A5 0x06
117 #define DMD_ATSC_CHIP_A7 0x07
118 #define DMD_ATSC_CHIP_A7P 0x08
119 #define DMD_ATSC_CHIP_AGATE 0x09
120 #define DMD_ATSC_CHIP_EDISON 0x0A
121 #define DMD_ATSC_CHIP_EINSTEIN 0x0B
122 #define DMD_ATSC_CHIP_EMERALD 0x0C
123 #define DMD_ATSC_CHIP_EIFFEL 0x0D
124 #define DMD_ATSC_CHIP_EDEN 0x0E
125 #define DMD_ATSC_CHIP_EINSTEIN3 0x0F
126 #define DMD_ATSC_CHIP_MONACO 0x10
127 #define DMD_ATSC_CHIP_MIAMI 0x11
128 #define DMD_ATSC_CHIP_MUJI 0x12
129 #define DMD_ATSC_CHIP_MUNICH 0x13
130 #define DMD_ATSC_CHIP_MAYA 0x14
131 #define DMD_ATSC_CHIP_MANHATTAN 0x15
132 #define DMD_ATSC_CHIP_WHISKY 0x16
133 #define DMD_ATSC_CHIP_MASERATI 0x17
134 #define DMD_ATSC_CHIP_MACAN 0x18
135 #define DMD_ATSC_CHIP_MUSTANG 0x19
136 #define DMD_ATSC_CHIP_MAXIM 0x1A
137 #define DMD_ATSC_CHIP_K3 0x80 //UTOF start from 0x80
138 #define DMD_ATSC_CHIP_KELTIC 0x81
139 #define DMD_ATSC_CHIP_KERES 0x82
140 #define DMD_ATSC_CHIP_KIRIN 0x83
141
142 #if defined(a1)
143 #define DMD_ATSC_CHIP_VERSION DMD_ATSC_CHIP_A1
144 #elif defined(a3)
145 #define DMD_ATSC_CHIP_VERSION DMD_ATSC_CHIP_A3
146 #elif defined(a5)
147 #define DMD_ATSC_CHIP_VERSION DMD_ATSC_CHIP_A5
148 #elif defined(a7)
149 #define DMD_ATSC_CHIP_VERSION DMD_ATSC_CHIP_A7
150 #elif defined(amethyst)
151 #define DMD_ATSC_CHIP_VERSION DMD_ATSC_CHIP_A7P
152 #elif defined(agate)
153 #define DMD_ATSC_CHIP_VERSION DMD_ATSC_CHIP_AGATE
154 #elif defined(edison)
155 #define DMD_ATSC_CHIP_VERSION DMD_ATSC_CHIP_EDISON
156 #elif defined(einstein)
157 #define DMD_ATSC_CHIP_VERSION DMD_ATSC_CHIP_EINSTEIN
158 #elif defined(einstein3)
159 #define DMD_ATSC_CHIP_VERSION DMD_ATSC_CHIP_EINSTEIN3
160 #elif defined(monaco)
161 #define DMD_ATSC_CHIP_VERSION DMD_ATSC_CHIP_MONACO
162 #elif defined(emerald)
163 #define DMD_ATSC_CHIP_VERSION DMD_ATSC_CHIP_EMERALD
164 #elif defined(eiffel)
165 #define DMD_ATSC_CHIP_VERSION DMD_ATSC_CHIP_EIFFEL
166 #elif defined(kaiser)
167 #define DMD_ATSC_CHIP_VERSION DMD_ATSC_CHIP_K3
168 #elif defined(keltic)
169 #define DMD_ATSC_CHIP_VERSION DMD_ATSC_CHIP_KELTIC
170 #elif defined(eden)
171 #define DMD_ATSC_CHIP_VERSION DMD_ATSC_CHIP_EDEN
172 #elif defined(miami)
173 #define DMD_ATSC_CHIP_VERSION DMD_ATSC_CHIP_MIAMI
174 #elif defined(keres)
175 #define DMD_ATSC_CHIP_VERSION DMD_ATSC_CHIP_KERES
176 #elif defined(muji)
177 #define DMD_ATSC_CHIP_VERSION DMD_ATSC_CHIP_MUJI
178 #elif defined(munich)
179 #define DMD_ATSC_CHIP_VERSION DMD_ATSC_CHIP_MUNICH
180 #elif defined(mustang)
181 #define DMD_ATSC_CHIP_VERSION DMD_ATSC_CHIP_MUSTANG
182 #elif defined(maxim)
183 #define DMD_ATSC_CHIP_VERSION DMD_ATSC_CHIP_MAXIM
184 #else
185 #define DMD_ATSC_CHIP_VERSION DMD_ATSC_CHIP_EMERALD
186 #endif
187
188 //-------------------------------------------------------------------------------------------------
189 // Local Defines
190 //-------------------------------------------------------------------------------------------------
191
192 #define _RIU_READ_BYTE(addr) ( READ_BYTE(psDMD_ATSC_ResData->sDMD_ATSC_PriData.virtDMDBaseAddr + (addr) ) )
193 #define _RIU_WRITE_BYTE(addr, val) ( WRITE_BYTE(psDMD_ATSC_ResData->sDMD_ATSC_PriData.virtDMDBaseAddr + (addr), val) )
194
195 #define HAL_INTERN_ATSC_DBINFO(y) //y
196
197 #if (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_A1)
198 #ifndef MBRegBase
199 #define MBRegBase 0x112600UL
200 #endif
201 #ifndef MBRegBase_DMD1
202 #define MBRegBase_DMD1 0x112400UL
203 #endif
204 #else
205 #ifndef MBRegBase
206 #define MBRegBase 0x110500UL
207 #endif
208 #endif
209
210 #if (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_T3_T10)
211 #ifndef DMDMcuBase
212 #define DMDMcuBase 0x103460UL
213 #endif
214 #else
215 #ifndef DMDMcuBase
216 #define DMDMcuBase 0x103480UL
217 #endif
218 #endif
219
220 #if (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_K3)
221 #define INTERN_ATSC_OUTER_STATE 0xF0
222 #else
223 #define INTERN_ATSC_OUTER_STATE 0x80
224 #endif
225 #define INTERN_ATSC_VSB_TRAIN_SNR_LIMIT 0x05//0xBE//14.5dB
226 #define INTERN_ATSC_FEC_ENABLE 0x1F
227
228 #define VSB_ATSC 0x04
229 #define QAM256_ATSC 0x02
230
231 #define QAM16_J83ABC 0x00
232 #define QAM32_J83ABC 0x01
233 #define QAM64_J83ABC 0x02
234 #define QAM128_J83ABC 0x03
235 #define QAM256_J83ABC 0x04
236
237 //-------------------------------------------------------------------------------------------------
238 // Local Variables
239 //-------------------------------------------------------------------------------------------------
240
241 const MS_U8 INTERN_ATSC_table[] = {
242 #include "DMD_INTERN_ATSC.dat"
243 };
244
245 static MS_U16 u16Lib_size = sizeof(INTERN_ATSC_table);
246
247 #if (DMD_ATSC_CHIP_VERSION < DMD_ATSC_CHIP_K3)
248
249 #if (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_T7)
250 static MS_U8 Demod_Flow_register[17] = {0x52, 0x72, 0x52, 0x72, 0x5C, 0x5C, 0xA3, 0xEC, 0xEA,
251 0x05, 0x74, 0x1E, 0x38, 0x3A, 0x08, 0x70, 0x68};
252 #else
253 static MS_U8 Demod_Flow_register[21] = {0x52, 0x72, 0x52, 0x72, 0x5C, 0x5C, 0xA3, 0xEC, 0xEA,
254 0x05, 0x74, 0x1E, 0x38, 0x3A, 0x00, 0x00, 0x00, 0x00,
255 0x00, 0x00, 0x00};
256 #endif
257
258 #endif
259
260 #ifndef UTPA2
261 static const float _LogApproxTableX[80] =
262 { 1.00, 1.30, 1.69, 2.20, 2.86, 3.71, 4.83, 6.27, 8.16, 10.60, 13.79,
263 17.92, 23.30, 30.29, 39.37, 51.19, 66.54, 86.50, 112.46, 146.19,
264 190.05, 247.06, 321.18, 417.54, 542.80, 705.64, 917.33, 1192.53,
265 1550.29, 2015.38, 2620.00, 3405.99, 4427.79, 5756.13, 7482.97,
266 9727.86, 12646.22, 16440.08, 21372.11, 27783.74, 36118.86,
267 46954.52, 61040.88, 79353.15, 103159.09, 134106.82, 174338.86,
268 226640.52, 294632.68, 383022.48, 497929.22, 647307.99, 841500.39, 1093950.50,
269 1422135.65, 1848776.35, 2403409.25, 3124432.03, 4061761.64, 5280290.13,
270 6864377.17, 8923690.32, 11600797.42, 15081036.65, 19605347.64, 25486951.94,
271 33133037.52, 43072948.77, 55994833.40, 72793283.42, 94631268.45,
272 123020648.99, 159926843.68, 207904896.79, 270276365.82, 351359275.57,
273 456767058.24, 593797175.72, 771936328.43, 1003517226.96
274 };
275
276 static const float _LogApproxTableY[80] =
277 { 0.00, 0.11, 0.23, 0.34, 0.46, 0.57, 0.68, 0.80, 0.91, 1.03, 1.14, 1.25,
278 1.37, 1.48, 1.60, 1.71, 1.82, 1.94, 2.05, 2.16, 2.28, 2.39, 2.51, 2.62,
279 2.73, 2.85, 2.96, 3.08, 3.19, 3.30, 3.42, 3.53, 3.65, 3.76, 3.87, 3.99,
280 4.10, 4.22, 4.33, 4.44, 4.56, 4.67, 4.79, 4.90, 5.01, 5.13, 5.24, 5.36,
281 5.47, 5.58, 5.70, 5.81, 5.93, 6.04, 6.15, 6.27, 6.04, 6.15, 6.27, 6.38,
282 6.49, 6.61, 6.72, 6.84, 6.95, 7.06, 7.18, 7.29, 7.41, 7.52, 7.63, 7.75,
283 7.86, 7.98, 8.09, 8.20, 8.32, 8.43, 8.55, 8.66
284 };
285 #endif
286
287 //-------------------------------------------------------------------------------------------------
288 // Global Variables
289 //-------------------------------------------------------------------------------------------------
290
291 extern MS_U8 u8DMD_ATSC_DMD_ID;
292
293 extern DMD_ATSC_ResData *psDMD_ATSC_ResData;
294
295 //-------------------------------------------------------------------------------------------------
296 // Local Functions
297 //-------------------------------------------------------------------------------------------------
298 #ifndef UTPA2
299 #ifndef MSOS_TYPE_LINUX
Log10Approx(float flt_x)300 static float Log10Approx(float flt_x)
301 {
302 MS_U8 indx = 0;
303
304 do {
305 if (flt_x < _LogApproxTableX[indx])
306 break;
307 indx++;
308 }while (indx < 79); //stop at indx = 80
309
310 return _LogApproxTableY[indx];
311 }
312 #endif
313 #endif
314
_HAL_DMD_RIU_ReadByte(MS_U32 u32Addr)315 static MS_U8 _HAL_DMD_RIU_ReadByte(MS_U32 u32Addr)
316 {
317 return _RIU_READ_BYTE(((u32Addr) << 1) - ((u32Addr) & 1));
318 }
319
_HAL_DMD_RIU_WriteByte(MS_U32 u32Addr,MS_U8 u8Value)320 static void _HAL_DMD_RIU_WriteByte(MS_U32 u32Addr, MS_U8 u8Value)
321 {
322 _RIU_WRITE_BYTE(((u32Addr) << 1) - ((u32Addr) & 1), u8Value);
323 }
324
_HAL_DMD_RIU_WriteByteMask(MS_U32 u32Addr,MS_U8 u8Value,MS_U8 u8Mask)325 static void _HAL_DMD_RIU_WriteByteMask(MS_U32 u32Addr, MS_U8 u8Value, MS_U8 u8Mask)
326 {
327 _RIU_WRITE_BYTE((((u32Addr) <<1) - ((u32Addr) & 1)), (_RIU_READ_BYTE((((u32Addr) <<1) - ((u32Addr) & 1))) & ~(u8Mask)) | ((u8Value) & (u8Mask)));
328 }
_MBX_WriteReg(MS_U16 u16Addr,MS_U8 u8Data)329 static MS_BOOL _MBX_WriteReg(MS_U16 u16Addr, MS_U8 u8Data)
330 {
331 MS_U8 u8CheckCount;
332 MS_U8 u8CheckFlag = 0xFF;
333 MS_U32 u32MBRegBase = MBRegBase;
334
335 if (u8DMD_ATSC_DMD_ID == 0)
336 u32MBRegBase = MBRegBase;
337 else if (u8DMD_ATSC_DMD_ID == 1)
338 u32MBRegBase = MBRegBase_DMD1;
339
340 _HAL_DMD_RIU_WriteByte(u32MBRegBase + 0x00, (u16Addr&0xff));
341 _HAL_DMD_RIU_WriteByte(u32MBRegBase + 0x01, (u16Addr>>8));
342 _HAL_DMD_RIU_WriteByte(u32MBRegBase + 0x10, u8Data);
343 _HAL_DMD_RIU_WriteByte(u32MBRegBase + 0x1E, 0x01);
344
345 _HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, _HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)|0x02); // assert interrupt to VD MCU51
346 _HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, _HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)&(~0x02)); // de-assert interrupt to VD MCU51
347
348 for (u8CheckCount=0; u8CheckCount < 10; u8CheckCount++)
349 {
350 u8CheckFlag = _HAL_DMD_RIU_ReadByte(u32MBRegBase + 0x1E);
351 if ((u8CheckFlag&0x01)==0)
352 break;
353 MsOS_DelayTask(1);
354 }
355
356 if (u8CheckFlag&0x01)
357 {
358 printf("ERROR: ATSC INTERN DEMOD MBX WRITE TIME OUT!\n");
359 return FALSE;
360 }
361
362 return TRUE;
363 }
364
_MBX_ReadReg(MS_U16 u16Addr,MS_U8 * u8Data)365 static MS_BOOL _MBX_ReadReg(MS_U16 u16Addr, MS_U8 *u8Data)
366 {
367 MS_U8 u8CheckCount;
368 MS_U8 u8CheckFlag = 0xFF;
369 MS_U32 u32MBRegBase = MBRegBase;
370
371 if (u8DMD_ATSC_DMD_ID == 0)
372 u32MBRegBase = MBRegBase;
373 else if (u8DMD_ATSC_DMD_ID == 1)
374 u32MBRegBase = MBRegBase_DMD1;
375
376 _HAL_DMD_RIU_WriteByte(u32MBRegBase + 0x00, (u16Addr&0xff));
377 _HAL_DMD_RIU_WriteByte(u32MBRegBase + 0x01, (u16Addr>>8));
378 _HAL_DMD_RIU_WriteByte(u32MBRegBase + 0x1E, 0x02);
379
380 _HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, _HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)|0x02); // assert interrupt to VD MCU51
381 _HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, _HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)&(~0x02)); // de-assert interrupt to VD MCU51
382
383 for (u8CheckCount=0; u8CheckCount < 10; u8CheckCount++)
384 {
385 u8CheckFlag = _HAL_DMD_RIU_ReadByte(u32MBRegBase + 0x1E);
386 if ((u8CheckFlag&0x02)==0)
387 {
388 *u8Data = _HAL_DMD_RIU_ReadByte(u32MBRegBase + 0x10);
389 break;
390 }
391 MsOS_DelayTask(1);
392 }
393
394 if (u8CheckFlag&0x02)
395 {
396 printf("ERROR: ATSC INTERN DEMOD MBX READ TIME OUT!\n");
397 return FALSE;
398 }
399
400 return TRUE;
401 }
402
403 #if (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_K3)
_SEL_DMD(void)404 static MS_BOOL _SEL_DMD(void)
405 {
406 MS_U8 u8data = 0;
407
408 u8data = _HAL_DMD_RIU_ReadByte(0x101e3c);
409
410 if (u8DMD_ATSC_DMD_ID == 0) //select DMD0
411 u8data &= (~0x10);
412 else if (u8DMD_ATSC_DMD_ID == 1) //sel DMD1
413 u8data |= 0x10;
414
415 _HAL_DMD_RIU_WriteByte(0x101e3c, u8data);
416
417 return TRUE;
418 }
419 #endif
420
421 #if ((DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_A1) && (DMD_ATSC_CHIP_VERSION < DMD_ATSC_CHIP_K3))
_initTable(void)422 static void _initTable(void)
423 {
424 DMD_ATSC_ResData *pRes = psDMD_ATSC_ResData + u8DMD_ATSC_DMD_ID;
425
426 if (pRes->sDMD_ATSC_InitData.bTunerGainInvert)
427 Demod_Flow_register[12]=1;
428 else Demod_Flow_register[12]=0;
429
430 if (pRes->sDMD_ATSC_InitData.bIQSwap)
431 Demod_Flow_register[14] = 1;
432 else Demod_Flow_register[14] = 0;
433
434 Demod_Flow_register[15] = pRes->sDMD_ATSC_InitData.u16IF_KHZ&0xFF;
435 Demod_Flow_register[16] = (pRes->sDMD_ATSC_InitData.u16IF_KHZ)>>8;
436
437 printf("\n#### IF_KHz = [%d]\n", pRes->sDMD_ATSC_InitData.u16IF_KHZ);
438 printf("\n#### IQ_SWAP = [%d]\n", pRes->sDMD_ATSC_InitData.bIQSwap);
439 printf("\n#### Tuner Gain Invert = [%d]\n", pRes->sDMD_ATSC_InitData.bTunerGainInvert);
440 }
441 #endif
442
443 #if (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_T3_T10)
_HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)444 static void _HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)
445 {
446 printf("--------------DMD_ATSC_CHIP_T3_T10--------------\n");
447
448 // MailBox
449 _HAL_DMD_RIU_WriteByte(0x100b44, 0x00); //clk mail box0 =xtal <<hk51 <--mail box 0--> aeon
450 _HAL_DMD_RIU_WriteByte(0x100b45, 0x00); //clk mail box0 =xtal <<hk51 <--mail box 1--> aeon
451
452 // Enable DMD MCU clock (108MHz)
453 if (_HAL_DMD_RIU_ReadByte(0x001ecf) == 0x00)
454 _HAL_DMD_RIU_WriteByte(0x100b42, 0x10);
455 else //after t3_u02
456 _HAL_DMD_RIU_WriteByte(0x100b42, 0x0D);
457
458 _HAL_DMD_RIU_WriteByte(0x100b43, 0x01); // Disable VD200 clock
459
460 _HAL_DMD_RIU_WriteByte(0x103314, 0x01); // Disable ADC clock
461
462 _HAL_DMD_RIU_WriteByte(0x103315, 0x01); // Disable DVB INNER clock
463
464 // Enable ATSC clock
465 _HAL_DMD_RIU_WriteByte(0x103302, 0x00);
466 _HAL_DMD_RIU_WriteByte(0x103303, 0x00);
467 _HAL_DMD_RIU_WriteByte(0x103304, 0x00);
468 _HAL_DMD_RIU_WriteByte(0x103305, 0x00);
469 _HAL_DMD_RIU_WriteByte(0x103306, 0x00);
470 _HAL_DMD_RIU_WriteByte(0x103307, 0x00);
471 _HAL_DMD_RIU_WriteByte(0x10330a, 0x08);
472
473 // Enable DVB INNERx1&2 clock
474 _HAL_DMD_RIU_WriteByte(0x10330c, 0x00);
475 _HAL_DMD_RIU_WriteByte(0x10330d, 0x00);
476
477 // Enable DVB SRAM0~SRAM3 clock
478 _HAL_DMD_RIU_WriteByte(0x103318, 0x00);
479 _HAL_DMD_RIU_WriteByte(0x103319, 0x00);
480
481 _HAL_DMD_RIU_WriteByte(0x103308, 0x00); // Enable ATSC TS clock
482 _HAL_DMD_RIU_WriteByte(0x103309, 0x01); // Disable DVB TS clock
483
484 _HAL_DMD_RIU_WriteByte(0x103300, 0x18); // Set DMD clock div
485 _HAL_DMD_RIU_WriteByte(0x103301, 0x04); // Enable DMD clock
486
487 MsOS_DelayTaskUs(1);
488
489 _HAL_DMD_RIU_WriteByte(0x103314, 0x00); // Enable ADC clock
490
491 _HAL_DMD_RIU_WriteByte(0x101e22, 0x02); // Set TS PAD
492 _HAL_DMD_RIU_WriteByte(0x101e23, 0x00);
493
494 _HAL_DMD_RIU_WriteByte(0x100b50, 0x08); // Enable TS0&1 clock
495 _HAL_DMD_RIU_WriteByte(0x100b51, 0x08);
496
497 if (bRFAGCTristateEnable)
498 _HAL_DMD_RIU_WriteByteMask(0x101e05, 0x20, 0x30); // Set IF&RF AGC output mode
499 else
500 _HAL_DMD_RIU_WriteByteMask(0x101e05, 0x00, 0x30); // Set IF&RF AGC output mode
501 }
502 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_T7)
_HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)503 static void _HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)
504 {
505 printf("--------------DMD_ATSC_CHIP_T7--------------\n");
506
507 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10); // Enable DMD MCU clock (108MHz)
508
509 _HAL_DMD_RIU_WriteByte(0x103314, 0x01); // Disable ADC clock
510
511 _HAL_DMD_RIU_WriteByte(0x103315, 0x01); // Disable DVB INNER clock
512
513 // Enable ATSC clock
514 _HAL_DMD_RIU_WriteByte(0x103302, 0x00);
515 _HAL_DMD_RIU_WriteByte(0x103303, 0x00);
516 _HAL_DMD_RIU_WriteByte(0x103304, 0x00);
517 _HAL_DMD_RIU_WriteByte(0x103305, 0x00);
518 _HAL_DMD_RIU_WriteByte(0x103306, 0x00);
519 _HAL_DMD_RIU_WriteByte(0x103307, 0x00);
520 _HAL_DMD_RIU_WriteByte(0x10330a, 0x08);
521
522 // Enable DVB INNERx1&2&4 clock
523 _HAL_DMD_RIU_WriteByte(0x10330c, 0x00);
524 _HAL_DMD_RIU_WriteByte(0x10330d, 0x00);
525 _HAL_DMD_RIU_WriteByte(0x10330e, 0x00);
526
527 // Enable DVB OUTERx1&2&2_c clock
528 _HAL_DMD_RIU_WriteByte(0x103310, 0x00);
529 _HAL_DMD_RIU_WriteByte(0x103311, 0x00);
530 _HAL_DMD_RIU_WriteByte(0x103312, 0x00);
531
532 // Enable DVB EQx1&8c clock
533 _HAL_DMD_RIU_WriteByte(0x103316, 0x00);
534 _HAL_DMD_RIU_WriteByte(0x103317, 0x00);
535
536 // Enable DVB SRAM0~SRAM3 clock
537 _HAL_DMD_RIU_WriteByte(0x103318, 0x00);
538 _HAL_DMD_RIU_WriteByte(0x103319, 0x00);
539
540 _HAL_DMD_RIU_WriteByte(0x103308, 0x00); // Enable ATSC TS clock
541 _HAL_DMD_RIU_WriteByte(0x103309, 0x01); // Disable DVB TS clock
542
543 _HAL_DMD_RIU_WriteByte(0x103300, 0x18); // Set DMD clock div
544 _HAL_DMD_RIU_WriteByte(0x103301, 0x04); // Enable DMD clock
545
546 MsOS_DelayTaskUs(1);
547
548 _HAL_DMD_RIU_WriteByte(0x103314, 0x00); // Enable ADC clock
549
550 _HAL_DMD_RIU_WriteByte(0x101e22, 0x02); // Set TS PAD
551 _HAL_DMD_RIU_WriteByte(0x101e23, 0x00);
552
553 _HAL_DMD_RIU_WriteByte(0x100b50, 0x08); // Enable TS0&1 clock
554 _HAL_DMD_RIU_WriteByte(0x100b51, 0x08);
555
556 _HAL_DMD_RIU_WriteByteMask(0x101e9e, 0x00, 0xCF); // Set IF&RF AGC PAD and PWM AGC mode
557
558 if (bRFAGCTristateEnable)
559 _HAL_DMD_RIU_WriteByteMask(0x101e05, 0x20, 0x30); // Set IF&RF AGC output mode
560 else
561 _HAL_DMD_RIU_WriteByteMask(0x101e05, 0x00, 0x30); // Set IF&RF AGC output mode
562
563 _HAL_DMD_RIU_WriteByteMask(0x101ea1, 0x00, 0x80); // Set all pads (except SPI) as output
564
565 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x01);
566 _HAL_DMD_RIU_WriteByteMask(0x112003, 0x20, 0x20); // Release Ana misc resest
567 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x01, 0x01);
568
569 // Set DMD ANA
570 _HAL_DMD_RIU_WriteByte(0x112864, 0x00); // Set VCO first and second div
571 _HAL_DMD_RIU_WriteByte(0x112865, 0x00);
572
573 _HAL_DMD_RIU_WriteByte(0x11286C, 0x20); // Disable T&RF-AGC
574 _HAL_DMD_RIU_WriteByte(0x11286D, 0x00);
575
576 _HAL_DMD_RIU_WriteByte(0x112868, 0x00);
577 _HAL_DMD_RIU_WriteByte(0x112869, 0x80);
578
579 _HAL_DMD_RIU_WriteByte(0x112862, 0x00); // Set PLL first and second div
580 _HAL_DMD_RIU_WriteByte(0x112863, 0x00);
581
582 _HAL_DMD_RIU_WriteByte(0x112818, 0x03); // ADC I&Q pown down
583 _HAL_DMD_RIU_WriteByte(0x112819, 0x00);
584
585 MsOS_DelayTaskUs(2);
586
587 _HAL_DMD_RIU_WriteByte(0x11286A, 0x86); // Initial MPLL procedure
588 _HAL_DMD_RIU_WriteByte(0x11286B, 0x1E);
589 MsOS_DelayTaskUs(2);
590 _HAL_DMD_RIU_WriteByte(0x11286A, 0x06);
591 _HAL_DMD_RIU_WriteByte(0x11286B, 0x1E);
592 MsOS_DelayTaskUs(2);
593 _HAL_DMD_RIU_WriteByte(0x11286A, 0x06);
594 _HAL_DMD_RIU_WriteByte(0x11286B, 0x06);
595
596 MsOS_DelayTaskUs(2);
597
598 _HAL_DMD_RIU_WriteByte(0x112866, 0x01); // Set MPLL first and second div
599 _HAL_DMD_RIU_WriteByte(0x112867, 0x1d);
600
601 _HAL_DMD_RIU_WriteByte(0x112860, 0x00); // MPLL power up
602 _HAL_DMD_RIU_WriteByte(0x112861, 0x1c); // Set ADC output div
603
604 _HAL_DMD_RIU_WriteByte(0x112802, 0x40); // Set ADC I&Q
605 _HAL_DMD_RIU_WriteByte(0x112803, 0x04);
606
607 _HAL_DMD_RIU_WriteByte(0x112816, 0x05); // set PGA gain
608 _HAL_DMD_RIU_WriteByte(0x112817, 0x05);
609
610 _HAL_DMD_RIU_WriteByte(0x112818, 0x00); // ADC I&Q pown up
611 _HAL_DMD_RIU_WriteByte(0x112819, 0x00);
612
613 _HAL_DMD_RIU_WriteByte(0x112840, 0x00); // Disable SIF&VIF
614 _HAL_DMD_RIU_WriteByte(0x112841, 0x00);
615 }
616 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_T8_T9)
_HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)617 static void _HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)
618 {
619 printf("--------------DMD_ATSC_CHIP_T8_T9--------------\n");
620
621 _HAL_DMD_RIU_WriteByte(0x10331E, 0x10); // Enable DMD MCU clock (108MHz)
622
623 _HAL_DMD_RIU_WriteByte(0x103314, 0x01); // Disable ADC clock
624
625 // Enable ATSC clock
626 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x08);
627 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
628 _HAL_DMD_RIU_WriteByte(0x111f02, 0x00);
629 _HAL_DMD_RIU_WriteByte(0x111f03, 0x00);
630 _HAL_DMD_RIU_WriteByte(0x111f04, 0x00);
631 _HAL_DMD_RIU_WriteByte(0x111f05, 0x00);
632 _HAL_DMD_RIU_WriteByte(0x111f06, 0x00);
633 _HAL_DMD_RIU_WriteByte(0x111f07, 0x00);
634
635 // Disable DVB INNERx1&2&4 clock
636 _HAL_DMD_RIU_WriteByte(0x111f0c, 0x01);
637 _HAL_DMD_RIU_WriteByte(0x111f0d, 0x01);
638 _HAL_DMD_RIU_WriteByte(0x111f0e, 0x01);
639
640 // Disable DVB OUTERx1&2&2_c clock
641 _HAL_DMD_RIU_WriteByte(0x111f10, 0x01);
642 _HAL_DMD_RIU_WriteByte(0x111f11, 0x01);
643 _HAL_DMD_RIU_WriteByte(0x111f12, 0x01);
644
645 // Disable DVB INNER clock
646 _HAL_DMD_RIU_WriteByte(0x111f15, 0x01);
647
648 // Disable DVB EQx1&8c clock
649 _HAL_DMD_RIU_WriteByte(0x111f16, 0x01);
650 _HAL_DMD_RIU_WriteByte(0x111f17, 0x01);
651
652 // Enable DVB SRAM0~SRAM3 clock
653 _HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
654 _HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
655
656 _HAL_DMD_RIU_WriteByte(0x103300, 0x11); // Set DMD clock div
657 _HAL_DMD_RIU_WriteByte(0x103301, 0x05); // Enable DMD clock
658
659 _HAL_DMD_RIU_WriteByte(0x103308, 0x00); // Enable ATSC TS clock
660 _HAL_DMD_RIU_WriteByte(0x103309, 0x01); // Disable DVB TS clock
661
662 // Disable VIF clock
663 _HAL_DMD_RIU_WriteByte(0x111f1c, 0x01);
664 _HAL_DMD_RIU_WriteByte(0x111f1d, 0x01);
665 _HAL_DMD_RIU_WriteByte(0x10331a, 0x01);
666 _HAL_DMD_RIU_WriteByte(0x10331b, 0x01);
667
668 MsOS_DelayTaskUs(1);
669
670 _HAL_DMD_RIU_WriteByte(0x103314, 0x00); // Enable ADC clock
671
672 _HAL_DMD_RIU_WriteByteMask(0x101eaf, 0x10, 0x18); // Set TS PAD
673
674 if (bRFAGCTristateEnable)
675 _HAL_DMD_RIU_WriteByteMask(0x101e05, 0x20, 0x30); // Set IF&RF AGC output mode
676 else
677 _HAL_DMD_RIU_WriteByteMask(0x101e05, 0x00, 0x30); // Set IF&RF AGC output mode
678
679 _HAL_DMD_RIU_WriteByteMask(0x101e9e, 0x00, 0xCF); // Set IF&RF AGC PAD and PWM AGC mode
680
681 _HAL_DMD_RIU_WriteByteMask(0x101ea0, 0x00, 0x03); // PWM2 uses PAD_PWM2 and PWM3 uses PAD_PWM3
682 _HAL_DMD_RIU_WriteByteMask(0x101ea1, 0x00, 0x80); // Set all pads (except SPI) as output
683
684 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
685 }
686 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_A1)
_HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)687 static void _HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)
688 {
689 printf("--------------DMD_ATSC_CHIP_A1--------------\n");
690
691 //Set register at CLKGEN1
692 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
693 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10); // Denny: change 0x10!! 108M
694
695 _HAL_DMD_RIU_WriteByte(0x103314, 0x01); // Disable ADC clock
696
697 // set parallet ts clock
698 _HAL_DMD_RIU_WriteByte(0x103301, 0x05);
699 _HAL_DMD_RIU_WriteByte(0x103300, 0x11);
700
701 // enable atsc, DVBTC ts clock
702 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
703 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
704
705 // enable dvbc adc clock
706 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
707
708 // enable vif DAC clock
709 _HAL_DMD_RIU_WriteByte(0x10331b, 0x00);
710 _HAL_DMD_RIU_WriteByte(0x10331a, 0x00);
711
712 // Set register at CLKGEN_DMD
713 _HAL_DMD_RIU_WriteByte(0x111f03, 0x00);
714 _HAL_DMD_RIU_WriteByte(0x111f02, 0x00);
715 _HAL_DMD_RIU_WriteByte(0x111f05, 0x00);
716 _HAL_DMD_RIU_WriteByte(0x111f04, 0x00);
717 _HAL_DMD_RIU_WriteByte(0x111f07, 0x00);
718 _HAL_DMD_RIU_WriteByte(0x111f06, 0x00);
719
720 // enable clk_atsc_adcd_sync
721 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
722 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x08);
723
724 // enable dvbt inner clock
725 _HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
726 _HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
727
728 // enable dvbt inner clock
729 _HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
730 _HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
731
732 // enable dvbt inner clock
733 _HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
734 _HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
735
736 // enable dvbc outer clock
737 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
738 _HAL_DMD_RIU_WriteByte(0x111f12, 0x08);
739
740 // enable dvbc inner-c clock
741 _HAL_DMD_RIU_WriteByte(0x111f15, 0x00);
742 _HAL_DMD_RIU_WriteByte(0x111f14, 0x00);
743
744 // enable dvbc eq clock
745 _HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
746 _HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
747
748 // enable vif clock
749 _HAL_DMD_RIU_WriteByte(0x111f1d, 0x00);
750 _HAL_DMD_RIU_WriteByte(0x111f1c, 0x00);
751
752 // For ADC DMA Dump
753 _HAL_DMD_RIU_WriteByte(0x111f21, 0x00);
754 _HAL_DMD_RIU_WriteByte(0x111f20, 0x00);
755
756 // select clock
757 _HAL_DMD_RIU_WriteByte(0x111f23, 0x00);
758 _HAL_DMD_RIU_WriteByte(0x111f22, 0x00);
759
760 MsOS_DelayTaskUs(1);
761
762 _HAL_DMD_RIU_WriteByte(0x103314, 0x00); // Enable ADC clock
763
764 // Turn TSP
765 _HAL_DMD_RIU_WriteByte(0x100b55, 0x00);
766 _HAL_DMD_RIU_WriteByte(0x100b54, 0x00);
767
768 // set the ts0_clk from demod
769 _HAL_DMD_RIU_WriteByte(0x100b51, 0x00);
770 _HAL_DMD_RIU_WriteByte(0x100b50, 0x0C);
771 _HAL_DMD_RIU_WriteByte(0x101e22, 0x02);
772
773 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
774 }
775 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_A7)
_HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)776 static void _HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)
777 {
778 printf("--------------DMD_ATSC_CHIP_A7--------------\n");
779
780 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
781 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
782
783 _HAL_DMD_RIU_WriteByte(0x103314, 0x01); // Disable ADC clock
784
785 _HAL_DMD_RIU_WriteByte(0x103301, 0x05);
786 _HAL_DMD_RIU_WriteByte(0x103300, 0x11);
787 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
788 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
789 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
790 _HAL_DMD_RIU_WriteByte(0x111f03, 0x00);
791 _HAL_DMD_RIU_WriteByte(0x111f02, 0x00);
792 _HAL_DMD_RIU_WriteByte(0x111f05, 0x00);
793 _HAL_DMD_RIU_WriteByte(0x111f04, 0x00);
794 _HAL_DMD_RIU_WriteByte(0x111f07, 0x00);
795 _HAL_DMD_RIU_WriteByte(0x111f06, 0x00);
796 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
797 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
798 _HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
799 _HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
800 _HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
801 _HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
802 _HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
803 _HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
804 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
805 _HAL_DMD_RIU_WriteByte(0x111f12, 0x08);
806 _HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
807 _HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
808 _HAL_DMD_RIU_WriteByte(0x111f25, 0x00);
809 _HAL_DMD_RIU_WriteByte(0x111f24, 0x00);
810 _HAL_DMD_RIU_WriteByte(0x111f23, 0x00);
811 _HAL_DMD_RIU_WriteByte(0x111f22, 0x00);
812
813 MsOS_DelayTaskUs(1);
814
815 _HAL_DMD_RIU_WriteByte(0x103314, 0x00); // Enable ADC clock
816
817 _HAL_DMD_RIU_WriteByteMask(0x000e13, 0x00, 0x04);
818
819 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
820 }
821 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_K3)
_HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)822 static void _HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)
823 {
824 DMD_ATSC_ResData *pRes = psDMD_ATSC_ResData + u8DMD_ATSC_DMD_ID;
825
826 printf("--------------DMD_ATSC_CHIP_K3--------------\n");
827
828 if (pRes->sDMD_ATSC_InitData.u8IS_DUAL)
829 {
830 _HAL_DMD_RIU_WriteByte(0x101e39, 0x00);
831 _HAL_DMD_RIU_WriteByte(0x101e3d, 0x00);
832
833 /****************DMD0****************/
834
835 //set CLK_DMDMCU as 108M Hz
836 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
837
838 // set parallet ts clock
839 _HAL_DMD_RIU_WriteByte(0x103301, 0x07);
840 _HAL_DMD_RIU_WriteByte(0x103300, 0x11);
841
842 // enable DVBTC ts clock
843 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
844
845 // enable dvbc adc clock
846 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
847 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
848
849 // enable clk_atsc_adcd_sync
850 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
851 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x04);
852
853 // enable dvbt inner clock
854 _HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
855
856 // enable dvbt outer clock
857 _HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
858
859 // enable dvbc outer clock
860 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
861 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
862
863 // enable dvbc inner-c clock
864 _HAL_DMD_RIU_WriteByte(0x111f15, 0x04);
865
866 // enable dvbc eq clock
867 _HAL_DMD_RIU_WriteByte(0x111f17, 0x00);
868 _HAL_DMD_RIU_WriteByte(0x111f16, 0x00);
869
870 // For ADC DMA Dump
871 _HAL_DMD_RIU_WriteByte(0x111f22, 0x04);
872
873 // Turn TSP
874 //_HAL_DMD_RIU_WriteByte(0x000e13, 0x01);
875
876 //set reg_allpad_in
877 _HAL_DMD_RIU_WriteByte(0x101ea1, 0x00);
878 _HAL_DMD_RIU_WriteByte(0x101e04, 0x02);
879 _HAL_DMD_RIU_WriteByte(0x101e76, 0x03);
880
881 /****************DMD1****************/
882 _HAL_DMD_RIU_WriteByte(0x10331f, 0x10);
883
884 _HAL_DMD_RIU_WriteByte(0x103321, 0x07);
885 _HAL_DMD_RIU_WriteByte(0x103320, 0x11);
886
887 _HAL_DMD_RIU_WriteByte(0x103323, 0x00);
888 _HAL_DMD_RIU_WriteByte(0x103322, 0x00);
889
890 _HAL_DMD_RIU_WriteByte(0x11220b, 0x00);
891 _HAL_DMD_RIU_WriteByte(0x11220a, 0x04);
892
893 _HAL_DMD_RIU_WriteByte(0x11220c, 0x00);
894 _HAL_DMD_RIU_WriteByte(0x112211, 0x00);
895
896 _HAL_DMD_RIU_WriteByte(0x112213, 0x00);
897 _HAL_DMD_RIU_WriteByte(0x112212, 0x00);
898
899 _HAL_DMD_RIU_WriteByte(0x112215, 0x04);
900
901 _HAL_DMD_RIU_WriteByte(0x112217, 0x00);
902 _HAL_DMD_RIU_WriteByte(0x112216, 0x00);
903
904 _HAL_DMD_RIU_WriteByte(0x112222, 0x04);
905
906 _HAL_DMD_RIU_WriteByte(0x101e39, 0x03); //force ANA MISC controlled by DMD0
907 _HAL_DMD_RIU_WriteByte(0x101e3d, 0x01);
908 }
909 else
910 {
911 _HAL_DMD_RIU_WriteByte(0x101e39, 0x00);
912
913 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
914 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
915
916 _HAL_DMD_RIU_WriteByte(0x103301, 0x07);
917 _HAL_DMD_RIU_WriteByte(0x103300, 0x11);
918
919 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
920
921 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
922 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
923
924 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
925 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
926
927 _HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
928
929 _HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
930
931 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
932 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
933
934 _HAL_DMD_RIU_WriteByte(0x111f15, 0x00);
935
936 _HAL_DMD_RIU_WriteByte(0x111f17, 0x00);
937 _HAL_DMD_RIU_WriteByte(0x111f16, 0x00);
938
939 _HAL_DMD_RIU_WriteByte(0x111f22, 0x00);
940
941 _HAL_DMD_RIU_WriteByte(0x101ea1, 0x00);
942 _HAL_DMD_RIU_WriteByte(0x101e04, 0x02);
943 _HAL_DMD_RIU_WriteByte(0x101e76, 0x03);
944
945 _HAL_DMD_RIU_WriteByte(0x101e39, 0x03); //force ANA MISC controlled by DMD0
946 _HAL_DMD_RIU_WriteByte(0x101e3d, 0x01);
947 }
948 }
949 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_KELTIC)
_HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)950 static void _HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)
951 {
952 printf("--------------DMD_ATSC_CHIP_KELTIC--------------\n");
953
954 _HAL_DMD_RIU_WriteByte(0x101e39, 0x00);
955
956 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
957 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
958
959 _HAL_DMD_RIU_WriteByte(0x103301, 0x07);
960 _HAL_DMD_RIU_WriteByte(0x103300, 0x11);
961
962 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
963
964 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
965 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
966
967 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
968 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
969
970 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
971 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
972
973 _HAL_DMD_RIU_WriteByte(0x111f15, 0x00);
974
975 _HAL_DMD_RIU_WriteByte(0x111f17, 0x00);
976 _HAL_DMD_RIU_WriteByte(0x111f16, 0x00);
977
978 _HAL_DMD_RIU_WriteByte(0x111f22, 0x00);
979
980 _HAL_DMD_RIU_WriteByte(0x1120bc, 0x00);
981
982 _HAL_DMD_RIU_WriteByte(0x101ea1, 0x00);
983 _HAL_DMD_RIU_WriteByte(0x101e04, 0x02);
984
985 _HAL_DMD_RIU_WriteByte(0x101e39, 0x03);
986 }
987 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_KERES)
_HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)988 static void _HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)
989 {
990 MS_U8 u8Val=0x00;
991
992 printf("--------------DMD_ATSC_CHIP_KERES--------------\n");
993
994 u8Val = _HAL_DMD_RIU_ReadByte(0x101e39);
995 _HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
996
997 _HAL_DMD_RIU_WriteByte(0x10331f,0x00);
998 _HAL_DMD_RIU_WriteByte(0x10331e,0x10);
999 _HAL_DMD_RIU_WriteByte(0x103301,0x07);
1000 _HAL_DMD_RIU_WriteByte(0x103300,0x11);
1001 _HAL_DMD_RIU_WriteByte(0x103309,0x00);
1002 _HAL_DMD_RIU_WriteByte(0x103315,0x00);
1003 _HAL_DMD_RIU_WriteByte(0x103314,0x00);
1004
1005 _HAL_DMD_RIU_WriteByte(0x111f0b,0x00);
1006 _HAL_DMD_RIU_WriteByte(0x111f0a,0x00);
1007 _HAL_DMD_RIU_WriteByte(0x111f0c,0x00);
1008 _HAL_DMD_RIU_WriteByte(0x111f11,0x00);
1009 _HAL_DMD_RIU_WriteByte(0x111f13,0x00);
1010 _HAL_DMD_RIU_WriteByte(0x111f12,0x00);
1011 _HAL_DMD_RIU_WriteByte(0x111f15,0x00);
1012 _HAL_DMD_RIU_WriteByte(0x111f17,0x00);
1013 _HAL_DMD_RIU_WriteByte(0x111f16,0x00);
1014 _HAL_DMD_RIU_WriteByte(0x111f22,0x00);
1015 _HAL_DMD_RIU_WriteByte(0x111f2b,0x00); //enable clk_rs
1016 _HAL_DMD_RIU_WriteByte(0x111f2a,0x10);
1017 //_HAL_DMD_RIU_WriteByte(0x000e13,0x01); // No need, it cause uart issue.
1018 _HAL_DMD_RIU_WriteByte(0x101ea1,0x00);
1019
1020 _HAL_DMD_RIU_WriteByte(0x101e04,0x02);
1021 _HAL_DMD_RIU_WriteByte(0x101e76,0x03);
1022
1023 u8Val = _HAL_DMD_RIU_ReadByte(0x101e39);
1024 _HAL_DMD_RIU_WriteByte(0x101e39, u8Val|0x03);
1025 }
1026 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_EDEN)
_HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)1027 static void _HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)
1028 {
1029 MS_U8 u8Val = 0x00;
1030
1031 printf("--------------DMD_ATSC_CHIP_EDEN--------------\n");
1032
1033 u8Val = _HAL_DMD_RIU_ReadByte(0x101e39);
1034 _HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
1035
1036 _HAL_DMD_RIU_WriteByte(0x10331e,0x10);
1037 _HAL_DMD_RIU_WriteByte(0x103301,0x04);
1038 _HAL_DMD_RIU_WriteByte(0x103300,0x0B);
1039 _HAL_DMD_RIU_WriteByte(0x103309,0x00);
1040 _HAL_DMD_RIU_WriteByte(0x103308,0x00);
1041 _HAL_DMD_RIU_WriteByte(0x103315,0x00);
1042 _HAL_DMD_RIU_WriteByte(0x103314,0x04);
1043
1044 _HAL_DMD_RIU_WriteByte(0x111f03,0x00);
1045 _HAL_DMD_RIU_WriteByte(0x111f02,0x00);
1046 _HAL_DMD_RIU_WriteByte(0x111f05,0x00);
1047 _HAL_DMD_RIU_WriteByte(0x111f04,0x00);
1048 _HAL_DMD_RIU_WriteByte(0x111f07,0x00);
1049 _HAL_DMD_RIU_WriteByte(0x111f06,0x00);
1050 _HAL_DMD_RIU_WriteByte(0x111f0b,0x00);
1051 _HAL_DMD_RIU_WriteByte(0x111f0a,0x08);
1052
1053 _HAL_DMD_RIU_WriteByte(0x111f0d,0x00);
1054 _HAL_DMD_RIU_WriteByte(0x111f0c,0x00);
1055 _HAL_DMD_RIU_WriteByte(0x111f0f,0x00);
1056 _HAL_DMD_RIU_WriteByte(0x111f0e,0x00);
1057
1058 _HAL_DMD_RIU_WriteByte(0x111f11,0x00);
1059 _HAL_DMD_RIU_WriteByte(0x111f10,0x00);
1060 _HAL_DMD_RIU_WriteByte(0x111f13,0x00);
1061 _HAL_DMD_RIU_WriteByte(0x111f12,0x08);
1062 _HAL_DMD_RIU_WriteByte(0x111f19,0x00);
1063 _HAL_DMD_RIU_WriteByte(0x111f18,0x00);
1064 _HAL_DMD_RIU_WriteByte(0x111f23,0x40);
1065 _HAL_DMD_RIU_WriteByte(0x111f22,0x00);
1066
1067 u8Val = _HAL_DMD_RIU_ReadByte(0x101e39);
1068 _HAL_DMD_RIU_WriteByte(0x101e39, (u8Val|0x03));
1069 }
1070 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_EMERALD)
_HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)1071 static void _HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)
1072 {
1073 MS_U8 u8Val = 0x00;
1074
1075 printf("--------------DMD_ATSC_CHIP_EMERALD--------------\n");
1076
1077 u8Val = _HAL_DMD_RIU_ReadByte(0x101e39);
1078 _HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
1079
1080 _HAL_DMD_RIU_WriteByte(0x10331f,0x00);//Different with EDEN!
1081 _HAL_DMD_RIU_WriteByte(0x10331e,0x10);
1082 _HAL_DMD_RIU_WriteByte(0x103301,0x05);//Different with EDEN!
1083 _HAL_DMD_RIU_WriteByte(0x103300,0x11);//Different with EDEN!
1084 _HAL_DMD_RIU_WriteByte(0x103309,0x00);
1085 _HAL_DMD_RIU_WriteByte(0x103308,0x00);
1086 _HAL_DMD_RIU_WriteByte(0x103315,0x00);
1087 _HAL_DMD_RIU_WriteByte(0x103314,0x00);//Different with EDEN!
1088
1089 _HAL_DMD_RIU_WriteByte(0x111f03,0x00);
1090 _HAL_DMD_RIU_WriteByte(0x111f02,0x00);
1091 _HAL_DMD_RIU_WriteByte(0x111f05,0x00);
1092 _HAL_DMD_RIU_WriteByte(0x111f04,0x00);
1093 _HAL_DMD_RIU_WriteByte(0x111f07,0x00);
1094 _HAL_DMD_RIU_WriteByte(0x111f06,0x00);
1095 _HAL_DMD_RIU_WriteByte(0x111f0b,0x00);
1096 _HAL_DMD_RIU_WriteByte(0x111f0a,0x08);
1097
1098 _HAL_DMD_RIU_WriteByte(0x111f0d,0x00);
1099 _HAL_DMD_RIU_WriteByte(0x111f0c,0x00);
1100 _HAL_DMD_RIU_WriteByte(0x111f0f,0x00);
1101 _HAL_DMD_RIU_WriteByte(0x111f0e,0x00);
1102
1103 _HAL_DMD_RIU_WriteByte(0x111f11,0x00);
1104 _HAL_DMD_RIU_WriteByte(0x111f10,0x00);
1105 _HAL_DMD_RIU_WriteByte(0x111f13,0x00);
1106 _HAL_DMD_RIU_WriteByte(0x111f12,0x08);
1107 _HAL_DMD_RIU_WriteByte(0x111f19,0x00);
1108 _HAL_DMD_RIU_WriteByte(0x111f18,0x00);
1109 _HAL_DMD_RIU_WriteByte(0x111f23,0x00);//Different with EDEN!
1110 _HAL_DMD_RIU_WriteByte(0x111f22,0x00);
1111
1112 _HAL_DMD_RIU_WriteByte(0x111f25,0x00);//Different with EDEN!
1113 _HAL_DMD_RIU_WriteByte(0x111f24,0x00);//Different with EDEN!
1114 _HAL_DMD_RIU_WriteByte(0x111f1E,0x00);//Different with EDEN!
1115 _HAL_DMD_RIU_WriteByte(0x111f09,0x00);//Different with EDEN!
1116
1117 u8Val = _HAL_DMD_RIU_ReadByte(0x000e13);
1118 _HAL_DMD_RIU_WriteByte(0x000e13, u8Val&0xFB);
1119
1120 u8Val = _HAL_DMD_RIU_ReadByte(0x101e39);
1121 _HAL_DMD_RIU_WriteByte(0x101e39, u8Val|0x03);
1122 }
1123 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_EINSTEIN)
_HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)1124 static void _HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)
1125 {
1126 MS_U8 u8Val = 0;
1127
1128 printf("--------------DMD_ATSC_CHIP_EINSTEIN--------------\n");
1129
1130 u8Val = _HAL_DMD_RIU_ReadByte(0x101e39);
1131 _HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
1132
1133 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
1134 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10); //Denny: change 0x10!! 108M
1135 _HAL_DMD_RIU_WriteByte(0x103301, 0x05); //addy update 0809 MAdp_Demod_WriteReg(0x103301, 0x06);
1136 _HAL_DMD_RIU_WriteByte(0x103300, 0x11); //addy update 0809 MAdp_Demod_WriteReg(0x103300, 0x0B);
1137 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
1138 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
1139 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
1140 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
1141
1142 _HAL_DMD_RIU_WriteByte(0x111f28, 0x00); //dan add for nugget
1143 _HAL_DMD_RIU_WriteByte(0x111f03, 0x00);
1144 _HAL_DMD_RIU_WriteByte(0x111f02, 0x00);
1145 _HAL_DMD_RIU_WriteByte(0x111f05, 0x00);
1146 _HAL_DMD_RIU_WriteByte(0x111f04, 0x00);
1147 _HAL_DMD_RIU_WriteByte(0x111f07, 0x00);
1148 _HAL_DMD_RIU_WriteByte(0x111f06, 0x00);
1149 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
1150 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x08); // note enable clk_atsc_adcd_sync=25.41
1151
1152 _HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
1153 _HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
1154 _HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
1155 _HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
1156
1157 _HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
1158 _HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
1159 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
1160 _HAL_DMD_RIU_WriteByte(0x111f12, 0x08); //0406 update 0->8
1161 _HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
1162 _HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
1163
1164 _HAL_DMD_RIU_WriteByte(0x111f43, 0x00); //dan add for nugget
1165 _HAL_DMD_RIU_WriteByte(0x111f42, 0x00); //dan add for nugget
1166 _HAL_DMD_RIU_WriteByte(0x111f45, 0x00); //dan add for nugget
1167 _HAL_DMD_RIU_WriteByte(0x111f44, 0x00); //dan add for nugget
1168 _HAL_DMD_RIU_WriteByte(0x111f46, 0x01); //dan add for nugget
1169 _HAL_DMD_RIU_WriteByte(0x111f49, 0x00); //dan add for nugget
1170 _HAL_DMD_RIU_WriteByte(0x111f48, 0x00); //dan add for nugget
1171 _HAL_DMD_RIU_WriteByte(0x111f4b, 0x00); //dan add for nugget
1172 _HAL_DMD_RIU_WriteByte(0x111f4a, 0x00); //dan add for nugget
1173 _HAL_DMD_RIU_WriteByte(0x111f4c, 0x00); //dan add for nugget
1174
1175 _HAL_DMD_RIU_WriteByte(0x111f23, 0x00);
1176 _HAL_DMD_RIU_WriteByte(0x111f22, 0x00);//0x08); VT found some err.
1177
1178 u8Val = _HAL_DMD_RIU_ReadByte(0x101e39);
1179 _HAL_DMD_RIU_WriteByte(0x101e39, u8Val|0x03);
1180 }
1181 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_EINSTEIN3)
_HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)1182 static void _HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)
1183 {
1184 MS_U8 u8Val = 0;
1185
1186 printf("--------------DMD_ATSC_CHIP_EINSTEIN3--------------\n");
1187
1188 u8Val = _HAL_DMD_RIU_ReadByte(0x101e39);
1189 _HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
1190
1191 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
1192 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);// Denny: change 0x10!! 108M
1193 _HAL_DMD_RIU_WriteByte(0x103301, 0x05);//addy update 0809 MAdp_Demod_WriteReg(0x103301, 0x06);
1194 _HAL_DMD_RIU_WriteByte(0x103300, 0x11);//addy update 0809 MAdp_Demod_WriteReg(0x103300, 0x0B);
1195 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
1196 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
1197 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
1198 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
1199
1200 _HAL_DMD_RIU_WriteByte(0x111f28, 0x00); //dan add for nugget
1201 _HAL_DMD_RIU_WriteByte(0x111f03, 0x00);
1202 _HAL_DMD_RIU_WriteByte(0x111f02, 0x00);
1203 _HAL_DMD_RIU_WriteByte(0x111f05, 0x00);
1204 _HAL_DMD_RIU_WriteByte(0x111f04, 0x00);
1205 _HAL_DMD_RIU_WriteByte(0x111f07, 0x00);
1206 _HAL_DMD_RIU_WriteByte(0x111f06, 0x00);
1207 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
1208 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x08); // note enable clk_atsc_adcd_sync=25.41
1209
1210 _HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
1211 _HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
1212 _HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
1213 _HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
1214
1215 _HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
1216 _HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
1217 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
1218 _HAL_DMD_RIU_WriteByte(0x111f12, 0x08);//0406 update 0->8
1219 _HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
1220 _HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
1221
1222 _HAL_DMD_RIU_WriteByte(0x111f43, 0x00); //dan add for nugget
1223 _HAL_DMD_RIU_WriteByte(0x111f42, 0x00); //dan add for nugget
1224 _HAL_DMD_RIU_WriteByte(0x111f45, 0x00); //dan add for nugget
1225 _HAL_DMD_RIU_WriteByte(0x111f44, 0x00); //dan add for nugget
1226 _HAL_DMD_RIU_WriteByte(0x111f46, 0x01); //dan add for nugget
1227 _HAL_DMD_RIU_WriteByte(0x111f49, 0x00); //dan add for nugget
1228 _HAL_DMD_RIU_WriteByte(0x111f48, 0x00); //dan add for nugget
1229 _HAL_DMD_RIU_WriteByte(0x111f4b, 0x00); //dan add for nugget
1230 _HAL_DMD_RIU_WriteByte(0x111f4a, 0x00); //dan add for nugget
1231 _HAL_DMD_RIU_WriteByte(0x111f4c, 0x00); //dan add for nugget
1232
1233 _HAL_DMD_RIU_WriteByte(0x111f23, 0x00);
1234 _HAL_DMD_RIU_WriteByte(0x111f22, 0x00);//0x08); VT found some err.
1235
1236 u8Val = _HAL_DMD_RIU_ReadByte(0x101e39);
1237 _HAL_DMD_RIU_WriteByte(0x101e39, u8Val|0x03);
1238 }
1239 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MONACO)
_HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)1240 static void _HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)
1241 {
1242 MS_U8 u8Val = 0;
1243
1244 printf("--------------DMD_ATSC_CHIP_MONACO--------------\n");
1245
1246 u8Val = _HAL_DMD_RIU_ReadByte(0x101e39);
1247 _HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
1248
1249 // DMDMCU 108M
1250 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
1251 // Set parallel TS clock
1252 // [11] : reg_ckg_demod_test_in_en = 0
1253 // 0: select internal ADC CLK
1254 // 1: select external test-in clock
1255 // [10] : reg_ckg_dvbtm_ts_out_mode = 1
1256 // 0: select gated clock
1257 // 1: select free-run clock
1258 // [9] : reg_ckg_atsc_dvbtc_ts_inv = 0
1259 // 0: normal phase to pad
1260 // 1: invert phase to pad
1261 // [8] : reg_ckg_atsc_dvb_div_sel = 1
1262 // 0: select clk_dmplldiv5
1263 // 1: select clk_dmplldiv3
1264 // [4:0]: reg_ckg_dvbtm_ts_divnum = 17
1265 // => TS clock = (864/3)/(2*(17+1)) = 8MHz
1266 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h00, 2'b11, 16'h0511);
1267 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h00, 2'b11, 16'h0511);
1268 _HAL_DMD_RIU_WriteByte(0x103301, 0x05);
1269 _HAL_DMD_RIU_WriteByte(0x103300, 0x11);
1270 // Enable ATSC, DVBTC TS clock
1271 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
1272 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
1273 // Enable ADC clock in clkgen_demod
1274 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
1275 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
1276 // Enable VIF DAC clock in clkgen_demod
1277 _HAL_DMD_RIU_WriteByte(0x111f29, 0x00);
1278 _HAL_DMD_RIU_WriteByte(0x111f28, 0x00);
1279 // Enable ATSC clock
1280 _HAL_DMD_RIU_WriteByte(0x111f03, 0x00);
1281 _HAL_DMD_RIU_WriteByte(0x111f02, 0x00);
1282 _HAL_DMD_RIU_WriteByte(0x111f05, 0x00);
1283 _HAL_DMD_RIU_WriteByte(0x111f04, 0x00);
1284 _HAL_DMD_RIU_WriteByte(0x111f07, 0x00);
1285 _HAL_DMD_RIU_WriteByte(0x111f06, 0x00);
1286 // Enable clk_atsc_adcd_sync = 25.41
1287 // [3:0]: reg_ckg_atsc_adcd_sync
1288 // [0] : disable clock
1289 // [1] : invert clock
1290 // [3:2]: Select clock source
1291 // 00: clk_dmdadc_sync
1292 // 01: clk_atsc50_p
1293 // ^^^^^^^^^^^^
1294 // if(reg_atsc_adc_sel_mplldiv2) => clk_dmplldiv2_div7(49.7 MHz)
1295 // else => clk_dmplldiv17(50.82 MHz)
1296 // 10: clk_atsc25_p
1297 // ^^^^^^^^^^^^
1298 // if(reg_atsc_adc_sel_mplldiv2) => clk_dmplldiv2_div7_div2(24.85 MHz)
1299 // else => clk_dmplldiv17_div2(25.41 MHz)
1300 // 11: 1'b0
1301 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h05, 2'b11, 16'h0008);
1302 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h05, 2'b11, 16'h0008);
1303 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
1304 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x08);
1305 // Enable DVBT inner clock
1306 _HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
1307 _HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
1308 _HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
1309 _HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
1310 // Enable DVBT outer clock
1311 _HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
1312 _HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
1313 // Enable DVBC outer clock
1314 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
1315 _HAL_DMD_RIU_WriteByte(0x111f12, 0x08);
1316 // Enable SRAM clock
1317 _HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
1318 _HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
1319 // Enable ISDBT SRAM share clock and symbol rate clock
1320 _HAL_DMD_RIU_WriteByte(0x111f49, 0x44);
1321 _HAL_DMD_RIU_WriteByte(0x111f48, 0x00);
1322 // select clock
1323 _HAL_DMD_RIU_WriteByte(0x111f23, 0x00);
1324 _HAL_DMD_RIU_WriteByte(0x111f22, 0x00);
1325 // [3:0] : reg_ckg_dtmb_eq2x_inner2x_12x
1326 // [0] : disable clock
1327 // [1] : invert clock
1328 // [3:2]: Select clock source
1329 // 00: dtmb_clk288_buf(256 MHz)
1330 // 01: dtmb_eq_sram_clk36_buf(32 MHz)
1331 // 10: dtmb_eq_sram_clk216_buf(192 MHz)
1332 // 11: 1'b0
1333 // [7:4] : reg_ckg_dtmb_inner1x_dvbc_eq1x => CCI LMS 1x
1334 // ^^^^^^^^^^
1335 // [0] : disable clock
1336 // [1] : invert clock
1337 // [3:2]: Select clock source
1338 // 00: dtmb_clk18_buf(16 MHz) => DTMB
1339 // 01: clk_dmplldiv3_div16(18 MHz) => DVBC,ISDBT(>= (24/2=12))
1340 // 10: clk_dmplldiv10_div8(10.8 MHz)=> DVBT
1341 // 11: clk_cci_lms_1x_atsc_p_buf => ATSC
1342 // ^^^^^^^^^^^^^^^^^^^^^^^^^
1343 // if(reg_atsc_eq_sel_mplldiv2) => clk_dmplldiv2_div2_inv_div8(21.75 MHz)
1344 // else => clk_dmplldiv5_inv_div8(21.6 MHz)
1345 // [11:8] : reg_ckg_dtmb_inner4x_dvbc_eq4x => CCI LMS 4x
1346 // ^^^^^^^^^^
1347 // [0] : disable clock
1348 // [1] : invert clock
1349 // [3:2]: Select clock source
1350 // 00: dtmb_clk72_buf(64 MHz) => DTMB
1351 // 01: clk_dmplldiv3_div4(72 MHz) => DVBC,ISDBT(>= 48)
1352 // 10: clk_dmplldiv10_div2(43.2 MHz)=> DVBT
1353 // 11: clk_cci_lms_4x_atsc_p_buf => ATSC
1354 // ^^^^^^^^^^^^^^^^^^^^^^^^^
1355 // if(reg_atsc_eq_sel_mplldiv2) => clk_dmplldiv2_div2_inv_div2(87 MHz)
1356 // else => clk_dmplldiv5_inv_div2(86.4 MHz)
1357 // [15:12]: reg_ckg_dtmb_sram_dump
1358 // [0] : disable clock
1359 // [1] : invert clock
1360 // [3:2]: Select clock source
1361 // 00: dtmb_clk18_buf(16 MHz)
1362 // 01: dtmb_sram_dump_clk144_buf(128 MHz)
1363 // 10: dtmb_sram_dump_clk216_buf(192 MHz)
1364 // 11: dtmb_sram_dump_dmplldiv5_buf(153.6 MHz)
1365 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h38, 2'b11, 16'h1cc1);
1366 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h38, 2'b11, 16'h1cc1);
1367 _HAL_DMD_RIU_WriteByte(0x111f71, 0x1C);
1368 _HAL_DMD_RIU_WriteByte(0x111f70, 0xC1);
1369 // [4:0] : reg_ckg_dtmb_inner4x_sr1x => symbol rate FFT 1x
1370 // ^^^^^^^^^^^^^^^^^^
1371 // [0] : disable clock
1372 // [1] : invert clock
1373 // [4:2]: Select clock source
1374 // 000: adc_clk_buf
1375 // 001: clk_atsc25_p
1376 // ^^^^^^^^^^^^
1377 // if(reg_atsc_adc_sel_mplldiv2) => clk_dmplldiv2_div7_div2(24.85 MHz)
1378 // else => clk_dmplldiv17_div2(25.41 MHz)
1379 // 010: clk_atsc_eq25_p
1380 // ^^^^^^^^^^^^^^^
1381 // case({reg_eq25_sel_mplldiv3,reg_atsc_eq_sel_mplldiv2})
1382 // 2'b00: clk_dmplldiv5_inv_div8 (21.6 MHz)
1383 // 2'b01: clk_dmplldiv2_div2_inv_div8 (21.75 MHz)
1384 // 2'b10: clk_dmplldiv3_div16 (18 MHz)
1385 // 2'b11: 1'b0
1386 // endcase
1387 // 011: dtmb_clk72_buf(72 MHz)
1388 // 100: dtmb_clk18_buf(18 MHz)
1389 // 101: 1'b0
1390 // 110: 1'b0
1391 // 111: 1'b0
1392 // [12:8] : reg_ckg_dtmb_inner2x_sr0p5x => symbol rate FFT 0.5x
1393 // ^^^^^^^^^^^^^^^^^^^^
1394 // [0] : disable clock
1395 // [1] : invert clock
1396 // [4:2]: Select clock source
1397 // 000: clk_adc_div2_buf
1398 // 001: clk_frontend_d2_p0
1399 // ^^^^^^^^^^^^^^^^^^
1400 // if(reg_atsc_adc_sel_mplldiv2) => clk_dmplldiv2_div7_div4(12.43 MHz)
1401 // else => clk_dmplldiv17_div4(12.705 MHz)
1402 // 010: clk_atsc_eq25_div2_p
1403 // ^^^^^^^^^^^^^^^^^^^^
1404 // case({reg_eq25_sel_mplldiv3,reg_atsc_eq_sel_mplldiv2})
1405 // 2'b00: clk_dmplldiv5_inv_div8_div2 (10.8 MHz)
1406 // 2'b01: clk_dmplldiv2_div2_inv_div8_div2 (10.875 MHz)
1407 // 2'b10: clk_dmplldiv3_div32 (9 MHz)
1408 // 2'b11: 1'b0
1409 // endcase
1410 // 011: dtmb_clk36_buf(36 MHz)
1411 // 100: dtmb_clk9_buf(9 MHz)
1412 // 101: 1'b0
1413 // 110: 1'b0
1414 // 111: 1'b0
1415 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h3b, 2'b11, 16'h0404);
1416 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h3b, 2'b11, 16'h0404);
1417 _HAL_DMD_RIU_WriteByte(0x111f77, 0x04);
1418 _HAL_DMD_RIU_WriteByte(0x111f76, 0x04);
1419
1420 //Enable SRAM power saving
1421 _HAL_DMD_RIU_WriteByte(0x112091, 0x44);
1422 _HAL_DMD_RIU_WriteByte(0x112090, 0x00);
1423
1424 u8Val = _HAL_DMD_RIU_ReadByte(0x101e39);
1425 _HAL_DMD_RIU_WriteByte(0x101e39, u8Val|0x03);
1426 }
1427 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_EDISON)
_HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)1428 static void _HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)
1429 {
1430 MS_U8 u8Val = 0x00;
1431
1432 printf("--------------DMD_ATSC_CHIP_EDISON--------------\n");
1433
1434 u8Val = _HAL_DMD_RIU_ReadByte(0x101e39);
1435 _HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
1436
1437 _HAL_DMD_RIU_WriteByte(0x10331f,0x00);//Different with EDEN!
1438 _HAL_DMD_RIU_WriteByte(0x10331e,0x10);
1439 _HAL_DMD_RIU_WriteByte(0x103301,0x06);//Different with EDEN!
1440 _HAL_DMD_RIU_WriteByte(0x103300,0x0B);//Different with EDEN!
1441 _HAL_DMD_RIU_WriteByte(0x103309,0x00);
1442 _HAL_DMD_RIU_WriteByte(0x103308,0x00);
1443 _HAL_DMD_RIU_WriteByte(0x103315,0x00);
1444 _HAL_DMD_RIU_WriteByte(0x103314,0x00);//Different with EDEN!
1445
1446 _HAL_DMD_RIU_WriteByte(0x111f03,0x00);
1447 _HAL_DMD_RIU_WriteByte(0x111f02,0x00);
1448 _HAL_DMD_RIU_WriteByte(0x111f05,0x00);
1449 _HAL_DMD_RIU_WriteByte(0x111f04,0x00);
1450 _HAL_DMD_RIU_WriteByte(0x111f07,0x00);
1451 _HAL_DMD_RIU_WriteByte(0x111f06,0x00);
1452 _HAL_DMD_RIU_WriteByte(0x111f0b,0x00);
1453 _HAL_DMD_RIU_WriteByte(0x111f0a,0x00);
1454
1455 _HAL_DMD_RIU_WriteByte(0x111f0d,0x00);
1456 _HAL_DMD_RIU_WriteByte(0x111f0c,0x00);
1457 _HAL_DMD_RIU_WriteByte(0x111f0f,0x00);
1458 _HAL_DMD_RIU_WriteByte(0x111f0e,0x00);
1459
1460 _HAL_DMD_RIU_WriteByte(0x111f11,0x00);
1461 _HAL_DMD_RIU_WriteByte(0x111f10,0x00);
1462 _HAL_DMD_RIU_WriteByte(0x111f13,0x00);
1463 _HAL_DMD_RIU_WriteByte(0x111f12,0x08);
1464 _HAL_DMD_RIU_WriteByte(0x111f19,0x00);
1465 _HAL_DMD_RIU_WriteByte(0x111f18,0x00);
1466 _HAL_DMD_RIU_WriteByte(0x111f23,0x00);//Different with EDEN!
1467 _HAL_DMD_RIU_WriteByte(0x111f22,0x00);
1468
1469 _HAL_DMD_RIU_WriteByte(0x111f25,0x00);
1470 _HAL_DMD_RIU_WriteByte(0x111f24,0x00);
1471
1472 _HAL_DMD_RIU_WriteByte(0x111F1E,0x00);
1473 _HAL_DMD_RIU_WriteByte(0x111F09,0x00);
1474
1475 u8Val = _HAL_DMD_RIU_ReadByte(0x000e13);
1476 _HAL_DMD_RIU_WriteByte(0x000e13, u8Val&0xFB);
1477
1478 u8Val = _HAL_DMD_RIU_ReadByte(0x101e39);
1479 _HAL_DMD_RIU_WriteByte(0x101e39, u8Val|0x03);
1480 }
1481 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_EIFFEL)
_HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)1482 static void _HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)
1483 {
1484 MS_U8 u8Val = 0x00;
1485
1486 printf("--------------DMD_ATSC_CHIP_EIFFEL--------------\n");
1487
1488 u8Val = _HAL_DMD_RIU_ReadByte(0x101e39);
1489 _HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
1490
1491 _HAL_DMD_RIU_WriteByte(0x101e39 ,0x00);
1492 _HAL_DMD_RIU_WriteByte(0x10331f ,0x00);
1493 _HAL_DMD_RIU_WriteByte(0x10331e ,0x10);
1494 _HAL_DMD_RIU_WriteByte(0x103301 ,0x05);
1495 _HAL_DMD_RIU_WriteByte(0x103300 ,0x11);
1496 _HAL_DMD_RIU_WriteByte(0x103309 ,0x00);
1497 _HAL_DMD_RIU_WriteByte(0x103308 ,0x00);
1498 _HAL_DMD_RIU_WriteByte(0x103315 ,0x00);
1499 _HAL_DMD_RIU_WriteByte(0x103314 ,0x00);
1500 _HAL_DMD_RIU_WriteByte(0x111f28 ,0x00);
1501 // _HAL_DMD_RIU_WriteByte(0x112028 ,0x03);
1502 _HAL_DMD_RIU_WriteByte(0x111f03 ,0x00);
1503 _HAL_DMD_RIU_WriteByte(0x111f02 ,0x00);
1504 _HAL_DMD_RIU_WriteByte(0x111f05 ,0x00);
1505 _HAL_DMD_RIU_WriteByte(0x111f04 ,0x00);
1506 _HAL_DMD_RIU_WriteByte(0x111f07 ,0x00);
1507 _HAL_DMD_RIU_WriteByte(0x111f06 ,0x00);
1508 _HAL_DMD_RIU_WriteByte(0x111f0b ,0x00);
1509 _HAL_DMD_RIU_WriteByte(0x111f0a ,0x08);
1510 _HAL_DMD_RIU_WriteByte(0x111f0d ,0x00);
1511 _HAL_DMD_RIU_WriteByte(0x111f0c ,0x00);
1512 _HAL_DMD_RIU_WriteByte(0x111f0f ,0x00);
1513 _HAL_DMD_RIU_WriteByte(0x111f0e ,0x00);
1514 _HAL_DMD_RIU_WriteByte(0x111f11 ,0x00);
1515 _HAL_DMD_RIU_WriteByte(0x111f10 ,0x00);
1516 _HAL_DMD_RIU_WriteByte(0x111f13 ,0x00);
1517 _HAL_DMD_RIU_WriteByte(0x111f12 ,0x08);
1518 _HAL_DMD_RIU_WriteByte(0x111f19 ,0x00);
1519 _HAL_DMD_RIU_WriteByte(0x111f18 ,0x00);
1520 _HAL_DMD_RIU_WriteByte(0x111f23 ,0x00);
1521 _HAL_DMD_RIU_WriteByte(0x111f22 ,0x00);
1522
1523 u8Val = _HAL_DMD_RIU_ReadByte(0x000e61);
1524 _HAL_DMD_RIU_WriteByte(0x000e61, u8Val&0xFE);
1525
1526 u8Val = _HAL_DMD_RIU_ReadByte(0x101e39);
1527 _HAL_DMD_RIU_WriteByte(0x101e39, u8Val|0x03);
1528 }
1529 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MIAMI)
_HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)1530 stativ void _HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)
1531 {
1532 MS_U8 u8Val = 0;
1533
1534 printf("--------------DMD_ATSC_CHIP_MIAMI--------------\n");
1535
1536 u8Val = _HAL_DMD_RIU_ReadByte(0x101e39);
1537 _HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
1538
1539 // DMDMCU 108M
1540 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
1541 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
1542 // Set parallel TS clock
1543 _HAL_DMD_RIU_WriteByte(0x103301, 0x05);
1544 _HAL_DMD_RIU_WriteByte(0x103300, 0x11);
1545 // Enable ATSC, DVBTC TS clock
1546 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
1547 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
1548 // Enable ADC clock in clkgen_demod
1549 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
1550 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
1551 // Select MPLLDIV17
1552 _HAL_DMD_RIU_WriteByte(0x111f28, 0x00);
1553 // Enable ATSC clock
1554 _HAL_DMD_RIU_WriteByte(0x111f03, 0x00);
1555 _HAL_DMD_RIU_WriteByte(0x111f02, 0x00);
1556 _HAL_DMD_RIU_WriteByte(0x111f05, 0x00);
1557 _HAL_DMD_RIU_WriteByte(0x111f04, 0x00);
1558 _HAL_DMD_RIU_WriteByte(0x111f07, 0x00);
1559 _HAL_DMD_RIU_WriteByte(0x111f06, 0x00);
1560 // enable clk_atsc_adcd_sync
1561 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
1562 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x08);
1563 // Enable DVBT inner clock
1564 _HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
1565 _HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
1566 _HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
1567 _HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
1568 // Enable DVBT outer clock
1569 _HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
1570 _HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
1571 // Enable DVBC outer clock
1572 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
1573 _HAL_DMD_RIU_WriteByte(0x111f12, 0x08);
1574 // Enable SRAM clock
1575 _HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
1576 _HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
1577 // enable clk_dvbtc_sram4_isdbt_inner4x & clk_adc1x_eq1x clock
1578 _HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
1579 _HAL_DMD_RIU_WriteByte(0x111f48, 0x00);
1580 // select clock
1581 _HAL_DMD_RIU_WriteByte(0x111f23, 0x00);
1582 _HAL_DMD_RIU_WriteByte(0x111f22, 0x00);
1583 // enable CCI LMS clock
1584 _HAL_DMD_RIU_WriteByte(0x111f51, 0x00);
1585 _HAL_DMD_RIU_WriteByte(0x111f50, 0xCC);
1586
1587 u8Val = _HAL_DMD_RIU_ReadByte(0x101e39);
1588 _HAL_DMD_RIU_WriteByte(0x101e39, u8Val|0x03);
1589 }
1590 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MUJI)
_HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)1591 static void _HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)
1592 {
1593 printf("--------------DMD_ATSC_CHIP_MUJI--------------\n");
1594
1595 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
1596
1597 // DMDMCU 108M
1598 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
1599 // Set parallel TS clock
1600 // [11] : reg_ckg_demod_test_in_en = 0
1601 // 0: select internal ADC CLK
1602 // 1: select external test-in clock
1603 // [10] : reg_ckg_dvbtm_ts_out_mode = 1
1604 // 0: select gated clock
1605 // 1: select free-run clock
1606 // [9] : reg_ckg_atsc_dvbtc_ts_inv = 0
1607 // 0: normal phase to pad
1608 // 1: invert phase to pad
1609 // [8] : reg_ckg_atsc_dvb_div_sel = 1
1610 // 0: select clk_dmplldiv5
1611 // 1: select clk_dmplldiv3
1612 // [4:0]: reg_ckg_dvbtm_ts_divnum = 17
1613 // => TS clock = (864/3)/(2*(17+1)) = 8MHz
1614 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h00, 2'b11, 16'h0511);
1615 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h00, 2'b11, 16'h0511);
1616 _HAL_DMD_RIU_WriteByte(0x103301, 0x05);
1617 _HAL_DMD_RIU_WriteByte(0x103300, 0x11);
1618 // Enable ATSC, DVBTC TS clock
1619 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
1620 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
1621 // Enable ADC clock in clkgen_demod
1622 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
1623 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
1624 // Reset TS divider
1625 _HAL_DMD_RIU_WriteByte(0x103302, 0x01);
1626 _HAL_DMD_RIU_WriteByte(0x103302, 0x00);
1627 // Enable VIF DAC clock in clkgen_demod
1628 _HAL_DMD_RIU_WriteByte(0x111f29, 0x00);
1629 _HAL_DMD_RIU_WriteByte(0x111f28, 0x00);
1630 // Enable ATSC clock
1631 _HAL_DMD_RIU_WriteByte(0x111f03, 0x00);
1632 _HAL_DMD_RIU_WriteByte(0x111f02, 0x00);
1633 _HAL_DMD_RIU_WriteByte(0x111f05, 0x00);
1634 _HAL_DMD_RIU_WriteByte(0x111f04, 0x00);
1635 _HAL_DMD_RIU_WriteByte(0x111f07, 0x00);
1636 _HAL_DMD_RIU_WriteByte(0x111f06, 0x00);
1637 // Enable clk_atsc_adcd_sync = 25.41
1638 // [3:0]: reg_ckg_atsc_adcd_sync
1639 // [0] : disable clock
1640 // [1] : invert clock
1641 // [3:2]: Select clock source
1642 // 00: clk_dmdadc_sync
1643 // 01: clk_atsc50_p
1644 // ^^^^^^^^^^^^
1645 // if(reg_atsc_adc_sel_mplldiv2) => clk_dmplldiv2_div7(49.7 MHz)
1646 // else => clk_dmplldiv17(50.82 MHz)
1647 // 10: clk_atsc25_p
1648 // ^^^^^^^^^^^^
1649 // if(reg_atsc_adc_sel_mplldiv2) => clk_dmplldiv2_div7_div2(24.85 MHz)
1650 // else => clk_dmplldiv17_div2(25.41 MHz)
1651 // 11: 1'b0
1652 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h05, 2'b11, 16'h0008);
1653 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h05, 2'b11, 16'h0008);
1654 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
1655 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x08);
1656 // Enable DVBT inner clock
1657 _HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
1658 _HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
1659 _HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
1660 _HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
1661 // Enable DVBT outer clock
1662 _HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
1663 _HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
1664 // Enable DVBC outer clock
1665 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
1666 _HAL_DMD_RIU_WriteByte(0x111f12, 0x08);
1667 // Enable SRAM clock
1668 _HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
1669 _HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
1670 // Enable ISDBT SRAM share clock and symbol rate clock
1671 _HAL_DMD_RIU_WriteByte(0x111f49, 0x44);
1672 _HAL_DMD_RIU_WriteByte(0x111f48, 0x00);
1673 // select clock
1674 _HAL_DMD_RIU_WriteByte(0x111f23, 0x00);
1675 _HAL_DMD_RIU_WriteByte(0x111f22, 0x00);
1676 // [3:0] : reg_ckg_dtmb_eq2x_inner2x_12x
1677 // [0] : disable clock
1678 // [1] : invert clock
1679 // [3:2]: Select clock source
1680 // 00: dtmb_clk288_buf(256 MHz)
1681 // 01: dtmb_eq_sram_clk36_buf(32 MHz)
1682 // 10: dtmb_eq_sram_clk216_buf(192 MHz)
1683 // 11: 1'b0
1684 // [7:4] : reg_ckg_dtmb_inner1x_dvbc_eq1x => CCI LMS 1x
1685 // ^^^^^^^^^^
1686 // [0] : disable clock
1687 // [1] : invert clock
1688 // [3:2]: Select clock source
1689 // 00: dtmb_clk18_buf(16 MHz) => DTMB
1690 // 01: clk_dmplldiv3_div16(18 MHz) => DVBC,ISDBT(>= (24/2=12))
1691 // 10: clk_dmplldiv10_div8(10.8 MHz)=> DVBT
1692 // 11: clk_cci_lms_1x_atsc_p_buf => ATSC
1693 // ^^^^^^^^^^^^^^^^^^^^^^^^^
1694 // if(reg_atsc_eq_sel_mplldiv2) => clk_dmplldiv2_div2_inv_div8(21.75 MHz)
1695 // else => clk_dmplldiv5_inv_div8(21.6 MHz)
1696 // [11:8] : reg_ckg_dtmb_inner4x_dvbc_eq4x => CCI LMS 4x
1697 // ^^^^^^^^^^
1698 // [0] : disable clock
1699 // [1] : invert clock
1700 // [3:2]: Select clock source
1701 // 00: dtmb_clk72_buf(64 MHz) => DTMB
1702 // 01: clk_dmplldiv3_div4(72 MHz) => DVBC,ISDBT(>= 48)
1703 // 10: clk_dmplldiv10_div2(43.2 MHz)=> DVBT
1704 // 11: clk_cci_lms_4x_atsc_p_buf => ATSC
1705 // ^^^^^^^^^^^^^^^^^^^^^^^^^
1706 // if(reg_atsc_eq_sel_mplldiv2) => clk_dmplldiv2_div2_inv_div2(87 MHz)
1707 // else => clk_dmplldiv5_inv_div2(86.4 MHz)
1708 // [15:12]: reg_ckg_dtmb_sram_dump
1709 // [0] : disable clock
1710 // [1] : invert clock
1711 // [3:2]: Select clock source
1712 // 00: dtmb_clk18_buf(16 MHz)
1713 // 01: dtmb_sram_dump_clk144_buf(128 MHz)
1714 // 10: dtmb_sram_dump_clk216_buf(192 MHz)
1715 // 11: dtmb_sram_dump_dmplldiv5_buf(153.6 MHz)
1716 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h38, 2'b11, 16'h1cc1);
1717 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h38, 2'b11, 16'h1cc1);
1718 _HAL_DMD_RIU_WriteByte(0x111f71, 0x1C);
1719 _HAL_DMD_RIU_WriteByte(0x111f70, 0xC1);
1720 // [4:0] : reg_ckg_dtmb_inner4x_sr1x => symbol rate FFT 1x
1721 // ^^^^^^^^^^^^^^^^^^
1722 // [0] : disable clock
1723 // [1] : invert clock
1724 // [4:2]: Select clock source
1725 // 000: adc_clk_buf
1726 // 001: clk_atsc25_p
1727 // ^^^^^^^^^^^^
1728 // if(reg_atsc_adc_sel_mplldiv2) => clk_dmplldiv2_div7_div2(24.85 MHz)
1729 // else => clk_dmplldiv17_div2(25.41 MHz)
1730 // 010: clk_atsc_eq25_p
1731 // ^^^^^^^^^^^^^^^
1732 // case({reg_eq25_sel_mplldiv3,reg_atsc_eq_sel_mplldiv2})
1733 // 2'b00: clk_dmplldiv5_inv_div8 (21.6 MHz)
1734 // 2'b01: clk_dmplldiv2_div2_inv_div8 (21.75 MHz)
1735 // 2'b10: clk_dmplldiv3_div16 (18 MHz)
1736 // 2'b11: 1'b0
1737 // endcase
1738 // 011: dtmb_clk72_buf(72 MHz)
1739 // 100: dtmb_clk18_buf(18 MHz)
1740 // 101: 1'b0
1741 // 110: 1'b0
1742 // 111: 1'b0
1743 // [12:8] : reg_ckg_dtmb_inner2x_sr0p5x => symbol rate FFT 0.5x
1744 // ^^^^^^^^^^^^^^^^^^^^
1745 // [0] : disable clock
1746 // [1] : invert clock
1747 // [4:2]: Select clock source
1748 // 000: clk_adc_div2_buf
1749 // 001: clk_frontend_d2_p0
1750 // ^^^^^^^^^^^^^^^^^^
1751 // if(reg_atsc_adc_sel_mplldiv2) => clk_dmplldiv2_div7_div4(12.43 MHz)
1752 // else => clk_dmplldiv17_div4(12.705 MHz)
1753 // 010: clk_atsc_eq25_div2_p
1754 // ^^^^^^^^^^^^^^^^^^^^
1755 // case({reg_eq25_sel_mplldiv3,reg_atsc_eq_sel_mplldiv2})
1756 // 2'b00: clk_dmplldiv5_inv_div8_div2 (10.8 MHz)
1757 // 2'b01: clk_dmplldiv2_div2_inv_div8_div2 (10.875 MHz)
1758 // 2'b10: clk_dmplldiv3_div32 (9 MHz)
1759 // 2'b11: 1'b0
1760 // endcase
1761 // 011: dtmb_clk36_buf(36 MHz)
1762 // 100: dtmb_clk9_buf(9 MHz)
1763 // 101: 1'b0
1764 // 110: 1'b0
1765 // 111: 1'b0
1766 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h3b, 2'b11, 16'h0404);
1767 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h3b, 2'b11, 16'h0404);
1768 _HAL_DMD_RIU_WriteByte(0x111f77, 0x04);
1769 _HAL_DMD_RIU_WriteByte(0x111f76, 0x04);
1770
1771 // Muji
1772 // [1:0] : reg_ckg_isdbt_outer1x_dvbt_outer1x
1773 // [0] : disable clock
1774 // [1] : invert clock
1775 // [3:2]: Select clock source
1776 // vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
1777 // sel[0]= (reg_demod_isdbt_on & reg_ckg_isdbt_outer1x[2])
1778 // sel[1]= (~reg_demod_isdbt_on)
1779 // ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
1780 // 00: isdbt_clk6_lat(6 MHz)
1781 // 01: isdbt_clk8_lat(8 MHz)
1782 // 10: clk_dmplldiv10_div2(43.2 MHz)
1783 // 11: 1'b0
1784 // [6:4] : reg_ckg_miu_dvbtc_outer2x
1785 // [0] : disable clock
1786 // [1] : invert clock
1787 // [2] : Select clock source
1788 // 0: clk_miu_p
1789 // 1: clk_dmplldiv10(86.4 MHz)
1790 // [12:8] : reg_ckg_dvbtc_rs
1791 // [0] : disable clock
1792 // [1] : invert clock
1793 // [4:2]: Select clock source
1794 // 000: clk_dmplldiv10(86.4 MHz)
1795 // 001: clk_dmplldiv10_div2(43.2 MHz)
1796 // 010: clk_atsc50_p
1797 // ^^^^^^^^^^^^
1798 // if(reg_atsc_adc_sel_mplldiv2) => clk_dmplldiv2_div7(49.7 MHz)
1799 // else => clk_dmplldiv17(50.82 MHz)
1800 // 011: clk_dvbtc_rs_216_buf(216 MHz)
1801 // 100: clk_dvbtc_rs_172_buf(172 MHz)
1802 // 101: clk_dvbtc_rs_144_buf(144 MHz)
1803 // 110: 1'b0
1804 // 111: 1'b0
1805 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h27, 2'b10, 16'h0800);
1806 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h27, 2'b10, 16'h0800);
1807 _HAL_DMD_RIU_WriteByte(0x111f4f, 0x08);
1808
1809 //Enable SRAM power saving
1810 _HAL_DMD_RIU_WriteByte(0x112091, 0x44);
1811 _HAL_DMD_RIU_WriteByte(0x112090, 0x00);
1812
1813 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
1814 }
1815 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MUNICH)
_HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)1816 static void _HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)
1817 {
1818 MS_U8 u8Val = 0;
1819
1820 printf("--------------DMD_ATSC_CHIP_MUNICH--------------\n");
1821
1822 u8Val = _HAL_DMD_RIU_ReadByte(0x101e39);
1823 _HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
1824
1825 // DMDMCU 108M
1826 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
1827 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
1828 // Set parallel TS clock
1829 _HAL_DMD_RIU_WriteByte(0x103301, 0x05);
1830 _HAL_DMD_RIU_WriteByte(0x103300, 0x11);
1831 // Enable ATSC, DVBTC TS clock
1832 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
1833 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
1834 // Enable ADC clock in clkgen_demod
1835 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
1836 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
1837 // Select MPLLDIV17
1838 _HAL_DMD_RIU_WriteByte(0x111f28, 0x00);
1839 // Enable ATSC clock
1840 _HAL_DMD_RIU_WriteByte(0x111f03, 0x00);
1841 _HAL_DMD_RIU_WriteByte(0x111f02, 0x00);
1842 _HAL_DMD_RIU_WriteByte(0x111f05, 0x00);
1843 _HAL_DMD_RIU_WriteByte(0x111f04, 0x00);
1844 _HAL_DMD_RIU_WriteByte(0x111f07, 0x00);
1845 _HAL_DMD_RIU_WriteByte(0x111f06, 0x00);
1846 // enable clk_atsc_adcd_sync
1847 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
1848 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x08);
1849 // Enable DVBT inner clock
1850 _HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
1851 _HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
1852 _HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
1853 _HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
1854 // Enable DVBT outer clock
1855 _HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
1856 _HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
1857 // Enable DVBC outer clock
1858 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
1859 _HAL_DMD_RIU_WriteByte(0x111f12, 0x08);
1860 // Enable SRAM clock
1861 _HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
1862 _HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
1863 // enable clk_dvbtc_sram4_isdbt_inner4x & clk_adc1x_eq1x clock
1864 _HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
1865 _HAL_DMD_RIU_WriteByte(0x111f48, 0x00);
1866 // select clock
1867 _HAL_DMD_RIU_WriteByte(0x111f23, 0x00);
1868 _HAL_DMD_RIU_WriteByte(0x111f22, 0x00);
1869 // enable CCI LMS clock
1870 _HAL_DMD_RIU_WriteByte(0x111f51, 0x00);
1871 _HAL_DMD_RIU_WriteByte(0x111f50, 0xCC);
1872
1873 u8Val = _HAL_DMD_RIU_ReadByte(0x101e39);
1874 _HAL_DMD_RIU_WriteByte(0x101e39, u8Val|0x03);
1875 }
1876 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_KIRIN)
_HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)1877 void _HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)
1878 {
1879 MS_U8 u8Val=0x00;
1880
1881 printf("--------------DMD_ATSC_CHIP_KIRIN--------------\n");
1882
1883 u8Val = _HAL_DMD_RIU_ReadByte(0x101e39);
1884 _HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
1885
1886 _HAL_DMD_RIU_WriteByte(0x10331f,0x00);
1887 _HAL_DMD_RIU_WriteByte(0x10331e,0x10);
1888 _HAL_DMD_RIU_WriteByte(0x103301,0x07);
1889 _HAL_DMD_RIU_WriteByte(0x103300,0x11);
1890 _HAL_DMD_RIU_WriteByte(0x103309,0x00);
1891 _HAL_DMD_RIU_WriteByte(0x103315,0x00);
1892 _HAL_DMD_RIU_WriteByte(0x103314,0x00);
1893
1894 _HAL_DMD_RIU_WriteByte(0x111f0b,0x00);
1895 _HAL_DMD_RIU_WriteByte(0x111f0a,0x00);
1896 _HAL_DMD_RIU_WriteByte(0x111f0c,0x00);
1897 _HAL_DMD_RIU_WriteByte(0x111f11,0x00);
1898 _HAL_DMD_RIU_WriteByte(0x111f13,0x00);
1899 _HAL_DMD_RIU_WriteByte(0x111f12,0x00);
1900 _HAL_DMD_RIU_WriteByte(0x111f15,0x00);
1901 _HAL_DMD_RIU_WriteByte(0x111f17,0x00);
1902 _HAL_DMD_RIU_WriteByte(0x111f16,0x00);
1903 _HAL_DMD_RIU_WriteByte(0x111f22,0x00);
1904 _HAL_DMD_RIU_WriteByte(0x111f2b,0x00);
1905 _HAL_DMD_RIU_WriteByte(0x111f2a,0x10);
1906 _HAL_DMD_RIU_WriteByte(0x101ea1,0x00);
1907
1908 _HAL_DMD_RIU_WriteByte(0x101e04,0x02);
1909 _HAL_DMD_RIU_WriteByte(0x101e76,0x03);
1910
1911 u8Val = _HAL_DMD_RIU_ReadByte(0x101e39);
1912 _HAL_DMD_RIU_WriteByte(0x101e39,(u8Val| 0x03));
1913 }
1914 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MAYA)
_HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)1915 void _HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)
1916 {
1917 MS_U8 u8Val=0x00;
1918
1919 printf("--------------DMD_ATSC_CHIP_MAYA--------------\n");
1920
1921 u8Val = _HAL_DMD_RIU_ReadByte(0x101e39);
1922 _HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
1923
1924 // DMDMCU 108M
1925 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
1926 // Set parallel TS clock
1927 _HAL_DMD_RIU_WriteByte(0x103301, 0x05);
1928 _HAL_DMD_RIU_WriteByte(0x103300, 0x11);
1929 // Enable ATSC, DVBTC TS clock
1930 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
1931 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
1932 // Enable ADC clock in clkgen_demod
1933 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
1934 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
1935 // Reset TS divider
1936 _HAL_DMD_RIU_WriteByte(0x103302, 0x01);
1937 _HAL_DMD_RIU_WriteByte(0x103302, 0x00);
1938 // ADC select MPLLDIV17 & EQ select MPLLDIV5
1939 _HAL_DMD_RIU_WriteByte(0x111f43, 0x00);
1940 _HAL_DMD_RIU_WriteByte(0x111f42, 0x00);
1941 // Enable ATSC clock
1942 _HAL_DMD_RIU_WriteByte(0x111f03, 0x00);
1943 _HAL_DMD_RIU_WriteByte(0x111f02, 0x00);
1944 // configure reg_ckg_atsc50, reg_ckg_atsc25, reg_ckg_atsc_eq25 and reg_ckg_atsc_ce25
1945 _HAL_DMD_RIU_WriteByte(0x111f04, 0x00);
1946 _HAL_DMD_RIU_WriteByte(0x111f07, 0x00);
1947 _HAL_DMD_RIU_WriteByte(0x111f06, 0x00);
1948 // enable clk_atsc_adcd_sync
1949 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
1950 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x08);
1951 // Enable DVBC outer clock
1952 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
1953 // Enable SRAM clock
1954 _HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
1955 _HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
1956 // select clock
1957 _HAL_DMD_RIU_WriteByte(0x111f23, 0x00);
1958 _HAL_DMD_RIU_WriteByte(0x111f22, 0x00);
1959 // enable CCI LMS clock
1960 _HAL_DMD_RIU_WriteByte(0x111f71, 0x00);
1961 _HAL_DMD_RIU_WriteByte(0x111f70, 0x00);
1962 // set symbol rate
1963 _HAL_DMD_RIU_WriteByte(0x111f77, 0x04);
1964 _HAL_DMD_RIU_WriteByte(0x111f76, 0x04);
1965 // reg_ckg_adc1x_eq1x
1966 _HAL_DMD_RIU_WriteByte(0x111f49, 0x04);
1967
1968 u8Val = _HAL_DMD_RIU_ReadByte(0x101e39);
1969 _HAL_DMD_RIU_WriteByte(0x101e39,(u8Val| 0x03));
1970 }
1971 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MANHATTAN)
_HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)1972 static void _HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)
1973 {
1974 MS_U8 u8Val = 0;
1975
1976 printf("--------------DMD_ATSC_CHIP_MANHATTAN--------------\n");
1977
1978 u8Val = _HAL_DMD_RIU_ReadByte(0x101e39);
1979 _HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
1980
1981 // DMDMCU 108M
1982 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
1983 // Set parallel TS clock
1984 // [11] : reg_ckg_demod_test_in_en = 0
1985 // 0: select internal ADC CLK
1986 // 1: select external test-in clock
1987 // [10] : reg_ckg_dvbtm_ts_out_mode = 1
1988 // 0: select gated clock
1989 // 1: select free-run clock
1990 // [9] : reg_ckg_atsc_dvbtc_ts_inv = 0
1991 // 0: normal phase to pad
1992 // 1: invert phase to pad
1993 // [8] : reg_ckg_atsc_dvb_div_sel = 1
1994 // 0: select clk_dmplldiv5
1995 // 1: select clk_dmplldiv3
1996 // [4:0]: reg_ckg_dvbtm_ts_divnum = 17
1997 // => TS clock = (864/3)/(2*(17+1)) = 8MHz
1998 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h00, 2'b11, 16'h0511);
1999 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h00, 2'b11, 16'h0511);
2000 _HAL_DMD_RIU_WriteByte(0x103301, 0x05);
2001 _HAL_DMD_RIU_WriteByte(0x103300, 0x11);
2002 // Enable ATSC, DVBTC TS clock
2003 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
2004 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
2005 // Enable ADC clock in clkgen_demod
2006 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
2007 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
2008 // Reset TS divider
2009 _HAL_DMD_RIU_WriteByte(0x103302, 0x01);
2010 _HAL_DMD_RIU_WriteByte(0x103302, 0x00);
2011 // Enable VIF DAC clock in clkgen_demod
2012 _HAL_DMD_RIU_WriteByte(0x111f29, 0x00);
2013 _HAL_DMD_RIU_WriteByte(0x111f28, 0x00);
2014 // Enable ATSC clock
2015 _HAL_DMD_RIU_WriteByte(0x111f03, 0x00);
2016 _HAL_DMD_RIU_WriteByte(0x111f02, 0x00);
2017 _HAL_DMD_RIU_WriteByte(0x111f05, 0x00);
2018 _HAL_DMD_RIU_WriteByte(0x111f04, 0x00);
2019 _HAL_DMD_RIU_WriteByte(0x111f07, 0x00);
2020 _HAL_DMD_RIU_WriteByte(0x111f06, 0x00);
2021 // Enable clk_atsc_adcd_sync = 25.41
2022 // [3:0]: reg_ckg_atsc_adcd_sync
2023 // [0] : disable clock
2024 // [1] : invert clock
2025 // [3:2]: Select clock source
2026 // 00: clk_dmdadc_sync
2027 // 01: clk_atsc50_p
2028 // ^^^^^^^^^^^^
2029 // if(reg_atsc_adc_sel_mplldiv2) => clk_dmplldiv2_div7(49.7 MHz)
2030 // else => clk_dmplldiv17(50.82 MHz)
2031 // 10: clk_atsc25_p
2032 // ^^^^^^^^^^^^
2033 // if(reg_atsc_adc_sel_mplldiv2) => clk_dmplldiv2_div7_div2(24.85 MHz)
2034 // else => clk_dmplldiv17_div2(25.41 MHz)
2035 // 11: 1'b0
2036 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h05, 2'b11, 16'h0008);
2037 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h05, 2'b11, 16'h0008);
2038 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
2039 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x08);
2040 // Enable DVBT inner clock
2041 _HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
2042 _HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
2043 _HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
2044 _HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
2045 // Enable DVBT outer clock
2046 _HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
2047 _HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
2048 // Enable DVBC outer clock
2049 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
2050 _HAL_DMD_RIU_WriteByte(0x111f12, 0x08);
2051 // Enable SRAM clock
2052 _HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
2053 _HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
2054 // Enable ISDBT SRAM share clock and symbol rate clock
2055 _HAL_DMD_RIU_WriteByte(0x111f49, 0x44);
2056 _HAL_DMD_RIU_WriteByte(0x111f48, 0x00);
2057 // select clock
2058 _HAL_DMD_RIU_WriteByte(0x111f23, 0x00);
2059 _HAL_DMD_RIU_WriteByte(0x111f22, 0x00);
2060 // [3:0] : reg_ckg_dtmb_eq2x_inner2x_12x
2061 // [0] : disable clock
2062 // [1] : invert clock
2063 // [3:2]: Select clock source
2064 // 00: dtmb_clk288_buf(256 MHz)
2065 // 01: dtmb_eq_sram_clk36_buf(32 MHz)
2066 // 10: dtmb_eq_sram_clk216_buf(192 MHz)
2067 // 11: 1'b0
2068 // [7:4] : reg_ckg_dtmb_inner1x_dvbc_eq1x => CCI LMS 1x
2069 // ^^^^^^^^^^
2070 // [0] : disable clock
2071 // [1] : invert clock
2072 // [3:2]: Select clock source
2073 // 00: dtmb_clk18_buf(16 MHz) => DTMB
2074 // 01: clk_dmplldiv3_div16(18 MHz) => DVBC,ISDBT(>= (24/2=12))
2075 // 10: clk_dmplldiv10_div8(10.8 MHz)=> DVBT
2076 // 11: clk_cci_lms_1x_atsc_p_buf => ATSC
2077 // ^^^^^^^^^^^^^^^^^^^^^^^^^
2078 // if(reg_atsc_eq_sel_mplldiv2) => clk_dmplldiv2_div2_inv_div8(21.75 MHz)
2079 // else => clk_dmplldiv5_inv_div8(21.6 MHz)
2080 // [11:8] : reg_ckg_dtmb_inner4x_dvbc_eq4x => CCI LMS 4x
2081 // ^^^^^^^^^^
2082 // [0] : disable clock
2083 // [1] : invert clock
2084 // [3:2]: Select clock source
2085 // 00: dtmb_clk72_buf(64 MHz) => DTMB
2086 // 01: clk_dmplldiv3_div4(72 MHz) => DVBC,ISDBT(>= 48)
2087 // 10: clk_dmplldiv10_div2(43.2 MHz)=> DVBT
2088 // 11: clk_cci_lms_4x_atsc_p_buf => ATSC
2089 // ^^^^^^^^^^^^^^^^^^^^^^^^^
2090 // if(reg_atsc_eq_sel_mplldiv2) => clk_dmplldiv2_div2_inv_div2(87 MHz)
2091 // else => clk_dmplldiv5_inv_div2(86.4 MHz)
2092 // [15:12]: reg_ckg_dtmb_sram_dump
2093 // [0] : disable clock
2094 // [1] : invert clock
2095 // [3:2]: Select clock source
2096 // 00: dtmb_clk18_buf(16 MHz)
2097 // 01: dtmb_sram_dump_clk144_buf(128 MHz)
2098 // 10: dtmb_sram_dump_clk216_buf(192 MHz)
2099 // 11: dtmb_sram_dump_dmplldiv5_buf(153.6 MHz)
2100 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h38, 2'b11, 16'h1cc1);
2101 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h38, 2'b11, 16'h1cc1);
2102 _HAL_DMD_RIU_WriteByte(0x111f71, 0x1C);
2103 _HAL_DMD_RIU_WriteByte(0x111f70, 0xC1);
2104 // [4:0] : reg_ckg_dtmb_inner4x_sr1x => symbol rate FFT 1x
2105 // ^^^^^^^^^^^^^^^^^^
2106 // [0] : disable clock
2107 // [1] : invert clock
2108 // [4:2]: Select clock source
2109 // 000: adc_clk_buf
2110 // 001: clk_atsc25_p
2111 // ^^^^^^^^^^^^
2112 // if(reg_atsc_adc_sel_mplldiv2) => clk_dmplldiv2_div7_div2(24.85 MHz)
2113 // else => clk_dmplldiv17_div2(25.41 MHz)
2114 // 010: clk_atsc_eq25_p
2115 // ^^^^^^^^^^^^^^^
2116 // case({reg_eq25_sel_mplldiv3,reg_atsc_eq_sel_mplldiv2})
2117 // 2'b00: clk_dmplldiv5_inv_div8 (21.6 MHz)
2118 // 2'b01: clk_dmplldiv2_div2_inv_div8 (21.75 MHz)
2119 // 2'b10: clk_dmplldiv3_div16 (18 MHz)
2120 // 2'b11: 1'b0
2121 // endcase
2122 // 011: dtmb_clk72_buf(72 MHz)
2123 // 100: dtmb_clk18_buf(18 MHz)
2124 // 101: 1'b0
2125 // 110: 1'b0
2126 // 111: 1'b0
2127 // [12:8] : reg_ckg_dtmb_inner2x_sr0p5x => symbol rate FFT 0.5x
2128 // ^^^^^^^^^^^^^^^^^^^^
2129 // [0] : disable clock
2130 // [1] : invert clock
2131 // [4:2]: Select clock source
2132 // 000: clk_adc_div2_buf
2133 // 001: clk_frontend_d2_p0
2134 // ^^^^^^^^^^^^^^^^^^
2135 // if(reg_atsc_adc_sel_mplldiv2) => clk_dmplldiv2_div7_div4(12.43 MHz)
2136 // else => clk_dmplldiv17_div4(12.705 MHz)
2137 // 010: clk_atsc_eq25_div2_p
2138 // ^^^^^^^^^^^^^^^^^^^^
2139 // case({reg_eq25_sel_mplldiv3,reg_atsc_eq_sel_mplldiv2})
2140 // 2'b00: clk_dmplldiv5_inv_div8_div2 (10.8 MHz)
2141 // 2'b01: clk_dmplldiv2_div2_inv_div8_div2 (10.875 MHz)
2142 // 2'b10: clk_dmplldiv3_div32 (9 MHz)
2143 // 2'b11: 1'b0
2144 // endcase
2145 // 011: dtmb_clk36_buf(36 MHz)
2146 // 100: dtmb_clk9_buf(9 MHz)
2147 // 101: 1'b0
2148 // 110: 1'b0
2149 // 111: 1'b0
2150 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h3b, 2'b11, 16'h0404);
2151 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h3b, 2'b11, 16'h0404);
2152 _HAL_DMD_RIU_WriteByte(0x111f77, 0x04);
2153 _HAL_DMD_RIU_WriteByte(0x111f76, 0x04);
2154
2155 // Muji
2156 // [1:0] : reg_ckg_isdbt_outer1x_dvbt_outer1x
2157 // [0] : disable clock
2158 // [1] : invert clock
2159 // [3:2]: Select clock source
2160 // vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
2161 // sel[0]= (reg_demod_isdbt_on & reg_ckg_isdbt_outer1x[2])
2162 // sel[1]= (~reg_demod_isdbt_on)
2163 // ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
2164 // 00: isdbt_clk6_lat(6 MHz)
2165 // 01: isdbt_clk8_lat(8 MHz)
2166 // 10: clk_dmplldiv10_div2(43.2 MHz)
2167 // 11: 1'b0
2168 // [6:4] : reg_ckg_miu_dvbtc_outer2x
2169 // [0] : disable clock
2170 // [1] : invert clock
2171 // [2] : Select clock source
2172 // 0: clk_miu_p
2173 // 1: clk_dmplldiv10(86.4 MHz)
2174 // [12:8] : reg_ckg_dvbtc_rs
2175 // [0] : disable clock
2176 // [1] : invert clock
2177 // [4:2]: Select clock source
2178 // 000: clk_dmplldiv10(86.4 MHz)
2179 // 001: clk_dmplldiv10_div2(43.2 MHz)
2180 // 010: clk_atsc50_p
2181 // ^^^^^^^^^^^^
2182 // if(reg_atsc_adc_sel_mplldiv2) => clk_dmplldiv2_div7(49.7 MHz)
2183 // else => clk_dmplldiv17(50.82 MHz)
2184 // 011: clk_dvbtc_rs_216_buf(216 MHz)
2185 // 100: clk_dvbtc_rs_172_buf(172 MHz)
2186 // 101: clk_dvbtc_rs_144_buf(144 MHz)
2187 // 110: 1'b0
2188 // 111: 1'b0
2189 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h27, 2'b10, 16'h0800);
2190 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h27, 2'b10, 16'h0800);
2191 _HAL_DMD_RIU_WriteByte(0x111f4f, 0x08);
2192
2193 // ================================================================
2194 // ISDBT SRAM pool clock enable
2195 // ================================================================
2196 // [3:0] : reg_ckg_share_dtmb_inner12x_isdbt_inner2x
2197 // [0] : disable clock
2198 // [1] : invert clock
2199 // [3:2] : 0 : clk_dmplldiv10_div2 \_________________> clk_isdbt_inner2x_dvbt_inner2x, *sel[0] = (reg_demod_isdbt_on) | TEST_CLK_EN
2200 // 1 : clk_isdbt_inner2x_p /
2201 // 2 : clk_dtmb_inner12x_4x_dvbtc_rs_mux --------> clk_dtmb_inner12x_4x_dvbtc_rs
2202 // 3 : 1'b0
2203 // [7:4] : reg_ckg_share_dtmb_inner8x_rs_isdbt_inner2x
2204 // [0] : disable clock
2205 // [1] : invert clock
2206 // [3:2] : 0 : clk_dmplldiv10_div2 \_________________> clk_isdbt_inner2x_dvbt_inner2x, *sel[0] = (reg_demod_isdbt_on) | TEST_CLK_EN
2207 // : 1 : clk_isdbt_inner2x_p /
2208 // : 2 : dtmb_clk144_buf \_________________> clk_dtmb_inner8x_dvbtc_rs, *sel[0] = reg_ckg_dtmb_inner8x_dvbtc_rs[2] | TEST_CLK_EN
2209 // : 3 : clk_dvbtc_rs_mux /
2210 // [11:8] : reg_ckg_share_dtmb_inner8x_isdbt_inner2x
2211 // [0] : disable clock
2212 // [1] : invert clock
2213 // [3:2] : 0 : clk_dmplldiv10_div2 \_________________> clk_isdbt_inner2x_dvbt_inner2x, *sel[0] = (reg_demod_isdbt_on) | TEST_CLK_EN
2214 // : 1 : clk_isdbt_inner2x_p /
2215 // : 2 : dtmb_clk144_buf ------------------> clk_dtmb_inner8x
2216 // : 3 : 1'b0
2217 // [15:12] : reg_ckg_share_dtmb_outer2x_isdbt_inner2x
2218 // [0] : disable clock
2219 // [1] : invert clock
2220 // [3:2] : 0 : clk_dmplldiv10_div2 \_________________> clk_isdbt_inner2x_dvbt_inner2x, *sel[0] = (reg_demod_isdbt_on) | TEST_CLK_EN
2221 // : 1 : clk_isdbt_inner2x_p /
2222 // : 2 : dtmb_eq_clk36_buf ------------------> clk_dtmb_outer2x
2223 // : 3 : 1'b0
2224 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h40, 2'b11, 16'h0000);
2225 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h40, 2'b11, 16'h0000);
2226 _HAL_DMD_RIU_WriteByte(0x111f81, 0x00);
2227 _HAL_DMD_RIU_WriteByte(0x111f80, 0x00);
2228
2229
2230 // [3:0] : reg_ckg_share_dtmb_inner2x_isdbt_inner2x
2231 // [0] : disable clock
2232 // [1] : invert clock
2233 // [3:2] : 0 : clk_dmplldiv10_div2 \_________________> clk_isdbt_inner2x_dvbt_inner2x, *sel[0] = (reg_demod_isdbt_on) | TEST_CLK_EN
2234 // : 1 : clk_isdbt_inner2x_p /
2235 // : 2 : dtmb_clk36_buf ------------------> clk_dtmb_inner2x
2236 // : 3 : 1'b0
2237 // [7:4] : reg_ckg_share_dtmb_inner12x_isdbt_inner4x
2238 // [0] : disable clock
2239 // [1] : invert clock
2240 // [3:2] : 0 : clk_dvbtc_sram4_p \_________________> clk_dvbtc_sram4_isdbt_inner4x, *sel[0] = reg_demod_isdbt_on | TEST_CLK_EN;
2241 // : 1 : clk_isdbt_inner4x_p /
2242 // : 2 : clk_dtmb_inner12x_4x_dvbtc_rs_mux --------> clk_dtmb_inner12x_4x_dvbtc_rs,
2243 // : 3 : 1'b0
2244 // [11:8] : reg_ckg_share_dtmb_eq2x_isdbt_outer6x
2245 // [0] : disable clock
2246 // [1] : invert clock
2247 // [3:2] : 0 : isdbt_clk36_lat \_________________> clk_isdbt_outer6x, *sel[0] = reg_ckg_isdbt_outer6x[2] | TEST_CLK_EN
2248 // : 1 : isdbt_clk48_lat /
2249 // : 2 : clk_dtmb_eq2x_inner12x_mux ---------------> clk_dtmb_eq2x_inner12x
2250 // : 3 : 1'b0
2251 // [15:12] : reg_ckg_share_dtmb_eq0p5x_isdbt_sram0
2252 // [0] : disable clock
2253 // [1] : invert clock
2254 // [3:2] : 0 : clk_dvbtc_sram0_p \_________________> clk_sram0, *sel[0] = reg_demod_isdbt_on | TEST_CLK_EN
2255 // : 1 : clk_isdbt_inner4x_p /
2256 // : 2 : dtmb_eq_clk72_buf \_________________> clk_dtmb_eq0p5x_inner4x *sel[0] = reg_ckg_dtmb_eq0p5x_inner4x[2] | extmd
2257 // : 3 : dtmb_clk72_buf /
2258 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h41, 2'b11, 16'h0000);
2259 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h41, 2'b11, 16'h0000);
2260 _HAL_DMD_RIU_WriteByte(0x111f83, 0x00);
2261 _HAL_DMD_RIU_WriteByte(0x111f82, 0x00);
2262
2263
2264 // [3:0] : reg_ckg_share_dtmb_eq2x_isdbt_sram1
2265 // [0] : disable clock
2266 // [1] : invert clock
2267 // [3:2] : 0 : clk_dvbtc_sram1_p \_________________> clk_sram1, *sel[0] = reg_demod_isdbt_on | TEST_CLK_EN
2268 // : 1 : clk_isdbt_inner4x_p /
2269 // : 2 : clk_dtmb_eq2x_inner2x_12x_mux ------------> clk_dtmb_eq2x_inner2x_12x
2270 // : 3 : 1'b0
2271 // [7:4] : reg_ckg_share_dtmb_inner6x_isdbt_sram3
2272 // [0] : disable clock
2273 // [1] : invert clock
2274 // [3:2] : 0 : clk_dvbtc_sram3_p \_________________> clk_sram3, *sel[0] = ((~reg_fed_srd_on) & reg_demod_isdbt_on) | TEST_CLK_EN
2275 // : 1 : clk_isdbt_inner2x_p /
2276 // : 2 : dtmb_clk108_buf ------------------> clk_dtmb_inner6x
2277 // : 3 : 1'b0
2278 // [11:8] : reg_ckg_share_dtmb_eq2x_isdbt_sram3
2279 // [0] : disable clock
2280 // [1] : invert clock
2281 // [3:2] : 0 : clk_dvbtc_sram3_p \_________________> clk_sram3, *sel[0] = ((~reg_fed_srd_on) & reg_demod_isdbt_on) | TEST_CLK_EN
2282 // : 1 : clk_isdbt_inner2x_p /
2283 // : 2 : clk_dtmb_eq2x_inner12x_mux ---------------> clk_dtmb_eq2x_inner12x
2284 // : 3 : 1'b0
2285 // [15:12] : reg_ckg_share_dtmb_inner12x_isdbt_sram4
2286 // [0] : disable clock
2287 // [1] : invert clock
2288 // [3:2] : 0 : clk_dvbtc_sram4_p \_________________> clk_sram4, *sel[0] = ((~reg_fed_srd_on) & reg_demod_isdbt_on) | TEST_CLK_EN
2289 // : 1 : clk_isdbt_inner2x_p /
2290 // : 2 : dtmb_clk216_buf ------------------> clk_dtmb_inner12x
2291 // : 3 : 1'b0
2292 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h42, 2'b11, 16'h0000);
2293 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h42, 2'b11, 16'h0000);
2294 _HAL_DMD_RIU_WriteByte(0x111f85, 0x00);
2295 _HAL_DMD_RIU_WriteByte(0x111f84, 0x00);
2296
2297
2298 // [3:0] : reg_ckg_share_dtmb_inner12x_eq0p5x_isdbt_sram4
2299 // [0] : disable clock
2300 // [1] : invert clock
2301 // [3:2] : 0 : clk_dvbtc_sram4_p \_________________> clk_sram4, *sel[0] = ((~reg_fed_srd_on) & reg_demod_isdbt_on) | TEST_CLK_EN
2302 // : 1 : clk_isdbt_inner2x_p /
2303 // : 2 : dtmb_clk216_buf \_________________> clk_dtmb_inner12x_eq0p5x, *sel[0] = reg_ckg_dtmb_inner12x_eq0p5x[2] | extmd
2304 // : 3 : dtmb_eq_clk72_buf /
2305 // [7:4] : reg_ckg_share_dtmb_eq0p25x_isdbt_sram4
2306 // [0] : disable clock
2307 // [1] : invert clock
2308 // [3:2] : 0 : clk_dvbtc_sram4_p \_________________> clk_sram4, *sel[0] = ((~reg_fed_srd_on) & reg_demod_isdbt_on) | TEST_CLK_EN
2309 // : 1 : clk_isdbt_inner2x_p /
2310 // : 2 : dtmb_eq_clk36_buf ------------------> clk_dtmb_eq0p25x
2311 // : 3 : 1'b0
2312 // [11:8] : reg_ckg_share_dtmb_inner2x_isdbt_sram4
2313 // [0] : disable clock
2314 // [1] : invert clock
2315 // [3:2] : 0 : clk_dvbtc_sram4_p \_________________> clk_sram4, *sel[0] = ((~reg_fed_srd_on) & reg_demod_isdbt_on) | TEST_CLK_EN
2316 // : 1 : clk_isdbt_inner2x_p /
2317 // : 2 : dtmb_clk36_buf \_________________> clk_dtmb_inner2x_dvbtc_rs, *sel[0] = reg_ckg_dtmb_inner2x_dvbtc_rs[2] | TEST_CLK_EN
2318 // : 3 : clk_dvbtc_rs_mux /
2319 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h43, 2'b11, 16'h0000);
2320 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h43, 2'b11, 16'h0000);
2321 _HAL_DMD_RIU_WriteByte(0x111f87, 0x00);
2322 _HAL_DMD_RIU_WriteByte(0x111f86, 0x00);
2323
2324 u8Val = _HAL_DMD_RIU_ReadByte(0x101e39);
2325 _HAL_DMD_RIU_WriteByte(0x101e39, u8Val|0x03);
2326 }
2327 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_WHISKY)
_HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)2328 void _HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)
2329 {
2330 MS_U8 u8Val=0x00;
2331
2332 printf("--------------DMD_ATSC_CHIP_WHISKY--------------\n");
2333
2334 u8Val = _HAL_DMD_RIU_ReadByte(0x101e39);
2335 _HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
2336
2337 // DMDMCU 108M
2338 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
2339 // Set parallel TS clock
2340 _HAL_DMD_RIU_WriteByte(0x103301, 0x05);
2341 _HAL_DMD_RIU_WriteByte(0x103300, 0x11);
2342 // Enable ATSC, DVBTC TS clock
2343 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
2344 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
2345 // Enable ADC clock in clkgen_demod
2346 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
2347 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
2348 // Reset TS divider
2349 _HAL_DMD_RIU_WriteByte(0x103302, 0x01);
2350 _HAL_DMD_RIU_WriteByte(0x103302, 0x00);
2351 // ADC select MPLLDIV17 & EQ select MPLLDIV5
2352 _HAL_DMD_RIU_WriteByte(0x111f43, 0x00);
2353 _HAL_DMD_RIU_WriteByte(0x111f42, 0x00);
2354 // Enable ATSC clock
2355 _HAL_DMD_RIU_WriteByte(0x111f03, 0x00);
2356 _HAL_DMD_RIU_WriteByte(0x111f02, 0x00);
2357 // configure reg_ckg_atsc50, reg_ckg_atsc25, reg_ckg_atsc_eq25 and reg_ckg_atsc_ce25
2358 _HAL_DMD_RIU_WriteByte(0x111f04, 0x00);
2359 _HAL_DMD_RIU_WriteByte(0x111f07, 0x00);
2360 _HAL_DMD_RIU_WriteByte(0x111f06, 0x00);
2361 // enable clk_atsc_adcd_sync
2362 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
2363 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x08);
2364 // Enable DVBC outer clock
2365 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
2366 // Enable SRAM clock
2367 _HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
2368 _HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
2369 // select clock
2370 _HAL_DMD_RIU_WriteByte(0x111f23, 0x00);
2371 _HAL_DMD_RIU_WriteByte(0x111f22, 0x00);
2372 // enable CCI LMS clock
2373 _HAL_DMD_RIU_WriteByte(0x111f71, 0x00);
2374 _HAL_DMD_RIU_WriteByte(0x111f70, 0x00);
2375 // set symbol rate
2376 _HAL_DMD_RIU_WriteByte(0x111f77, 0x04);
2377 _HAL_DMD_RIU_WriteByte(0x111f76, 0x04);
2378 // reg_ckg_adc1x_eq1x
2379 _HAL_DMD_RIU_WriteByte(0x111f49, 0x04);
2380
2381 u8Val = _HAL_DMD_RIU_ReadByte(0x101e39);
2382 _HAL_DMD_RIU_WriteByte(0x101e39,(u8Val| 0x03));
2383 }
2384 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MASERATI || DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MACAN)
_HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)2385 static void _HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)
2386 {
2387 MS_U8 u8Val = 0;
2388
2389 #if DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MASERATI
2390 printf("--------------DMD_ATSC_CHIP_MASERATI--------------\n");
2391 #else
2392 printf("--------------DMD_ATSC_CHIP_MACAN--------------\n");
2393 #endif
2394
2395 u8Val = _HAL_DMD_RIU_ReadByte(0x101e39);
2396 _HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
2397
2398 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
2399
2400 _HAL_DMD_RIU_WriteByte(0x103301, 0x05);
2401 _HAL_DMD_RIU_WriteByte(0x103300, 0x11);
2402
2403 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
2404 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
2405
2406 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
2407 _HAL_DMD_RIU_WriteByte(0x103314, 0x08);
2408
2409 _HAL_DMD_RIU_WriteByte(0x103302, 0x01);
2410 _HAL_DMD_RIU_WriteByte(0x103302, 0x00);
2411
2412 _HAL_DMD_RIU_WriteByte(0x152928, 0x00);
2413
2414 _HAL_DMD_RIU_WriteByte(0x152903, 0x00);
2415 _HAL_DMD_RIU_WriteByte(0x152902, 0x00);
2416
2417 _HAL_DMD_RIU_WriteByte(0x152905, 0x00);
2418 _HAL_DMD_RIU_WriteByte(0x152904, 0x00);
2419
2420 _HAL_DMD_RIU_WriteByte(0x152907, 0x00);
2421 _HAL_DMD_RIU_WriteByte(0x152906, 0x00);
2422
2423 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
2424 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x08);
2425
2426 _HAL_DMD_RIU_WriteByte(0x111f21, 0x44);
2427 _HAL_DMD_RIU_WriteByte(0x111f20, 0x40);
2428
2429 _HAL_DMD_RIU_WriteByte(0x111f23, 0x10);
2430 _HAL_DMD_RIU_WriteByte(0x111f22, 0x44);
2431
2432 _HAL_DMD_RIU_WriteByte(0x111f3b, 0x08);
2433 _HAL_DMD_RIU_WriteByte(0x111f3a, 0x08);
2434
2435 _HAL_DMD_RIU_WriteByte(0x111f71, 0x00);
2436 _HAL_DMD_RIU_WriteByte(0x111f70, 0x00);
2437
2438 _HAL_DMD_RIU_WriteByte(0x111f73, 0x00);
2439 _HAL_DMD_RIU_WriteByte(0x111f72, 0x00);
2440
2441 _HAL_DMD_RIU_WriteByte(0x111f79, 0x11);
2442 _HAL_DMD_RIU_WriteByte(0x111f78, 0x18);
2443
2444 _HAL_DMD_RIU_WriteByte(0x152991, 0x88);
2445 _HAL_DMD_RIU_WriteByte(0x152990, 0x88);
2446
2447 _HAL_DMD_RIU_WriteByte(0x111f69, 0x44);
2448 _HAL_DMD_RIU_WriteByte(0x111f68, 0x00);
2449
2450 _HAL_DMD_RIU_WriteByte(0x111f75, 0x81);
2451 _HAL_DMD_RIU_WriteByte(0x111f74, 0x11);
2452
2453 _HAL_DMD_RIU_WriteByte(0x111f77, 0x81);
2454 _HAL_DMD_RIU_WriteByte(0x111f76, 0x88);
2455
2456 _HAL_DMD_RIU_WriteByte(0x15298f, 0x11);
2457 _HAL_DMD_RIU_WriteByte(0x15298e, 0x88);
2458
2459 _HAL_DMD_RIU_WriteByte(0x152923, 0x00);
2460 _HAL_DMD_RIU_WriteByte(0x152922, 0x00);
2461
2462 _HAL_DMD_RIU_WriteByte(0x111f25, 0x10);
2463 _HAL_DMD_RIU_WriteByte(0x111f24, 0x11);
2464
2465 _HAL_DMD_RIU_WriteByte(0x152971, 0x1c);
2466 _HAL_DMD_RIU_WriteByte(0x152970, 0xc1);
2467
2468 _HAL_DMD_RIU_WriteByte(0x152977, 0x04);
2469 _HAL_DMD_RIU_WriteByte(0x152976, 0x04);
2470
2471 _HAL_DMD_RIU_WriteByte(0x111f6f, 0x11);
2472 _HAL_DMD_RIU_WriteByte(0x111f6e, 0x00);
2473
2474 _HAL_DMD_RIU_WriteByte(0x111feb, 0x18);
2475
2476 _HAL_DMD_RIU_WriteByte(0x111f7f, 0x10);
2477 _HAL_DMD_RIU_WriteByte(0x111f7e, 0x11);
2478
2479 _HAL_DMD_RIU_WriteByte(0x111f31, 0x14);
2480
2481 _HAL_DMD_RIU_WriteByte(0x152981, 0x00);
2482 _HAL_DMD_RIU_WriteByte(0x152980, 0x00);
2483
2484 _HAL_DMD_RIU_WriteByte(0x152983, 0x00);
2485 _HAL_DMD_RIU_WriteByte(0x152982, 0x00);
2486
2487 _HAL_DMD_RIU_WriteByte(0x152985, 0x00);
2488 _HAL_DMD_RIU_WriteByte(0x152984, 0x00);
2489
2490 _HAL_DMD_RIU_WriteByte(0x152987, 0x00);
2491 _HAL_DMD_RIU_WriteByte(0x152986, 0x00);
2492
2493 _HAL_DMD_RIU_WriteByte(0x152979, 0x11);
2494 _HAL_DMD_RIU_WriteByte(0x152978, 0x14);
2495
2496 _HAL_DMD_RIU_WriteByte(0x15298d, 0x81);
2497 _HAL_DMD_RIU_WriteByte(0x15298c, 0x44);
2498
2499 u8Val = _HAL_DMD_RIU_ReadByte(0x101e39);
2500 _HAL_DMD_RIU_WriteByte(0x101e39, u8Val|0x03);
2501 }
2502 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MUSTANG )
_HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)2503 static void _HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)
2504 {
2505 MS_U8 u8Val = 0;
2506
2507 printf("--------------DMD_ATSC_CHIP_MUSTANG--------------\n");
2508
2509 u8Val = _HAL_DMD_RIU_ReadByte(0x101e39);
2510 _HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
2511
2512
2513 _HAL_DMD_RIU_WriteByte(0x101e39,0x00);
2514 // SRAM End Address
2515 _HAL_DMD_RIU_WriteByte(0x111707,0xff);
2516 _HAL_DMD_RIU_WriteByte(0x111706,0xff);
2517
2518 // DRAM Disable
2519 _HAL_DMD_RIU_WriteByte(0x111718,_HAL_DMD_RIU_ReadByte(0x111718)&(~0x04));
2520 _HAL_DMD_RIU_WriteByte(0x10331e,0x10);
2521
2522
2523 _HAL_DMD_RIU_WriteByte(0x103301,0x05);
2524 _HAL_DMD_RIU_WriteByte(0x103300,0x11);
2525
2526
2527 _HAL_DMD_RIU_WriteByte(0x103309,0x00);
2528 _HAL_DMD_RIU_WriteByte(0x103308,0x00);
2529
2530
2531 _HAL_DMD_RIU_WriteByte(0x103315,0x00);
2532 _HAL_DMD_RIU_WriteByte(0x103314,0x08);
2533
2534 _HAL_DMD_RIU_WriteByte(0x103302,0x01);
2535 _HAL_DMD_RIU_WriteByte(0x103302,0x00);
2536
2537
2538 _HAL_DMD_RIU_WriteByte(0x152928,0x00);
2539
2540
2541 _HAL_DMD_RIU_WriteByte(0x152903,0x00);
2542 _HAL_DMD_RIU_WriteByte(0x152902,0x00);
2543
2544 _HAL_DMD_RIU_WriteByte(0x152905,0x00);
2545 _HAL_DMD_RIU_WriteByte(0x152904,0x00);
2546
2547 _HAL_DMD_RIU_WriteByte(0x152907,0x00);
2548 _HAL_DMD_RIU_WriteByte(0x152906,0x00);
2549
2550 _HAL_DMD_RIU_WriteByte(0x111f0b,0x00);
2551 _HAL_DMD_RIU_WriteByte(0x111f0a,0x08);
2552
2553 _HAL_DMD_RIU_WriteByte(0x111f21,0x44);
2554 _HAL_DMD_RIU_WriteByte(0x111f20,0x40);
2555
2556
2557 _HAL_DMD_RIU_WriteByte(0x111f23,0x10);
2558 _HAL_DMD_RIU_WriteByte(0x111f22,0x44);
2559
2560 _HAL_DMD_RIU_WriteByte(0x111f3b,0x08);
2561 _HAL_DMD_RIU_WriteByte(0x111f3a,0x08);
2562
2563 _HAL_DMD_RIU_WriteByte(0x111f71,0x00);
2564 _HAL_DMD_RIU_WriteByte(0x111f70,0x00);
2565 _HAL_DMD_RIU_WriteByte(0x111f73,0x00);
2566 _HAL_DMD_RIU_WriteByte(0x111f72,0x00);
2567
2568 _HAL_DMD_RIU_WriteByte(0x111f79,0x11);
2569 _HAL_DMD_RIU_WriteByte(0x111f78,0x18);
2570
2571 _HAL_DMD_RIU_WriteByte(0x152991,0x88);
2572 _HAL_DMD_RIU_WriteByte(0x152990,0x88);
2573
2574
2575 _HAL_DMD_RIU_WriteByte(0x111f69,0x44);
2576 _HAL_DMD_RIU_WriteByte(0x111f68,0x00);
2577
2578 _HAL_DMD_RIU_WriteByte(0x111f75,0x81);
2579 _HAL_DMD_RIU_WriteByte(0x111f74,0x11);
2580
2581
2582 _HAL_DMD_RIU_WriteByte(0x111f77,0x81);
2583 _HAL_DMD_RIU_WriteByte(0x111f76,0x88);
2584
2585
2586 _HAL_DMD_RIU_WriteByte(0x15298f,0x11);
2587 _HAL_DMD_RIU_WriteByte(0x15298e,0x88);
2588
2589 _HAL_DMD_RIU_WriteByte(0x152923,0x00);
2590 _HAL_DMD_RIU_WriteByte(0x152922,0x00);
2591
2592 _HAL_DMD_RIU_WriteByte(0x111f25,0x10);
2593 _HAL_DMD_RIU_WriteByte(0x111f24,0x11);
2594
2595 _HAL_DMD_RIU_WriteByte(0x152971,0x1c);
2596 _HAL_DMD_RIU_WriteByte(0x152970,0xc1);
2597
2598
2599 _HAL_DMD_RIU_WriteByte(0x152977,0x04);
2600 _HAL_DMD_RIU_WriteByte(0x152976,0x04);
2601
2602
2603 _HAL_DMD_RIU_WriteByte(0x111f6f,0x11);
2604 _HAL_DMD_RIU_WriteByte(0x111f6e,0x00);
2605
2606 _HAL_DMD_RIU_WriteByte(0x111feb,0x18);
2607 _HAL_DMD_RIU_WriteByte(0x111f7f,0x10);
2608 _HAL_DMD_RIU_WriteByte(0x111f7e,0x11);
2609 _HAL_DMD_RIU_WriteByte(0x111f31,0x14);
2610
2611
2612 _HAL_DMD_RIU_WriteByte(0x152981,0x00);
2613 _HAL_DMD_RIU_WriteByte(0x152980,0x00);
2614
2615
2616
2617 _HAL_DMD_RIU_WriteByte(0x152983,0x00);
2618 _HAL_DMD_RIU_WriteByte(0x152982,0x00);
2619
2620
2621
2622 _HAL_DMD_RIU_WriteByte(0x152985,0x00);
2623 _HAL_DMD_RIU_WriteByte(0x152984,0x00);
2624
2625
2626 _HAL_DMD_RIU_WriteByte(0x152987,0x00);
2627 _HAL_DMD_RIU_WriteByte(0x152986,0x00);
2628
2629 _HAL_DMD_RIU_WriteByte(0x152979,0x11);
2630 _HAL_DMD_RIU_WriteByte(0x152978,0x14);
2631
2632
2633 _HAL_DMD_RIU_WriteByte(0x15298d,0x81);
2634 _HAL_DMD_RIU_WriteByte(0x15298c,0x44);
2635 _HAL_DMD_RIU_WriteByte(0x112830,0x01);
2636 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
2637 }
2638 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MAXIM )
_HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)2639 static void _HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)
2640 {
2641 MS_U8 u8Val = 0;
2642
2643 printf("--------------DMD_ATSC_CHIP_MAXIM--------------\n");
2644
2645 u8Val = _HAL_DMD_RIU_ReadByte(0x101e39);
2646 _HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
2647
2648 _HAL_DMD_RIU_WriteByte(0x10331e,0x10);
2649
2650 _HAL_DMD_RIU_WriteByte(0x103301,0x05);
2651 _HAL_DMD_RIU_WriteByte(0x103300,0x11);
2652
2653
2654 _HAL_DMD_RIU_WriteByte(0x103309,0x00);
2655 _HAL_DMD_RIU_WriteByte(0x103308,0x00);
2656
2657 _HAL_DMD_RIU_WriteByte(0x103315,0x00);
2658 _HAL_DMD_RIU_WriteByte(0x103314,0x08);
2659
2660
2661 _HAL_DMD_RIU_WriteByte(0x103302,0x01);
2662
2663 _HAL_DMD_RIU_WriteByte(0x103302,0x00);
2664
2665
2666 _HAL_DMD_RIU_WriteByte(0x103321,0x00);
2667 _HAL_DMD_RIU_WriteByte(0x103320,0x08);
2668
2669
2670 _HAL_DMD_RIU_WriteByte(0x152928,0x00);
2671
2672
2673 _HAL_DMD_RIU_WriteByte(0x152903,0x00);
2674 _HAL_DMD_RIU_WriteByte(0x152902,0x00);
2675
2676
2677 _HAL_DMD_RIU_WriteByte(0x152905,0x00);
2678 _HAL_DMD_RIU_WriteByte(0x152904,0x00);
2679
2680
2681 _HAL_DMD_RIU_WriteByte(0x152907,0x00);
2682 _HAL_DMD_RIU_WriteByte(0x152906,0x00);
2683
2684
2685 _HAL_DMD_RIU_WriteByte(0x111f0b,0x00);
2686 _HAL_DMD_RIU_WriteByte(0x111f0a,0x08);
2687
2688
2689 _HAL_DMD_RIU_WriteByte(0x111f21,0x44);
2690 _HAL_DMD_RIU_WriteByte(0x111f20,0x40);
2691
2692
2693 _HAL_DMD_RIU_WriteByte(0x111f23,0x10);
2694 _HAL_DMD_RIU_WriteByte(0x111f22,0x44);
2695
2696 _HAL_DMD_RIU_WriteByte(0x111f3b,0x08);
2697 _HAL_DMD_RIU_WriteByte(0x111f3a,0x08);
2698
2699 _HAL_DMD_RIU_WriteByte(0x111f71,0x00);
2700 _HAL_DMD_RIU_WriteByte(0x111f70,0x00);
2701 _HAL_DMD_RIU_WriteByte(0x111f73,0x00);
2702 _HAL_DMD_RIU_WriteByte(0x111f72,0x00);
2703
2704 _HAL_DMD_RIU_WriteByte(0x111f79,0x11);
2705 _HAL_DMD_RIU_WriteByte(0x111f78,0x18);
2706
2707 _HAL_DMD_RIU_WriteByte(0x152991,0x88);
2708 _HAL_DMD_RIU_WriteByte(0x152990,0x88);
2709
2710 _HAL_DMD_RIU_WriteByte(0x111f69,0x44);
2711 _HAL_DMD_RIU_WriteByte(0x111f68,0x00);
2712
2713 _HAL_DMD_RIU_WriteByte(0x111f75,0x81);
2714 _HAL_DMD_RIU_WriteByte(0x111f74,0x11);
2715
2716 _HAL_DMD_RIU_WriteByte(0x111f77,0x81);
2717 _HAL_DMD_RIU_WriteByte(0x111f76,0x88);
2718
2719 _HAL_DMD_RIU_WriteByte(0x15298f,0x11);
2720 _HAL_DMD_RIU_WriteByte(0x15298e,0x88);
2721
2722 _HAL_DMD_RIU_WriteByte(0x152923,0x00);
2723 _HAL_DMD_RIU_WriteByte(0x152922,0x00);
2724
2725 _HAL_DMD_RIU_WriteByte(0x111f25,0x10);
2726 _HAL_DMD_RIU_WriteByte(0x111f24,0x11);
2727
2728 _HAL_DMD_RIU_WriteByte(0x152971,0x1c);
2729 _HAL_DMD_RIU_WriteByte(0x152970,0xc1);
2730
2731
2732 _HAL_DMD_RIU_WriteByte(0x152977,0x04);
2733 _HAL_DMD_RIU_WriteByte(0x152976,0x04);
2734
2735
2736 _HAL_DMD_RIU_WriteByte(0x111f6f,0x11);
2737 _HAL_DMD_RIU_WriteByte(0x111f6e,0x00);
2738
2739 _HAL_DMD_RIU_WriteByte(0x111feb,0x18);
2740
2741 _HAL_DMD_RIU_WriteByte(0x111f7f,0x10);
2742 _HAL_DMD_RIU_WriteByte(0x111f7e,0x11);
2743
2744 _HAL_DMD_RIU_WriteByte(0x111f31,0x14);
2745
2746 _HAL_DMD_RIU_WriteByte(0x152981,0x00);
2747 _HAL_DMD_RIU_WriteByte(0x152980,0x00);
2748
2749
2750 _HAL_DMD_RIU_WriteByte(0x152983,0x00);
2751 _HAL_DMD_RIU_WriteByte(0x152982,0x00);
2752
2753
2754 _HAL_DMD_RIU_WriteByte(0x152985,0x00);
2755 _HAL_DMD_RIU_WriteByte(0x152984,0x00);
2756
2757
2758
2759 _HAL_DMD_RIU_WriteByte(0x152987,0x00);
2760 _HAL_DMD_RIU_WriteByte(0x152986,0x00);
2761
2762 _HAL_DMD_RIU_WriteByte(0x152979,0x11);
2763 _HAL_DMD_RIU_WriteByte(0x152978,0x14);
2764
2765 _HAL_DMD_RIU_WriteByte(0x15298d,0x81);
2766 _HAL_DMD_RIU_WriteByte(0x15298c,0x44);
2767
2768 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
2769 }
2770
2771 #else
_HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)2772 static void _HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)
2773 {
2774 printf("--------------DMD_ATSC_CHIP_NONE--------------\n");
2775 }
2776 #endif
2777
_HAL_INTERN_ATSC_Download(void)2778 static MS_BOOL _HAL_INTERN_ATSC_Download(void)
2779 {
2780 DMD_ATSC_ResData *pRes = psDMD_ATSC_ResData + u8DMD_ATSC_DMD_ID;
2781
2782 MS_U8 udata = 0x00;
2783 MS_U16 i=0;
2784 MS_U16 fail_cnt=0;
2785 #if (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_K3)
2786 MS_U8 u8TmpData;
2787 MS_U16 u16AddressOffset;
2788 #endif
2789
2790 #if (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_T3_T10)
2791 if (_HAL_DMD_RIU_ReadByte(0x101E3E) != 0x08) HAL_PWS_Stop_VDMCU();
2792 else
2793 {
2794 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x01); // reset VD_MCU
2795 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x00);
2796 MsOS_DelayTask(20);
2797 return TRUE;
2798 }
2799 #else
2800 if (pRes->sDMD_ATSC_PriData.bDownloaded)
2801 {
2802 #if (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MUSTANG)
2803 udata=_HAL_DMD_RIU_ReadByte(DMDMcuBase+0x00);
2804 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, (udata|0x02)); // reset RIU remapping reset
2805 udata=_HAL_DMD_RIU_ReadByte(DMDMcuBase+0x00);
2806 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, (udata|0x01)); // reset VD_MCU
2807 #else
2808 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x01); // reset MCU, madison patch
2809 #endif
2810 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x00);
2811 MsOS_DelayTask(20);
2812 return TRUE;
2813 }
2814 #endif
2815
2816 #if (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MUSTANG)
2817 udata=_HAL_DMD_RIU_ReadByte(DMDMcuBase+0x00);
2818 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, (udata|0x02)); // reset RIU remapping reset
2819 udata=_HAL_DMD_RIU_ReadByte(DMDMcuBase+0x00);
2820 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, (udata|0x01)); // reset VD_MCU
2821 #else
2822 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x01); // reset MCU, madison patch
2823 #endif
2824 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x01, 0x00); // disable SRAM
2825 #if (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MUSTANG)
2826 udata=_HAL_DMD_RIU_ReadByte(DMDMcuBase+0x00);
2827 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, (udata&(~0x01))); // release MCU, madison patch
2828 #else
2829 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x00);// release MCU, madison patchs
2830 #endif
2831 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x50); // enable "vdmcu51_if"
2832 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x51); // enable auto-increase
2833 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x04, 0x00); // sram address low byte
2834 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x05, 0x00); // sram address high byte
2835
2836 //// Load code thru VDMCU_IF ////
2837 HAL_INTERN_ATSC_DBINFO(printf(">Load Code...\n"));
2838
2839 for (i = 0; i < u16Lib_size; i++)
2840 {
2841 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, INTERN_ATSC_table[i]); // write data to VD MCU 51 code sram
2842 }
2843
2844 //// Content verification ////
2845 HAL_INTERN_ATSC_DBINFO(printf(">Verify Code...\n"));
2846
2847 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x04, 0x00); // sram address low byte
2848 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x05, 0x00); // sram address high byte
2849
2850 for (i = 0; i < u16Lib_size; i++)
2851 {
2852 udata = _HAL_DMD_RIU_ReadByte(DMDMcuBase+0x10); // read sram data
2853
2854 if (udata != INTERN_ATSC_table[i])
2855 {
2856 HAL_INTERN_ATSC_DBINFO(printf(">fail add = 0x%x\n", i));
2857 HAL_INTERN_ATSC_DBINFO(printf(">code = 0x%x\n", INTERN_ATSC_table[i]));
2858 HAL_INTERN_ATSC_DBINFO(printf(">data = 0x%x\n", udata));
2859
2860 if (fail_cnt++ > 10)
2861 {
2862 HAL_INTERN_ATSC_DBINFO(printf(">DSP Loadcode fail!"));
2863 return FALSE;
2864 }
2865 }
2866 }
2867
2868 #if (DMD_ATSC_CHIP_VERSION < DMD_ATSC_CHIP_K3)
2869 #if (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_A1)
2870 _initTable();
2871 #endif
2872
2873 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x04, 0x80); // sram address low byte
2874 #if (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_T8_T9 || DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_A1)
2875 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x05, 0x6B); // sram address high byte
2876 #else
2877 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x05, 0x5B); // sram address high byte
2878 #endif
2879
2880 for (i = 0; i < sizeof(Demod_Flow_register); i++)
2881 {
2882 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, Demod_Flow_register[i]);
2883 }
2884 #else // #if (DMD_ATSC_CHIP_VERSION < DMD_ATSC_CHIP_K3)
2885 u16AddressOffset = (INTERN_ATSC_table[0x400] << 8)|INTERN_ATSC_table[0x401];
2886
2887 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x04, (u16AddressOffset&0xFF)); // sram address low byte
2888 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x05, (u16AddressOffset>>8)); // sram address high byte
2889
2890 u8TmpData = (MS_U8)pRes->sDMD_ATSC_InitData.u16IF_KHZ;
2891 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
2892 u8TmpData = (MS_U8)(pRes->sDMD_ATSC_InitData.u16IF_KHZ >> 8);
2893 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
2894 u8TmpData = (MS_U8)pRes->sDMD_ATSC_InitData.bIQSwap;
2895 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
2896 u8TmpData = (MS_U8)pRes->sDMD_ATSC_InitData.u16AGC_REFERENCE;
2897 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
2898 u8TmpData = (MS_U8)(pRes->sDMD_ATSC_InitData.u16AGC_REFERENCE >> 8);
2899 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
2900 u8TmpData = (MS_U8)pRes->sDMD_ATSC_InitData.u8IS_DUAL;
2901 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
2902 u8TmpData = (MS_U8)u8DMD_ATSC_DMD_ID;
2903 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
2904 #endif // #if (DMD_ATSC_CHIP_VERSION < DMD_ATSC_CHIP_K3)
2905
2906 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x50); // diable auto-increase
2907 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x00); // disable "vdmcu51_if"
2908
2909 #if (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MUSTANG)
2910 udata=_HAL_DMD_RIU_ReadByte(DMDMcuBase+0x00);
2911 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, (udata|0x01)); // reset VD_MCU
2912 #else
2913 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x01); // reset MCU, madison patch
2914 #endif
2915 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x01, 0x01); // enable SRAM
2916 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x00); // release VD_MCU
2917
2918 #if (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_T3_T10)
2919 _HAL_DMD_RIU_WriteByte(0x101E3E, 0x08); // ATSC = BIT3 -> 0x08
2920 _HAL_DMD_RIU_WriteByte(0x11051C, 0x00);
2921 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_T7)
2922 _HAL_DMD_RIU_WriteByte(0x11261C, 0x00);
2923 pRes->sDMD_ATSC_PriData.bDownloaded = true;
2924 #else
2925 pRes->sDMD_ATSC_PriData.bDownloaded = true;
2926 #endif
2927
2928 MsOS_DelayTask(20);
2929
2930 HAL_INTERN_ATSC_DBINFO(printf(">DSP Loadcode done.\n"));
2931
2932 return TRUE;
2933 }
2934
_HAL_INTERN_ATSC_FWVERSION(void)2935 static void _HAL_INTERN_ATSC_FWVERSION(void)
2936 {
2937 MS_U8 data1,data2,data3;
2938
2939 #if (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_K3)
2940 _MBX_ReadReg(0x20C4, &data1);
2941 _MBX_ReadReg(0x20C5, &data2);
2942 _MBX_ReadReg(0x20C6, &data3);
2943 #else
2944 _MBX_ReadReg(0x20C4, &data1);
2945 _MBX_ReadReg(0x20CF, &data2);
2946 _MBX_ReadReg(0x20D0, &data3);
2947 #endif
2948
2949 HAL_INTERN_ATSC_DBINFO(printf("INTERN_ATSC_FW_VERSION:%x.%x.%x\n", data1, data2, data3));
2950 }
2951
_HAL_INTERN_ATSC_Exit(void)2952 static MS_BOOL _HAL_INTERN_ATSC_Exit(void)
2953 {
2954 MS_U8 u8CheckCount = 0;
2955
2956 _HAL_DMD_RIU_WriteByte(MBRegBase + 0x1C, 0x01);
2957
2958 _HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, _HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)|0x02); // assert interrupt to VD MCU51
2959 _HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, _HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)&(~0x02)); // de-assert interrupt to VD MCU51
2960
2961 while ((_HAL_DMD_RIU_ReadByte(MBRegBase + 0x1C)&0x02) != 0x02)
2962 {
2963 MsOS_DelayTaskUs(10);
2964
2965 if (u8CheckCount++ == 0xFF)
2966 {
2967 printf(">> ATSC Exit Fail!\n");
2968 return FALSE;
2969 }
2970 }
2971
2972 printf(">> ATSC Exit Ok!\n");
2973
2974 return TRUE;
2975 }
2976
_HAL_INTERN_ATSC_SoftReset(void)2977 static MS_BOOL _HAL_INTERN_ATSC_SoftReset(void)
2978 {
2979 MS_U8 u8Data = 0xFF;
2980
2981 //Reset FSM
2982 if (_MBX_WriteReg(0x20C0, 0x00)==FALSE) return FALSE;
2983
2984 #if (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_K3)
2985 while (u8Data != 0x02)
2986 #else
2987 while (u8Data != 0x00)
2988 #endif
2989 {
2990 if (_MBX_ReadReg(0x20C1, &u8Data)==FALSE) return FALSE;
2991 }
2992
2993 #if (DMD_ATSC_CHIP_VERSION < DMD_ATSC_CHIP_K3)
2994 //Execute demod top reset
2995 _MBX_ReadReg(0x2002, &u8Data);
2996 _MBX_WriteReg(0x2002, (u8Data|0x10));
2997 return _MBX_WriteReg(0x2002, (u8Data&(~0x10)));
2998 #else
2999 return TRUE;
3000 #endif
3001 }
3002
_HAL_INTERN_ATSC_SetVsbMode(void)3003 static MS_BOOL _HAL_INTERN_ATSC_SetVsbMode(void)
3004 {
3005 return _MBX_WriteReg(0x20C0, 0x08);
3006 }
3007
_HAL_INTERN_ATSC_Set64QamMode(void)3008 static MS_BOOL _HAL_INTERN_ATSC_Set64QamMode(void)
3009 {
3010 #if (DMD_ATSC_CHIP_VERSION < DMD_ATSC_CHIP_K3)
3011 if (_MBX_WriteReg(0x20C3, 0x00)==FALSE) return FALSE;
3012 #endif
3013 return _MBX_WriteReg(0x20C0, 0x04);
3014 }
3015
_HAL_INTERN_ATSC_Set256QamMode(void)3016 static MS_BOOL _HAL_INTERN_ATSC_Set256QamMode(void)
3017 {
3018 #if (DMD_ATSC_CHIP_VERSION < DMD_ATSC_CHIP_K3)
3019 if (_MBX_WriteReg(0x20C3, 0x01)==FALSE) return FALSE;
3020 #endif
3021 return _MBX_WriteReg(0x20C0, 0x04);
3022 }
3023
_HAL_INTERN_ATSC_SetModeClean(void)3024 static MS_BOOL _HAL_INTERN_ATSC_SetModeClean(void)
3025 {
3026 return _MBX_WriteReg(0x20C0, 0x00);
3027 }
3028
_HAL_INTERN_ATSC_Check8VSB64_256QAM(void)3029 static DMD_ATSC_DEMOD_TYPE _HAL_INTERN_ATSC_Check8VSB64_256QAM(void)
3030 {
3031 MS_U8 mode = 0;
3032
3033 #if (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_K3)
3034 _MBX_ReadReg(0x2A02, &mode); //EQ mode check
3035
3036 mode &= 0x07;
3037
3038 if (mode == QAM16_J83ABC) return DMD_ATSC_DEMOD_ATSC_16QAM;
3039 else if (mode == QAM32_J83ABC) return DMD_ATSC_DEMOD_ATSC_32QAM;
3040 else if (mode == QAM64_J83ABC) return DMD_ATSC_DEMOD_ATSC_64QAM;
3041 else if (mode == QAM128_J83ABC) return DMD_ATSC_DEMOD_ATSC_128QAM;
3042 else if (mode == QAM256_J83ABC) return DMD_ATSC_DEMOD_ATSC_256QAM;
3043 else return DMD_ATSC_DEMOD_ATSC_256QAM;
3044 #else
3045 #if (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MASERATI || DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MACAN \
3046 || DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MAXIM)
3047 _MBX_ReadReg(0x1700, &mode); //mode check
3048 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MUSTANG)
3049 _MBX_ReadReg(0x0400, &mode); //mode check (atsc_dmd)
3050 #else
3051 _MBX_ReadReg(0x2900, &mode); //mode check
3052 #endif
3053
3054 if ((mode&VSB_ATSC) == VSB_ATSC) return DMD_ATSC_DEMOD_ATSC_VSB;
3055 else if ((mode & QAM256_ATSC) == QAM256_ATSC) return DMD_ATSC_DEMOD_ATSC_256QAM;
3056 else return DMD_ATSC_DEMOD_ATSC_64QAM;
3057 #endif
3058 }
3059
_HAL_INTERN_ATSC_Vsb_QAM_AGCLock(void)3060 static MS_BOOL _HAL_INTERN_ATSC_Vsb_QAM_AGCLock(void)
3061 {
3062 MS_U8 data1 = 0;
3063
3064 #if (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_A1)
3065 #if (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MASERATI || DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MACAN \
3066 || DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MUSTANG || DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MAXIM)
3067 _MBX_ReadReg(0x2829, &data1); //AGC_LOCK
3068 #else
3069 _MBX_ReadReg(0x271D, &data1); //AGC_LOCK
3070 #endif
3071 #else
3072 _MBX_ReadReg(0x293A, &data1); //AGC_LOCK
3073 #endif
3074
3075 if(data1&0x01)
3076 {
3077 return TRUE;
3078 }
3079 else
3080 {
3081 return FALSE;
3082 }
3083 }
3084
_HAL_INTERN_ATSC_Vsb_PreLock(void)3085 static MS_BOOL _HAL_INTERN_ATSC_Vsb_PreLock(void)
3086 {
3087 MS_U8 data1 = 0;
3088 MS_U8 data2 = 0;
3089 MS_U16 checkValue;
3090
3091 _MBX_ReadReg(0x20C2, &data1); //<0>TR_LOCK, <1>PTK_LOCK
3092
3093 if ((data1&0x02) == 0x02)
3094 {
3095 #if (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MASERATI || DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MACAN \
3096 || DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MAXIM)
3097 _MBX_ReadReg(0x18EA, &data1);
3098 _MBX_ReadReg(0x18EB, &data2);
3099 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MUSTANG)
3100 _MBX_ReadReg(0x05EA, &data1); //atsc_dmdext
3101 _MBX_ReadReg(0x05EB, &data2); //atsc_dmdext
3102 #else
3103 _MBX_ReadReg(0x2AEA, &data1);
3104 _MBX_ReadReg(0x2AEB, &data2);
3105 #endif
3106
3107 checkValue = data1 << 8;
3108 checkValue |= data2;
3109
3110 HAL_INTERN_ATSC_DBINFO(printf("Internal Pre Locking time :[%d]ms\n",checkValue));
3111
3112 return TRUE;
3113 }
3114 else
3115 {
3116 HAL_INTERN_ATSC_DBINFO(printf("\nPreLock - FALSE"));
3117
3118 return FALSE;
3119 }
3120 }
3121
_HAL_INTERN_ATSC_Vsb_FSync_Lock(void)3122 static MS_BOOL _HAL_INTERN_ATSC_Vsb_FSync_Lock(void)
3123 {
3124 MS_U8 data1 = 0;
3125 MS_U8 data2 = 0;
3126 MS_U16 checkValue;
3127
3128 #if (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MASERATI || DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MACAN \
3129 || DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MAXIM)
3130 _MBX_ReadReg(0x1824, &data1); //<4>1:Field Sync lock = Fsync lock
3131 #else
3132 _MBX_ReadReg(0x2A24, &data1); //<4>1:Field Sync lock = Fsync lock
3133 #endif
3134
3135 if ((data1&0x10) == 0x10)
3136 {
3137 #if (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MASERATI || DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MACAN \
3138 || DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MAXIM)
3139 _MBX_ReadReg(0x18EE, &data1);
3140 _MBX_ReadReg(0x18EF, &data2);
3141 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MUSTANG)
3142 _MBX_ReadReg(0x05EE, &data1); //atsc_dmdext
3143 _MBX_ReadReg(0x05EF, &data2); //atsc_dmdext
3144 #else
3145 _MBX_ReadReg(0x2AEE, &data1);
3146 _MBX_ReadReg(0x2AEF, &data2);
3147 #endif
3148
3149 checkValue = data1 << 8;
3150 checkValue |= data2;
3151
3152 HAL_INTERN_ATSC_DBINFO(printf("Internal Fsync Locking time :[%d]ms\n",checkValue));
3153
3154 return TRUE;
3155 }
3156 else
3157 {
3158 HAL_INTERN_ATSC_DBINFO(printf("\nFsync Lock - FALSE"));
3159
3160 return FALSE;
3161 }
3162 }
3163
_HAL_INTERN_ATSC_Vsb_CE_Lock(void)3164 static MS_BOOL _HAL_INTERN_ATSC_Vsb_CE_Lock(void)
3165 {
3166 #if (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_A1)
3167 return TRUE;
3168 #else
3169 MS_U8 data1 = 0;
3170
3171 _MBX_ReadReg(0x20C2, &data1); //<4>1:CE Search Fail
3172
3173 if((data1&0x10) == 0)
3174 {
3175 HAL_INTERN_ATSC_DBINFO(printf("\nCE Lock"));
3176 return TRUE;
3177 }
3178 else
3179 {
3180 HAL_INTERN_ATSC_DBINFO(printf("\nCE unLock"));
3181 return FALSE;
3182 }
3183 #endif
3184 }
3185
_HAL_INTERN_ATSC_Vsb_FEC_Lock(void)3186 static MS_BOOL _HAL_INTERN_ATSC_Vsb_FEC_Lock(void)
3187 {
3188 MS_U8 data1=0, data2=0, data3=0, data4=0, data5=0;
3189 #if (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_A1)
3190 MS_U8 data6 =0, data7 = 0;
3191 #endif
3192
3193 #if (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_A1)
3194 _MBX_ReadReg(0x20C1, &data1);
3195 #if (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MASERATI || DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MACAN \
3196 || DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MAXIM)
3197 _MBX_ReadReg(0x1A17, &data2);//AD_NOISE_PWR_TRAIN1
3198 #else
3199 _MBX_ReadReg(0x2C17, &data2);//AD_NOISE_PWR_TRAIN1
3200 #endif
3201 _MBX_ReadReg(0x20C2, &data3);//<0>TR_LOCK, <1>PTK_LOCK
3202 #if (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MASERATI || DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MACAN \
3203 || DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MAXIM)
3204 _MBX_ReadReg(0x1901, &data4);//FEC_EN_CTL
3205 _MBX_ReadReg(0x1C67, &data5);//addy
3206 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MUSTANG)
3207 _MBX_ReadReg(0x0601, &data4);//FEC_EN_CTL (atsc_fec)
3208 _MBX_ReadReg(0x2D67, &data5);//addy (atsc_eqext)
3209 #else
3210 _MBX_ReadReg(0x2B01, &data4);//FEC_EN_CTL
3211 _MBX_ReadReg(0x2D67, &data5);//addy
3212 #endif
3213 _MBX_ReadReg(0x1F01, &data6);
3214 _MBX_ReadReg(0x1F40, &data7);
3215
3216 //Driver update 0426 :suggestion for field claim
3217 if (data1==INTERN_ATSC_OUTER_STATE &&
3218 ((data2<=INTERN_ATSC_VSB_TRAIN_SNR_LIMIT) || (data5 <= INTERN_ATSC_VSB_TRAIN_SNR_LIMIT)) &&
3219 ((data3&0x02)==0x02) &&
3220 ((data4&INTERN_ATSC_FEC_ENABLE)==INTERN_ATSC_FEC_ENABLE) &&
3221 ((data6&0x10) == 0x10) && ((data7&0x01) == 0x01))
3222 {
3223 HAL_INTERN_ATSC_DBINFO(printf("\nFEC Lock"));
3224 return TRUE;
3225 }
3226 else
3227 {
3228 HAL_INTERN_ATSC_DBINFO(printf("\nFEC unLock"));
3229 return FALSE;
3230 }
3231 #else
3232 _MBX_ReadReg(0x20C1, &data1);
3233 _MBX_ReadReg(0x2C17, &data2); //AD_NOISE_PWR_TRAIN1 (DFS)
3234 _MBX_ReadReg(0x20C2, &data3); //<0>TR_LOCK, <1>PTK_LOCK
3235 _MBX_ReadReg(0x2B01, &data4); //FEC_EN_CTL
3236 _MBX_ReadReg(0x2C15, &data5); //AD_NOISE_PWR_TRAIN1 (DSS)
3237
3238 if ((data1 == INTERN_ATSC_OUTER_STATE) &&
3239 ((data2 <= INTERN_ATSC_VSB_TRAIN_SNR_LIMIT) || (data5 <= INTERN_ATSC_VSB_TRAIN_SNR_LIMIT)) &&
3240 ((data3&0x02)==0x02) &&
3241 ((data4&INTERN_ATSC_FEC_ENABLE) == INTERN_ATSC_FEC_ENABLE))
3242 {
3243 HAL_INTERN_ATSC_DBINFO(printf("\nFEC Lock"));
3244 return TRUE;
3245 }
3246 else
3247 {
3248 HAL_INTERN_ATSC_DBINFO(printf("\nFEC unLock"));
3249 return FALSE;
3250 }
3251 #endif
3252 }
3253
_HAL_INTERN_ATSC_QAM_PreLock(void)3254 static MS_BOOL _HAL_INTERN_ATSC_QAM_PreLock(void)
3255 {
3256 MS_U8 data1 = 0;
3257
3258 #if (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_K3)
3259 _MBX_ReadReg(0x2950, &data1); //TR_LOCK
3260 #elif (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_A1)
3261 #if (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MASERATI || DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MACAN \
3262 || DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MAXIM)
3263 _MBX_ReadReg(0x1B15, &data1); //TR_LOCK
3264 #else
3265 _MBX_ReadReg(0x2615, &data1); //TR_LOCK
3266 #endif
3267 #else
3268 _MBX_ReadReg(0x2921, &data1); //TR_LOCK
3269 #endif
3270
3271 #if (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_K3)
3272 if (data1&0x01)
3273 {
3274 HAL_INTERN_ATSC_DBINFO(printf(" QAM preLock OK \n"));
3275 return TRUE;
3276 }
3277 else
3278 {
3279 HAL_INTERN_ATSC_DBINFO(printf(" QAM preLock NOT OK \n"));
3280 return FALSE;
3281 }
3282 #else
3283 if((data1&0x10) == 0x10)
3284 {
3285 HAL_INTERN_ATSC_DBINFO(printf(" QAM preLock OK \n"));
3286 return TRUE;
3287 }
3288 else
3289 {
3290 HAL_INTERN_ATSC_DBINFO(printf(" QAM preLock NOT OK \n"));
3291 return FALSE;
3292 }
3293 #endif
3294 }
3295
_HAL_INTERN_ATSC_QAM_Main_Lock(void)3296 static MS_BOOL _HAL_INTERN_ATSC_QAM_Main_Lock(void)
3297 {
3298 #if DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_A1
3299 MS_U8 data1=0, data2=0, data3=0, data4=0, data5=0, data6=0;
3300 #else
3301 MS_U8 data1=0, data4=0, data5=0, data6=0;
3302 #endif
3303
3304 #if (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_K3)
3305 _MBX_ReadReg(0x20C1, &data1);
3306 _MBX_ReadReg(0x2B18, &data2); //boundary detected
3307 _MBX_ReadReg(0x2950, &data3); //TR_LOCK
3308 _MBX_ReadReg(0x2B01, &data4); //FEC_EN_CTL
3309 _MBX_ReadReg(0x2101, &data5); //RS_backend
3310 _MBX_ReadReg(0x2140, &data6); //RS_backend
3311
3312 if (data1==INTERN_ATSC_OUTER_STATE && (data2&0x01)==0x01 &&
3313 data4==INTERN_ATSC_FEC_ENABLE && (data3&0x01) ==0x01 &&
3314 ((data5&0x10) == 0x10) && ((data6&0x01) == 0x01))
3315 {
3316 return TRUE;
3317 }
3318 else
3319 {
3320 return FALSE;
3321 }
3322 #elif (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_A1)
3323 _MBX_ReadReg(0x20C1, &data1);
3324 #if (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MASERATI || DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MACAN \
3325 || DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MAXIM)
3326 _MBX_ReadReg(0x1918, &data2); //boundary detected
3327 _MBX_ReadReg(0x1B15, &data3); //TR_LOCK
3328 _MBX_ReadReg(0x1901, &data4); //FEC_EN_CTL
3329 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MUSTANG)
3330 _MBX_ReadReg(0x0618, &data2); //boundary detected (atsc_fec)
3331 _MBX_ReadReg(0x2615, &data3); //TR_LOCK (dmd_tr)
3332 _MBX_ReadReg(0x0601, &data4); //FEC_EN_CTL (atsc_fec)
3333 #else
3334 _MBX_ReadReg(0x2B18, &data2); //boundary detected
3335 _MBX_ReadReg(0x2615, &data3); //TR_LOCK
3336 _MBX_ReadReg(0x2B01, &data4); //FEC_EN_CTL
3337 #endif
3338 _MBX_ReadReg(0x1F01, &data5);
3339 _MBX_ReadReg(0x1F40, &data6);
3340
3341 if (data1==INTERN_ATSC_OUTER_STATE && (data2&0x01)==0x01 &&
3342 data4==INTERN_ATSC_FEC_ENABLE && (data3&0x10)==0x10 &&
3343 ((data5&0x10) == 0x10) && ((data6&0x01) == 0x01))
3344 {
3345 return TRUE;
3346 }
3347 else
3348 {
3349 return FALSE;
3350 }
3351 #else
3352 _MBX_ReadReg(0x2B18, &data4); //boundary detected
3353 _MBX_ReadReg(0x2B01, &data5); //FEC_EN_CTL
3354 _MBX_ReadReg(0x2921, &data6); //TR_LOCK
3355 _MBX_ReadReg(0x20C1, &data1);
3356
3357 if (data1==INTERN_ATSC_OUTER_STATE && (data4&0x01) == 0x01 &&
3358 (data5&INTERN_ATSC_FEC_ENABLE) == INTERN_ATSC_FEC_ENABLE &&
3359 (data6&0x10) == 0x10)
3360 {
3361 return TRUE;
3362 }
3363 else
3364 {
3365 return FALSE;
3366 }
3367 #endif
3368 }
3369
_HAL_INTERN_ATSC_ReadIFAGC(void)3370 static MS_U8 _HAL_INTERN_ATSC_ReadIFAGC(void)
3371 {
3372 MS_U16 data = 0;
3373
3374 #if (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_K3)
3375 _MBX_ReadReg(0x2726, ((MS_U8*)(&data))+1); //reg_frontend
3376 _MBX_ReadReg(0x2727, (MS_U8*)(&data));
3377 #elif (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_A1)
3378 #if (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MASERATI || DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MACAN \
3379 || DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MUSTANG|| DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MAXIM)
3380 _MBX_ReadReg(0x280E, ((MS_U8*)(&data))+1);
3381 _MBX_ReadReg(0x280F, (MS_U8*)(&data));
3382 #else
3383 _MBX_ReadReg(0x2944, ((MS_U8*)(&data))+1);
3384 _MBX_ReadReg(0x2945, (MS_U8*)(&data));
3385 #endif
3386 #endif
3387
3388 return data;
3389 }
3390
_HAL_INTERN_ATSC_CheckSignalCondition(DMD_ATSC_SIGNAL_CONDITION * pstatus)3391 static void _HAL_INTERN_ATSC_CheckSignalCondition(DMD_ATSC_SIGNAL_CONDITION* pstatus)
3392 {
3393 DMD_ATSC_DEMOD_TYPE eMode;
3394 #if (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_K3)
3395 MS_U8 u8NoisePowerH = 0, u8NoisePowerL = 0;
3396 static MS_U8 u8NoisePowerL_Last = 0xff;
3397 #else
3398 MS_U8 u8NoisePowerH=0;
3399 #endif
3400 static MS_U8 u8NoisePowerH_Last = 0xff;
3401
3402 eMode = _HAL_INTERN_ATSC_Check8VSB64_256QAM();
3403
3404 #if (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_K3)
3405 _MBX_ReadReg(0x2ABE, &u8NoisePowerL); //DVBC_EQ
3406 _MBX_ReadReg(0x2ABF, &u8NoisePowerH);
3407 #else
3408 #if (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MASERATI || DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MACAN \
3409 || DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MAXIM)
3410 _MBX_ReadReg(0x1A15, &u8NoisePowerH);
3411 #else
3412 _MBX_ReadReg(0x2C15, &u8NoisePowerH); //(atsc_eq)
3413 #endif
3414 #endif
3415
3416 if (eMode == DMD_ATSC_DEMOD_ATSC_VSB) //VSB mode//SNR=10*log10((1344<<10)/noisepower)
3417 {
3418 if (!_HAL_INTERN_ATSC_Vsb_FEC_Lock()) u8NoisePowerH=0xFF;
3419 else if (abs(u8NoisePowerH_Last-u8NoisePowerH) > 5)
3420 u8NoisePowerH_Last = u8NoisePowerH;
3421 else u8NoisePowerH = u8NoisePowerH_Last;
3422
3423 if (u8NoisePowerH > 0xBE) //SNR<14.5
3424 *pstatus=DMD_ATSC_SIGNAL_NO;
3425 else if (u8NoisePowerH > 0x4D) //SNR<18.4
3426 *pstatus=DMD_ATSC_SIGNAL_WEAK;
3427 else if (u8NoisePowerH > 0x23) //SNR<21.8
3428 *pstatus=DMD_ATSC_SIGNAL_MODERATE;
3429 else if (u8NoisePowerH > 0x0A) //SNR<26.9
3430 *pstatus=DMD_ATSC_SIGNAL_STRONG;
3431 else
3432 *pstatus=DMD_ATSC_SIGNAL_VERY_STRONG;
3433 }
3434 else //QAM MODE
3435 {
3436 #if (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_K3)
3437 if (!_HAL_INTERN_ATSC_QAM_Main_Lock() || u8NoisePowerH) u8NoisePowerL=0xFF;
3438 else if (abs(u8NoisePowerL_Last-u8NoisePowerL) > 5)
3439 u8NoisePowerL_Last = u8NoisePowerL;
3440 else u8NoisePowerL = u8NoisePowerL_Last;
3441
3442 //SNR=10*log10(65536/noisepower)
3443 if (eMode == DMD_ATSC_DEMOD_ATSC_256QAM)
3444 {
3445 if (u8NoisePowerL > 0x71) //SNR<27.6
3446 *pstatus=DMD_ATSC_SIGNAL_NO;
3447 else if (u8NoisePowerL > 0x31) //SNR<31.2
3448 *pstatus=DMD_ATSC_SIGNAL_WEAK;
3449 else if (u8NoisePowerL > 0x25) //SNR<32.4
3450 *pstatus=DMD_ATSC_SIGNAL_MODERATE;
3451 else if (u8NoisePowerL > 0x17) //SNR<34.4
3452 *pstatus=DMD_ATSC_SIGNAL_STRONG;
3453 else
3454 *pstatus=DMD_ATSC_SIGNAL_VERY_STRONG;
3455 }
3456 else
3457 {
3458 if (u8NoisePowerL > 0x1D) //SNR<21.5
3459 *pstatus=DMD_ATSC_SIGNAL_NO;
3460 else if (u8NoisePowerL > 0x14) //SNR<25.4
3461 *pstatus=DMD_ATSC_SIGNAL_WEAK;
3462 else if (u8NoisePowerL > 0x0F) //SNR<27.8
3463 *pstatus=DMD_ATSC_SIGNAL_MODERATE;
3464 else if (u8NoisePowerL > 0x0B) //SNR<31.4
3465 *pstatus=DMD_ATSC_SIGNAL_STRONG;
3466 else
3467 *pstatus=DMD_ATSC_SIGNAL_VERY_STRONG;
3468 }
3469 #else
3470 if (!_HAL_INTERN_ATSC_QAM_Main_Lock()) u8NoisePowerH=0xFF;
3471 else if (abs(u8NoisePowerH_Last-u8NoisePowerH) > 5)
3472 u8NoisePowerH_Last = u8NoisePowerH;
3473 else u8NoisePowerH = u8NoisePowerH_Last;
3474
3475 if (eMode == DMD_ATSC_DEMOD_ATSC_256QAM) //256QAM//SNR=10*log10((2720<<10)/noisepower)
3476 {
3477 if (u8NoisePowerH > 0x13) //SNR<27.5
3478 *pstatus=DMD_ATSC_SIGNAL_NO;
3479 else if (u8NoisePowerH > 0x08) //SNR<31.2
3480 *pstatus=DMD_ATSC_SIGNAL_WEAK;
3481 else if (u8NoisePowerH > 0x06) //SNR<32.4
3482 *pstatus=DMD_ATSC_SIGNAL_MODERATE;
3483 else if (u8NoisePowerH > 0x04) //SNR<34.2
3484 *pstatus=DMD_ATSC_SIGNAL_STRONG;
3485 else
3486 *pstatus=DMD_ATSC_SIGNAL_VERY_STRONG;
3487 }
3488 else //64QAM//SNR=10*log10((2688<<10)/noisepower)
3489 {
3490 if (u8NoisePowerH > 0x4C) //SNR<21.5
3491 *pstatus=DMD_ATSC_SIGNAL_NO;
3492 else if (u8NoisePowerH > 0x1F) //SNR<25.4
3493 *pstatus=DMD_ATSC_SIGNAL_WEAK;
3494 else if (u8NoisePowerH > 0x11) //SNR<27.8
3495 *pstatus=DMD_ATSC_SIGNAL_MODERATE;
3496 else if (u8NoisePowerH > 0x07) //SNR<31.4
3497 *pstatus=DMD_ATSC_SIGNAL_STRONG;
3498 else
3499 *pstatus=DMD_ATSC_SIGNAL_VERY_STRONG;
3500 }
3501 #endif
3502 }
3503 }
3504
_HAL_INTERN_ATSC_ReadSNRPercentage(void)3505 static MS_U8 _HAL_INTERN_ATSC_ReadSNRPercentage(void)
3506 {
3507 DMD_ATSC_DEMOD_TYPE eMode;
3508 MS_U8 u8NoisePowerH = 0, u8NoisePowerL = 0;
3509 MS_U16 u16NoisePower;
3510
3511 eMode = _HAL_INTERN_ATSC_Check8VSB64_256QAM();
3512
3513 #if (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_K3)
3514 _MBX_ReadReg(0x2ABE, &u8NoisePowerL); //DVBC_EQ
3515 _MBX_ReadReg(0x2ABF, &u8NoisePowerH);
3516 #else
3517 #if (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MASERATI || DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MACAN \
3518 || DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MAXIM)
3519 _MBX_ReadReg(0x1A14, &u8NoisePowerL);
3520 _MBX_ReadReg(0x1A15, &u8NoisePowerH);
3521 #else
3522 _MBX_ReadReg(0x2C14, &u8NoisePowerL); //atsc_eq
3523 _MBX_ReadReg(0x2C15, &u8NoisePowerH);
3524 #endif
3525 #endif
3526
3527 u16NoisePower = (u8NoisePowerH<<8) | u8NoisePowerL;
3528
3529 if (eMode == DMD_ATSC_DEMOD_ATSC_VSB) //VSB mode//SNR=10*log10((1344<<10)/noisepower)
3530 {
3531 if (!_HAL_INTERN_ATSC_Vsb_FEC_Lock())
3532 return 0;//SNR=0;
3533 else if (u16NoisePower<=0x008A)//SNR>=40dB
3534 return 100;//SNR=MAX_SNR;
3535 else if (u16NoisePower<=0x0097)//SNR>=39.6dB
3536 return 99;//
3537 else if (u16NoisePower<=0x00A5)//SNR>=39.2dB
3538 return 98;//
3539 else if (u16NoisePower<=0x00B5)//SNR>=38.8dB
3540 return 97;//
3541 else if (u16NoisePower<=0x00C7)//SNR>=38.4dB
3542 return 96;//
3543 else if (u16NoisePower<=0x00DA)//SNR>=38.0dB
3544 return 95;//
3545 else if (u16NoisePower<=0x00EF)//SNR>=37.6dB
3546 return 94;//
3547 else if (u16NoisePower<=0x0106)//SNR>=37.2dB
3548 return 93;//
3549 else if (u16NoisePower<=0x0120)//SNR>=36.8dB
3550 return 92;//
3551 else if (u16NoisePower<=0x013B)//SNR>=36.4dB
3552 return 91;//
3553 else if (u16NoisePower<=0x015A)//SNR>=36.0dB
3554 return 90;//
3555 else if (u16NoisePower<=0x017B)//SNR>=35.6dB
3556 return 89;//
3557 else if (u16NoisePower<=0x01A0)//SNR>=35.2dB
3558 return 88;//
3559 else if (u16NoisePower<=0x01C8)//SNR>=34.8dB
3560 return 87;//
3561 else if (u16NoisePower<=0x01F4)//SNR>=34.4dB
3562 return 86;//
3563 else if (u16NoisePower<=0x0224)//SNR>=34.0dB
3564 return 85;//
3565 else if (u16NoisePower<=0x0259)//SNR>=33.6dB
3566 return 84;//
3567 else if (u16NoisePower<=0x0293)//SNR>=33.2dB
3568 return 83;//
3569 else if (u16NoisePower<=0x02D2)//SNR>=32.8dB
3570 return 82;//
3571 else if (u16NoisePower<=0x0318)//SNR>=32.4dB
3572 return 81;//
3573 else if (u16NoisePower<=0x0364)//SNR>=32.0dB
3574 return 80;//
3575 else if (u16NoisePower<=0x03B8)//SNR>=31.6dB
3576 return 79;//
3577 else if (u16NoisePower<=0x0414)//SNR>=31.2dB
3578 return 78;//
3579 else if (u16NoisePower<=0x0479)//SNR>=30.8dB
3580 return 77;//
3581 else if (u16NoisePower<=0x04E7)//SNR>=30.4dB
3582 return 76;//
3583 else if (u16NoisePower<=0x0560)//SNR>=30.0dB
3584 return 75;//
3585 else if (u16NoisePower<=0x05E5)//SNR>=29.6dB
3586 return 74;//
3587 else if (u16NoisePower<=0x0677)//SNR>=29.2dB
3588 return 73;//
3589 else if (u16NoisePower<=0x0716)//SNR>=28.8dB
3590 return 72;//
3591 else if (u16NoisePower<=0x07C5)//SNR>=28.4dB
3592 return 71;//
3593 else if (u16NoisePower<=0x0885)//SNR>=28.0dB
3594 return 70;//
3595 else if (u16NoisePower<=0x0958)//SNR>=27.6dB
3596 return 69;//
3597 else if (u16NoisePower<=0x0A3E)//SNR>=27.2dB
3598 return 68;//
3599 else if (u16NoisePower<=0x0B3B)//SNR>=26.8dB
3600 return 67;//
3601 else if (u16NoisePower<=0x0C51)//SNR>=26.4dB
3602 return 66;//
3603 else if (u16NoisePower<=0x0D81)//SNR>=26.0dB
3604 return 65;//
3605 else if (u16NoisePower<=0x0ECF)//SNR>=25.6dB
3606 return 64;//
3607 else if (u16NoisePower<=0x103C)//SNR>=25.2dB
3608 return 63;//
3609 else if (u16NoisePower<=0x11CD)//SNR>=24.8dB
3610 return 62;//
3611 else if (u16NoisePower<=0x1385)//SNR>=24.4dB
3612 return 61;//
3613 else if (u16NoisePower<=0x1567)//SNR>=24.0dB
3614 return 60;//
3615 else if (u16NoisePower<=0x1778)//SNR>=23.6dB
3616 return 59;//
3617 else if (u16NoisePower<=0x19BB)//SNR>=23.2dB
3618 return 58;//
3619 else if (u16NoisePower<=0x1C37)//SNR>=22.8dB
3620 return 57;//
3621 else if (u16NoisePower<=0x1EF0)//SNR>=22.4dB
3622 return 56;//
3623 else if (u16NoisePower<=0x21EC)//SNR>=22.0dB
3624 return 55;//
3625 else if (u16NoisePower<=0x2531)//SNR>=21.6dB
3626 return 54;//
3627 else if (u16NoisePower<=0x28C8)//SNR>=21.2dB
3628 return 53;//
3629 else if (u16NoisePower<=0x2CB7)//SNR>=20.8dB
3630 return 52;//
3631 else if (u16NoisePower<=0x3108)//SNR>=20.4dB
3632 return 51;//
3633 else if (u16NoisePower<=0x35C3)//SNR>=20.0dB
3634 return 50;//
3635 else if (u16NoisePower<=0x3AF2)//SNR>=19.6dB
3636 return 49;//
3637 else if (u16NoisePower<=0x40A2)//SNR>=19.2dB
3638 return 48;//
3639 else if (u16NoisePower<=0x46DF)//SNR>=18.8dB
3640 return 47;//
3641 else if (u16NoisePower<=0x4DB5)//SNR>=18.4dB
3642 return 46;//
3643 else if (u16NoisePower<=0x5534)//SNR>=18.0dB
3644 return 45;//
3645 else if (u16NoisePower<=0x5D6D)//SNR>=17.6dB
3646 return 44;//
3647 else if (u16NoisePower<=0x6670)//SNR>=17.2dB
3648 return 43;//
3649 else if (u16NoisePower<=0x7052)//SNR>=16.8dB
3650 return 42;//
3651 else if (u16NoisePower<=0x7B28)//SNR>=16.4dB
3652 return 41;//
3653 else if (u16NoisePower<=0x870A)//SNR>=16.0dB
3654 return 40;//
3655 else if (u16NoisePower<=0x9411)//SNR>=15.6dB
3656 return 39;//
3657 else if (u16NoisePower<=0xA25A)//SNR>=15.2dB
3658 return 38;//
3659 else if (u16NoisePower<=0xB204)//SNR>=14.8dB
3660 return 37;//
3661 else if (u16NoisePower<=0xC331)//SNR>=14.4dB
3662 return 36;//
3663 else if (u16NoisePower<=0xD606)//SNR>=14.0dB
3664 return 35;//
3665 else if (u16NoisePower<=0xEAAC)//SNR>=13.6dB
3666 return 34;//
3667 else// if (u16NoisePower>=0xEAAC)//SNR<13.6dB
3668 return 33;//
3669 }
3670 else //QAM MODE
3671 {
3672 if( eMode == DMD_ATSC_DEMOD_ATSC_256QAM ) //256QAM//SNR=10*log10((2720<<10)/noisepower)
3673 {
3674 if (!_HAL_INTERN_ATSC_QAM_Main_Lock())
3675 return 0;//SNR=0;
3676 else if (u16NoisePower<=0x0117)//SNR>=40dB
3677 return 100;//
3678 else if (u16NoisePower<=0x0131)//SNR>=39.6dB
3679 return 99;//
3680 else if (u16NoisePower<=0x014F)//SNR>=39.2dB
3681 return 98;//
3682 else if (u16NoisePower<=0x016F)//SNR>=38.8dB
3683 return 97;//
3684 else if (u16NoisePower<=0x0193)//SNR>=38.4dB
3685 return 96;//
3686 else if (u16NoisePower<=0x01B9)//SNR>=38.0dB
3687 return 95;//
3688 else if (u16NoisePower<=0x01E4)//SNR>=37.6dB
3689 return 94;//
3690 else if (u16NoisePower<=0x0213)//SNR>=37.2dB
3691 return 93;//
3692 else if (u16NoisePower<=0x0246)//SNR>=36.8dB
3693 return 92;//
3694 else if (u16NoisePower<=0x027E)//SNR>=36.4dB
3695 return 91;//
3696 else if (u16NoisePower<=0x02BC)//SNR>=36.0dB
3697 return 90;//
3698 else if (u16NoisePower<=0x02FF)//SNR>=35.6dB
3699 return 89;//
3700 else if (u16NoisePower<=0x0349)//SNR>=35.2dB
3701 return 88;//
3702 else if (u16NoisePower<=0x039A)//SNR>=34.8dB
3703 return 87;//
3704 else if (u16NoisePower<=0x03F3)//SNR>=34.4dB
3705 return 86;//
3706 else if (u16NoisePower<=0x0455)//SNR>=34.0dB
3707 return 85;//
3708 else if (u16NoisePower<=0x04C0)//SNR>=33.6dB
3709 return 84;//
3710 else if (u16NoisePower<=0x0535)//SNR>=33.2dB
3711 return 83;//
3712 else if (u16NoisePower<=0x05B6)//SNR>=32.8dB
3713 return 82;//
3714 else if (u16NoisePower<=0x0643)//SNR>=32.4dB
3715 return 81;//
3716 else if (u16NoisePower<=0x06DD)//SNR>=32.0dB
3717 return 80;//
3718 else if (u16NoisePower<=0x0787)//SNR>=31.6dB
3719 return 79;//
3720 else if (u16NoisePower<=0x0841)//SNR>=31.2dB
3721 return 78;//
3722 else if (u16NoisePower<=0x090D)//SNR>=30.8dB
3723 return 77;//
3724 else if (u16NoisePower<=0x09EC)//SNR>=30.4dB
3725 return 76;//
3726 else if (u16NoisePower<=0x0AE1)//SNR>=30.0dB
3727 return 75;//
3728 else if (u16NoisePower<=0x0BEE)//SNR>=29.6dB
3729 return 74;//
3730 else if (u16NoisePower<=0x0D15)//SNR>=29.2dB
3731 return 73;//
3732 else if (u16NoisePower<=0x0E58)//SNR>=28.8dB
3733 return 72;//
3734 else if (u16NoisePower<=0x0FBA)//SNR>=28.4dB
3735 return 71;//
3736 else if (u16NoisePower<=0x113E)//SNR>=28.0dB
3737 return 70;//
3738 else if (u16NoisePower<=0x12E8)//SNR>=27.6dB
3739 return 69;//
3740 else if (u16NoisePower<=0x14BB)//SNR>=27.2dB
3741 return 68;//
3742 else if (u16NoisePower<=0x16BB)//SNR>=26.8dB
3743 return 67;//
3744 else if (u16NoisePower<=0x18ED)//SNR>=26.4dB
3745 return 66;//
3746 else if (u16NoisePower<=0x1B54)//SNR>=26.0dB
3747 return 65;//
3748 else if (u16NoisePower<=0x1DF7)//SNR>=25.6dB
3749 return 64;//
3750 else if (u16NoisePower<=0x20DB)//SNR>=25.2dB
3751 return 63;//
3752 else if (u16NoisePower<=0x2407)//SNR>=24.8dB
3753 return 62;//
3754 else if (u16NoisePower<=0x2781)//SNR>=24.4dB
3755 return 61;//
3756 else if (u16NoisePower<=0x2B50)//SNR>=24.0dB
3757 return 60;//
3758 else if (u16NoisePower<=0x2F7E)//SNR>=23.6dB
3759 return 59;//
3760 else if (u16NoisePower<=0x3413)//SNR>=23.2dB
3761 return 58;//
3762 else if (u16NoisePower<=0x3919)//SNR>=22.8dB
3763 return 57;//
3764 else if (u16NoisePower<=0x3E9C)//SNR>=22.4dB
3765 return 56;//
3766 else if (u16NoisePower<=0x44A6)//SNR>=22.0dB
3767 return 55;//
3768 else if (u16NoisePower<=0x4B45)//SNR>=21.6dB
3769 return 54;//
3770 else if (u16NoisePower<=0x5289)//SNR>=21.2dB
3771 return 53;//
3772 else if (u16NoisePower<=0x5A7F)//SNR>=20.8dB
3773 return 52;//
3774 else if (u16NoisePower<=0x633A)//SNR>=20.4dB
3775 return 51;//
3776 else if (u16NoisePower<=0x6CCD)//SNR>=20.0dB
3777 return 50;//
3778 else if (u16NoisePower<=0x774C)//SNR>=19.6dB
3779 return 49;//
3780 else if (u16NoisePower<=0x82CE)//SNR>=19.2dB
3781 return 48;//
3782 else if (u16NoisePower<=0x8F6D)//SNR>=18.8dB
3783 return 47;//
3784 else if (u16NoisePower<=0x9D44)//SNR>=18.4dB
3785 return 46;//
3786 else if (u16NoisePower<=0xAC70)//SNR>=18.0dB
3787 return 45;//
3788 else if (u16NoisePower<=0xBD13)//SNR>=17.6dB
3789 return 44;//
3790 else if (u16NoisePower<=0xCF50)//SNR>=17.2dB
3791 return 43;//
3792 else if (u16NoisePower<=0xE351)//SNR>=16.8dB
3793 return 42;//
3794 else if (u16NoisePower<=0xF93F)//SNR>=16.4dB
3795 return 41;//
3796 else// if (u16NoisePower>=0xF93F)//SNR<16.4dB
3797 return 40;//
3798 }
3799 else //64QAM//SNR=10*log10((2688<<10)/noisepower)
3800 {
3801 if (!_HAL_INTERN_ATSC_QAM_Main_Lock())
3802 return 0;//SNR=0;
3803 else if (u16NoisePower<=0x0113)//SNR>=40dB
3804 return 100;//
3805 else if (u16NoisePower<=0x012E)//SNR>=39.6dB
3806 return 99;//
3807 else if (u16NoisePower<=0x014B)//SNR>=39.2dB
3808 return 98;//
3809 else if (u16NoisePower<=0x016B)//SNR>=38.8dB
3810 return 97;//
3811 else if (u16NoisePower<=0x018E)//SNR>=38.4dB
3812 return 96;//
3813 else if (u16NoisePower<=0x01B4)//SNR>=38.0dB
3814 return 95;//
3815 else if (u16NoisePower<=0x01DE)//SNR>=37.6dB
3816 return 94;//
3817 else if (u16NoisePower<=0x020C)//SNR>=37.2dB
3818 return 93;//
3819 else if (u16NoisePower<=0x023F)//SNR>=36.8dB
3820 return 92;//
3821 else if (u16NoisePower<=0x0277)//SNR>=36.4dB
3822 return 91;//
3823 else if (u16NoisePower<=0x02B3)//SNR>=36.0dB
3824 return 90;//
3825 else if (u16NoisePower<=0x02F6)//SNR>=35.6dB
3826 return 89;//
3827 else if (u16NoisePower<=0x033F)//SNR>=35.2dB
3828 return 88;//
3829 else if (u16NoisePower<=0x038F)//SNR>=34.8dB
3830 return 87;//
3831 else if (u16NoisePower<=0x03E7)//SNR>=34.4dB
3832 return 86;//
3833 else if (u16NoisePower<=0x0448)//SNR>=34.0dB
3834 return 85;//
3835 else if (u16NoisePower<=0x04B2)//SNR>=33.6dB
3836 return 84;//
3837 else if (u16NoisePower<=0x0525)//SNR>=33.2dB
3838 return 83;//
3839 else if (u16NoisePower<=0x05A5)//SNR>=32.8dB
3840 return 82;//
3841 else if (u16NoisePower<=0x0630)//SNR>=32.4dB
3842 return 81;//
3843 else if (u16NoisePower<=0x06C9)//SNR>=32.0dB
3844 return 80;//
3845 else if (u16NoisePower<=0x0770)//SNR>=31.6dB
3846 return 79;//
3847 else if (u16NoisePower<=0x0828)//SNR>=31.2dB
3848 return 78;//
3849 else if (u16NoisePower<=0x08F1)//SNR>=30.8dB
3850 return 77;//
3851 else if (u16NoisePower<=0x09CE)//SNR>=30.4dB
3852 return 76;//
3853 else if (u16NoisePower<=0x0AC1)//SNR>=30.0dB
3854 return 75;//
3855 else if (u16NoisePower<=0x0BCA)//SNR>=29.6dB
3856 return 74;//
3857 else if (u16NoisePower<=0x0CED)//SNR>=29.2dB
3858 return 73;//
3859 else if (u16NoisePower<=0x0E2D)//SNR>=28.8dB
3860 return 72;//
3861 else if (u16NoisePower<=0x0F8B)//SNR>=28.4dB
3862 return 71;//
3863 else if (u16NoisePower<=0x110A)//SNR>=28.0dB
3864 return 70;//
3865 else if (u16NoisePower<=0x12AF)//SNR>=27.6dB
3866 return 69;//
3867 else if (u16NoisePower<=0x147D)//SNR>=27.2dB
3868 return 68;//
3869 else if (u16NoisePower<=0x1677)//SNR>=26.8dB
3870 return 67;//
3871 else if (u16NoisePower<=0x18A2)//SNR>=26.4dB
3872 return 66;//
3873 else if (u16NoisePower<=0x1B02)//SNR>=26.0dB
3874 return 65;//
3875 else if (u16NoisePower<=0x1D9D)//SNR>=25.6dB
3876 return 64;//
3877 else if (u16NoisePower<=0x2078)//SNR>=25.2dB
3878 return 63;//
3879 else if (u16NoisePower<=0x239A)//SNR>=24.8dB
3880 return 62;//
3881 else if (u16NoisePower<=0x270A)//SNR>=24.4dB
3882 return 61;//
3883 else if (u16NoisePower<=0x2ACE)//SNR>=24.0dB
3884 return 60;//
3885 else if (u16NoisePower<=0x2EEF)//SNR>=23.6dB
3886 return 59;//
3887 else if (u16NoisePower<=0x3376)//SNR>=23.2dB
3888 return 58;//
3889 else if (u16NoisePower<=0x386D)//SNR>=22.8dB
3890 return 57;//
3891 else if (u16NoisePower<=0x3DDF)//SNR>=22.4dB
3892 return 56;//
3893 else if (u16NoisePower<=0x43D7)//SNR>=22.0dB
3894 return 55;//
3895 else if (u16NoisePower<=0x4A63)//SNR>=21.6dB
3896 return 54;//
3897 else if (u16NoisePower<=0x5190)//SNR>=21.2dB
3898 return 53;//
3899 else if (u16NoisePower<=0x596E)//SNR>=20.8dB
3900 return 52;//
3901 else if (u16NoisePower<=0x620F)//SNR>=20.4dB
3902 return 51;//
3903 else if (u16NoisePower<=0x6B85)//SNR>=20.0dB
3904 return 50;//
3905 else if (u16NoisePower<=0x75E5)//SNR>=19.6dB
3906 return 49;//
3907 else if (u16NoisePower<=0x8144)//SNR>=19.2dB
3908 return 48;//
3909 else if (u16NoisePower<=0x8DBD)//SNR>=18.8dB
3910 return 47;//
3911 else if (u16NoisePower<=0x9B6A)//SNR>=18.4dB
3912 return 46;//
3913 else if (u16NoisePower<=0xAA68)//SNR>=18.0dB
3914 return 45;//
3915 else if (u16NoisePower<=0xBAD9)//SNR>=17.6dB
3916 return 44;//
3917 else if (u16NoisePower<=0xCCE0)//SNR>=17.2dB
3918 return 43;//
3919 else if (u16NoisePower<=0xE0A4)//SNR>=16.8dB
3920 return 42;//
3921 else if (u16NoisePower<=0xF650)//SNR>=16.4dB
3922 return 41;//
3923 else// if (u16NoisePower>=0xF650)//SNR<16.4dB
3924 return 40;//
3925 }
3926 }
3927 }
3928
3929 #ifdef UTPA2
_HAL_INTERN_ATSC_GET_QAM_SNR(MS_U16 * pNoisepower,MS_U32 * pSym_num)3930 static MS_BOOL _HAL_INTERN_ATSC_GET_QAM_SNR(MS_U16 *pNoisepower, MS_U32 *pSym_num)
3931 #else
3932 static MS_BOOL _HAL_INTERN_ATSC_GET_QAM_SNR(float *f_snr)
3933 #endif
3934 {
3935 MS_U8 u8Data = 0;
3936 MS_U16 noisepower = 0;
3937
3938 if (_HAL_INTERN_ATSC_QAM_Main_Lock())
3939 {
3940 // latch
3941 _MBX_WriteReg(0x2905, 0x80);
3942 // read noise power
3943 _MBX_ReadReg(0x2A45, &u8Data);
3944 noisepower = u8Data;
3945 _MBX_ReadReg(0x2A44, &u8Data);
3946 noisepower = (noisepower<<8)|u8Data;
3947 // unlatch
3948 _MBX_WriteReg(0x2905, 0x00);
3949
3950 if (noisepower == 0x0000)
3951 noisepower = 0x0001;
3952
3953 #ifdef UTPA2
3954 *pNoisepower = noisepower;
3955 *pSym_num = 65536;
3956 #else
3957 #ifdef MSOS_TYPE_LINUX
3958 *f_snr = 10.0f*log10f(65536.0f/(float)noisepower);
3959 #else
3960 *f_snr = 10.0f*Log10Approx(65536.0f/(float)noisepower);
3961 #endif
3962 #endif
3963 }
3964 else
3965 {
3966 #ifdef UTPA2
3967 *pNoisepower = 0;
3968 *pSym_num = 0;
3969 #else
3970 *f_snr = 0.0f;
3971 #endif
3972 }
3973
3974 return TRUE;
3975 }
3976
_HAL_INTERN_ATSC_ReadPKTERR(void)3977 static MS_U16 _HAL_INTERN_ATSC_ReadPKTERR(void)
3978 {
3979 MS_U16 data = 0;
3980 MS_U8 reg = 0;
3981 DMD_ATSC_DEMOD_TYPE eMode;
3982
3983 eMode = _HAL_INTERN_ATSC_Check8VSB64_256QAM();
3984
3985 if (eMode == DMD_ATSC_DEMOD_ATSC_VSB)
3986 {
3987 if (!_HAL_INTERN_ATSC_Vsb_FEC_Lock()) data = 0;
3988 else
3989 {
3990 #if (DMD_ATSC_CHIP_VERSION < DMD_ATSC_CHIP_A1)
3991 _MBX_ReadReg(0x2B20, ®);
3992 data = reg;
3993 _MBX_ReadReg(0x2B21, ®);
3994 data = (data << 8)|reg;
3995 #else
3996 _MBX_ReadReg(0x1F67, ®);
3997 data = reg;
3998 _MBX_ReadReg(0x1F66, ®);
3999 data = (data << 8)|reg;
4000 #endif
4001 }
4002 }
4003 else
4004 {
4005 if (!_HAL_INTERN_ATSC_QAM_Main_Lock()) data = 0;
4006 else
4007 {
4008 #if (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_K3)
4009 _MBX_ReadReg(0x2166, ®);
4010 data = reg;
4011 _MBX_ReadReg(0x2167, ®);
4012 data = (data << 8)|reg;
4013 #elif (DMD_ATSC_CHIP_VERSION < DMD_ATSC_CHIP_A1)
4014 _MBX_ReadReg(0x2B20, ®);
4015 data = reg;
4016 _MBX_ReadReg(0x2B21, ®);
4017 data = (data << 8)|reg;
4018 #else
4019 _MBX_ReadReg(0x1F66, ®);
4020 data = reg;
4021 _MBX_ReadReg(0x1F67, ®);
4022 data = (data << 8)|reg;
4023 #endif
4024 }
4025 }
4026
4027 return data;
4028 }
4029
4030 #ifdef UTPA2
_HAL_INTERN_ATSC_ReadBER(MS_U32 * pBitErr,MS_U16 * pError_window,MS_U32 * pWin_unit)4031 static MS_BOOL _HAL_INTERN_ATSC_ReadBER(MS_U32 *pBitErr, MS_U16 *pError_window, MS_U32 *pWin_unit)
4032 #else
4033 static MS_BOOL _HAL_INTERN_ATSC_ReadBER(float *pBer)
4034 #endif
4035 {
4036 MS_BOOL status = true;
4037 MS_U8 reg = 0, reg_frz = 0;
4038 MS_U16 BitErrPeriod;
4039 MS_U32 BitErr;
4040 DMD_ATSC_DEMOD_TYPE eMode;
4041
4042 eMode = _HAL_INTERN_ATSC_Check8VSB64_256QAM();
4043
4044 if (eMode == DMD_ATSC_DEMOD_ATSC_VSB)
4045 {
4046 if (!_HAL_INTERN_ATSC_Vsb_FEC_Lock())
4047 {
4048 #ifdef UTPA2
4049 *pBitErr = 0;
4050 *pError_window = 0;
4051 *pWin_unit = 0;
4052 #else
4053 *pBer = 0;
4054 #endif
4055 }
4056 else
4057 {
4058 _MBX_ReadReg(0x1F03, ®_frz);
4059 _MBX_WriteReg(0x1F03, reg_frz|0x03);
4060
4061 _MBX_ReadReg(0x1F47, ®);
4062 BitErrPeriod = reg;
4063 _MBX_ReadReg(0x1F46, ®);
4064 BitErrPeriod = (BitErrPeriod << 8)|reg;
4065
4066 status &= _MBX_ReadReg(0x1F6d, ®);
4067 BitErr = reg;
4068 status &= _MBX_ReadReg(0x1F6c, ®);
4069 BitErr = (BitErr << 8)|reg;
4070 status &= _MBX_ReadReg(0x1F6b, ®);
4071 BitErr = (BitErr << 8)|reg;
4072 status &= _MBX_ReadReg(0x1F6a, ®);
4073 BitErr = (BitErr << 8)|reg;
4074
4075 reg_frz=reg_frz&(~0x03);
4076 _MBX_WriteReg(0x1F03, reg_frz);
4077
4078 if (BitErrPeriod == 0 ) //protect 0
4079 BitErrPeriod = 1;
4080
4081 #ifdef UTPA2
4082 *pBitErr = BitErr;
4083 *pError_window = BitErrPeriod;
4084 *pWin_unit = 8*187*128;
4085 #else
4086 if (BitErr <=0 )
4087 *pBer = 0.5f / ((float)BitErrPeriod*8*187*128);
4088 else
4089 *pBer = (float)BitErr / ((float)BitErrPeriod*8*187*128);
4090 #endif
4091 }
4092 }
4093 else
4094 {
4095 if (!_HAL_INTERN_ATSC_QAM_Main_Lock())
4096 {
4097 #ifdef UTPA2
4098 *pBitErr = 0;
4099 *pError_window = 0;
4100 *pWin_unit = 0;
4101 #else
4102 *pBer = 0;
4103 #endif
4104 }
4105 else
4106 {
4107 #if (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_K3)
4108 _MBX_ReadReg(0x2103, ®_frz);
4109 _MBX_WriteReg(0x2103, reg_frz|0x03);
4110
4111 _MBX_ReadReg(0x2147, ®);
4112 BitErrPeriod = reg;
4113 _MBX_ReadReg(0x2146, ®);
4114 BitErrPeriod = (BitErrPeriod << 8)|reg;
4115
4116 status &= _MBX_ReadReg(0x216d, ®);
4117 BitErr = reg;
4118 status &= _MBX_ReadReg(0x216c, ®);
4119 BitErr = (BitErr << 8)|reg;
4120 status &= _MBX_ReadReg(0x216b, ®);
4121 BitErr = (BitErr << 8)|reg;
4122 status &= _MBX_ReadReg(0x216a, ®);
4123 BitErr = (BitErr << 8)|reg;
4124
4125 reg_frz=reg_frz&(~0x03);
4126 _MBX_WriteReg(0x2103, reg_frz);
4127
4128 if (BitErrPeriod == 0) //protect 0
4129 BitErrPeriod = 1;
4130
4131 #ifdef UTPA2
4132 *pBitErr = BitErr;
4133 *pError_window = BitErrPeriod;
4134 *pWin_unit = 8*188*128;
4135 #else
4136 if (BitErr <=0)
4137 *pBer = 0.5f / ((float)BitErrPeriod*8*188*128);
4138 else
4139 *pBer = (float)BitErr / ((float)BitErrPeriod*8*188*128);
4140 #endif
4141 #else // #if (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_K3)
4142 _MBX_ReadReg(0x1F03, ®_frz);
4143 _MBX_WriteReg(0x1F03, reg_frz|0x03);
4144
4145 _MBX_ReadReg(0x1F47, ®);
4146 BitErrPeriod = reg;
4147 _MBX_ReadReg(0x1F46, ®);
4148 BitErrPeriod = (BitErrPeriod << 8)|reg;
4149
4150 BitErr = reg;
4151 status &= _MBX_ReadReg(0x1F6c, ®);
4152 BitErr = (BitErr << 8)|reg;
4153 status &= _MBX_ReadReg(0x1F6b, ®);
4154 BitErr = (BitErr << 8)|reg;
4155 status &= _MBX_ReadReg(0x1F6a, ®);
4156 BitErr = (BitErr << 8)|reg;
4157
4158 reg_frz=reg_frz&(~0x03);
4159 _MBX_WriteReg(0x1F03, reg_frz);
4160
4161 if (BitErrPeriod == 0 ) //protect 0
4162 BitErrPeriod = 1;
4163
4164 #ifdef UTPA2
4165 *pBitErr = BitErr;
4166 *pError_window = BitErrPeriod;
4167 *pWin_unit = 7*122*128;
4168 #else
4169 if (BitErr <=0 )
4170 *pBer = 0.5f / ((float)BitErrPeriod*7*122*128);
4171 else
4172 *pBer = (float)BitErr / ((float)BitErrPeriod*7*122*128);
4173 #endif
4174 #endif // #if (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_K3)
4175 }
4176 }
4177
4178 return status;
4179 }
4180
4181 #ifdef UTPA2
_HAL_INTERN_ATSC_ReadFrequencyOffset(MS_U8 * pMode,MS_S16 * pFF,MS_S16 * pRate)4182 static MS_BOOL _HAL_INTERN_ATSC_ReadFrequencyOffset(MS_U8 *pMode, MS_S16 *pFF, MS_S16 *pRate)
4183 #else
4184 static MS_S16 _HAL_INTERN_ATSC_ReadFrequencyOffset(void)
4185 #endif
4186 {
4187 DMD_ATSC_DEMOD_TYPE eMode;
4188 MS_U8 u8PTK_LOOP_FF_R3=0, u8PTK_LOOP_FF_R2=0;
4189 MS_U8 u8PTK_RATE_2=0;
4190 MS_U8 u8AD_CRL_LOOP_VALUE0=0, u8AD_CRL_LOOP_VALUE1=0;
4191 MS_U8 u8MIX_RATE_0=0, u8MIX_RATE_1=0, u8MIX_RATE_2=0;
4192 MS_S16 PTK_LOOP_FF;
4193 MS_S16 AD_CRL_LOOP_VALUE;
4194 MS_S16 MIX_RATE;
4195 #ifndef UTPA2
4196 MS_S16 FreqOffset = 0; //kHz
4197 #endif
4198
4199 eMode = _HAL_INTERN_ATSC_Check8VSB64_256QAM();
4200
4201 #ifdef UTPA2
4202 *pMode = eMode;
4203 #endif
4204
4205 if (eMode == DMD_ATSC_DEMOD_ATSC_VSB) //VSB mode//
4206 {
4207 #if (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MASERATI || DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MACAN \
4208 || DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MAXIM)
4209 _MBX_WriteReg(0x177E, 0x01);
4210 _MBX_WriteReg(0x17E6, 0xff);
4211 _MBX_ReadReg(0x177C, &u8PTK_LOOP_FF_R2);
4212 _MBX_ReadReg(0x177D, &u8PTK_LOOP_FF_R3);
4213 _MBX_WriteReg(0x177E, 0x00);
4214 _MBX_WriteReg(0x17E6, 0xff);
4215 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MUSTANG)
4216 _MBX_WriteReg(0x047E, 0x01); //atsc_dmd
4217 _MBX_WriteReg(0x04E6, 0xff);
4218 _MBX_ReadReg(0x047C, &u8PTK_LOOP_FF_R2);
4219 _MBX_ReadReg(0x047D, &u8PTK_LOOP_FF_R3);
4220 _MBX_WriteReg(0x047E, 0x00);
4221 _MBX_WriteReg(0x04E6, 0xff);
4222 #else
4223 _MBX_WriteReg(0x297E, 0x01);
4224 _MBX_WriteReg(0x29E6, 0xff);
4225 _MBX_ReadReg(0x297C, &u8PTK_LOOP_FF_R2);
4226 _MBX_ReadReg(0x297D, &u8PTK_LOOP_FF_R3);
4227 _MBX_WriteReg(0x297E, 0x00);
4228 _MBX_WriteReg(0x29E6, 0xff);
4229 #endif
4230
4231 PTK_LOOP_FF = (u8PTK_LOOP_FF_R3<<8) | u8PTK_LOOP_FF_R2;
4232 #ifdef UTPA2
4233 *pFF = PTK_LOOP_FF;
4234 #else
4235 FreqOffset = (float)(-PTK_LOOP_FF*0.04768);
4236 #endif
4237
4238 #if (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MASERATI || DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MACAN \
4239 || DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MAXIM)
4240 _MBX_ReadReg(0x1782, &u8PTK_RATE_2);
4241 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MUSTANG)
4242 _MBX_ReadReg(0x0482, &u8PTK_RATE_2); //atsc_dmd
4243 #else
4244 _MBX_ReadReg(0x2982, &u8PTK_RATE_2);
4245 #endif
4246
4247 #ifdef UTPA2
4248 *pRate = u8PTK_RATE_2;
4249 #else
4250 if (u8PTK_RATE_2 == 0x07)
4251 FreqOffset = FreqOffset-100;
4252 else if (u8PTK_RATE_2 == 0x08)
4253 FreqOffset = FreqOffset-500;
4254 #endif
4255 }
4256 else //QAM MODE
4257 {
4258 #if (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_K3)
4259 _MBX_ReadReg(0x2A40, &u8AD_CRL_LOOP_VALUE0);
4260 _MBX_ReadReg(0x2A41, &u8AD_CRL_LOOP_VALUE1);
4261 _MBX_ReadReg(0x2758, &u8MIX_RATE_0);
4262 _MBX_ReadReg(0x2759, &u8MIX_RATE_1);
4263 _MBX_ReadReg(0x275A, &u8MIX_RATE_2);
4264
4265 AD_CRL_LOOP_VALUE = (u8AD_CRL_LOOP_VALUE1 << 8) | u8AD_CRL_LOOP_VALUE0;
4266 MIX_RATE = ((u8MIX_RATE_2 << 16) | (u8MIX_RATE_1 << 8) | u8MIX_RATE_0) >> 4;
4267
4268 #ifdef UTPA2
4269 *pMode |= 0x80;
4270 *pFF = AD_CRL_LOOP_VALUE;
4271 *pRate = MIX_RATE;
4272 #else
4273 if (eMode == DMD_ATSC_DEMOD_ATSC_256QAM) //256QAM//
4274 {
4275 FreqOffset = (float)(AD_CRL_LOOP_VALUE*0.0000199); //5.360537E6/2^28*1000
4276 }
4277 else if (eMode == DMD_ATSC_DEMOD_ATSC_64QAM)//64QAM//
4278 {
4279 FreqOffset = (float)(AD_CRL_LOOP_VALUE*0.0000188); //5.056941E6/2^21*1000
4280 }
4281
4282 FreqOffset = FreqOffset+(float)(MIX_RATE-0x3A07)/330.13018; //(0.001/25.41*2^27/16)???
4283 #endif
4284 #else // #if (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_K3)
4285 #if (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MASERATI || DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MACAN \
4286 || DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MAXIM)
4287 _MBX_ReadReg(0x1A04, &u8AD_CRL_LOOP_VALUE0);
4288 _MBX_ReadReg(0x1A05, &u8AD_CRL_LOOP_VALUE1);
4289 #else
4290 _MBX_ReadReg(0x2C04, &u8AD_CRL_LOOP_VALUE0);
4291 _MBX_ReadReg(0x2C05, &u8AD_CRL_LOOP_VALUE1);
4292 #endif
4293
4294 AD_CRL_LOOP_VALUE = (u8AD_CRL_LOOP_VALUE1<<8) | u8AD_CRL_LOOP_VALUE0;
4295
4296 #if (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MASERATI || DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MACAN \
4297 || DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MAXIM)
4298 _MBX_ReadReg(0x1704, &u8MIX_RATE_0);
4299 _MBX_ReadReg(0x1705, &u8MIX_RATE_1);
4300 _MBX_ReadReg(0x1706, &u8MIX_RATE_2);
4301 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MUSTANG)
4302 _MBX_ReadReg(0x0404, &u8MIX_RATE_0); //atsc_dmd
4303 _MBX_ReadReg(0x0405, &u8MIX_RATE_1);
4304 _MBX_ReadReg(0x0406, &u8MIX_RATE_2);
4305 #else
4306 _MBX_ReadReg(0x2904, &u8MIX_RATE_0);
4307 _MBX_ReadReg(0x2905, &u8MIX_RATE_1);
4308 _MBX_ReadReg(0x2906, &u8MIX_RATE_2);
4309 #endif
4310
4311 MIX_RATE = (u8MIX_RATE_2<<12)|(u8MIX_RATE_1<<4)|(u8MIX_RATE_0>>4);
4312
4313 #ifdef UTPA2
4314 *pFF = AD_CRL_LOOP_VALUE;
4315 *pRate = MIX_RATE;
4316 #else
4317 if (eMode == DMD_ATSC_DEMOD_ATSC_256QAM) //256QAM//
4318 {
4319 FreqOffset = (float)(AD_CRL_LOOP_VALUE*0.0025561); //5.360537E6/2^21*1000
4320 }
4321 else if (eMode == DMD_ATSC_DEMOD_ATSC_64QAM)//64QAM//
4322 {
4323 FreqOffset = (float)(AD_CRL_LOOP_VALUE*0.00241134); //5.056941E6/2^21*1000
4324 }
4325
4326 FreqOffset = FreqOffset+(float)(MIX_RATE-0x3D70)/2.62144; //(0.001/25*2^20/16)
4327 #endif
4328 #endif // #if (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_K3)
4329 }
4330
4331 #ifdef UTPA2
4332 return TRUE;
4333 #else
4334 return FreqOffset;
4335 #endif
4336 }
4337
_HAL_INTERN_ATSC_GetReg(MS_U16 u16Addr,MS_U8 * pu8Data)4338 static MS_BOOL _HAL_INTERN_ATSC_GetReg(MS_U16 u16Addr, MS_U8 *pu8Data)
4339 {
4340 return _MBX_ReadReg(u16Addr, pu8Data);
4341 }
4342
_HAL_INTERN_ATSC_SetReg(MS_U16 u16Addr,MS_U8 u8Data)4343 static MS_BOOL _HAL_INTERN_ATSC_SetReg(MS_U16 u16Addr, MS_U8 u8Data)
4344 {
4345 return _MBX_WriteReg(u16Addr, u8Data);
4346 }
4347
4348 //-------------------------------------------------------------------------------------------------
4349 // Global Functions
4350 //-------------------------------------------------------------------------------------------------
HAL_INTERN_ATSC_IOCTL_CMD(DMD_ATSC_HAL_COMMAND eCmd,void * pArgs)4351 MS_BOOL HAL_INTERN_ATSC_IOCTL_CMD(DMD_ATSC_HAL_COMMAND eCmd, void *pArgs)
4352 {
4353 MS_BOOL bResult = TRUE;
4354
4355 #if (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_K3)
4356 _SEL_DMD();
4357 #endif
4358
4359 switch(eCmd)
4360 {
4361 case DMD_ATSC_HAL_CMD_Exit:
4362 bResult = _HAL_INTERN_ATSC_Exit();
4363 break;
4364 case DMD_ATSC_HAL_CMD_InitClk:
4365 _HAL_INTERN_ATSC_InitClk(false);
4366 break;
4367 case DMD_ATSC_HAL_CMD_Download:
4368 bResult = _HAL_INTERN_ATSC_Download();
4369 break;
4370 case DMD_ATSC_HAL_CMD_FWVERSION:
4371 _HAL_INTERN_ATSC_FWVERSION();
4372 break;
4373 case DMD_ATSC_HAL_CMD_SoftReset:
4374 bResult = _HAL_INTERN_ATSC_SoftReset();
4375 break;
4376 case DMD_ATSC_HAL_CMD_SetVsbMode:
4377 bResult = _HAL_INTERN_ATSC_SetVsbMode();
4378 break;
4379 case DMD_ATSC_HAL_CMD_Set64QamMode:
4380 bResult = _HAL_INTERN_ATSC_Set64QamMode();
4381 break;
4382 case DMD_ATSC_HAL_CMD_Set256QamMode:
4383 bResult = _HAL_INTERN_ATSC_Set256QamMode();
4384 break;
4385 case DMD_ATSC_HAL_CMD_SetModeClean:
4386 bResult = _HAL_INTERN_ATSC_SetModeClean();
4387 break;
4388 case DMD_ATSC_HAL_CMD_Set_QAM_SR:
4389 break;
4390 case DMD_ATSC_HAL_CMD_Active:
4391 break;
4392 case DMD_ATSC_HAL_CMD_Check8VSB64_256QAM:
4393 *((DMD_ATSC_DEMOD_TYPE *)pArgs) = _HAL_INTERN_ATSC_Check8VSB64_256QAM();
4394 break;
4395 case DMD_ATSC_HAL_CMD_AGCLock:
4396 bResult = _HAL_INTERN_ATSC_Vsb_QAM_AGCLock();
4397 break;
4398 case DMD_ATSC_HAL_CMD_Vsb_PreLock:
4399 bResult = _HAL_INTERN_ATSC_Vsb_PreLock();
4400 break;
4401 case DMD_ATSC_HAL_CMD_Vsb_FSync_Lock:
4402 bResult = _HAL_INTERN_ATSC_Vsb_FSync_Lock();
4403 break;
4404 case DMD_ATSC_HAL_CMD_Vsb_CE_Lock:
4405 bResult = _HAL_INTERN_ATSC_Vsb_CE_Lock();
4406 break;
4407 case DMD_ATSC_HAL_CMD_Vsb_FEC_Lock:
4408 bResult = _HAL_INTERN_ATSC_Vsb_FEC_Lock();
4409 break;
4410 case DMD_ATSC_HAL_CMD_QAM_PreLock:
4411 bResult = _HAL_INTERN_ATSC_QAM_PreLock();
4412 break;
4413 case DMD_ATSC_HAL_CMD_QAM_Main_Lock:
4414 bResult = _HAL_INTERN_ATSC_QAM_Main_Lock();
4415 break;
4416 case DMD_ATSC_HAL_CMD_ReadIFAGC:
4417 *((MS_U16 *)pArgs) = _HAL_INTERN_ATSC_ReadIFAGC();
4418 break;
4419 case DMD_ATSC_HAL_CMD_CheckSignalCondition:
4420 _HAL_INTERN_ATSC_CheckSignalCondition((DMD_ATSC_SIGNAL_CONDITION *)pArgs);
4421 break;
4422 case DMD_ATSC_HAL_CMD_ReadSNRPercentage:
4423 *((MS_U8 *)pArgs) = _HAL_INTERN_ATSC_ReadSNRPercentage();
4424 break;
4425 case DMD_ATSC_HAL_CMD_GET_QAM_SNR:
4426 #ifdef UTPA2
4427 bResult = _HAL_INTERN_ATSC_GET_QAM_SNR(&((*((DMD_ATSC_SNR_DATA *)pArgs)).noisepower), &((*((DMD_ATSC_SNR_DATA *)pArgs)).sym_num));
4428 #else
4429 bResult = _HAL_INTERN_ATSC_GET_QAM_SNR((float *)pArgs);
4430 #endif
4431 break;
4432 case DMD_ATSC_HAL_CMD_ReadPKTERR:
4433 *((MS_U16 *)pArgs) = _HAL_INTERN_ATSC_ReadPKTERR();
4434 break;
4435 case DMD_ATSC_HAL_CMD_GetPreViterbiBer:
4436 break;
4437 case DMD_ATSC_HAL_CMD_GetPostViterbiBer:
4438 #ifdef UTPA2
4439 bResult = _HAL_INTERN_ATSC_ReadBER(&((*((DMD_ATSC_BER_DATA *)pArgs)).BitErr), &((*((DMD_ATSC_BER_DATA *)pArgs)).Error_window), &((*((DMD_ATSC_BER_DATA *)pArgs)).Win_unit));
4440 #else
4441 bResult = _HAL_INTERN_ATSC_ReadBER((float *)pArgs);
4442 #endif
4443 break;
4444 case DMD_ATSC_HAL_CMD_ReadFrequencyOffset:
4445 #ifdef UTPA2
4446 bResult = _HAL_INTERN_ATSC_ReadFrequencyOffset(&((*((DMD_ATSC_CFO_DATA *)pArgs)).Mode), &((*((DMD_ATSC_CFO_DATA *)pArgs)).FF), &((*((DMD_ATSC_CFO_DATA *)pArgs)).Rate));
4447 #else
4448 *((MS_S16 *)pArgs) = _HAL_INTERN_ATSC_ReadFrequencyOffset();
4449 #endif
4450 break;
4451 case DMD_ATSC_HAL_CMD_TS_INTERFACE_CONFIG:
4452 break;
4453 case DMD_ATSC_HAL_CMD_IIC_Bypass_Mode:
4454 break;
4455 case DMD_ATSC_HAL_CMD_SSPI_TO_GPIO:
4456 break;
4457 case DMD_ATSC_HAL_CMD_GPIO_GET_LEVEL:
4458 break;
4459 case DMD_ATSC_HAL_CMD_GPIO_SET_LEVEL:
4460 break;
4461 case DMD_ATSC_HAL_CMD_GPIO_OUT_ENABLE:
4462 break;
4463 case DMD_ATSC_HAL_CMD_GET_REG:
4464 bResult = _HAL_INTERN_ATSC_GetReg((*((DMD_ATSC_REG_DATA *)pArgs)).u16Addr, &((*((DMD_ATSC_REG_DATA *)pArgs)).u8Data));
4465 break;
4466 case DMD_ATSC_HAL_CMD_SET_REG:
4467 bResult = _HAL_INTERN_ATSC_SetReg((*((DMD_ATSC_REG_DATA *)pArgs)).u16Addr, (*((DMD_ATSC_REG_DATA *)pArgs)).u8Data);
4468 break;
4469 default:
4470 break;
4471 }
4472
4473 return bResult;
4474 }
4475
MDrv_DMD_ATSC_Initial_Hal_Interface(void)4476 MS_BOOL MDrv_DMD_ATSC_Initial_Hal_Interface(void)
4477 {
4478 return TRUE;
4479 }
4480