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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 #ifndef _INTERN_DVBC_H_ 96 #define _INTERN_DVBC_H_ 97 98 #ifdef _INTERN_DVBT_C_ 99 #define EXTSEL 100 #else 101 #define EXTSEL extern 102 #endif 103 104 #define NEW_TR_MODULE 105 //-------------------------------------------------------------------- 106 107 // #define DEMOD_DYNAMIC_SLAVE_ID_1 0x32 108 // #define DEMOD_DYNAMIC_SLAVE_ID_2 0x72 109 // #define DEMOD_DYNAMIC_SLAVE_ID_3 0xB2 110 // #define DEMOD_DYNAMIC_SLAVE_ID_4 0xF2 111 112 #define DEMOD_ADDR_H 0x00 113 #define DEMOD_ADDR_L 0x01 114 #define DEMOD_WRITE_REG 0x02 115 #define DEMOD_WRITE_REG_EX 0x03 116 #define DEMOD_READ_REG 0x04 117 #define DEMOD_RAM_CONTROL 0x05 118 119 #if 0//DTV_SCAN_AUTO_FINE_TUNE_ENABLE 120 //INTERN_DVBT_ Capture Range fix to 500K 121 #define DEMOD_CAPTURE_RANGE_500_K 500 122 #define DEMOD_CAPTURE_RANGE_SIZE DEMOD_CAPTURE_RANGE_500_K 123 #endif 124 125 #define MDrv_ReadByte(x) HAL_DMD_RIU_ReadByte(x) 126 #define MDrv_WriteByte(x,y) HAL_DMD_RIU_WriteByte(x,y) 127 128 #if 1 129 #define U8 MAPI_U8 130 #define U16 MAPI_U16 131 #define U32 MAPI_U32 132 #define BOOL MAPI_BOOL 133 #define BOOLEAN MAPI_BOOL 134 #if 0 135 #define BIT0 0x01 136 #define BIT1 0x02 137 #define BIT2 0x04 138 #define BIT3 0x08 139 #define BIT4 0x10 140 #define BIT5 0x20 141 #define BIT6 0x40 142 #define BIT7 0x80 143 #endif 144 #define BYTE MAPI_U8 145 146 #define WORD MAPI_WORD 147 #define E_RESULT_SUCCESS MAPI_TRUE 148 #define E_RESULT_FAILURE MAPI_FALSE 149 #define FUNCTION_RESULT MAPI_BOOL 150 151 152 153 154 #define INTERN_DVBC_TS_SERIAL_INVERSION 0 155 #define INTERN_DVBC_TS_PARALLEL_INVERSION 1 156 #define INTERN_DVBC_DTV_DRIVING_LEVEL 1 157 #define INTERN_DVBC_WEAK_SIGNAL_PICTURE_FREEZE_ENABLE 1 158 #endif 159 160 typedef enum 161 { 162 E_RF_QAM_MODE_16QAM = 0x00, ///< 16QAM 163 E_RF_QAM_MODE_32QAM = 0x01, ///< 32QAM 164 E_RF_QAM_MODE_64QAM = 0x02, ///< 64QAM 165 E_RF_QAM_MODE_128QAM = 0x03, ///< 128QAM 166 E_RF_QAM_MODE_256QAM = 0x04, ///< 256QAM 167 E_RF_QAM_MODE_INVALID ///< Invalid 168 } RF_CHANNEL_QAM_MODE; 169 170 #if 0 171 typedef enum 172 { 173 COFDM_FEC_LOCK, 174 COFDM_PSYNC_LOCK, 175 COFDM_TPS_LOCK, 176 COFDM_DCR_LOCK, 177 COFDM_AGC_LOCK, 178 COFDM_MODE_DET, 179 180 } COFDM_LOCK_STATUS; 181 182 //-------------------------------------------------------------------- 183 typedef enum 184 { 185 E_SYS_UNKOWN = -1, 186 E_SYS_DVBT, 187 E_SYS_DVBC, 188 E_SYS_ATSC, 189 E_SYS_VIF, 190 191 E_SYS_NUM 192 }E_SYSTEM; 193 194 typedef enum 195 { 196 CMD_SYSTEM_INIT = 0, 197 CMD_DAC_CALI, 198 CMD_DVBT_CONFIG, 199 CMD_DVBC_CONFIG, 200 CMD_VIF_CTRL, 201 CMD_FSM_CTRL, 202 CMD_INDIR_RREG, 203 CMD_INDIR_WREG, 204 CMD_GET_INFO, 205 CMD_TS_CTRL, 206 CMD_TUNED_VALUE, 207 208 CMD_MAX_NUM 209 }E_CMD_CODE; 210 211 typedef enum 212 { 213 pc_op_code = 0, 214 pc_if_freq, 215 pc_sound_sys, 216 pc_vif_vga_maximum_l, 217 pc_vif_vga_maximum_h, 218 pc_scan_mode, 219 pc_vif_top, 220 pc_gain_distribution_thr_l, 221 pc_gain_distribution_thr_h, 222 223 VIF_PARAM_MAX_NUM 224 }E_VIF_PARAM; 225 226 typedef enum 227 { 228 pc_system = 0, 229 230 SYS_PARAM_MAX_NUM 231 }E_SYS_PARAM; 232 233 typedef enum 234 { 235 SET_IF_FREQ = 0, 236 SET_SOUND_SYS, 237 VIF_INIT, 238 SET_VIF_HANDLER, 239 VIF_TOP_ADJUST, 240 241 VIF_CMD_MAX_NUM 242 }E_VIF_CMD; 243 244 typedef enum 245 { 246 TS_PARALLEL = 0, 247 TS_SERIAL = 1, 248 249 TS_MODE_MAX_NUM 250 }E_TS_MODE; 251 252 typedef enum 253 { 254 dac_op_code = 0, 255 dac_idac_ch0, 256 dac_idac_ch1, 257 258 DAC_PARAM_MAX_NUM 259 } 260 E_DAC_PARAM; 261 262 typedef enum 263 { 264 DAC_RUN_CALI = 0, 265 DAC_IDAC_ASSIGN, 266 267 DAC_CMD_MAX_NUM 268 } 269 E_DAC_CMD; 270 271 typedef enum 272 { 273 agc_ref_small, 274 agc_ref_large, 275 agc_ref_aci, 276 ripple_switch_th_l, 277 ripple_switch_th_h, 278 279 TUNED_PARAM_MAX_NUM 280 }E_TUNED_PARAM; 281 282 //@@++ Arki 20100125 283 typedef enum 284 { 285 TS_MODUL_MODE, 286 TS_FFX_VALUE, 287 TS_GUARD_INTERVAL, 288 TS_CODE_RATE, 289 290 TS_PARAM_MAX_NUM 291 }E_SIGNAL_TYPE; 292 //@@-- Arki 20100125 293 294 typedef struct 295 { 296 MS_U8 cmd_code; 297 MS_U8 param[64]; 298 } S_CMDPKTREG; 299 300 typedef enum 301 { 302 E_RF_QAM_MODE_16QAM = 0x00, ///< 16QAM 303 E_RF_QAM_MODE_32QAM = 0x01, ///< 32QAM 304 E_RF_QAM_MODE_64QAM = 0x02, ///< 64QAM 305 E_RF_QAM_MODE_128QAM = 0x03, ///< 128QAM 306 E_RF_QAM_MODE_256QAM = 0x04, ///< 256QAM 307 E_RF_QAM_MODE_INVALID ///< Invalid 308 } RF_CHANNEL_QAM_MODE; 309 310 typedef enum 311 { 312 S0_entry_num, 313 S10_PSYNC_fail_num, 314 S10_TPS_invalid_num, 315 S8_TPS_invalid_num, 316 S6_TPS_unlock_num, 317 S4_Mode_CP_unlock_num, 318 CCI_Tracking_lock_num, 319 CCI_Tracking_lock_p1_num, 320 CCI_Tracking_lock_p2_num, 321 S11_PSYNC_FAIL_LOCKED_num, 322 S11_PSYNC_FAIL_SEARCH_num, 323 lock_time_l, 324 lock_time_h, 325 hw_channel_length_l, 326 hw_channel_length_h, 327 sw_channel_length_l, 328 sw_channel_length_h, 329 sw_offset_SA_l, 330 sw_offset_SA_h, 331 sw_oneshot_peak_num, 332 CI_Indicator, 333 ACI_Indicator, 334 FD_coeff, 335 TD_coeff, 336 SNR_Select, 337 FsaMode, 338 InGI, 339 Fsa_Stop_Track, 340 short_echo_Det, 341 342 DBG_LIST_NUM 343 }DBG_table_type; 344 #endif 345 346 /* 347 // Move to Tuner_SSI.h 348 typedef enum 349 { 350 _QPSK = 0x0, 351 _16QAM = 0x1, 352 _64QAM = 0x2, 353 }E_CONSTEL; 354 355 typedef enum 356 { 357 _CR1Y2 = 0x0, 358 _CR2Y3 = 0x1, 359 _CR3Y4 = 0x2, 360 _CR5Y6 = 0x3, 361 _CR7Y8 = 0x4, 362 }E_CODERATE; 363 364 365 typedef struct 366 { 367 U8 constel; 368 U8 code_rate; 369 float cn_ref; 370 }S_SQI_CN_NORDIGP1_INTERN_DVBT; 371 372 typedef struct 373 { 374 float power_db; 375 U8 sar3_val; 376 }S_INTERN_DVBT_RFAGC_SSI; 377 378 typedef struct 379 { 380 float power_db; 381 U8 agc_val; 382 }S_INTERN_DVBT_IFAGC_SSI; 383 384 typedef struct 385 { 386 U8 constel; 387 U8 code_rate; 388 float p_ref; 389 }S_INTERN_DVBT_SSI_PREF; 390 391 typedef struct 392 { 393 float attn_db; 394 U8 agc_err; 395 }S_INTERN_DVBT_IFAGC_ERR; 396 */ 397 //-------------------------------------------------------------------- 398 typedef struct 399 { 400 MS_U8 cmd_code; 401 MS_U8 param[64]; 402 } S_CMDPKTREG; 403 404 typedef enum 405 { 406 TS_MODUL_MODE, 407 TS_FFX_VALUE, 408 TS_GUARD_INTERVAL, 409 TS_CODE_RATE, 410 411 TS_PARAM_MAX_NUM 412 }E_SIGNAL_TYPE; 413 414 typedef enum 415 { 416 CMD_SYSTEM_INIT = 0, 417 CMD_DAC_CALI, 418 CMD_DVBT_CONFIG, 419 CMD_DVBC_CONFIG, 420 CMD_VIF_CTRL, 421 CMD_FSM_CTRL, 422 CMD_INDIR_RREG, 423 CMD_INDIR_WREG, 424 CMD_GET_INFO, 425 CMD_TS_CTRL, 426 CMD_TUNED_VALUE, 427 428 CMD_MAX_NUM 429 }E_CMD_CODE; 430 431 typedef enum 432 { 433 TS_PARALLEL = 0, 434 TS_SERIAL = 1, 435 436 TS_MODE_MAX_NUM 437 }E_TS_MODE; 438 439 typedef enum 440 { 441 E_SYS_UNKOWN = -1, 442 E_SYS_DVBT, 443 E_SYS_DVBC, 444 E_SYS_ATSC, 445 E_SYS_VIF, 446 447 E_SYS_NUM 448 }E_SYSTEM; 449 //-------------------------------------------------------------------- 450 MS_BOOL INTERN_DVBC_Reset ( void ); 451 MS_BOOL INTERN_DVBC_Active(MS_BOOL bEnable); 452 MS_BOOL INTERN_DVBC_Cmd_Packet_Send(S_CMDPKTREG* pCmdPacket, MS_U8 param_cnt); 453 MS_BOOL INTERN_DVBC_Exit ( void ); 454 MS_BOOL INTERN_DVBC_Power_On_Initialization(MS_BOOL bRFAGCTristateEnable, MS_U8 u8ADCIQMode, MS_U8 u8PadSel, MS_BOOL bPGAEnable, MS_U8 u8PGAGain, const MS_U8 *u8DMD_DVBC_DSPRegInitExt, MS_U8 u8DMD_DVBC_DSPRegInitSize); 455 MS_U16 INTERN_DVBC_DSPReg_Init(const MS_U8 *u8DVBC_DSPReg, MS_U8 u8Size); 456 MS_BOOL INTERN_DVBC_Serial_Control(MS_BOOL bEnable, MS_U8 u8TSClk); 457 MS_BOOL INTERN_DVBC_Config(MS_U16 u16SymbolRate, DMD_DVBC_MODULATION_TYPE eQamMode, MS_U32 u32IFFreq, MS_BOOL bSpecInv, MS_BOOL bSerialTS, MS_U8 u8TSClk, MS_U16 *pu16_symbol_rate_list,MS_U8 u8_symbol_rate_list_num); 458 MS_BOOL INTERN_DVBC_Active(MS_BOOL bEnable); 459 MS_BOOL INTERN_DVBC_GetLock(DMD_DVBC_GETLOCK_TYPE eType, float fCurrRFPowerDbm, float fNoChannelRFPowerDbm, MS_U32 u32TimeInterval); 460 MS_BOOL INTERN_DVBC_GetSignalStrength(MS_U16 *strength, const DMD_DVBC_InitData *sDMD_DVBC_InitData, MS_U8 u8SarValue, float fRFPowerDbm); 461 MS_BOOL INTERN_DVBC_GetSignalQuality(MS_U16 *quality, const DMD_DVBC_InitData *sDMD_DVBC_InitData, MS_U8 u8SarValue, float fRFPowerDbm); 462 MS_BOOL INTERN_DVBC_GetPostViterbiBer(float *ber); 463 MS_BOOL INTERN_DVBC_GetPacketErr(MS_U16 *pktErr); 464 MS_BOOL INTERN_DVBC_GetSNR(float *f_snr); 465 MS_BOOL INTERN_DVBC_Get_CELL_ID(MS_U16 *cell_id); 466 // MS_BOOL INTERN_DVBC_Get_TPS_Parameter_Const( MS_U16 * TPS_parameter, E_SIGNAL_TYPE eSignalType); 467 MS_BOOL INTERN_DVBC_Version(MS_U16 *ver); 468 MS_BOOL INTERN_DVBC_GetCurrentSymbolRate(MS_U16 *u16SymbolRate); 469 MS_BOOL INTERN_DVBC_Get_FreqOffset(float *pFreqOff, MS_U8 u8BW); 470 MS_BOOL INTERN_DVBC_GetCurrentModulationType(DMD_DVBC_MODULATION_TYPE *pQAMMode); 471 void INTERN_DVBC_info(void); 472 MS_BOOL INTERN_DVBC_Show_AGC_Info(void); 473 //-------------------------------------------------------------------- 474 475 #define INTERN_DVBC_LOAD_FW_FROM_CODE_MEMORY 476 477 #undef EXTSEL 478 #endif 479 480