1 //<MStar Software>
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77 //<MStar Software>
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93 ////////////////////////////////////////////////////////////////////////////////
94
95
96 //-------------------------------------------------------------------------------------------------
97 // Include Files
98 //-------------------------------------------------------------------------------------------------
99
100 #ifndef MSOS_TYPE_LINUX_KERNEL
101 #include <stdio.h>
102 #include <math.h>
103 #endif
104
105 #include "drvDMD_ISDBT.h"
106
107 //-------------------------------------------------------------------------------------------------
108 // Driver Compiler Options
109 //-------------------------------------------------------------------------------------------------
110
111 #define DMD_ISDBT_CHIP_EULER 0x00
112 #define DMD_ISDBT_CHIP_NUGGET 0x01
113 #define DMD_ISDBT_CHIP_KAPPA 0x02
114 #define DMD_ISDBT_CHIP_EINSTEIN 0x03
115 #define DMD_ISDBT_CHIP_NAPOLI 0x04
116 #define DMD_ISDBT_CHIP_MONACO 0x05
117 #define DMD_ISDBT_CHIP_MIAMI 0x06
118 #define DMD_ISDBT_CHIP_MUJI 0x07
119 #define DMD_ISDBT_CHIP_MUNICH 0x08
120 #define DMD_ISDBT_CHIP_MANHATTAN 0x09
121 #define DMD_ISDBT_CHIP_MULAN 0x0A
122 #define DMD_ISDBT_CHIP_MESSI 0x0B
123 #define DMD_ISDBT_CHIP_MASERATI 0x0C
124 #define DMD_ISDBT_CHIP_KIWI 0x0D
125 #define DMD_ISDBT_CHIP_MACAN 0x0E
126 #define DMD_ISDBT_CHIP_MUSTANG 0x0F
127 #define DMD_ISDBT_CHIP_MAXIM 0x10
128 #define DMD_ISDBT_CHIP_MARLON 0x11
129 #define DMD_ISDBT_CHIP_KENTUCKY 0x12
130 #define DMD_ISDBT_CHIP_MAINZ 0x13
131 #if defined(CHIP_EULER)
132 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_EULER
133 #elif defined(CHIP_NUGGET)
134 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_NUGGET
135 #elif defined(CHIP_KAPPA)
136 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_KAPPA
137 #elif defined(CHIP_EINSTEIN)
138 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_EINSTEIN
139 #elif defined(CHIP_NAPOLI)
140 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_NAPOLI
141 #elif defined(CHIP_MIAMI)
142 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_MIAMI
143 #elif defined(CHIP_MUJI)
144 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_MUJI
145 #elif defined(CHIP_MUNICH)
146 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_MUNICH
147 #elif defined(CHIP_MANHATTAN)
148 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_MANHATTAN
149 #elif defined(CHIP_MULAN)
150 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_MULAN
151 #elif defined(CHIP_MESSI)
152 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_MESSI
153 #elif defined(CHIP_MASERATI)
154 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_MASERATI
155 #elif defined(CHIP_KIWI)
156 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_KIWI
157 #elif defined(CHIP_MACAN)
158 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_MACAN
159 #elif defined(CHIP_MUSTANG)
160 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_MUSTANG
161 #elif defined(CHIP_MAXIM)
162 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_MAXIM
163 #elif defined(CHIP_MARLON)
164 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_MARLON
165 #elif defined(CHIP_K5TN)
166 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_KENTUCKY
167 #elif defined(CHIP_MAINZ)
168 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_MAINZ
169 #else
170 #define DMD_ISDBT_CHIP_VERSION DMD_ISDBT_CHIP_EULER
171 #endif
172
173 //-------------------------------------------------------------------------------------------------
174 // Local Defines
175 //-------------------------------------------------------------------------------------------------
176 #if (DMD_ISDBT_CHIP_VERSION >= DMD_ISDBT_CHIP_MULAN)
177 #define DMD_ISDBT_TBVA_EN 1
178 #else
179 #define DMD_ISDBT_TBVA_EN 0
180 #endif
181 #define _RIU_READ_BYTE(addr) ( READ_BYTE(psDMD_ISDBT_ResData->sDMD_ISDBT_PriData.virtDMDBaseAddr + (addr) ) )
182 #define _RIU_WRITE_BYTE(addr, val) ( WRITE_BYTE(psDMD_ISDBT_ResData->sDMD_ISDBT_PriData.virtDMDBaseAddr + (addr), val) )
183
184 #define HAL_INTERN_ISDBT_DBINFO(y) //y
185 #ifndef MBRegBase
186 #define MBRegBase 0x112600UL
187 #endif
188 #ifndef MBRegBase_DMD1
189 #define MBRegBase_DMD1 0x112400UL
190 #endif
191 #ifndef DMDMcuBase
192 #define DMDMcuBase 0x103480UL
193 #endif
194
195 #if (DMD_ISDBT_CHIP_VERSION >= DMD_ISDBT_CHIP_MULAN) && (DMD_ISDBT_CHIP_VERSION != DMD_ISDBT_CHIP_MESSI) && (DMD_ISDBT_CHIP_VERSION != DMD_ISDBT_CHIP_MAINZ) && (DMD_ISDBT_CHIP_VERSION != DMD_ISDBT_CHIP_KIWI)
196 #define REG_ISDBT_LOCK_STATUS 0x11F5
197 #define ISDBT_TDP_REG_BASE 0x1400
198 #define ISDBT_FDP_REG_BASE 0x1500
199 #define ISDBT_FDPEXT_REG_BASE 0x1600
200 #define ISDBT_OUTER_REG_BASE 0x1700
201 #else
202 #define REG_ISDBT_LOCK_STATUS 0x36F5
203 #define ISDBT_TDP_REG_BASE 0x3700
204 #define ISDBT_FDP_REG_BASE 0x3800
205 #define ISDBT_FDPEXT_REG_BASE 0x3900
206 #define ISDBT_OUTER_REG_BASE 0x3A00
207 #endif
208
209 #if (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_EULER) || (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_NUGGET) || (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MUNICH)
210 #define ISDBT_MIU_CLIENTW_ADDR 0xF5
211 #define ISDBT_MIU_CLIENTR_ADDR 0xF5
212 #define ISDBT_MIU_CLIENTW_MASK 0x87
213 #define ISDBT_MIU_CLIENTR_MASK 0x87
214 #define ISDBT_MIU_CLIENTW_BIT_MASK 0x01
215 #define ISDBT_MIU_CLIENTR_BIT_MASK 0x02
216 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_EINSTEIN) || (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_NAPOLI) || (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MONACO) || \
217 (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MIAMI) || (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MUJI) || (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MANHATTAN) || \
218 (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MESSI)
219 #define ISDBT_MIU_CLIENTW_ADDR 0xF2
220 #define ISDBT_MIU_CLIENTR_ADDR 0xF2
221 #define ISDBT_MIU_CLIENTW_MASK 0x66
222 #define ISDBT_MIU_CLIENTR_MASK 0x66
223 #define ISDBT_MIU_CLIENTW_BIT_MASK 0x02
224 #define ISDBT_MIU_CLIENTR_BIT_MASK 0x04
225 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_KAPPA)
226 #define ISDBT_MIU_CLIENTW_ADDR 0xF1
227 #define ISDBT_MIU_CLIENTR_ADDR 0xF0
228 #define ISDBT_MIU_CLIENTW_MASK 0x47
229 #define ISDBT_MIU_CLIENTR_MASK 0x46
230 #define ISDBT_MIU_CLIENTW_BIT_MASK 0x02
231 #define ISDBT_MIU_CLIENTR_BIT_MASK 0x20
232 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_KIWI)
233 #define ISDBT_MIU_CLIENTW_ADDR 0xF1
234 #define ISDBT_MIU_CLIENTR_ADDR 0xF0
235 #define ISDBT_MIU_CLIENTW_MASK 0x47
236 #define ISDBT_MIU_CLIENTR_MASK 0x46
237 #define ISDBT_MIU_CLIENTW_BIT_MASK 0x04
238 #define ISDBT_MIU_CLIENTR_BIT_MASK 0x20
239 #endif
240 //-------------------------------------------------------------------------------------------------
241 // Local Variables
242 //-------------------------------------------------------------------------------------------------
243
244 const MS_U8 INTERN_ISDBT_table[] = {
245 #include "DMD_INTERN_ISDBT.dat"
246 };
247
248 #ifndef UTPA2
249 static const float _LogApproxTableX[80] =
250 { 1.00, 1.30, 1.69, 2.20, 2.86, 3.71, 4.83, 6.27, 8.16, 10.60, 13.79,
251 17.92, 23.30, 30.29, 39.37, 51.19, 66.54, 86.50, 112.46, 146.19,
252 190.05, 247.06, 321.18, 417.54, 542.80, 705.64, 917.33, 1192.53,
253 1550.29, 2015.38, 2620.00, 3405.99, 4427.79, 5756.13, 7482.97,
254 9727.86, 12646.22, 16440.08, 21372.11, 27783.74, 36118.86,
255 46954.52, 61040.88, 79353.15, 103159.09, 134106.82, 174338.86,
256 226640.52, 294632.68, 383022.48, 497929.22, 647307.99, 841500.39, 1093950.50,
257 1422135.65, 1848776.35, 2403409.25, 3124432.03, 4061761.64, 5280290.13,
258 6864377.17, 8923690.32, 11600797.42, 15081036.65, 19605347.64, 25486951.94,
259 33133037.52, 43072948.77, 55994833.40, 72793283.42, 94631268.45,
260 123020648.99, 159926843.68, 207904896.79, 270276365.82, 351359275.57,
261 456767058.24, 593797175.72, 771936328.43, 1003517226.96
262 };
263
264 static const float _LogApproxTableY[80] =
265 { 0.00, 0.11, 0.23, 0.34, 0.46, 0.57, 0.68, 0.80, 0.91, 1.03, 1.14, 1.25,
266 1.37, 1.48, 1.60, 1.71, 1.82, 1.94, 2.05, 2.16, 2.28, 2.39, 2.51, 2.62,
267 2.73, 2.85, 2.96, 3.08, 3.19, 3.30, 3.42, 3.53, 3.65, 3.76, 3.87, 3.99,
268 4.10, 4.22, 4.33, 4.44, 4.56, 4.67, 4.79, 4.90, 5.01, 5.13, 5.24, 5.36,
269 5.47, 5.58, 5.70, 5.81, 5.93, 6.04, 6.15, 6.27, 6.04, 6.15, 6.27, 6.38,
270 6.49, 6.61, 6.72, 6.84, 6.95, 7.06, 7.18, 7.29, 7.41, 7.52, 7.63, 7.75,
271 7.86, 7.98, 8.09, 8.20, 8.32, 8.43, 8.55, 8.66
272 };
273 #endif
274
275 //-------------------------------------------------------------------------------------------------
276 // Global Variables
277 //-------------------------------------------------------------------------------------------------
278
279 extern MS_U8 u8DMD_ISDBT_DMD_ID;
280
281 extern DMD_ISDBT_ResData *psDMD_ISDBT_ResData;
282
283 //-------------------------------------------------------------------------------------------------
284 // Local Functions
285 //-------------------------------------------------------------------------------------------------
286 #ifndef UTPA2
287
288 #ifndef MSOS_TYPE_LINUX
Log10Approx(float flt_x)289 static float Log10Approx(float flt_x)
290 {
291 MS_U8 indx = 0;
292
293 do {
294 if (flt_x < _LogApproxTableX[indx])
295 break;
296 indx++;
297 }while (indx < 79); //stop at indx = 80
298
299 return _LogApproxTableY[indx];
300 }
301 #endif
302
_CALCULATE_SQI(float fber)303 static MS_U16 _CALCULATE_SQI(float fber)
304 {
305 float flog_ber;
306 MS_U16 u16SQI;
307
308 #ifdef MSOS_TYPE_LINUX
309 flog_ber = (float)log10((double)fber);
310 #else
311 if (fber != 0.0)
312 flog_ber = (float)(-1.0*Log10Approx((double)(1.0 / fber)));
313 else
314 flog_ber = -8.0;//when fber=0 means u16SQI=100
315 #endif
316
317 //printf("dan fber = %f\n", fber);
318 //printf("dan flog_ber = %f\n", flog_ber);
319 // Part 2: transfer ber value to u16SQI value.
320 if (flog_ber <= ( - 7.0))
321 {
322 u16SQI = 100; //*quality = 100;
323 }
324 else if (flog_ber < -6.0)
325 {
326 u16SQI = (90+((( - 6.0) - flog_ber) / (( - 6.0) - ( - 7.0))*(100-90)));
327 }
328 else if (flog_ber < -5.5)
329 {
330 u16SQI = (80+((( - 5.5) - flog_ber) / (( - 5.5) - ( - 6.0))*(90-80)));
331 }
332 else if (flog_ber < -5.0)
333 {
334 u16SQI = (70+((( - 5.0) - flog_ber) / (( - 5.0) - ( - 5.5))*(80-70)));
335 }
336 else if (flog_ber < -4.5)
337 {
338 u16SQI = (60+((( - 4.5) - flog_ber) / (( -4.5) - ( - 5.0))*(70-50)));
339 }
340 else if (flog_ber < -4.0)
341 {
342 u16SQI = (50+((( - 4.0) - flog_ber) / (( - 4.0) - ( - 45))*(60-50)));
343 }
344 else if (flog_ber < -3.5)
345 {
346 u16SQI = (40+((( - 3.5) - flog_ber) / (( - 3.5) - ( - 4.0))*(50-40)));
347 }
348 else if (flog_ber < -3.0)
349 {
350 u16SQI = (30+((( - 3.0) - flog_ber) / (( - 3.0) - ( - 3.5))*(40-30)));
351 }
352 else if (flog_ber < -2.5)
353 {
354 u16SQI = (20+((( - 2.5) - flog_ber) / (( - 2.5) - ( -3.0))*(30-20)));
355 }
356 else if (flog_ber < -2.0)
357 {
358 u16SQI = (0+((( - 2.0) - flog_ber) / (( - 2.0) - ( - 2.5))*(20-0)));
359 }
360 else
361 {
362 u16SQI = 0;
363 }
364
365 return u16SQI;
366 }
367 #endif
368
_HAL_DMD_RIU_ReadByte(MS_U32 u32Addr)369 static MS_U8 _HAL_DMD_RIU_ReadByte(MS_U32 u32Addr)
370 {
371 return _RIU_READ_BYTE(((u32Addr) << 1) - ((u32Addr) & 1));
372 }
373
_HAL_DMD_RIU_WriteByte(MS_U32 u32Addr,MS_U8 u8Value)374 static void _HAL_DMD_RIU_WriteByte(MS_U32 u32Addr, MS_U8 u8Value)
375 {
376 _RIU_WRITE_BYTE(((u32Addr) << 1) - ((u32Addr) & 1), u8Value);
377 }
378
_HAL_DMD_RIU_WriteByteMask(MS_U32 u32Addr,MS_U8 u8Value,MS_U8 u8Mask)379 static void _HAL_DMD_RIU_WriteByteMask(MS_U32 u32Addr, MS_U8 u8Value, MS_U8 u8Mask)
380 {
381 _RIU_WRITE_BYTE((((u32Addr) <<1) - ((u32Addr) & 1)), (_RIU_READ_BYTE((((u32Addr) <<1) - ((u32Addr) & 1))) & ~(u8Mask)) | ((u8Value) & (u8Mask)));
382 }
383
_MBX_WriteReg(MS_U16 u16Addr,MS_U8 u8Data)384 static MS_BOOL _MBX_WriteReg(MS_U16 u16Addr, MS_U8 u8Data)
385 {
386 MS_U8 u8CheckCount;
387 MS_U8 u8CheckFlag = 0xFF;
388 MS_U32 u32MBRegBase = MBRegBase;
389
390 if (u8DMD_ISDBT_DMD_ID == 0)
391 u32MBRegBase = MBRegBase;
392 else if (u8DMD_ISDBT_DMD_ID == 1)
393 u32MBRegBase = MBRegBase_DMD1;
394
395 _HAL_DMD_RIU_WriteByte(u32MBRegBase + 0x00, (u16Addr&0xff));
396 _HAL_DMD_RIU_WriteByte(u32MBRegBase + 0x01, (u16Addr>>8));
397 _HAL_DMD_RIU_WriteByte(u32MBRegBase + 0x10, u8Data);
398 _HAL_DMD_RIU_WriteByte(u32MBRegBase + 0x1E, 0x01);
399
400 _HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, _HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)|0x02); // assert interrupt to VD MCU51
401 _HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, _HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)&(~0x02)); // de-assert interrupt to VD MCU51
402
403 for (u8CheckCount=0; u8CheckCount < 10; u8CheckCount++)
404 {
405 u8CheckFlag = _HAL_DMD_RIU_ReadByte(u32MBRegBase + 0x1E);
406 if ((u8CheckFlag&0x01)==0)
407 break;
408 MsOS_DelayTask(1);
409 }
410
411 if (u8CheckFlag&0x01)
412 {
413 printf("ERROR: ATSC INTERN DEMOD MBX WRITE TIME OUT!\n");
414 return FALSE;
415 }
416
417 return TRUE;
418 }
419
_MBX_ReadReg(MS_U16 u16Addr,MS_U8 * u8Data)420 static MS_BOOL _MBX_ReadReg(MS_U16 u16Addr, MS_U8 *u8Data)
421 {
422 MS_U8 u8CheckCount;
423 MS_U8 u8CheckFlag = 0xFF;
424 MS_U32 u32MBRegBase = MBRegBase;
425
426 if (u8DMD_ISDBT_DMD_ID == 0)
427 u32MBRegBase = MBRegBase;
428 else if (u8DMD_ISDBT_DMD_ID == 1)
429 u32MBRegBase = MBRegBase_DMD1;
430
431 _HAL_DMD_RIU_WriteByte(u32MBRegBase + 0x00, (u16Addr&0xff));
432 _HAL_DMD_RIU_WriteByte(u32MBRegBase + 0x01, (u16Addr>>8));
433 _HAL_DMD_RIU_WriteByte(u32MBRegBase + 0x1E, 0x02);
434
435 _HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, _HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)|0x02); // assert interrupt to VD MCU51
436 _HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, _HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)&(~0x02)); // de-assert interrupt to VD MCU51
437
438 for (u8CheckCount=0; u8CheckCount < 10; u8CheckCount++)
439 {
440 u8CheckFlag = _HAL_DMD_RIU_ReadByte(u32MBRegBase + 0x1E);
441 if ((u8CheckFlag&0x02)==0)
442 {
443 *u8Data = _HAL_DMD_RIU_ReadByte(u32MBRegBase + 0x10);
444 break;
445 }
446 MsOS_DelayTask(1);
447 }
448
449 if (u8CheckFlag&0x02)
450 {
451 printf("ERROR: ATSC INTERN DEMOD MBX READ TIME OUT!\n");
452 return FALSE;
453 }
454
455 return TRUE;
456 }
457
458
459
460 #if (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_EULER)
_HAL_INTERN_ISDBT_InitClk(void)461 static void _HAL_INTERN_ISDBT_InitClk(void)
462 {
463 HAL_INTERN_ISDBT_DBINFO(printf("--------------DMD_ISDBT_CHIP_EULER--------------\n"));
464
465 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
466
467 // Init by HKMCU
468 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
469 _HAL_DMD_RIU_WriteByte(0x103301, 0x06);
470 _HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
471 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
472 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
473 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
474 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
475
476 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
477 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
478 _HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
479 _HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
480 _HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
481 _HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
482 _HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
483 _HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
484 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
485 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
486 _HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
487 _HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
488 _HAL_DMD_RIU_WriteByte(0x111f43, 0x00);
489 _HAL_DMD_RIU_WriteByte(0x111f42, 0x00);
490 _HAL_DMD_RIU_WriteByte(0x111f45, 0x00);
491 _HAL_DMD_RIU_WriteByte(0x111f44, 0x00);
492 _HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
493 _HAL_DMD_RIU_WriteByte(0x111f48, 0x00);
494 _HAL_DMD_RIU_WriteByte(0x111f4b, 0x00);
495 _HAL_DMD_RIU_WriteByte(0x111f4a, 0x00);
496 _HAL_DMD_RIU_WriteByte(0x111f4c, 0x00);
497 _HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
498 _HAL_DMD_RIU_WriteByte(0x111f22, 0x44);
499
500 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
501 }
502 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_NUGGET)
_HAL_INTERN_ISDBT_InitClk(void)503 static void _HAL_INTERN_ISDBT_InitClk(void)
504 {
505 MS_U8 u8Val = 0;
506
507 HAL_INTERN_ISDBT_DBINFO(printf("--------------DMD_ISDBT_CHIP_NUGGET--------------\n"));
508
509 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
510
511 // Init by HKMCU
512 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
513 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
514 _HAL_DMD_RIU_WriteByte(0x103301, 0x06);
515 _HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
516 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
517 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
518 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
519 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
520 _HAL_DMD_RIU_WriteByte(0x111f28, 0x03);
521
522 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
523 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
524 _HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
525 _HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
526 _HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
527 _HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
528 _HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
529 _HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
530 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
531 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
532 _HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
533 _HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
534 _HAL_DMD_RIU_WriteByte(0x111f43, 0x00);
535 _HAL_DMD_RIU_WriteByte(0x111f42, 0x00);
536 _HAL_DMD_RIU_WriteByte(0x111f45, 0x00);
537 _HAL_DMD_RIU_WriteByte(0x111f44, 0x00);
538 _HAL_DMD_RIU_WriteByte(0x111f46, 0x01);
539 _HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
540 _HAL_DMD_RIU_WriteByte(0x111f48, 0x00);
541 _HAL_DMD_RIU_WriteByte(0x111f4b, 0x00);
542 _HAL_DMD_RIU_WriteByte(0x111f4a, 0x00);
543 _HAL_DMD_RIU_WriteByte(0x111f4c, 0x00);
544 _HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
545 _HAL_DMD_RIU_WriteByte(0x111f22, 0x44);
546
547 u8Val = _HAL_DMD_RIU_ReadByte(0x1006F5);
548 _HAL_DMD_RIU_WriteByte(0x1006F5, (u8Val & ~0x03));
549
550 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
551 }
552 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_KAPPA)
_HAL_INTERN_ISDBT_InitClk(void)553 static void _HAL_INTERN_ISDBT_InitClk(void)
554 {
555 HAL_INTERN_ISDBT_DBINFO(printf("--------------DMD_ISDBT_CHIP_KAPPA--------------\n"));
556
557 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
558
559 // Init by HKMCU
560 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
561 _HAL_DMD_RIU_WriteByte(0x103301, 0x06);
562 _HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
563 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
564 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
565 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
566 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
567
568 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
569 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
570 _HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
571 _HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
572 _HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
573 _HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
574 _HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
575 _HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
576 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
577 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
578 _HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
579 _HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
580 _HAL_DMD_RIU_WriteByte(0x111f43, 0x00);
581 _HAL_DMD_RIU_WriteByte(0x111f42, 0x00);
582 _HAL_DMD_RIU_WriteByte(0x111f45, 0x00);
583 _HAL_DMD_RIU_WriteByte(0x111f44, 0x00);
584 _HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
585 _HAL_DMD_RIU_WriteByte(0x111f48, 0x00);
586 _HAL_DMD_RIU_WriteByte(0x111f4b, 0x00);
587 _HAL_DMD_RIU_WriteByte(0x111f4a, 0x00);
588 _HAL_DMD_RIU_WriteByte(0x111f4c, 0x00);
589 _HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
590 _HAL_DMD_RIU_WriteByte(0x111f22, 0x44);
591
592 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
593 }
594 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_EINSTEIN)
_HAL_INTERN_ISDBT_InitClk(void)595 static void _HAL_INTERN_ISDBT_InitClk(void)
596 {
597 MS_U8 u8Val = 0;
598
599 HAL_INTERN_ISDBT_DBINFO(printf("--------------DMD_ISDBT_CHIP_EINSTEIN--------------\n"));
600
601 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
602
603 // Init by HKMCU
604 u8Val = _HAL_DMD_RIU_ReadByte(0x11208E); //dan add to clear bit 0
605 u8Val &= ~0x01;
606 _HAL_DMD_RIU_WriteByte(0x11208E, u8Val);
607
608 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
609 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
610 _HAL_DMD_RIU_WriteByte(0x103301, 0x06);
611 _HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
612 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
613 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
614 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
615 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
616 _HAL_DMD_RIU_WriteByte(0x111f28, 0x03);
617
618 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
619 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
620 _HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
621 _HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
622 _HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
623 _HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
624 _HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
625 _HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
626 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
627 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
628 _HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
629 _HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
630 _HAL_DMD_RIU_WriteByte(0x111f43, 0x00);
631 _HAL_DMD_RIU_WriteByte(0x111f42, 0x00);
632 _HAL_DMD_RIU_WriteByte(0x111f45, 0x00);
633 _HAL_DMD_RIU_WriteByte(0x111f44, 0x00);
634 _HAL_DMD_RIU_WriteByte(0x111f46, 0x01);
635 _HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
636 _HAL_DMD_RIU_WriteByte(0x111f48, 0x00);
637 _HAL_DMD_RIU_WriteByte(0x111f4b, 0x00);
638 _HAL_DMD_RIU_WriteByte(0x111f4a, 0x00);
639 _HAL_DMD_RIU_WriteByte(0x111f4c, 0x00);
640 _HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
641 _HAL_DMD_RIU_WriteByte(0x111f22, 0x44);
642
643 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
644 }
645 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_NAPOLI)
_HAL_INTERN_ISDBT_InitClk(void)646 static MS_BOOL _HAL_INTERN_ISDBT_InitClk(void) /* Ok */
647 {
648 MS_U8 u8Val = 0;
649
650 HAL_INTERN_ISDBT_DBINFO(printf("--------------DMD_ISDBT_CHIP_NAPOLI--------------\n"));
651
652 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
653
654 // Init by HKMCU
655 u8Val = _HAL_DMD_RIU_ReadByte(0x11208E); //dan add to clear bit 0
656 u8Val &= ~0x01;
657 _HAL_DMD_RIU_WriteByte(0x11208E, u8Val);
658
659 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
660 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
661 _HAL_DMD_RIU_WriteByte(0x103301, 0x06); //ts clock = 7.2M
662 _HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
663 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
664 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
665 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
666 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
667 _HAL_DMD_RIU_WriteByte(0x111f28, 0x03);
668
669 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
670 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
671 _HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
672 _HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
673 _HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
674 _HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
675 _HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
676 _HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
677 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
678 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
679 _HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
680 _HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
681 _HAL_DMD_RIU_WriteByte(0x111f43, 0x00);
682 _HAL_DMD_RIU_WriteByte(0x111f42, 0x00);
683 _HAL_DMD_RIU_WriteByte(0x111f45, 0x00);
684 _HAL_DMD_RIU_WriteByte(0x111f44, 0x00);
685 _HAL_DMD_RIU_WriteByte(0x111f46, 0x01);
686 _HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
687 _HAL_DMD_RIU_WriteByte(0x111f48, 0x00);
688 _HAL_DMD_RIU_WriteByte(0x111f4b, 0x00);
689 _HAL_DMD_RIU_WriteByte(0x111f4a, 0x00);
690 _HAL_DMD_RIU_WriteByte(0x111f4c, 0x00);
691 _HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
692 _HAL_DMD_RIU_WriteByte(0x111f22, 0x44);
693
694 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
695 }
696 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MONACO)
_HAL_INTERN_ISDBT_InitClk(void)697 static void _HAL_INTERN_ISDBT_InitClk(void)
698 {
699 MS_U8 u8Val = 0;
700
701 HAL_INTERN_ISDBT_DBINFO(printf("--------------DMD_ISDBT_CHIP_MONACO--------------\n"));
702
703 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
704
705 // Init by HKMCU
706 u8Val = _HAL_DMD_RIU_ReadByte(0x11208E); //dan add to clear bit 0
707 u8Val &= ~0x01;
708 _HAL_DMD_RIU_WriteByte(0x11208E, u8Val);
709
710 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
711 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
712 _HAL_DMD_RIU_WriteByte(0x103301, 0x06); //ts clock = 7.2M
713 _HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
714 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
715 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
716 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
717 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
718
719 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
720 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
721 _HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
722 _HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
723 _HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
724 _HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
725 _HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
726 _HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
727 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
728 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
729 _HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
730 _HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
731 _HAL_DMD_RIU_WriteByte(0x111f43, 0x00);
732 _HAL_DMD_RIU_WriteByte(0x111f42, 0x00);
733 _HAL_DMD_RIU_WriteByte(0x111f45, 0x00);
734 _HAL_DMD_RIU_WriteByte(0x111f44, 0x00);
735 _HAL_DMD_RIU_WriteByte(0x111f46, 0x01);
736 _HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
737 _HAL_DMD_RIU_WriteByte(0x111f48, 0x00);
738 _HAL_DMD_RIU_WriteByte(0x111f4b, 0x00);
739 _HAL_DMD_RIU_WriteByte(0x111f4a, 0x00);
740 _HAL_DMD_RIU_WriteByte(0x111f4c, 0x00);
741 _HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
742 _HAL_DMD_RIU_WriteByte(0x111f22, 0x44);
743 _HAL_DMD_RIU_WriteByte(0x111f71, 0x14);
744 _HAL_DMD_RIU_WriteByte(0x111f70, 0x41);
745 _HAL_DMD_RIU_WriteByte(0x111f77, 0x00);
746 _HAL_DMD_RIU_WriteByte(0x111f76, 0x00);
747
748 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
749 }
750 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MIAMI)
_HAL_INTERN_ISDBT_InitClk(void)751 static void _HAL_INTERN_ISDBT_InitClk(void)
752 {
753 HAL_INTERN_ISDBT_DBINFO(printf("--------------DMD_ISDBT_CHIP_MIAMI--------------\n"));
754
755 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
756
757 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
758 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
759 _HAL_DMD_RIU_WriteByte(0x103301, 0x06); //ts clock = 7.2M
760 _HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
761 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
762 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
763 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
764 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
765
766 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
767 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
768 _HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
769 _HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
770 _HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
771 _HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
772 _HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
773 _HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
774 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
775 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
776 _HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
777 _HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
778 _HAL_DMD_RIU_WriteByte(0x111f43, 0x00);
779 _HAL_DMD_RIU_WriteByte(0x111f42, 0x00);
780 _HAL_DMD_RIU_WriteByte(0x111f45, 0x00);
781 _HAL_DMD_RIU_WriteByte(0x111f44, 0x00);
782 _HAL_DMD_RIU_WriteByte(0x111f46, 0x01);
783 _HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
784 _HAL_DMD_RIU_WriteByte(0x111f48, 0x00);
785 _HAL_DMD_RIU_WriteByte(0x111f4b, 0x00);
786 _HAL_DMD_RIU_WriteByte(0x111f4a, 0x00);
787 _HAL_DMD_RIU_WriteByte(0x111f4d, 0x00); //inner clock
788 _HAL_DMD_RIU_WriteByte(0x111f4c, 0x00);
789 _HAL_DMD_RIU_WriteByte(0x111f4e, 0x00); //outer clock
790 _HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
791 _HAL_DMD_RIU_WriteByte(0x111f22, 0x44);
792 _HAL_DMD_RIU_WriteByte(0x111f51, 0x00); //cci lms clock
793 _HAL_DMD_RIU_WriteByte(0x111f50, 0x88); //cci lms clock
794
795 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
796 }
797 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MUJI)
_HAL_INTERN_ISDBT_InitClk(void)798 static void _HAL_INTERN_ISDBT_InitClk(void)
799 {
800 HAL_INTERN_ISDBT_DBINFO(printf("--------------DMD_ISDBT_CHIP_MUJI--------------\n"));
801
802 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
803
804 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
805 _HAL_DMD_RIU_WriteByte(0x103301, 0x06); //ts clock = 7.2M
806 _HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
807 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
808 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
809 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
810 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
811 _HAL_DMD_RIU_WriteByte(0x103302, 0x01);
812 _HAL_DMD_RIU_WriteByte(0x103302, 0x00);
813
814 _HAL_DMD_RIU_WriteByte(0x111f29, 0x00);
815 _HAL_DMD_RIU_WriteByte(0x111f28, 0x10);
816 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
817 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
818 _HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
819 _HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
820 _HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
821 _HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
822 _HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
823 _HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
824 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
825 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
826 _HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
827 _HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
828 _HAL_DMD_RIU_WriteByte(0x111f43, 0x00);
829 _HAL_DMD_RIU_WriteByte(0x111f42, 0x00);
830 _HAL_DMD_RIU_WriteByte(0x111f45, 0x44);
831 _HAL_DMD_RIU_WriteByte(0x111f44, 0x44);
832 _HAL_DMD_RIU_WriteByte(0x111f46, 0x01);
833 _HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
834 _HAL_DMD_RIU_WriteByte(0x111f48, 0x00);
835 _HAL_DMD_RIU_WriteByte(0x111f4b, 0x00);
836 _HAL_DMD_RIU_WriteByte(0x111f4a, 0x00);
837 _HAL_DMD_RIU_WriteByte(0x111f4d, 0x00); //inner clock
838 _HAL_DMD_RIU_WriteByte(0x111f4c, 0x40);
839 _HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
840 _HAL_DMD_RIU_WriteByte(0x111f22, 0x44);
841 _HAL_DMD_RIU_WriteByte(0x111f71, 0x14);
842 _HAL_DMD_RIU_WriteByte(0x111f70, 0x41);
843 _HAL_DMD_RIU_WriteByte(0x111f77, 0x00);
844 _HAL_DMD_RIU_WriteByte(0x111f76, 0x00);
845 _HAL_DMD_RIU_WriteByte(0x111f4f, 0x01);
846 _HAL_DMD_RIU_WriteByte(0x111f4e, 0x00);
847 _HAL_DMD_RIU_WriteByte(0x112091, 0x46);
848 _HAL_DMD_RIU_WriteByte(0x112090, 0x00);
849
850 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
851 }
852 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MUNICH)
_HAL_INTERN_ISDBT_InitClk(void)853 static void _HAL_INTERN_ISDBT_InitClk(void)
854 {
855 HAL_INTERN_ISDBT_DBINFO(printf("--------------DMD_ISDBT_CHIP_MUNICH--------------\n"));
856
857 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
858
859 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
860 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
861 _HAL_DMD_RIU_WriteByte(0x103301, 0x06); //ts clock = 7.2M
862 _HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
863 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
864 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
865 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
866 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
867
868 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
869 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
870 _HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
871 _HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
872 _HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
873 _HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
874 _HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
875 _HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
876 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
877 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
878 _HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
879 _HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
880 _HAL_DMD_RIU_WriteByte(0x111f43, 0x00);
881 _HAL_DMD_RIU_WriteByte(0x111f42, 0x00);
882 _HAL_DMD_RIU_WriteByte(0x111f45, 0x00);
883 _HAL_DMD_RIU_WriteByte(0x111f44, 0x00);
884 _HAL_DMD_RIU_WriteByte(0x111f46, 0x01);
885 _HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
886 _HAL_DMD_RIU_WriteByte(0x111f48, 0x00);
887 _HAL_DMD_RIU_WriteByte(0x111f4b, 0x00);
888 _HAL_DMD_RIU_WriteByte(0x111f4a, 0x00);
889 _HAL_DMD_RIU_WriteByte(0x111f4d, 0x00); //inner clock
890 _HAL_DMD_RIU_WriteByte(0x111f4c, 0x00);
891 _HAL_DMD_RIU_WriteByte(0x111f4e, 0x00); //outer clock
892 _HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
893 _HAL_DMD_RIU_WriteByte(0x111f22, 0x44);
894 _HAL_DMD_RIU_WriteByte(0x111f51, 0x00); //cci lms clock
895 _HAL_DMD_RIU_WriteByte(0x111f50, 0x88); //cci lms clock
896
897 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
898 }
899 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MANHATTAN)
_HAL_INTERN_ISDBT_InitClk(void)900 static void _HAL_INTERN_ISDBT_InitClk(void)
901 {
902 HAL_INTERN_ISDBT_DBINFO(printf("--------------DMD_ISDBT_CHIP_MANHATTAN--------------\n"));
903
904 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
905
906 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
907 _HAL_DMD_RIU_WriteByte(0x103301, 0x06); //ts clock = 7.2M
908 _HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
909 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
910 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
911 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
912 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
913 _HAL_DMD_RIU_WriteByte(0x103302, 0x01);
914 _HAL_DMD_RIU_WriteByte(0x103302, 0x00);
915
916 _HAL_DMD_RIU_WriteByte(0x111f29, 0x00);
917 _HAL_DMD_RIU_WriteByte(0x111f28, 0x10);
918 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
919 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
920 _HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
921 _HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
922 _HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
923 _HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
924 _HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
925 _HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
926 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
927 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
928 _HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
929 _HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
930 _HAL_DMD_RIU_WriteByte(0x111f43, 0x00);
931 _HAL_DMD_RIU_WriteByte(0x111f42, 0x00);
932 _HAL_DMD_RIU_WriteByte(0x111f45, 0x44);
933 _HAL_DMD_RIU_WriteByte(0x111f44, 0x44);
934 _HAL_DMD_RIU_WriteByte(0x111f46, 0x01);
935 _HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
936 _HAL_DMD_RIU_WriteByte(0x111f48, 0x00);
937 _HAL_DMD_RIU_WriteByte(0x111f4b, 0x00);
938 _HAL_DMD_RIU_WriteByte(0x111f4a, 0x00);
939 _HAL_DMD_RIU_WriteByte(0x111f4d, 0x00); //inner clock
940 _HAL_DMD_RIU_WriteByte(0x111f4c, 0x40);
941 _HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
942 _HAL_DMD_RIU_WriteByte(0x111f22, 0x44);
943 _HAL_DMD_RIU_WriteByte(0x111f71, 0x14);
944 _HAL_DMD_RIU_WriteByte(0x111f70, 0x41);
945 _HAL_DMD_RIU_WriteByte(0x111f77, 0x00);
946 _HAL_DMD_RIU_WriteByte(0x111f76, 0x00);
947 _HAL_DMD_RIU_WriteByte(0x111f4f, 0x01);
948 _HAL_DMD_RIU_WriteByte(0x111f4e, 0x00);
949 _HAL_DMD_RIU_WriteByte(0x111f81, 0x44);
950 _HAL_DMD_RIU_WriteByte(0x111f80, 0x44);
951 _HAL_DMD_RIU_WriteByte(0x111f83, 0x44);
952 _HAL_DMD_RIU_WriteByte(0x111f82, 0x44);
953 _HAL_DMD_RIU_WriteByte(0x111f85, 0x44);
954 _HAL_DMD_RIU_WriteByte(0x111f84, 0x44);
955 _HAL_DMD_RIU_WriteByte(0x111f87, 0x44);
956 _HAL_DMD_RIU_WriteByte(0x111f86, 0x44);
957
958 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
959 }
960 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MULAN)
_HAL_INTERN_ISDBT_InitClk(void)961 static void _HAL_INTERN_ISDBT_InitClk(void)
962 {
963 HAL_INTERN_ISDBT_DBINFO(printf("--------------DMD_ISDBT_CHIP_MULAN--------------\n"));
964
965 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
966
967 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
968 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
969 _HAL_DMD_RIU_WriteByte(0x103301, 0x06); //ts clock = 7.2M
970 _HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
971 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
972 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
973 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
974 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
975 _HAL_DMD_RIU_WriteByte(0x103302, 0x01); //reset ts divider
976
977 _HAL_DMD_RIU_WriteByte(0x111f28, 0x10);
978 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
979 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
980 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
981 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
982 _HAL_DMD_RIU_WriteByte(0x111f25, 0x04);
983 _HAL_DMD_RIU_WriteByte(0x111f31, 0x00);
984 _HAL_DMD_RIU_WriteByte(0x111f30, 0x01);
985 _HAL_DMD_RIU_WriteByte(0x111f43, 0x80);
986 _HAL_DMD_RIU_WriteByte(0x111f42, 0x08);
987 _HAL_DMD_RIU_WriteByte(0x111f24, 0x05);
988 _HAL_DMD_RIU_WriteByte(0x111f45, 0x00);
989 _HAL_DMD_RIU_WriteByte(0x111f44, 0x00);
990 _HAL_DMD_RIU_WriteByte(0x111f63, 0x00);
991 _HAL_DMD_RIU_WriteByte(0x111f62, 0x00);
992 _HAL_DMD_RIU_WriteByte(0x111f65, 0x44);
993 _HAL_DMD_RIU_WriteByte(0x111f64, 0x44);
994 _HAL_DMD_RIU_WriteByte(0x111f66, 0x01);
995 _HAL_DMD_RIU_WriteByte(0x111f69, 0x00);
996 _HAL_DMD_RIU_WriteByte(0x111f68, 0x00);
997 _HAL_DMD_RIU_WriteByte(0x111f6b, 0x00);
998 _HAL_DMD_RIU_WriteByte(0x111f6a, 0x00);
999 _HAL_DMD_RIU_WriteByte(0x111f6d, 0x00);
1000 _HAL_DMD_RIU_WriteByte(0x111f6c, 0x40);
1001 _HAL_DMD_RIU_WriteByte(0x111f6f, 0x01);
1002 _HAL_DMD_RIU_WriteByte(0x111f6e, 0x00);
1003 _HAL_DMD_RIU_WriteByte(0x111f71, 0x44);
1004 _HAL_DMD_RIU_WriteByte(0x111f70, 0x44);
1005 _HAL_DMD_RIU_WriteByte(0x111f73, 0x00);
1006 _HAL_DMD_RIU_WriteByte(0x111f72, 0x04);
1007 _HAL_DMD_RIU_WriteByte(0x111f75, 0x44);
1008 _HAL_DMD_RIU_WriteByte(0x111f74, 0x44);
1009 _HAL_DMD_RIU_WriteByte(0x111f77, 0x44);
1010 _HAL_DMD_RIU_WriteByte(0x111f76, 0x44);
1011 _HAL_DMD_RIU_WriteByte(0x111f79, 0x44);
1012 _HAL_DMD_RIU_WriteByte(0x111f78, 0x44);
1013 _HAL_DMD_RIU_WriteByte(0x111f7b, 0x44);
1014 _HAL_DMD_RIU_WriteByte(0x111f7a, 0x44);
1015 _HAL_DMD_RIU_WriteByte(0x111f7d, 0x44);
1016 _HAL_DMD_RIU_WriteByte(0x111f7c, 0x44);
1017 _HAL_DMD_RIU_WriteByte(0x111f7f, 0x44);
1018 _HAL_DMD_RIU_WriteByte(0x111f7e, 0x44);
1019 _HAL_DMD_RIU_WriteByte(0x111fe1, 0x01);
1020 _HAL_DMD_RIU_WriteByte(0x111fe0, 0x88);
1021 _HAL_DMD_RIU_WriteByte(0x111fe3, 0x08);
1022 _HAL_DMD_RIU_WriteByte(0x111fe2, 0x10);
1023 _HAL_DMD_RIU_WriteByte(0x111feb, 0x11);
1024 _HAL_DMD_RIU_WriteByte(0x111fea, 0x00);
1025 _HAL_DMD_RIU_WriteByte(0x111fef, 0x00);
1026 _HAL_DMD_RIU_WriteByte(0x111fee, 0x88);
1027
1028 _HAL_DMD_RIU_WriteByte(0x103302, 0x00); //reset ts divider
1029
1030 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
1031 }
1032 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MESSI) || (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MAINZ)
_HAL_INTERN_ISDBT_InitClk(void)1033 static void _HAL_INTERN_ISDBT_InitClk(void)
1034 {
1035 #if (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MESSI)
1036 HAL_INTERN_ISDBT_DBINFO(printf("--------------DMD_ISDBT_CHIP_MESSI--------------\n"));
1037 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MAINZ)
1038 HAL_INTERN_ISDBT_DBINFO(printf("--------------DMD_ISDBT_CHIP_MAINZ--------------\n"));
1039 #endif
1040
1041 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
1042
1043 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
1044 _HAL_DMD_RIU_WriteByte(0x103301, 0x06); //ts clock = 7.2M
1045 _HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
1046 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
1047 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
1048 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
1049 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
1050 _HAL_DMD_RIU_WriteByte(0x103302, 0x01);
1051 _HAL_DMD_RIU_WriteByte(0x103302, 0x00);
1052
1053 _HAL_DMD_RIU_WriteByte(0x111f29, 0x00);
1054 _HAL_DMD_RIU_WriteByte(0x111f28, 0x10);
1055 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
1056 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
1057 _HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
1058 _HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
1059 _HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
1060 _HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
1061 _HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
1062 _HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
1063 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
1064 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
1065 _HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
1066 _HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
1067 _HAL_DMD_RIU_WriteByte(0x111f43, 0x00);
1068 _HAL_DMD_RIU_WriteByte(0x111f42, 0x00);
1069 _HAL_DMD_RIU_WriteByte(0x111f45, 0x44);
1070 _HAL_DMD_RIU_WriteByte(0x111f44, 0x44);
1071 _HAL_DMD_RIU_WriteByte(0x111f46, 0x01);
1072 _HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
1073 _HAL_DMD_RIU_WriteByte(0x111f48, 0x00);
1074 _HAL_DMD_RIU_WriteByte(0x111f4b, 0x00);
1075 _HAL_DMD_RIU_WriteByte(0x111f4a, 0x00);
1076 _HAL_DMD_RIU_WriteByte(0x111f4d, 0x00); //inner clock
1077 _HAL_DMD_RIU_WriteByte(0x111f4c, 0x40);
1078 _HAL_DMD_RIU_WriteByte(0x111f23, 0x04);
1079 _HAL_DMD_RIU_WriteByte(0x111f22, 0x44);
1080 _HAL_DMD_RIU_WriteByte(0x111f71, 0x14);
1081 _HAL_DMD_RIU_WriteByte(0x111f70, 0x41);
1082 _HAL_DMD_RIU_WriteByte(0x111f77, 0x00);
1083 _HAL_DMD_RIU_WriteByte(0x111f76, 0x00);
1084 _HAL_DMD_RIU_WriteByte(0x111f4f, 0x0C);
1085 _HAL_DMD_RIU_WriteByte(0x111f4e, 0x00);
1086 _HAL_DMD_RIU_WriteByte(0x111f51, 0x48);
1087 _HAL_DMD_RIU_WriteByte(0x111f50, 0x44);
1088 _HAL_DMD_RIU_WriteByte(0x111f81, 0x44);
1089 _HAL_DMD_RIU_WriteByte(0x111f80, 0x44);
1090 _HAL_DMD_RIU_WriteByte(0x111f83, 0x44);
1091 _HAL_DMD_RIU_WriteByte(0x111f82, 0x44);
1092 _HAL_DMD_RIU_WriteByte(0x111f85, 0x44);
1093 _HAL_DMD_RIU_WriteByte(0x111f84, 0x44);
1094 _HAL_DMD_RIU_WriteByte(0x111f87, 0x44);
1095 _HAL_DMD_RIU_WriteByte(0x111f86, 0x44);
1096 _HAL_DMD_RIU_WriteByte(0x111f89, 0x44);
1097 _HAL_DMD_RIU_WriteByte(0x111f88, 0x44);
1098 _HAL_DMD_RIU_WriteByte(0x111f8b, 0x00);
1099 _HAL_DMD_RIU_WriteByte(0x111f8a, 0x44);
1100 _HAL_DMD_RIU_WriteByte(0x111f8d, 0x18);
1101 _HAL_DMD_RIU_WriteByte(0x111f8c, 0x44);
1102 _HAL_DMD_RIU_WriteByte(0x111f8f, 0x00);
1103 _HAL_DMD_RIU_WriteByte(0x111f8e, 0x44);
1104
1105 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
1106 }
1107
1108 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MASERATI)
_HAL_INTERN_ISDBT_InitClk(void)1109 static void _HAL_INTERN_ISDBT_InitClk(void)
1110 {
1111 HAL_INTERN_ISDBT_DBINFO(printf("--------------DMD_ISDBT_CHIP_MASERATI--------------\n"));
1112
1113 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
1114
1115 _HAL_DMD_RIU_WriteByte(0x1128d0, 0x01);
1116 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
1117 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
1118 _HAL_DMD_RIU_WriteByte(0x103301, 0x06); //ts clock = 7.2M
1119 _HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
1120 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
1121 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
1122 _HAL_DMD_RIU_WriteByte(0x103302, 0x01);
1123 _HAL_DMD_RIU_WriteByte(0x103302, 0x00);
1124
1125 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
1126 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
1127 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
1128 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
1129 _HAL_DMD_RIU_WriteByte(0x1128d0, 0x00);
1130 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
1131 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
1132 _HAL_DMD_RIU_WriteByte(0x111f25, 0x04);
1133 _HAL_DMD_RIU_WriteByte(0x111f31, 0x00);
1134 _HAL_DMD_RIU_WriteByte(0x111f30, 0x01);
1135 _HAL_DMD_RIU_WriteByte(0x111f3b, 0x00);
1136 _HAL_DMD_RIU_WriteByte(0x111f3a, 0x00);
1137 _HAL_DMD_RIU_WriteByte(0x111f43, 0x80);
1138 _HAL_DMD_RIU_WriteByte(0x111f42, 0x08);
1139 _HAL_DMD_RIU_WriteByte(0x111f45, 0x04);
1140 _HAL_DMD_RIU_WriteByte(0x111f44, 0x44);
1141 _HAL_DMD_RIU_WriteByte(0x111f63, 0x00);
1142 _HAL_DMD_RIU_WriteByte(0x111f62, 0x00);
1143 _HAL_DMD_RIU_WriteByte(0x111f65, 0x44);
1144 _HAL_DMD_RIU_WriteByte(0x111f64, 0x44);
1145 _HAL_DMD_RIU_WriteByte(0x111f66, 0x01);
1146 _HAL_DMD_RIU_WriteByte(0x111f69, 0x00);
1147 _HAL_DMD_RIU_WriteByte(0x111f68, 0x00);
1148 _HAL_DMD_RIU_WriteByte(0x111f6b, 0x00);
1149 _HAL_DMD_RIU_WriteByte(0x111f6a, 0x00);
1150 _HAL_DMD_RIU_WriteByte(0x111f6d, 0x00);
1151 _HAL_DMD_RIU_WriteByte(0x111f6c, 0x40);
1152 _HAL_DMD_RIU_WriteByte(0x111f6f, 0x01);
1153 _HAL_DMD_RIU_WriteByte(0x111f6e, 0x00);
1154 _HAL_DMD_RIU_WriteByte(0x111f71, 0x44);
1155 _HAL_DMD_RIU_WriteByte(0x111f70, 0x44);
1156 _HAL_DMD_RIU_WriteByte(0x111f73, 0x00);
1157 _HAL_DMD_RIU_WriteByte(0x111f72, 0x04);
1158 _HAL_DMD_RIU_WriteByte(0x111f75, 0x44);
1159 _HAL_DMD_RIU_WriteByte(0x111f74, 0x44);
1160 _HAL_DMD_RIU_WriteByte(0x111f77, 0x44);
1161 _HAL_DMD_RIU_WriteByte(0x111f76, 0x44);
1162 _HAL_DMD_RIU_WriteByte(0x111f79, 0x44);
1163 _HAL_DMD_RIU_WriteByte(0x111f78, 0x44);
1164 _HAL_DMD_RIU_WriteByte(0x111f7b, 0x44);
1165 _HAL_DMD_RIU_WriteByte(0x111f7a, 0x44);
1166 _HAL_DMD_RIU_WriteByte(0x111f7d, 0x44);
1167 _HAL_DMD_RIU_WriteByte(0x111f7c, 0x44);
1168 _HAL_DMD_RIU_WriteByte(0x111f7f, 0x44);
1169 _HAL_DMD_RIU_WriteByte(0x111f7e, 0x44);
1170 _HAL_DMD_RIU_WriteByte(0x111fe1, 0x01);
1171 _HAL_DMD_RIU_WriteByte(0x111fe0, 0x08);
1172 _HAL_DMD_RIU_WriteByte(0x111ff0, 0x08);
1173 _HAL_DMD_RIU_WriteByte(0x111fe3, 0x08);
1174 _HAL_DMD_RIU_WriteByte(0x111fe2, 0x10);
1175 _HAL_DMD_RIU_WriteByte(0x111feb, 0x11);
1176 _HAL_DMD_RIU_WriteByte(0x111fea, 0x00);
1177 _HAL_DMD_RIU_WriteByte(0x111fef, 0x00);
1178 _HAL_DMD_RIU_WriteByte(0x111fee, 0x88);
1179 _HAL_DMD_RIU_WriteByte(0x15298f, 0x44);
1180 _HAL_DMD_RIU_WriteByte(0x15298e, 0x44);
1181 _HAL_DMD_RIU_WriteByte(0x152991, 0x44);
1182 _HAL_DMD_RIU_WriteByte(0x152990, 0x44);
1183 _HAL_DMD_RIU_WriteByte(0x152992, 0x04);
1184 _HAL_DMD_RIU_WriteByte(0x1529e5, 0x00);
1185 _HAL_DMD_RIU_WriteByte(0x1529e4, 0x04);
1186 _HAL_DMD_RIU_WriteByte(0x152971, 0x10);
1187 _HAL_DMD_RIU_WriteByte(0x152970, 0x01);
1188
1189 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
1190 }
1191 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MACAN)
_HAL_INTERN_ISDBT_InitClk(void)1192 static void _HAL_INTERN_ISDBT_InitClk(void)
1193 {
1194 HAL_INTERN_ISDBT_DBINFO(printf("--------------DMD_ISDBT_CHIP_MACAN--------------\n"));
1195
1196 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
1197
1198 _HAL_DMD_RIU_WriteByte(0x1128d0, 0x01);
1199 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
1200 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
1201 _HAL_DMD_RIU_WriteByte(0x103301, 0x06); //ts clock = 7.2M
1202 _HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
1203 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
1204 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
1205 _HAL_DMD_RIU_WriteByte(0x103302, 0x01);
1206 _HAL_DMD_RIU_WriteByte(0x103302, 0x00);
1207
1208 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
1209 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
1210 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
1211 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
1212 _HAL_DMD_RIU_WriteByte(0x1128d0, 0x00);
1213 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
1214 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
1215 _HAL_DMD_RIU_WriteByte(0x111f25, 0x04);
1216 _HAL_DMD_RIU_WriteByte(0x111f31, 0x00);
1217 _HAL_DMD_RIU_WriteByte(0x111f30, 0x01);
1218 _HAL_DMD_RIU_WriteByte(0x111f3b, 0x00);
1219 _HAL_DMD_RIU_WriteByte(0x111f3a, 0x00);
1220 _HAL_DMD_RIU_WriteByte(0x111f43, 0x80);
1221 _HAL_DMD_RIU_WriteByte(0x111f42, 0x08);
1222 _HAL_DMD_RIU_WriteByte(0x111f45, 0x04);
1223 _HAL_DMD_RIU_WriteByte(0x111f44, 0x44);
1224 _HAL_DMD_RIU_WriteByte(0x111f63, 0x00);
1225 _HAL_DMD_RIU_WriteByte(0x111f62, 0x00);
1226 _HAL_DMD_RIU_WriteByte(0x111f65, 0x44);
1227 _HAL_DMD_RIU_WriteByte(0x111f64, 0x44);
1228 _HAL_DMD_RIU_WriteByte(0x111f66, 0x01);
1229 _HAL_DMD_RIU_WriteByte(0x111f69, 0x00);
1230 _HAL_DMD_RIU_WriteByte(0x111f68, 0x00);
1231 _HAL_DMD_RIU_WriteByte(0x111f6b, 0x00);
1232 _HAL_DMD_RIU_WriteByte(0x111f6a, 0x00);
1233 _HAL_DMD_RIU_WriteByte(0x111f6d, 0x00);
1234 _HAL_DMD_RIU_WriteByte(0x111f6c, 0x40);
1235 _HAL_DMD_RIU_WriteByte(0x111f6f, 0x01);
1236 _HAL_DMD_RIU_WriteByte(0x111f6e, 0x00);
1237 _HAL_DMD_RIU_WriteByte(0x111f71, 0x44);
1238 _HAL_DMD_RIU_WriteByte(0x111f70, 0x44);
1239 _HAL_DMD_RIU_WriteByte(0x111f73, 0x00);
1240 _HAL_DMD_RIU_WriteByte(0x111f72, 0x04);
1241 _HAL_DMD_RIU_WriteByte(0x111f75, 0x44);
1242 _HAL_DMD_RIU_WriteByte(0x111f74, 0x44);
1243 _HAL_DMD_RIU_WriteByte(0x111f77, 0x44);
1244 _HAL_DMD_RIU_WriteByte(0x111f76, 0x44);
1245 _HAL_DMD_RIU_WriteByte(0x111f79, 0x44);
1246 _HAL_DMD_RIU_WriteByte(0x111f78, 0x44);
1247 _HAL_DMD_RIU_WriteByte(0x111f7b, 0x44);
1248 _HAL_DMD_RIU_WriteByte(0x111f7a, 0x44);
1249 _HAL_DMD_RIU_WriteByte(0x111f7d, 0x44);
1250 _HAL_DMD_RIU_WriteByte(0x111f7c, 0x44);
1251 _HAL_DMD_RIU_WriteByte(0x111f7f, 0x44);
1252 _HAL_DMD_RIU_WriteByte(0x111f7e, 0x44);
1253 _HAL_DMD_RIU_WriteByte(0x111fe1, 0x01);
1254 _HAL_DMD_RIU_WriteByte(0x111fe0, 0x08);
1255 _HAL_DMD_RIU_WriteByte(0x111ff0, 0x08);
1256 _HAL_DMD_RIU_WriteByte(0x111fe3, 0x08);
1257 _HAL_DMD_RIU_WriteByte(0x111fe2, 0x10);
1258 _HAL_DMD_RIU_WriteByte(0x111feb, 0x11);
1259 _HAL_DMD_RIU_WriteByte(0x111fea, 0x00);
1260 _HAL_DMD_RIU_WriteByte(0x111fef, 0x00);
1261 _HAL_DMD_RIU_WriteByte(0x111fee, 0x88);
1262 _HAL_DMD_RIU_WriteByte(0x15298f, 0x44);
1263 _HAL_DMD_RIU_WriteByte(0x15298e, 0x44);
1264 _HAL_DMD_RIU_WriteByte(0x152991, 0x44);
1265 _HAL_DMD_RIU_WriteByte(0x152990, 0x44);
1266 _HAL_DMD_RIU_WriteByte(0x152992, 0x04);
1267 _HAL_DMD_RIU_WriteByte(0x1529e5, 0x00);
1268 _HAL_DMD_RIU_WriteByte(0x1529e4, 0x04);
1269 _HAL_DMD_RIU_WriteByte(0x152971, 0x10);
1270 _HAL_DMD_RIU_WriteByte(0x152970, 0x01);
1271
1272 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
1273 }
1274 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MUSTANG)
_HAL_INTERN_ISDBT_InitClk(void)1275 static void _HAL_INTERN_ISDBT_InitClk(void)
1276 {
1277 HAL_INTERN_ISDBT_DBINFO(printf("--------------DMD_ISDBT_CHIP_MUSTANG--------------\n"));
1278
1279 // SRAM End Address
1280 _HAL_DMD_RIU_WriteByte(0x111707,0xff);
1281 _HAL_DMD_RIU_WriteByte(0x111706,0xff);
1282
1283 // DRAM Disable
1284 _HAL_DMD_RIU_WriteByte(0x111718,_HAL_DMD_RIU_ReadByte(0x111718)&(~0x04));
1285
1286 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
1287
1288 _HAL_DMD_RIU_WriteByte(0x1128d0, 0x01);
1289 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
1290 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
1291 _HAL_DMD_RIU_WriteByte(0x103301, 0x06); //ts clock = 7.2M
1292 _HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
1293 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
1294 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
1295 _HAL_DMD_RIU_WriteByte(0x103302, 0x01);
1296 _HAL_DMD_RIU_WriteByte(0x103302, 0x00);
1297
1298 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
1299 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
1300 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
1301 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
1302 _HAL_DMD_RIU_WriteByte(0x1128d0, 0x00);
1303 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
1304 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
1305 _HAL_DMD_RIU_WriteByte(0x111f25, 0x04);
1306 _HAL_DMD_RIU_WriteByte(0x111f31, 0x00);
1307 _HAL_DMD_RIU_WriteByte(0x111f30, 0x01);
1308 _HAL_DMD_RIU_WriteByte(0x111f3b, 0x00);
1309 _HAL_DMD_RIU_WriteByte(0x111f3a, 0x00);
1310 _HAL_DMD_RIU_WriteByte(0x111f43, 0x80);
1311 _HAL_DMD_RIU_WriteByte(0x111f42, 0x08);
1312 _HAL_DMD_RIU_WriteByte(0x111f45, 0x04);
1313 _HAL_DMD_RIU_WriteByte(0x111f44, 0x44);
1314 _HAL_DMD_RIU_WriteByte(0x111f63, 0x00);
1315 _HAL_DMD_RIU_WriteByte(0x111f62, 0x00);
1316 _HAL_DMD_RIU_WriteByte(0x111f65, 0x44);
1317 _HAL_DMD_RIU_WriteByte(0x111f64, 0x44);
1318 _HAL_DMD_RIU_WriteByte(0x111f66, 0x01);
1319 _HAL_DMD_RIU_WriteByte(0x111f69, 0x00);
1320 _HAL_DMD_RIU_WriteByte(0x111f68, 0x00);
1321 _HAL_DMD_RIU_WriteByte(0x111f6b, 0x00);
1322 _HAL_DMD_RIU_WriteByte(0x111f6a, 0x00);
1323 _HAL_DMD_RIU_WriteByte(0x111f6d, 0x00);
1324 _HAL_DMD_RIU_WriteByte(0x111f6c, 0x40);
1325 _HAL_DMD_RIU_WriteByte(0x111f6f, 0x01);
1326 _HAL_DMD_RIU_WriteByte(0x111f6e, 0x00);
1327 _HAL_DMD_RIU_WriteByte(0x111f71, 0x44);
1328 _HAL_DMD_RIU_WriteByte(0x111f70, 0x44);
1329 _HAL_DMD_RIU_WriteByte(0x111f73, 0x00);
1330 _HAL_DMD_RIU_WriteByte(0x111f72, 0x04);
1331 _HAL_DMD_RIU_WriteByte(0x111f75, 0x44);
1332 _HAL_DMD_RIU_WriteByte(0x111f74, 0x44);
1333 _HAL_DMD_RIU_WriteByte(0x111f77, 0x44);
1334 _HAL_DMD_RIU_WriteByte(0x111f76, 0x44);
1335 _HAL_DMD_RIU_WriteByte(0x111f79, 0x44);
1336 _HAL_DMD_RIU_WriteByte(0x111f78, 0x44);
1337 _HAL_DMD_RIU_WriteByte(0x111f7b, 0x44);
1338 _HAL_DMD_RIU_WriteByte(0x111f7a, 0x44);
1339 _HAL_DMD_RIU_WriteByte(0x111f7d, 0x44);
1340 _HAL_DMD_RIU_WriteByte(0x111f7c, 0x44);
1341 _HAL_DMD_RIU_WriteByte(0x111f7f, 0x44);
1342 _HAL_DMD_RIU_WriteByte(0x111f7e, 0x44);
1343 _HAL_DMD_RIU_WriteByte(0x111fe1, 0x01);
1344 _HAL_DMD_RIU_WriteByte(0x111fe0, 0x08);
1345 _HAL_DMD_RIU_WriteByte(0x111ff0, 0x08);
1346 _HAL_DMD_RIU_WriteByte(0x111fe3, 0x08);
1347 _HAL_DMD_RIU_WriteByte(0x111fe2, 0x10);
1348 _HAL_DMD_RIU_WriteByte(0x111feb, 0x11);
1349 _HAL_DMD_RIU_WriteByte(0x111fea, 0x00);
1350 _HAL_DMD_RIU_WriteByte(0x111fef, 0x00);
1351 _HAL_DMD_RIU_WriteByte(0x111fee, 0x88);
1352 _HAL_DMD_RIU_WriteByte(0x15298f, 0x44);
1353 _HAL_DMD_RIU_WriteByte(0x15298e, 0x44);
1354 _HAL_DMD_RIU_WriteByte(0x152991, 0x44);
1355 _HAL_DMD_RIU_WriteByte(0x152990, 0x44);
1356 _HAL_DMD_RIU_WriteByte(0x152992, 0x04);
1357 _HAL_DMD_RIU_WriteByte(0x1529e5, 0x00);
1358 _HAL_DMD_RIU_WriteByte(0x1529e4, 0x04);
1359 _HAL_DMD_RIU_WriteByte(0x152971, 0x10);
1360 _HAL_DMD_RIU_WriteByte(0x152970, 0x01);
1361
1362 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
1363 }
1364 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MAXIM)
_HAL_INTERN_ISDBT_InitClk(void)1365 static void _HAL_INTERN_ISDBT_InitClk(void)
1366 {
1367 HAL_INTERN_ISDBT_DBINFO(printf("--------------DMD_ISDBT_CHIP_MAXIM--------------\n"));
1368
1369 // SRAM End Address
1370 _HAL_DMD_RIU_WriteByte(0x111707,0xff);
1371 _HAL_DMD_RIU_WriteByte(0x111706,0xff);
1372
1373 // DRAM Disable
1374 _HAL_DMD_RIU_WriteByte(0x111718,_HAL_DMD_RIU_ReadByte(0x111718)&(~0x04));
1375
1376 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
1377
1378 _HAL_DMD_RIU_WriteByte(0x1128e5, 0x01); // DMD_ANA_ADC_SYNC CLK_W
1379 _HAL_DMD_RIU_WriteByte(0x1128e4, 0x01); // DMD_ANA_ADC_SYNC CLK_W
1380
1381 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
1382 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
1383 _HAL_DMD_RIU_WriteByte(0x103301, 0x06); //ts clock = 7.2M
1384 _HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
1385 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
1386 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
1387 //_HAL_DMD_RIU_WriteByte(0x103315, 0x00); //ADC SYNC FLOW
1388 //_HAL_DMD_RIU_WriteByte(0x103314, 0x00); //ADC SYNC FLOW
1389 _HAL_DMD_RIU_WriteByte(0x103302, 0x01);
1390 _HAL_DMD_RIU_WriteByte(0x103302, 0x00);
1391
1392 //_HAL_DMD_RIU_WriteByte(0x103321, 0x00); //Add in MAXIM //ADC SYNC FLOW
1393 //_HAL_DMD_RIU_WriteByte(0x103320, 0x00); //Add in MAXIM //ADC SYNC FLOW
1394
1395 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
1396 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
1397
1398 _HAL_DMD_RIU_WriteByte(0x103321, 0x00); //ADC_SYNC CLK_W / DMD_ANA_ADC_SYNC CLK_R
1399 _HAL_DMD_RIU_WriteByte(0x103320, 0x00); //ADC_SYNC CLK_W / DMD_ANA_ADC_SYNC CLK_R
1400
1401 _HAL_DMD_RIU_WriteByte(0x1128e4, 0x00); // DMD_ANA_ADC_SYNC CLK_W
1402
1403 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
1404 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
1405 _HAL_DMD_RIU_WriteByte(0x111f25, 0x04);
1406 _HAL_DMD_RIU_WriteByte(0x111f31, 0x00);
1407 _HAL_DMD_RIU_WriteByte(0x111f30, 0x01);
1408 _HAL_DMD_RIU_WriteByte(0x111f3b, 0x00);
1409 _HAL_DMD_RIU_WriteByte(0x111f3a, 0x00);
1410 _HAL_DMD_RIU_WriteByte(0x111f43, 0x80);
1411 _HAL_DMD_RIU_WriteByte(0x111f42, 0x08);
1412 _HAL_DMD_RIU_WriteByte(0x111f45, 0x04);
1413 _HAL_DMD_RIU_WriteByte(0x111f44, 0x44);
1414 _HAL_DMD_RIU_WriteByte(0x111f63, 0x00);
1415 _HAL_DMD_RIU_WriteByte(0x111f62, 0x00);
1416 _HAL_DMD_RIU_WriteByte(0x111f65, 0x44);
1417 _HAL_DMD_RIU_WriteByte(0x111f64, 0x44);
1418 _HAL_DMD_RIU_WriteByte(0x111f66, 0x01);
1419 _HAL_DMD_RIU_WriteByte(0x111f69, 0x00);
1420 _HAL_DMD_RIU_WriteByte(0x111f68, 0x00);
1421 _HAL_DMD_RIU_WriteByte(0x111f6b, 0x00);
1422 _HAL_DMD_RIU_WriteByte(0x111f6a, 0x00);
1423 _HAL_DMD_RIU_WriteByte(0x111f6d, 0x00);
1424 _HAL_DMD_RIU_WriteByte(0x111f6c, 0x40);
1425 _HAL_DMD_RIU_WriteByte(0x111f6f, 0x01);
1426 _HAL_DMD_RIU_WriteByte(0x111f6e, 0x00);
1427 _HAL_DMD_RIU_WriteByte(0x111f71, 0x44);
1428 _HAL_DMD_RIU_WriteByte(0x111f70, 0x44);
1429 _HAL_DMD_RIU_WriteByte(0x111f73, 0x00);
1430 _HAL_DMD_RIU_WriteByte(0x111f72, 0x04);
1431 _HAL_DMD_RIU_WriteByte(0x111f75, 0x44);
1432 _HAL_DMD_RIU_WriteByte(0x111f74, 0x44);
1433 _HAL_DMD_RIU_WriteByte(0x111f77, 0x44);
1434 _HAL_DMD_RIU_WriteByte(0x111f76, 0x44);
1435 _HAL_DMD_RIU_WriteByte(0x111f79, 0x44);
1436 _HAL_DMD_RIU_WriteByte(0x111f78, 0x44);
1437 _HAL_DMD_RIU_WriteByte(0x111f7b, 0x44);
1438 _HAL_DMD_RIU_WriteByte(0x111f7a, 0x44);
1439 _HAL_DMD_RIU_WriteByte(0x111f7d, 0x44);
1440 _HAL_DMD_RIU_WriteByte(0x111f7c, 0x44);
1441 _HAL_DMD_RIU_WriteByte(0x111f7f, 0x44);
1442 _HAL_DMD_RIU_WriteByte(0x111f7e, 0x44);
1443 _HAL_DMD_RIU_WriteByte(0x111fe1, 0x01);
1444 _HAL_DMD_RIU_WriteByte(0x111fe0, 0x08);
1445 _HAL_DMD_RIU_WriteByte(0x111ff0, 0x08);
1446 _HAL_DMD_RIU_WriteByte(0x111fe3, 0x08);
1447 _HAL_DMD_RIU_WriteByte(0x111fe2, 0x10);
1448 _HAL_DMD_RIU_WriteByte(0x111feb, 0x11);
1449 _HAL_DMD_RIU_WriteByte(0x111fea, 0x00);
1450 _HAL_DMD_RIU_WriteByte(0x111fef, 0x00);
1451 _HAL_DMD_RIU_WriteByte(0x111fee, 0x88);
1452 _HAL_DMD_RIU_WriteByte(0x15298f, 0x44);
1453 _HAL_DMD_RIU_WriteByte(0x15298e, 0x44);
1454 _HAL_DMD_RIU_WriteByte(0x152991, 0x44);
1455 _HAL_DMD_RIU_WriteByte(0x152990, 0x44);
1456 _HAL_DMD_RIU_WriteByte(0x152992, 0x04);
1457 _HAL_DMD_RIU_WriteByte(0x1529e5, 0x00);
1458 _HAL_DMD_RIU_WriteByte(0x1529e4, 0x04);
1459 _HAL_DMD_RIU_WriteByte(0x152971, 0x10);
1460 _HAL_DMD_RIU_WriteByte(0x152970, 0x01);
1461
1462 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
1463 //_HAL_DMD_RIU_WriteByteMask(0x103480, 0x00, 0x02);
1464 }
1465 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MARLON)
_HAL_INTERN_ISDBT_InitClk(void)1466 static void _HAL_INTERN_ISDBT_InitClk(void)
1467 {
1468 printf("--------------DMD_ISDBT_CHIP_MARLON--------------\n");
1469
1470 // SRAM End Address
1471 _HAL_DMD_RIU_WriteByte(0x111707,0xff);
1472 _HAL_DMD_RIU_WriteByte(0x111706,0xff);
1473
1474 // DRAM Disable
1475 _HAL_DMD_RIU_WriteByte(0x111718,_HAL_DMD_RIU_ReadByte(0x111718)&(~0x04));
1476
1477 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
1478
1479 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
1480 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
1481 _HAL_DMD_RIU_WriteByte(0x103301, 0x26); //ts clock = 7.2M
1482 _HAL_DMD_RIU_WriteByte(0x103300, 0x13);
1483 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
1484 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
1485 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
1486 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
1487 _HAL_DMD_RIU_WriteByte(0x103302, 0x01);
1488 _HAL_DMD_RIU_WriteByte(0x103302, 0x00);
1489
1490 //_HAL_DMD_RIU_WriteByte(0x103321, 0x00); //Add in MAXIM
1491 //_HAL_DMD_RIU_WriteByte(0x103320, 0x00); //Add in MAXIM
1492
1493 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
1494 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
1495 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
1496 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
1497 _HAL_DMD_RIU_WriteByte(0x111f25, 0x04);
1498 _HAL_DMD_RIU_WriteByte(0x111f31, 0x00);
1499 _HAL_DMD_RIU_WriteByte(0x111f30, 0x01);
1500 _HAL_DMD_RIU_WriteByte(0x111f3b, 0x00);
1501 _HAL_DMD_RIU_WriteByte(0x111f3a, 0x00);
1502 _HAL_DMD_RIU_WriteByte(0x111f43, 0x80);
1503 _HAL_DMD_RIU_WriteByte(0x111f42, 0x08);
1504 _HAL_DMD_RIU_WriteByte(0x111f45, 0x04);
1505 _HAL_DMD_RIU_WriteByte(0x111f44, 0x44);
1506 _HAL_DMD_RIU_WriteByte(0x111f63, 0x00);
1507 _HAL_DMD_RIU_WriteByte(0x111f62, 0x00);
1508 _HAL_DMD_RIU_WriteByte(0x111f65, 0x44);
1509 _HAL_DMD_RIU_WriteByte(0x111f64, 0x44);
1510 _HAL_DMD_RIU_WriteByte(0x111f66, 0x01);
1511 _HAL_DMD_RIU_WriteByte(0x111f69, 0x00);
1512 _HAL_DMD_RIU_WriteByte(0x111f68, 0x00);
1513 _HAL_DMD_RIU_WriteByte(0x111f6b, 0x00);
1514 _HAL_DMD_RIU_WriteByte(0x111f6a, 0x00);
1515 _HAL_DMD_RIU_WriteByte(0x111f6d, 0x00);
1516 _HAL_DMD_RIU_WriteByte(0x111f6c, 0x40);
1517 _HAL_DMD_RIU_WriteByte(0x111f6f, 0x01);
1518 _HAL_DMD_RIU_WriteByte(0x111f6e, 0x00);
1519 _HAL_DMD_RIU_WriteByte(0x111f71, 0x44);
1520 _HAL_DMD_RIU_WriteByte(0x111f70, 0x44);
1521 _HAL_DMD_RIU_WriteByte(0x111f73, 0x00);
1522 _HAL_DMD_RIU_WriteByte(0x111f72, 0x04);
1523 _HAL_DMD_RIU_WriteByte(0x111f75, 0x44);
1524 _HAL_DMD_RIU_WriteByte(0x111f74, 0x44);
1525 _HAL_DMD_RIU_WriteByte(0x111f77, 0x44);
1526 _HAL_DMD_RIU_WriteByte(0x111f76, 0x44);
1527 _HAL_DMD_RIU_WriteByte(0x111f79, 0x44);
1528 _HAL_DMD_RIU_WriteByte(0x111f78, 0x44);
1529 _HAL_DMD_RIU_WriteByte(0x111f7b, 0x44);
1530 _HAL_DMD_RIU_WriteByte(0x111f7a, 0x44);
1531 _HAL_DMD_RIU_WriteByte(0x111f7d, 0x44);
1532 _HAL_DMD_RIU_WriteByte(0x111f7c, 0x44);
1533 _HAL_DMD_RIU_WriteByte(0x111f7f, 0x44);
1534 _HAL_DMD_RIU_WriteByte(0x111f7e, 0x44);
1535 _HAL_DMD_RIU_WriteByte(0x111fe1, 0x01);
1536 _HAL_DMD_RIU_WriteByte(0x111fe0, 0x08);
1537 _HAL_DMD_RIU_WriteByte(0x111ff0, 0x08);
1538 _HAL_DMD_RIU_WriteByte(0x111fe3, 0x08);
1539 _HAL_DMD_RIU_WriteByte(0x111fe2, 0x10);
1540 _HAL_DMD_RIU_WriteByte(0x111feb, 0x11);
1541 _HAL_DMD_RIU_WriteByte(0x111fea, 0x00);
1542 _HAL_DMD_RIU_WriteByte(0x111fef, 0x00);
1543 _HAL_DMD_RIU_WriteByte(0x111fee, 0x88);
1544 _HAL_DMD_RIU_WriteByte(0x15298f, 0x44);
1545 _HAL_DMD_RIU_WriteByte(0x15298e, 0x44);
1546 _HAL_DMD_RIU_WriteByte(0x152991, 0x44);
1547 _HAL_DMD_RIU_WriteByte(0x152990, 0x44);
1548 _HAL_DMD_RIU_WriteByte(0x152992, 0x04);
1549 _HAL_DMD_RIU_WriteByte(0x1529e5, 0x00);
1550 _HAL_DMD_RIU_WriteByte(0x1529e4, 0x04);
1551 _HAL_DMD_RIU_WriteByte(0x152971, 0x10);
1552 _HAL_DMD_RIU_WriteByte(0x152970, 0x01);
1553
1554 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
1555 //_HAL_DMD_RIU_WriteByteMask(0x103480, 0x00, 0x02);
1556 }
1557 #elif (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_KENTUCKY)
_HAL_INTERN_ISDBT_InitClk(void)1558 static void _HAL_INTERN_ISDBT_InitClk(void)
1559 {
1560 HAL_INTERN_ISDBT_DBINFO(printf("--------------DMD_ISDBT_CHIP_KENTUCKY--------------\n"));
1561
1562 // SRAM End Address
1563 _HAL_DMD_RIU_WriteByte(0x163407,0xff);
1564 _HAL_DMD_RIU_WriteByte(0x163406,0xff);
1565
1566 // DRAM Disable
1567 _HAL_DMD_RIU_WriteByte(0x163418,_HAL_DMD_RIU_ReadByte(0x163418)&(~0x04));
1568
1569 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
1570
1571 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
1572 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
1573 _HAL_DMD_RIU_WriteByte(0x103301, 0x30); //ts clock = 7.2M
1574 _HAL_DMD_RIU_WriteByte(0x103300, 0x0b);
1575 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
1576 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
1577 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
1578 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
1579 _HAL_DMD_RIU_WriteByte(0x103302, 0x01);
1580 _HAL_DMD_RIU_WriteByte(0x103302, 0x00);
1581
1582 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
1583 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
1584 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
1585 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
1586 _HAL_DMD_RIU_WriteByte(0x111f25, 0x04);
1587 _HAL_DMD_RIU_WriteByte(0x111f31, 0x00);
1588 _HAL_DMD_RIU_WriteByte(0x111f30, 0x01);
1589 _HAL_DMD_RIU_WriteByte(0x111f3b, 0x00);
1590 _HAL_DMD_RIU_WriteByte(0x111f3a, 0x00);
1591 _HAL_DMD_RIU_WriteByte(0x111f43, 0x80);
1592 _HAL_DMD_RIU_WriteByte(0x111f42, 0x08);
1593 _HAL_DMD_RIU_WriteByte(0x111f45, 0x04);
1594 _HAL_DMD_RIU_WriteByte(0x111f44, 0x44);
1595 _HAL_DMD_RIU_WriteByte(0x111f63, 0x00);
1596 _HAL_DMD_RIU_WriteByte(0x111f62, 0x00);
1597 _HAL_DMD_RIU_WriteByte(0x111f65, 0x44);
1598 _HAL_DMD_RIU_WriteByte(0x111f64, 0x44);
1599 _HAL_DMD_RIU_WriteByte(0x111f66, 0x01);
1600 _HAL_DMD_RIU_WriteByte(0x111f69, 0x00);
1601 _HAL_DMD_RIU_WriteByte(0x111f68, 0x00);
1602 _HAL_DMD_RIU_WriteByte(0x111f6b, 0x00);
1603 _HAL_DMD_RIU_WriteByte(0x111f6a, 0x00);
1604 _HAL_DMD_RIU_WriteByte(0x111f6d, 0x00);
1605 _HAL_DMD_RIU_WriteByte(0x111f6c, 0x40);
1606 _HAL_DMD_RIU_WriteByte(0x111f6f, 0x01);
1607 _HAL_DMD_RIU_WriteByte(0x111f6e, 0x00);
1608 _HAL_DMD_RIU_WriteByte(0x111f71, 0x44);
1609 _HAL_DMD_RIU_WriteByte(0x111f70, 0x44);
1610 _HAL_DMD_RIU_WriteByte(0x111f73, 0x00);
1611 _HAL_DMD_RIU_WriteByte(0x111f72, 0x44);
1612 _HAL_DMD_RIU_WriteByte(0x111f75, 0x44);
1613 _HAL_DMD_RIU_WriteByte(0x111f74, 0x44);
1614 _HAL_DMD_RIU_WriteByte(0x111f77, 0x44);
1615 _HAL_DMD_RIU_WriteByte(0x111f76, 0x44);
1616 _HAL_DMD_RIU_WriteByte(0x111f79, 0x44);
1617 _HAL_DMD_RIU_WriteByte(0x111f78, 0x44);
1618 _HAL_DMD_RIU_WriteByte(0x111f7b, 0x44);
1619 _HAL_DMD_RIU_WriteByte(0x111f7a, 0x44);
1620 _HAL_DMD_RIU_WriteByte(0x111f7d, 0x44);
1621 _HAL_DMD_RIU_WriteByte(0x111f7c, 0x44);
1622 _HAL_DMD_RIU_WriteByte(0x111f7f, 0x44);
1623 _HAL_DMD_RIU_WriteByte(0x111f7e, 0x44);
1624 _HAL_DMD_RIU_WriteByte(0x111fe1, 0x01);
1625 _HAL_DMD_RIU_WriteByte(0x111fe0, 0x08);
1626 _HAL_DMD_RIU_WriteByte(0x111ff0, 0x08);
1627 _HAL_DMD_RIU_WriteByte(0x111fe3, 0x08);
1628 _HAL_DMD_RIU_WriteByte(0x111fe2, 0x10);
1629 _HAL_DMD_RIU_WriteByte(0x111feb, 0x11);
1630 _HAL_DMD_RIU_WriteByte(0x111fea, 0x00);
1631 _HAL_DMD_RIU_WriteByte(0x111fef, 0x00);
1632 _HAL_DMD_RIU_WriteByte(0x111fee, 0x88);
1633 _HAL_DMD_RIU_WriteByte(0x15298f, 0x44);
1634 _HAL_DMD_RIU_WriteByte(0x15298e, 0x44);
1635 _HAL_DMD_RIU_WriteByte(0x152991, 0x44);
1636 _HAL_DMD_RIU_WriteByte(0x152990, 0x44);
1637 _HAL_DMD_RIU_WriteByte(0x152992, 0x04);
1638 _HAL_DMD_RIU_WriteByte(0x1529e5, 0x00);
1639 _HAL_DMD_RIU_WriteByte(0x1529e4, 0x04);
1640 _HAL_DMD_RIU_WriteByte(0x152971, 0x10);
1641 _HAL_DMD_RIU_WriteByte(0x152970, 0x01);
1642
1643 if ((_HAL_DMD_RIU_ReadByte(0x0e00+2*0x64) & 0x03) == 2)
1644 {
1645 _HAL_DMD_RIU_WriteByte(0x112830,0x01);
1646 _HAL_DMD_RIU_WriteByte(0x112831,0x00);
1647 _HAL_DMD_RIU_WriteByte(0x1128b2,0x11);
1648 }
1649 else
1650 {
1651 _HAL_DMD_RIU_WriteByte(0x112830,0x00);
1652 _HAL_DMD_RIU_WriteByte(0x112831,0x01);
1653 _HAL_DMD_RIU_WriteByte(0x1128b2,0x21);
1654 }
1655
1656 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
1657 }
1658
1659 #else
_HAL_INTERN_ISDBT_InitClk(void)1660 static void _HAL_INTERN_ISDBT_InitClk(void)
1661 {
1662 printf("--------------DMD_ISDBT_CHIP_NONE--------------\n");
1663 }
1664 #endif
1665
_HAL_INTERN_ISDBT_Ready(void)1666 static MS_BOOL _HAL_INTERN_ISDBT_Ready(void)
1667 {
1668 MS_U8 udata = 0x00;
1669
1670 _HAL_DMD_RIU_WriteByte(MBRegBase + 0x1E, 0x02);
1671
1672 _HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, _HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)|0x02); // assert interrupt to VD MCU51
1673 _HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, _HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)&(~0x02)); // de-assert interrupt to VD MCU51
1674
1675 MsOS_DelayTask(1);
1676
1677 udata = _HAL_DMD_RIU_ReadByte(MBRegBase + 0x1E);
1678
1679 if (udata) return FALSE;
1680
1681 return TRUE;
1682 }
1683
_HAL_INTERN_ISDBT_Download(void)1684 static MS_BOOL _HAL_INTERN_ISDBT_Download(void)
1685 {
1686 DMD_ISDBT_ResData *pRes = psDMD_ISDBT_ResData + u8DMD_ISDBT_DMD_ID;
1687
1688 MS_U8 udata = 0x00;
1689 MS_U16 i = 0;
1690 MS_U16 fail_cnt = 0;
1691 MS_U8 u8TmpData;
1692 MS_U16 u16AddressOffset;
1693 const MS_U8 *ISDBT_table;
1694 MS_U16 u16Lib_size;
1695
1696 if (pRes->sDMD_ISDBT_PriData.bDownloaded)
1697 {
1698 if (_HAL_INTERN_ISDBT_Ready())
1699 {
1700 #if DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MUSTANG
1701 _HAL_DMD_RIU_WriteByteMask(DMDMcuBase+0x00, 0x02, 0x02); // reset RIU remapping
1702 #endif
1703 _HAL_DMD_RIU_WriteByteMask(DMDMcuBase+0x00, 0x01, 0x01); // reset VD_MCU
1704 _HAL_DMD_RIU_WriteByteMask(DMDMcuBase+0x00, 0x00, 0x03);
1705
1706 MsOS_DelayTask(20);
1707 return TRUE;
1708 }
1709 }
1710
1711 ISDBT_table = &INTERN_ISDBT_table[0];
1712 u16Lib_size = sizeof(INTERN_ISDBT_table);
1713
1714 #if DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MUSTANG
1715 _HAL_DMD_RIU_WriteByteMask(DMDMcuBase+0x00, 0x02, 0x02); // reset RIU remapping
1716 #endif
1717 _HAL_DMD_RIU_WriteByteMask(DMDMcuBase+0x00, 0x01, 0x01); // reset VD_MCU
1718 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x01, 0x00); // disable SRAM
1719
1720 _HAL_DMD_RIU_WriteByteMask(DMDMcuBase+0x00, 0x00, 0x01); // release MCU, madison patch
1721
1722 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x50); // enable "vdmcu51_if"
1723 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x51); // enable auto-increase
1724 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x04, 0x00); // sram address low byte
1725 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x05, 0x00); // sram address high byte
1726
1727 //// Load code thru VDMCU_IF ////
1728 HAL_INTERN_ISDBT_DBINFO(printf(">Load Code...\n"));
1729
1730 for (i = 0; i < u16Lib_size; i++)
1731 {
1732 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, ISDBT_table[i]); // write data to VD MCU 51 code sram
1733 }
1734
1735 //// Content verification ////
1736 HAL_INTERN_ISDBT_DBINFO(printf(">Verify Code...\n"));
1737
1738 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x04, 0x00); // sram address low byte
1739 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x05, 0x00); // sram address high byte
1740
1741 for (i = 0; i < u16Lib_size; i++)
1742 {
1743 udata = _HAL_DMD_RIU_ReadByte(DMDMcuBase+0x10); // read sram data
1744
1745 if (udata != ISDBT_table[i])
1746 {
1747 HAL_INTERN_ISDBT_DBINFO(printf(">fail add = 0x%x\n", i));
1748 HAL_INTERN_ISDBT_DBINFO(printf(">code = 0x%x\n", INTERN_ISDBT_table[i]));
1749 HAL_INTERN_ISDBT_DBINFO(printf(">data = 0x%x\n", udata));
1750
1751 if (fail_cnt++ > 10)
1752 {
1753 HAL_INTERN_ISDBT_DBINFO(printf(">DSP Loadcode fail!"));
1754 return FALSE;
1755 }
1756 }
1757 }
1758
1759 u16AddressOffset = (ISDBT_table[0x400] << 8)|ISDBT_table[0x401];
1760
1761 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x04, (u16AddressOffset&0xFF)); // sram address low byte
1762 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x05, (u16AddressOffset>>8)); // sram address high byte
1763
1764 u8TmpData = (MS_U8)pRes->sDMD_ISDBT_InitData.u16IF_KHZ;
1765 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1766 u8TmpData = (MS_U8)(pRes->sDMD_ISDBT_InitData.u16IF_KHZ >> 8);
1767 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1768 u8TmpData = (MS_U8)pRes->sDMD_ISDBT_InitData.bIQSwap;
1769 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1770 u8TmpData = (MS_U8)pRes->sDMD_ISDBT_InitData.u16AgcReferenceValue;
1771 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1772 u8TmpData = (MS_U8)(pRes->sDMD_ISDBT_InitData.u16AgcReferenceValue >> 8);
1773 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1774 u8TmpData = (MS_U8)pRes->sDMD_ISDBT_InitData.u32TdiStartAddr;
1775 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1776 u8TmpData = (MS_U8)(pRes->sDMD_ISDBT_InitData.u32TdiStartAddr >> 8);
1777 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1778 u8TmpData = (MS_U8)(pRes->sDMD_ISDBT_InitData.u32TdiStartAddr >> 16);
1779 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1780 u8TmpData = (MS_U8)(pRes->sDMD_ISDBT_InitData.u32TdiStartAddr >> 24);
1781 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
1782
1783 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x50); // diable auto-increase
1784 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x00); // disable "vdmcu51_if"
1785
1786 _HAL_DMD_RIU_WriteByteMask(DMDMcuBase+0x00, 0x01, 0x01); // reset MCU, madison patch
1787
1788 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x01, 0x01); // enable SRAM
1789 _HAL_DMD_RIU_WriteByteMask(DMDMcuBase+0x00, 0x00, 0x03); // release VD_MCU
1790
1791 pRes->sDMD_ISDBT_PriData.bDownloaded = true;
1792
1793 MsOS_DelayTask(20);
1794
1795 HAL_INTERN_ISDBT_DBINFO(printf(">DSP Loadcode done."));
1796
1797 return TRUE;
1798 }
1799
_HAL_INTERN_ISDBT_FWVERSION(void)1800 static void _HAL_INTERN_ISDBT_FWVERSION(void)
1801 {
1802 MS_U8 data1 = 0;
1803 MS_U8 data2 = 0;
1804 MS_U8 data3 = 0;
1805
1806 _MBX_ReadReg(0x20C4, &data1);
1807 _MBX_ReadReg(0x20C5, &data2);
1808 _MBX_ReadReg(0x20C6, &data3);
1809
1810 printf("INTERN_ISDBT_FW_VERSION:%x.%x.%x\n", data1, data2, data3);
1811 }
1812
_HAL_INTERN_ISDBT_Exit(void)1813 static MS_BOOL _HAL_INTERN_ISDBT_Exit(void)
1814 {
1815 MS_U8 u8CheckCount = 0;
1816 #if (DMD_ISDBT_CHIP_VERSION < DMD_ISDBT_CHIP_MULAN) || (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MESSI) || (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_KIWI)
1817 MS_U8 u8RegValTmp = 0;
1818
1819 u8RegValTmp = _HAL_DMD_RIU_ReadByte(0x101200+ISDBT_MIU_CLIENTW_ADDR);
1820 if (u8RegValTmp & ISDBT_MIU_CLIENTW_BIT_MASK)
1821 {
1822 _HAL_DMD_RIU_WriteByteMask(0x100600+ISDBT_MIU_CLIENTW_MASK, ISDBT_MIU_CLIENTW_BIT_MASK, ISDBT_MIU_CLIENTW_BIT_MASK);
1823 _HAL_DMD_RIU_WriteByteMask(0x100600+ISDBT_MIU_CLIENTR_MASK, ISDBT_MIU_CLIENTR_BIT_MASK, ISDBT_MIU_CLIENTR_BIT_MASK);
1824 }
1825 else
1826 {
1827 _HAL_DMD_RIU_WriteByteMask(0x101200+ISDBT_MIU_CLIENTW_MASK, ISDBT_MIU_CLIENTW_BIT_MASK, ISDBT_MIU_CLIENTW_BIT_MASK);
1828 _HAL_DMD_RIU_WriteByteMask(0x101200+ISDBT_MIU_CLIENTR_MASK, ISDBT_MIU_CLIENTR_BIT_MASK, ISDBT_MIU_CLIENTR_BIT_MASK);
1829 }
1830 #endif
1831 _HAL_DMD_RIU_WriteByte(MBRegBase + 0x1C, 0x01);
1832
1833 _HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, _HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)|0x02); // assert interrupt to VD MCU51
1834 _HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, _HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)&(~0x02)); // de-assert interrupt to VD MCU51
1835
1836 while ((_HAL_DMD_RIU_ReadByte(MBRegBase + 0x1C)&0x02) != 0x02)
1837 {
1838 MsOS_DelayTaskUs(10);
1839
1840 if (u8CheckCount++ == 0xFF)
1841 {
1842 printf(">> ISDBT Exit Fail!\n");
1843 return FALSE;
1844 }
1845 }
1846
1847 printf(">> ISDBT Exit Ok!\n");
1848
1849 return TRUE;
1850 }
1851
_HAL_INTERN_ISDBT_SoftReset(void)1852 static MS_BOOL _HAL_INTERN_ISDBT_SoftReset(void)
1853 {
1854 MS_U8 u8Data = 0;
1855
1856 #if (DMD_ISDBT_CHIP_VERSION < DMD_ISDBT_CHIP_MULAN) || (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MESSI) || (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_KIWI)
1857 MS_U8 u8RegValTmp = 0;
1858
1859 u8RegValTmp = _HAL_DMD_RIU_ReadByte(0x101200+ISDBT_MIU_CLIENTW_ADDR);
1860 if (u8RegValTmp & ISDBT_MIU_CLIENTW_BIT_MASK)
1861 {
1862 _HAL_DMD_RIU_WriteByteMask(0x100600+ISDBT_MIU_CLIENTW_MASK, ISDBT_MIU_CLIENTW_BIT_MASK, ISDBT_MIU_CLIENTW_BIT_MASK);
1863 _HAL_DMD_RIU_WriteByteMask(0x100600+ISDBT_MIU_CLIENTR_MASK, ISDBT_MIU_CLIENTR_BIT_MASK, ISDBT_MIU_CLIENTR_BIT_MASK);
1864 }
1865 else
1866 {
1867 _HAL_DMD_RIU_WriteByteMask(0x101200+ISDBT_MIU_CLIENTW_MASK, ISDBT_MIU_CLIENTW_BIT_MASK, ISDBT_MIU_CLIENTW_BIT_MASK);
1868 _HAL_DMD_RIU_WriteByteMask(0x101200+ISDBT_MIU_CLIENTR_MASK, ISDBT_MIU_CLIENTR_BIT_MASK, ISDBT_MIU_CLIENTR_BIT_MASK);
1869 }
1870 #endif
1871
1872 //Reset FSM
1873 if (_MBX_WriteReg(0x20C0, 0x00)==FALSE) return FALSE;
1874
1875 while (u8Data!=0x02)
1876 {
1877 if (_MBX_ReadReg(0x20C1, &u8Data)==FALSE) return FALSE;
1878 }
1879
1880 return TRUE;
1881 }
1882
_HAL_INTERN_ISDBT_SetACICoef(void)1883 static MS_BOOL _HAL_INTERN_ISDBT_SetACICoef(void)
1884 {
1885 return TRUE;
1886 }
1887
_HAL_INTERN_ISDBT_SetIsdbtMode(void)1888 static MS_BOOL _HAL_INTERN_ISDBT_SetIsdbtMode(void)
1889 {
1890 #if (DMD_ISDBT_CHIP_VERSION < DMD_ISDBT_CHIP_MULAN) || (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_MESSI) || (DMD_ISDBT_CHIP_VERSION == DMD_ISDBT_CHIP_KIWI)
1891 MS_U8 u8RegValTmp = 0;
1892
1893 u8RegValTmp = _HAL_DMD_RIU_ReadByte(0x101200+ISDBT_MIU_CLIENTW_ADDR);
1894 if (u8RegValTmp & ISDBT_MIU_CLIENTW_BIT_MASK)
1895 {
1896 _HAL_DMD_RIU_WriteByteMask(0x100600+ISDBT_MIU_CLIENTW_MASK, 0, ISDBT_MIU_CLIENTW_BIT_MASK);
1897 _HAL_DMD_RIU_WriteByteMask(0x100600+ISDBT_MIU_CLIENTR_MASK, 0, ISDBT_MIU_CLIENTR_BIT_MASK);
1898 }
1899 else
1900 {
1901 _HAL_DMD_RIU_WriteByteMask(0x101200+ISDBT_MIU_CLIENTW_MASK, 0, ISDBT_MIU_CLIENTW_BIT_MASK);
1902 _HAL_DMD_RIU_WriteByteMask(0x101200+ISDBT_MIU_CLIENTR_MASK, 0, ISDBT_MIU_CLIENTR_BIT_MASK);
1903 }
1904 #endif
1905
1906 if (_MBX_WriteReg(0x20C2, 0x04)==FALSE) return FALSE;
1907 return _MBX_WriteReg(0x20C0, 0x04);
1908 }
1909
_HAL_INTERN_ISDBT_SetModeClean(void)1910 static MS_BOOL _HAL_INTERN_ISDBT_SetModeClean(void)
1911 {
1912 if (_MBX_WriteReg(0x20C2, 0x07)==FALSE) return FALSE;
1913 return _MBX_WriteReg(0x20C0, 0x00);
1914 }
1915
_HAL_INTERN_ISDBT_Check_FEC_Lock(void)1916 static MS_BOOL _HAL_INTERN_ISDBT_Check_FEC_Lock(void)
1917 {
1918 MS_BOOL bCheckPass = FALSE;
1919 MS_U8 u8Data = 0;
1920
1921 _MBX_ReadReg(REG_ISDBT_LOCK_STATUS, &u8Data);
1922
1923 if ((u8Data & 0x02) != 0x00) // Check FEC Lock Flag
1924 bCheckPass = TRUE;
1925
1926 return bCheckPass;
1927 }
1928
_HAL_INTERN_ISDBT_Check_FSA_TRACK_Lock(void)1929 static MS_BOOL _HAL_INTERN_ISDBT_Check_FSA_TRACK_Lock(void)
1930 {
1931 MS_BOOL bCheckPass = FALSE;
1932 MS_U8 u8Data = 0;
1933
1934 _MBX_ReadReg(REG_ISDBT_LOCK_STATUS, &u8Data);
1935
1936 if ((u8Data & 0x01) != 0x00) // Check FSA Track Lock Flag
1937 bCheckPass = TRUE;
1938
1939 return bCheckPass;
1940 }
1941
_HAL_INTERN_ISDBT_Check_PSYNC_Lock(void)1942 static MS_BOOL _HAL_INTERN_ISDBT_Check_PSYNC_Lock(void)
1943 {
1944 MS_BOOL bCheckPass = FALSE;
1945 MS_U8 u8Data = 0;
1946
1947 _MBX_ReadReg(REG_ISDBT_LOCK_STATUS, &u8Data);
1948
1949 if ((u8Data & 0x04) != 0x00) // Check Psync Lock Flag
1950 bCheckPass = TRUE;
1951
1952 return bCheckPass;
1953 }
1954
_HAL_INTERN_ISDBT_Check_ICFO_CH_EXIST_Lock(void)1955 static MS_BOOL _HAL_INTERN_ISDBT_Check_ICFO_CH_EXIST_Lock(void)
1956 {
1957 MS_BOOL bCheckPass = FALSE;
1958 MS_U8 u8Data = 0;
1959
1960 _MBX_ReadReg(REG_ISDBT_LOCK_STATUS, &u8Data);
1961
1962 if ((u8Data & 0x80) != 0x00) // Check Psync Lock Flag
1963 bCheckPass = TRUE;
1964
1965 return bCheckPass;
1966 }
1967
_HAL_INTERN_ISDBT_GetSignalCodeRate(EN_ISDBT_Layer eLayerIndex,EN_ISDBT_CODE_RATE * peIsdbtCodeRate)1968 static MS_BOOL _HAL_INTERN_ISDBT_GetSignalCodeRate(EN_ISDBT_Layer eLayerIndex, EN_ISDBT_CODE_RATE *peIsdbtCodeRate)
1969 {
1970 MS_BOOL bRet = TRUE;
1971 MS_U8 u8Data = 0;
1972 MS_U8 u8CodeRate = 0;
1973
1974 switch (eLayerIndex)
1975 {
1976 case E_ISDBT_Layer_A:
1977 // [10:8] reg_tmcc_cur_convolution_code_rate_a
1978 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE+0x04*2+1, &u8Data);
1979 u8CodeRate = u8Data & 0x07;
1980 break;
1981 case E_ISDBT_Layer_B:
1982 // [10:8] reg_tmcc_cur_convolution_code_rate_b
1983 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE+0x05*2+1, &u8Data);
1984 u8CodeRate = u8Data & 0x07;
1985 break;
1986 case E_ISDBT_Layer_C:
1987 // [10:8] reg_tmcc_cur_convolution_code_rate_c
1988 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE+0x06*2+1, &u8Data);
1989 u8CodeRate = u8Data & 0x07;
1990 break;
1991 default:
1992 u8CodeRate = 15;
1993 break;
1994 }
1995
1996 switch (u8CodeRate)
1997 {
1998 case 0:
1999 *peIsdbtCodeRate = E_ISDBT_CODERATE_1_2;
2000 break;
2001 case 1:
2002 *peIsdbtCodeRate = E_ISDBT_CODERATE_2_3;
2003 break;
2004 case 2:
2005 *peIsdbtCodeRate = E_ISDBT_CODERATE_3_4;
2006 break;
2007 case 3:
2008 *peIsdbtCodeRate = E_ISDBT_CODERATE_5_6;
2009 break;
2010 case 4:
2011 *peIsdbtCodeRate = E_ISDBT_CODERATE_7_8;
2012 break;
2013 default:
2014 *peIsdbtCodeRate = E_ISDBT_CODERATE_INVALID;
2015 break;
2016 }
2017
2018 return bRet;
2019 }
2020
_HAL_INTERN_ISDBT_GetSignalGuardInterval(EN_ISDBT_GUARD_INTERVAL * peIsdbtGI)2021 static MS_BOOL _HAL_INTERN_ISDBT_GetSignalGuardInterval(EN_ISDBT_GUARD_INTERVAL *peIsdbtGI)
2022 {
2023 MS_BOOL bRet = TRUE;
2024 MS_U8 u8Data = 0;
2025 MS_U8 u8CP = 0;
2026
2027 // [7:6] reg_mcd_out_cp
2028 // output cp -> 00: 1/4
2029 // 01: 1/8
2030 // 10: 1/16
2031 // 11: 1/32
2032 bRet &= _MBX_ReadReg(ISDBT_TDP_REG_BASE+0x34*2, &u8Data);
2033
2034 u8CP = (u8Data >> 6) & 0x03;
2035
2036 switch (u8CP)
2037 {
2038 case 0:
2039 *peIsdbtGI = E_ISDBT_GUARD_INTERVAL_1_4;
2040 break;
2041 case 1:
2042 *peIsdbtGI = E_ISDBT_GUARD_INTERVAL_1_8;
2043 break;
2044 case 2:
2045 *peIsdbtGI = E_ISDBT_GUARD_INTERVAL_1_16;
2046 break;
2047 case 3:
2048 *peIsdbtGI = E_ISDBT_GUARD_INTERVAL_1_32;
2049 break;
2050 }
2051
2052 return bRet;
2053 }
2054
_HAL_INTERN_ISDBT_GetSignalTimeInterleaving(EN_ISDBT_Layer eLayerIndex,EN_ISDBT_TIME_INTERLEAVING * peIsdbtTDI)2055 static MS_BOOL _HAL_INTERN_ISDBT_GetSignalTimeInterleaving(EN_ISDBT_Layer eLayerIndex, EN_ISDBT_TIME_INTERLEAVING *peIsdbtTDI)
2056 {
2057 MS_BOOL bRet = TRUE;
2058 MS_U8 u8Data = 0;
2059 MS_U8 u8Mode = 0;
2060 MS_U8 u8Tdi = 0;
2061
2062 // [5:4] reg_mcd_out_mode
2063 // output mode -> 00: 2k
2064 // 01: 4k
2065 // 10: 8k
2066 bRet &= _MBX_ReadReg(ISDBT_TDP_REG_BASE+0x34*2, &u8Data);
2067
2068 u8Mode = (u8Data >> 4) & 0x03;
2069
2070 switch (eLayerIndex)
2071 {
2072 case E_ISDBT_Layer_A:
2073 // [14:12] reg_tmcc_cur_interleaving_length_a
2074 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE+0x04*2+1, &u8Data);
2075 u8Tdi = (u8Data >> 4) & 0x07;
2076 break;
2077 case E_ISDBT_Layer_B:
2078 // [14:12] reg_tmcc_cur_interleaving_length_b
2079 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE+0x05*2+1, &u8Data);
2080 u8Tdi = (u8Data >> 4) & 0x07;
2081 break;
2082 case E_ISDBT_Layer_C:
2083 // [14:12] reg_tmcc_cur_interleaving_length_c
2084 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE+0x06*2+1, &u8Data);
2085 u8Tdi = (u8Data >> 4) & 0x07;
2086 break;
2087 default:
2088 u8Tdi = 15;
2089 break;
2090 }
2091
2092 // u8Tdi+u8Mode*4
2093 // => 0~3: 2K
2094 // => 4~7: 4K
2095 // => 8~11:8K
2096 switch (u8Tdi+u8Mode*4)
2097 {
2098 case 0:
2099 *peIsdbtTDI = E_ISDBT_2K_TDI_0;
2100 break;
2101 case 1:
2102 *peIsdbtTDI = E_ISDBT_2K_TDI_4;
2103 break;
2104 case 2:
2105 *peIsdbtTDI = E_ISDBT_2K_TDI_8;
2106 break;
2107 case 3:
2108 *peIsdbtTDI = E_ISDBT_2K_TDI_16;
2109 break;
2110 case 4:
2111 *peIsdbtTDI = E_ISDBT_4K_TDI_0;
2112 break;
2113 case 5:
2114 *peIsdbtTDI = E_ISDBT_4K_TDI_2;
2115 break;
2116 case 6:
2117 *peIsdbtTDI = E_ISDBT_4K_TDI_4;
2118 break;
2119 case 7:
2120 *peIsdbtTDI = E_ISDBT_4K_TDI_8;
2121 break;
2122 case 8:
2123 *peIsdbtTDI = E_ISDBT_8K_TDI_0;
2124 break;
2125 case 9:
2126 *peIsdbtTDI = E_ISDBT_8K_TDI_1;
2127 break;
2128 case 10:
2129 *peIsdbtTDI = E_ISDBT_8K_TDI_2;
2130 break;
2131 case 11:
2132 *peIsdbtTDI = E_ISDBT_8K_TDI_4;
2133 break;
2134 default:
2135 *peIsdbtTDI = E_ISDBT_TDI_INVALID;
2136 break;
2137 }
2138
2139 return bRet;
2140 }
2141
_HAL_INTERN_ISDBT_GetSignalFFTValue(EN_ISDBT_FFT_VAL * peIsdbtFFT)2142 static MS_BOOL _HAL_INTERN_ISDBT_GetSignalFFTValue(EN_ISDBT_FFT_VAL *peIsdbtFFT)
2143 {
2144 MS_BOOL bRet = TRUE;
2145 MS_U8 u8Data = 0;
2146 MS_U8 u8Mode = 0;
2147
2148 // [5:4] reg_mcd_out_mode
2149 // output mode -> 00: 2k
2150 // 01: 4k
2151 // 10: 8k
2152 bRet &= _MBX_ReadReg(ISDBT_TDP_REG_BASE+0x34*2, &u8Data);
2153
2154 u8Mode = (u8Data >> 4) & 0x03;
2155
2156 switch (u8Mode)
2157 {
2158 case 0:
2159 *peIsdbtFFT = E_ISDBT_FFT_2K;
2160 break;
2161 case 1:
2162 *peIsdbtFFT = E_ISDBT_FFT_4K;
2163 break;
2164 case 2:
2165 *peIsdbtFFT = E_ISDBT_FFT_8K;
2166 break;
2167 default:
2168 *peIsdbtFFT = E_ISDBT_FFT_INVALID;
2169 break;
2170 }
2171
2172 return bRet;
2173 }
2174
_HAL_INTERN_ISDBT_GetSignalModulation(EN_ISDBT_Layer eLayerIndex,EN_ISDBT_CONSTEL_TYPE * peIsdbtConstellation)2175 static MS_BOOL _HAL_INTERN_ISDBT_GetSignalModulation(EN_ISDBT_Layer eLayerIndex, EN_ISDBT_CONSTEL_TYPE *peIsdbtConstellation)
2176 {
2177 MS_BOOL bRet = TRUE;
2178 MS_U8 u8Data = 0;
2179 MS_U8 u8QAM = 0;
2180
2181 switch(eLayerIndex)
2182 {
2183 case E_ISDBT_Layer_A:
2184 // [6:4] reg_tmcc_cur_carrier_modulation_a
2185 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE+0x04*2, &u8Data);
2186 u8QAM = (u8Data >> 4) & 0x07;
2187 break;
2188 case E_ISDBT_Layer_B:
2189 // [6:4] reg_tmcc_cur_carrier_modulation_b
2190 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE+0x05*2, &u8Data);
2191 u8QAM = (u8Data >> 4) & 0x07;
2192 break;
2193 case E_ISDBT_Layer_C:
2194 // [6:4] reg_tmcc_cur_carrier_modulation_c
2195 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE+0x06*2, &u8Data);
2196 u8QAM = (u8Data >> 4) & 0x07;
2197 break;
2198 default:
2199 u8QAM = 15;
2200 break;
2201 }
2202
2203 switch(u8QAM)
2204 {
2205 case 0:
2206 *peIsdbtConstellation = E_ISDBT_DQPSK;
2207 break;
2208 case 1:
2209 *peIsdbtConstellation = E_ISDBT_QPSK;
2210 break;
2211 case 2:
2212 *peIsdbtConstellation = E_ISDBT_16QAM;
2213 break;
2214 case 3:
2215 *peIsdbtConstellation = E_ISDBT_64QAM;
2216 break;
2217 default:
2218 *peIsdbtConstellation = E_ISDBT_QAM_INVALID;
2219 break;
2220 }
2221
2222 return bRet;
2223 }
2224
_HAL_INTERN_ISDBT_ReadIFAGC(void)2225 static MS_U8 _HAL_INTERN_ISDBT_ReadIFAGC(void)
2226 {
2227 MS_U8 data = 0;
2228
2229 _MBX_ReadReg(0x28FD, &data);
2230
2231 return data;
2232 }
2233
2234 #ifdef UTPA2
_HAL_INTERN_ISDBT_GetFreqOffset(MS_U8 * pFFT_Mode,MS_S32 * pTdCfoRegValue,MS_S32 * pFdCfoRegValue,MS_S16 * pIcfoRegValue)2235 static MS_BOOL _HAL_INTERN_ISDBT_GetFreqOffset(MS_U8 *pFFT_Mode, MS_S32 *pTdCfoRegValue, MS_S32 *pFdCfoRegValue, MS_S16 *pIcfoRegValue)
2236 #else
2237 static MS_BOOL _HAL_INTERN_ISDBT_GetFreqOffset(float *pFreqOff)
2238 #endif
2239 {
2240 MS_BOOL bRet = TRUE;
2241 MS_U8 u8Data = 0;
2242 MS_S32 s32TdCfoRegValue = 0;
2243 MS_S32 s32FdCfoRegValue = 0;
2244 MS_S16 s16IcfoRegValue = 0;
2245 #ifndef UTPA2
2246 float fTdCfoFreq = 0.0;
2247 float fICfoFreq = 0.0;
2248 float fFdCfoFreq = 0.0;
2249 #endif
2250
2251 //Get TD CFO
2252 bRet &= _MBX_ReadReg(ISDBT_TDP_REG_BASE + 0x04, &u8Data); //0x02 * 2
2253 bRet &= _MBX_WriteReg(ISDBT_TDP_REG_BASE + 0x04, (u8Data|0x01));
2254
2255 //read td_freq_error
2256 //Read <29,38>
2257 bRet &= _MBX_ReadReg(ISDBT_TDP_REG_BASE + 0x8A, &u8Data); //0x45 * 2
2258 s32TdCfoRegValue = u8Data;
2259 bRet &= _MBX_ReadReg(ISDBT_TDP_REG_BASE + 0x8B, &u8Data); //0x45 * 2 + 1
2260 s32TdCfoRegValue |= u8Data << 8;
2261 bRet &= _MBX_ReadReg(ISDBT_TDP_REG_BASE + 0x8C, &u8Data); //0x46 * 2
2262 s32TdCfoRegValue = u8Data << 16;
2263 bRet &= _MBX_ReadReg(ISDBT_TDP_REG_BASE + 0x8D, &u8Data); //0x46 * 2 + 1
2264 s32TdCfoRegValue |= u8Data << 24;
2265
2266 if (u8Data >= 0x10)
2267 s32TdCfoRegValue = 0xE0000000 | s32TdCfoRegValue;
2268
2269 s32TdCfoRegValue >>=4;
2270
2271 //TD_cfo_Hz = RegCfoTd * fb
2272 bRet &= _MBX_ReadReg(ISDBT_TDP_REG_BASE + 0x04, &u8Data); //0x02 * 2
2273 bRet &= _MBX_WriteReg(ISDBT_TDP_REG_BASE + 0x04, (u8Data&~0x01));
2274
2275 #ifndef UTPA2
2276 fTdCfoFreq = ((float)s32TdCfoRegValue) / 17179869184.0; //<25,34>
2277 fTdCfoFreq = fTdCfoFreq * 8126980.0;
2278 #endif
2279
2280 //Get FD CFO
2281 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0xFE, &u8Data); //0x7f * 2
2282 bRet &= _MBX_WriteReg(ISDBT_FDP_REG_BASE + 0xFE, (u8Data|0x01));
2283 //load
2284 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0xFF, &u8Data); //0x7f * 2 + 1
2285 bRet &= _MBX_WriteReg(ISDBT_FDP_REG_BASE + 0xFF, (u8Data|0x01));
2286
2287 //read CFO_KI
2288 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0x5E, &u8Data); //0x2F * 2
2289 s32FdCfoRegValue = u8Data;
2290 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0x5F, &u8Data); //0x2F * 2 + 1
2291 s32FdCfoRegValue |= u8Data << 8;
2292 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0x60, &u8Data); //0x30 * 2
2293 s32FdCfoRegValue |= u8Data << 16;
2294 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0x61, &u8Data); //0x30 * 2
2295 s32FdCfoRegValue |= u8Data << 24;
2296
2297 if(u8Data >= 0x01)
2298 s32FdCfoRegValue = 0xFE000000 | s32FdCfoRegValue;
2299
2300 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0xFE, &u8Data); //0x7f * 2
2301 bRet &= _MBX_WriteReg(ISDBT_FDP_REG_BASE + 0xFE, (u8Data&~0x01));
2302 //load
2303 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0xFF, &u8Data); //0x7f * 2 + 1
2304 bRet &= _MBX_WriteReg(ISDBT_FDP_REG_BASE + 0xFF, (u8Data|0x01));
2305
2306 #ifndef UTPA2
2307 fFdCfoFreq = ((float)s32FdCfoRegValue) / 17179869184.0;
2308 fFdCfoFreq = fFdCfoFreq * 8126980.0;
2309 #endif
2310
2311 //Get ICFO
2312 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0x5C, &u8Data); //0x2E * 2
2313 s16IcfoRegValue = u8Data;
2314 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0x5D, &u8Data); //0x2E * 2 + 1
2315 s16IcfoRegValue |= u8Data << 8;
2316 s16IcfoRegValue = (s16IcfoRegValue >> 4) & 0x07FF;
2317
2318 if(s16IcfoRegValue >= 0x400)
2319 s16IcfoRegValue = s16IcfoRegValue | 0xFFFFF800;
2320
2321 bRet &= _MBX_ReadReg(ISDBT_TDP_REG_BASE + 0x68, &u8Data); //0x34 * 2
2322
2323 #ifdef UTPA2
2324 *pFFT_Mode = u8Data;
2325 *pTdCfoRegValue = s32TdCfoRegValue;
2326 *pFdCfoRegValue = s32TdCfoRegValue;
2327 *pIcfoRegValue = s16IcfoRegValue;
2328 #else
2329 if((u8Data & 0x30) == 0x0000) // 2k
2330 fICfoFreq = (float)s16IcfoRegValue*250000.0/63.0;
2331 else if((u8Data & 0x0030) == 0x0010) // 4k
2332 fICfoFreq = (float)s16IcfoRegValue*125000.0/63.0;
2333 else //if(u16data & 0x0030 == 0x0020) // 8k
2334 fICfoFreq = (float)s16IcfoRegValue*125000.0/126.0;
2335
2336 *pFreqOff = fTdCfoFreq + fFdCfoFreq + fICfoFreq;
2337
2338 HAL_INTERN_ISDBT_DBINFO(printf("Total CFO value = %f\n", *pFreqOff));
2339 #endif
2340
2341 return bRet;
2342 }
2343
2344 #ifdef UTPA2
_HAL_INTERN_ISDBT_GetPreViterbiBer(EN_ISDBT_Layer eLayerIndex,MS_U32 * pBerValue,MS_U16 * pBerPeriod)2345 static MS_BOOL _HAL_INTERN_ISDBT_GetPreViterbiBer(EN_ISDBT_Layer eLayerIndex, MS_U32 *pBerValue, MS_U16 *pBerPeriod )
2346 #else
2347 static MS_BOOL _HAL_INTERN_ISDBT_GetPreViterbiBer(EN_ISDBT_Layer eLayerIndex, float *pfber)
2348 #endif
2349 {
2350 MS_BOOL bRet = TRUE;
2351 MS_U8 u8Data = 0;
2352 MS_U16 u16BerValue = 0;
2353 MS_U32 u32BerPeriod = 0;
2354
2355 // reg_rd_freezeber
2356 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x60, &u8Data);
2357 bRet &= _MBX_WriteReg(ISDBT_OUTER_REG_BASE + 0x60, u8Data|0x08);
2358
2359 if (eLayerIndex == E_ISDBT_Layer_A)
2360 {
2361 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x90, &u8Data); //0x48 * 2
2362 u16BerValue=u8Data;
2363 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x91, &u8Data); //0x48 * 2+1
2364 u16BerValue |= (u8Data << 8);
2365 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x76, &u8Data); //0x3b * 2
2366 u32BerPeriod = (u8Data&0x3F);
2367 u32BerPeriod <<= 16;
2368 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x70, &u8Data); //0x38 * 2
2369 u32BerPeriod |= u8Data;
2370 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x70, &u8Data); //0x38 * 2 +1
2371 u32BerPeriod |= (u8Data << 8);
2372 }
2373 else if (eLayerIndex == E_ISDBT_Layer_B)
2374 {
2375 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x92, &u8Data); //0x49 * 2
2376 u16BerValue=u8Data;
2377 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x93, &u8Data); //0x49 * 2+1
2378 u16BerValue |= (u8Data << 8);
2379 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x77, &u8Data); //0x3b * 2 + 1
2380 u32BerPeriod = (u8Data&0x3F);
2381 u32BerPeriod <<= 16;
2382 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x72, &u8Data); //0x39 * 2
2383 u32BerPeriod |= u8Data;
2384 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x73, &u8Data); //0x39 * 2 +1
2385 u32BerPeriod |= (u8Data << 8);
2386 }
2387 else if (eLayerIndex == E_ISDBT_Layer_C)
2388 {
2389 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x94, &u8Data); //0x4A * 2
2390 u16BerValue=u8Data;
2391 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x95, &u8Data); //0x4A * 2+1
2392 u16BerValue |= (u8Data << 8);
2393 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x78, &u8Data); //0x3C
2394 u32BerPeriod = (u8Data&0x003F);
2395 u32BerPeriod <<= 16;
2396 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x74, &u8Data); //0x3A * 2
2397 u32BerPeriod |= u8Data;
2398 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x75, &u8Data); //0x3A * 2 +1
2399 u32BerPeriod |= (u8Data << 8);
2400 }
2401 else
2402 {
2403 HAL_INTERN_ISDBT_DBINFO(printf("Please select correct Layer\n"));
2404 bRet = FALSE;
2405 }
2406
2407 // reg_rd_freezeber
2408 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x60, &u8Data);
2409 bRet &= _MBX_WriteReg(ISDBT_OUTER_REG_BASE + 0x60, (u8Data&~0x08));
2410
2411 u32BerPeriod <<= 8; // *256
2412
2413 if(u32BerPeriod == 0) u32BerPeriod = 1;
2414
2415 #ifdef UTPA2
2416 *pBerPeriod = u32BerPeriod;
2417 *pBerValue = u16BerValue;
2418 #else
2419 *pfber = (float)u16BerValue/u32BerPeriod;
2420 HAL_INTERN_ISDBT_DBINFO(printf("Layer: 0x%x, Pre-Ber = %e\n", eLayerIndex, *pfber));
2421 #endif
2422
2423 return bRet;
2424 }
2425
2426 #ifdef UTPA2
_HAL_INTERN_ISDBT_GetPostViterbiBer(EN_ISDBT_Layer eLayerIndex,MS_U32 * pBerValue,MS_U16 * pBerPeriod)2427 static MS_BOOL _HAL_INTERN_ISDBT_GetPostViterbiBer(EN_ISDBT_Layer eLayerIndex, MS_U32 *pBerValue, MS_U16 *pBerPeriod )
2428 #else
2429 static MS_BOOL _HAL_INTERN_ISDBT_GetPostViterbiBer(EN_ISDBT_Layer eLayerIndex, float *pfber)
2430 #endif
2431 {
2432 MS_BOOL bRet = TRUE;
2433 MS_U8 u8Data = 0;
2434 MS_U8 u8FrzData = 0;
2435 MS_U32 u32BerValue = 0;
2436 MS_U16 u16BerPeriod = 0;
2437
2438 // reg_rd_freezeber
2439 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x01*2+1, &u8FrzData);
2440 u8Data = u8FrzData | 0x01;
2441 bRet &= _MBX_WriteReg(ISDBT_OUTER_REG_BASE+0x01*2+1, u8Data);
2442
2443 if (eLayerIndex == E_ISDBT_Layer_A)
2444 {
2445 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x14, &u8Data); //0x0A * 2
2446 u32BerValue = u8Data;
2447 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x15, &u8Data); //0x0A * 2+1
2448 u32BerValue |= u8Data << 8;
2449 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x16, &u8Data); //0x0B * 2
2450 u32BerValue |= u8Data << 16;
2451 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x17, &u8Data); //0x0B * 2+1
2452 u32BerValue |= u8Data << 24;
2453
2454 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x0A, &u8Data); //0x05 * 2
2455 u16BerPeriod = u8Data;
2456 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x0B, &u8Data); //0x05 * 2+1
2457 u16BerPeriod |= u8Data << 8;
2458 }
2459 else if (eLayerIndex == E_ISDBT_Layer_B)
2460 {
2461 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x46, &u8Data); //0x23 * 2
2462 u32BerValue = u8Data;
2463 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x47, &u8Data); //0x23 * 2+1
2464 u32BerValue |= u8Data << 8;
2465 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x48, &u8Data); //0x24 * 2
2466 u32BerValue |= u8Data << 16;
2467 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x49, &u8Data); //0x24 * 2+1
2468 u32BerValue |= u8Data << 24;
2469
2470 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x3A, &u8Data); //0x1d * 2
2471 u16BerPeriod = u8Data;
2472 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x3B, &u8Data); //0x1d * 2+1
2473 u16BerPeriod |= u8Data << 8;
2474 }
2475 else if (eLayerIndex == E_ISDBT_Layer_C)
2476 {
2477 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x88, &u8Data); //0x44 * 2
2478 u32BerValue = u8Data;
2479 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x89, &u8Data); //0x44 * 2+1
2480 u32BerValue |= u8Data << 8;
2481 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x8A, &u8Data); //0x45 * 2
2482 u32BerValue |= u8Data << 16;
2483 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x8B, &u8Data); //0x45 * 2+1
2484 u32BerValue |= u8Data << 24;
2485
2486 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x3E, &u8Data); //0x1f * 2
2487 u16BerPeriod = u8Data;
2488 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE + 0x3F, &u8Data); //0x1d * 2+1
2489 u16BerPeriod |= u8Data << 8;
2490 }
2491 else
2492 {
2493 HAL_INTERN_ISDBT_DBINFO(printf("Please select correct Layer\n"));
2494 bRet = FALSE;
2495 }
2496
2497 // reg_rd_freezeber
2498 bRet &= _MBX_WriteReg(ISDBT_OUTER_REG_BASE+0x01*2+1, u8FrzData);
2499
2500 if(u16BerPeriod == 0) u16BerPeriod = 1;
2501
2502 #ifdef UTPA2
2503 *pBerPeriod = u16BerPeriod;
2504 *pBerValue = u32BerValue;
2505 #else
2506 *pfber = (float)u32BerValue/u16BerPeriod/(128.0*188.0*8.0);
2507 HAL_INTERN_ISDBT_DBINFO(printf("Layer: 0x%x, Post-Ber = %e\n", eLayerIndex, *pfber));
2508 #endif
2509 return bRet;
2510 }
2511
2512 #ifndef UTPA2
_HAL_INTERN_ISDBT_GetSignalQualityOfLayerA(void)2513 static MS_U16 _HAL_INTERN_ISDBT_GetSignalQualityOfLayerA(void)
2514 {
2515 float fber;
2516 MS_BOOL bRet = TRUE;
2517 EN_ISDBT_Layer eLayerIndex;
2518 MS_U16 u16SQI;
2519
2520 // Tmp solution
2521 eLayerIndex = E_ISDBT_Layer_A;
2522
2523 if(_HAL_INTERN_ISDBT_Check_FEC_Lock() == FALSE)
2524 {
2525 //printf("Dan Demod unlock!!!\n");
2526 u16SQI = 0;
2527 }
2528 else
2529 {
2530 // Part 1: get ber value from demod.
2531 bRet &= _HAL_INTERN_ISDBT_GetPostViterbiBer(eLayerIndex, &fber);
2532
2533 u16SQI = _CALCULATE_SQI(fber);
2534 }
2535
2536 //printf("dan SQI = %d\n", SQI);
2537 return u16SQI;
2538 }
2539
_HAL_INTERN_ISDBT_GetSignalQualityOfLayerB(void)2540 static MS_U16 _HAL_INTERN_ISDBT_GetSignalQualityOfLayerB(void)
2541 {
2542 float fber;
2543 MS_BOOL bRet = TRUE;
2544 EN_ISDBT_Layer eLayerIndex;
2545 MS_U16 u16SQI;
2546
2547 // Tmp solution
2548 eLayerIndex = E_ISDBT_Layer_B;
2549
2550 if(_HAL_INTERN_ISDBT_Check_FEC_Lock() == FALSE)
2551 {
2552 //printf("Dan Demod unlock!!!\n");
2553 u16SQI = 0;
2554 }
2555 else
2556 {
2557 // Part 1: get ber value from demod.
2558 bRet &= _HAL_INTERN_ISDBT_GetPostViterbiBer(eLayerIndex, &fber);
2559
2560 u16SQI = _CALCULATE_SQI(fber);
2561 }
2562
2563 //printf("dan SQI = %d\n", SQI);
2564 return u16SQI;
2565 }
2566
_HAL_INTERN_ISDBT_GetSignalQualityOfLayerC(void)2567 static MS_U16 _HAL_INTERN_ISDBT_GetSignalQualityOfLayerC(void)
2568 {
2569 float fber;
2570 MS_BOOL bRet = TRUE;
2571 EN_ISDBT_Layer eLayerIndex;
2572 MS_U16 u16SQI;
2573
2574 // Tmp solution
2575 eLayerIndex = E_ISDBT_Layer_C;
2576
2577 if(_HAL_INTERN_ISDBT_Check_FEC_Lock() == FALSE)
2578 {
2579 //printf("Dan Demod unlock!!!\n");
2580 u16SQI = 0;
2581 }
2582 else
2583 {
2584 // Part 1: get ber value from demod.
2585 bRet &= _HAL_INTERN_ISDBT_GetPostViterbiBer(eLayerIndex, &fber);
2586
2587 u16SQI = _CALCULATE_SQI(fber);
2588 }
2589
2590 //printf("dan SQI = %d\n", SQI);
2591 return u16SQI;
2592 }
2593
_HAL_INTERN_ISDBT_GetSignalQualityOfLayerCombine(void)2594 static MS_U16 _HAL_INTERN_ISDBT_GetSignalQualityOfLayerCombine(void)
2595 {
2596 MS_S8 s8LayerAValue = 0, s8LayerBValue = 0, s8LayerCValue = 0;
2597 MS_U16 u16SQI;
2598 EN_ISDBT_Layer eLayerIndex;
2599 EN_ISDBT_CONSTEL_TYPE eIsdbtConstellationA, eIsdbtConstellationB, eIsdbtConstellationC;
2600
2601 //Get modulation of each layer
2602 eLayerIndex = E_ISDBT_Layer_A;
2603 _HAL_INTERN_ISDBT_GetSignalModulation(eLayerIndex, &eIsdbtConstellationA);
2604 eLayerIndex = E_ISDBT_Layer_B;
2605 _HAL_INTERN_ISDBT_GetSignalModulation(eLayerIndex, &eIsdbtConstellationB);
2606 eLayerIndex = E_ISDBT_Layer_C;
2607 _HAL_INTERN_ISDBT_GetSignalModulation(eLayerIndex, &eIsdbtConstellationC);
2608
2609 if (eIsdbtConstellationA != E_ISDBT_QAM_INVALID)
2610 s8LayerAValue = (MS_S8)eIsdbtConstellationA;
2611 else
2612 s8LayerAValue = -1;
2613
2614 if (eIsdbtConstellationB != E_ISDBT_QAM_INVALID)
2615 s8LayerBValue = (MS_S8)eIsdbtConstellationB;
2616 else
2617 s8LayerBValue = -1;
2618
2619 if (eIsdbtConstellationC != E_ISDBT_QAM_INVALID)
2620 s8LayerCValue = (MS_S8)eIsdbtConstellationC;
2621 else
2622 s8LayerCValue = -1;
2623
2624 //printf("Layer info A:%d, B:%d, C:%d\n", s8LayerAValue, s8LayerBValue, s8LayerCValue);
2625 if (s8LayerAValue >= s8LayerBValue)
2626 {
2627 if (s8LayerCValue >= s8LayerAValue)
2628 {
2629 //Get Layer C u16SQI
2630 u16SQI = _HAL_INTERN_ISDBT_GetSignalQualityOfLayerC();
2631 //printf("dan u16SQI Layer C1: %d\n", u16SQI);
2632 }
2633 else //A>C
2634 {
2635 //Get Layer A u16SQI
2636 u16SQI = _HAL_INTERN_ISDBT_GetSignalQualityOfLayerA();
2637 //printf("dan u16SQI Layer A: %d\n", u16SQI);
2638 }
2639 }
2640 else // B >= A
2641 {
2642 if (s8LayerCValue >= s8LayerBValue)
2643 {
2644 //Get Layer C u16SQI
2645 u16SQI = _HAL_INTERN_ISDBT_GetSignalQualityOfLayerC();
2646 //printf("dan u16SQI Layer C2: %d\n", u16SQI);
2647 }
2648 else //B>C
2649 {
2650 //Get Layer B u16SQI
2651 u16SQI = _HAL_INTERN_ISDBT_GetSignalQualityOfLayerB();
2652 //printf("dan u16SQI Layer B: %d\n", u16SQI);
2653 }
2654 }
2655
2656 return u16SQI;
2657 }
2658 #endif
2659
2660 #ifdef UTPA2
_HAL_INTERN_ISDBT_GetSNR(MS_U32 * pRegSNR,MS_U16 * pRegSnrObsNum)2661 static MS_BOOL _HAL_INTERN_ISDBT_GetSNR(MS_U32 *pRegSNR, MS_U16 *pRegSnrObsNum)
2662 #else
2663 static MS_BOOL _HAL_INTERN_ISDBT_GetSNR(float *pf_snr)
2664 #endif
2665 {
2666 MS_BOOL bRet = TRUE;
2667 MS_U8 u8Data = 0;
2668 MS_U32 u32RegSNR = 0;
2669 MS_U16 u16RegSnrObsNum = 0;
2670 #ifndef UTPA2
2671 float fSNRAvg = 0.0;
2672 #endif
2673
2674 //set freeze
2675 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0xFE, &u8Data); //0x7f * 2
2676 bRet &= _MBX_WriteReg(ISDBT_FDP_REG_BASE + 0xFE, (u8Data|0x01));
2677 //load
2678 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0xFF, &u8Data); //0x7f * 2 + 1
2679 bRet &= _MBX_WriteReg(ISDBT_FDP_REG_BASE + 0xFF, (u8Data|0x01));
2680
2681 // ==============Average SNR===============//
2682 // [26:0] reg_snr_accu
2683 bRet &= _MBX_ReadReg(ISDBT_FDPEXT_REG_BASE+0x2d*2+1, &u8Data);
2684 u32RegSNR = u8Data&0x07;
2685 bRet &= _MBX_ReadReg(ISDBT_FDPEXT_REG_BASE+0x2d*2, &u8Data);
2686 u32RegSNR = (u32RegSNR<<8) | u8Data;
2687 bRet &= _MBX_ReadReg(ISDBT_FDPEXT_REG_BASE+0x2c*2+1, &u8Data);
2688 u32RegSNR = (u32RegSNR<<8) | u8Data;
2689 bRet &= _MBX_ReadReg(ISDBT_FDPEXT_REG_BASE+0x2c*2, &u8Data);
2690 u32RegSNR = (u32RegSNR<<8) | u8Data;
2691
2692 // [12:0] reg_snr_observe_sum_num
2693 bRet &= _MBX_ReadReg(ISDBT_FDPEXT_REG_BASE+0x2a*2+1, &u8Data);
2694 u16RegSnrObsNum = u8Data&0x1f;
2695 bRet &= _MBX_ReadReg(ISDBT_FDPEXT_REG_BASE+0x2a*2, &u8Data);
2696 u16RegSnrObsNum = (u16RegSnrObsNum<<8) | u8Data;
2697
2698 //release freeze
2699 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0xFE, &u8Data); //0x7f * 2
2700 bRet &= _MBX_WriteReg(ISDBT_FDP_REG_BASE + 0xFE, (u8Data&~0x01));
2701 //load
2702 bRet &= _MBX_ReadReg(ISDBT_FDP_REG_BASE + 0xFF, &u8Data); //0x7f * 2 + 1
2703 bRet &= _MBX_WriteReg(ISDBT_FDP_REG_BASE + 0xFF, (u8Data|0x01));
2704
2705 if (u16RegSnrObsNum == 0)
2706 u16RegSnrObsNum = 1;
2707
2708
2709 #ifdef UTPA2
2710 *pRegSNR = u32RegSNR;
2711 *pRegSnrObsNum = u16RegSnrObsNum;
2712 #else
2713 fSNRAvg = (float)u32RegSNR/u16RegSnrObsNum;
2714 if (fSNRAvg == 0) //protect value 0
2715 fSNRAvg = 0.01;
2716
2717 #ifdef MSOS_TYPE_LINUX
2718 *pf_snr = 10.0f*(float)log10f((double)fSNRAvg/2);
2719 #else
2720 *pf_snr = 10.0f*(float)Log10Approx((double)fSNRAvg/2);
2721 #endif
2722 HAL_INTERN_ISDBT_DBINFO(printf("SNR value = %f\n", *pf_snr));
2723 #endif
2724
2725 return bRet;
2726 }
2727
_HAL_INTERN_ISDBT_Read_PKT_ERR(EN_ISDBT_Layer eLayerIndex,MS_U16 * pu16PacketErr)2728 static MS_BOOL _HAL_INTERN_ISDBT_Read_PKT_ERR(EN_ISDBT_Layer eLayerIndex, MS_U16 *pu16PacketErr)
2729 {
2730 MS_U8 bRet = true;
2731 MS_U8 u8Data = 0;
2732 MS_U8 u8FrzData = 0;
2733 MS_U16 u16PacketErrA = 0xFFFF, u16PacketErrB = 0xFFFF, u16PacketErrC = 0xFFFF;
2734 #if DMD_ISDBT_TBVA_EN
2735 MS_U8 bTbvaBypass = 0;
2736 MS_U8 u8TbvaLayer = 0;
2737 #endif
2738 // Read packet errors of three layers
2739 // OUTER_FUNCTION_ENABLE
2740 // [8] reg_biterr_num_pcktprd_freeze
2741 // Freeze Packet error
2742 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x01*2+1, &u8FrzData);
2743 u8Data = u8FrzData | 0x01;
2744 bRet &= _MBX_WriteReg(ISDBT_OUTER_REG_BASE+0x01*2+1, u8Data);
2745 #if DMD_ISDBT_TBVA_EN
2746 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x10*2, &u8Data);
2747 bTbvaBypass = u8Data & 0x01;
2748 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x11*2, &u8Data);
2749 u8TbvaLayer = u8Data & 0x03;
2750 switch(eLayerIndex)
2751 {
2752 case E_ISDBT_Layer_A:
2753 // [15:0] OUTER_UNCRT_PKT_NUM_PCKTPRD_A
2754 if (!bTbvaBypass && u8TbvaLayer == 0)
2755 {
2756 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x17*2+1, &u8Data);
2757 u16PacketErrA = u8Data << 8;
2758 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x17*2, &u8Data);
2759 u16PacketErrA = u16PacketErrA | u8Data;
2760 *pu16PacketErr = u16PacketErrA;
2761 }
2762 else
2763 {
2764 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x08*2+1, &u8Data);
2765 u16PacketErrA = u8Data << 8;
2766 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x08*2, &u8Data);
2767 u16PacketErrA = u16PacketErrA | u8Data;
2768 *pu16PacketErr = u16PacketErrA;
2769 }
2770 break;
2771 case E_ISDBT_Layer_B:
2772 // [15:0] OUTER_UNCRT_PKT_NUM_PCKTPRD_B
2773 if (!bTbvaBypass && u8TbvaLayer == 1)
2774 {
2775 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x17*2+1, &u8Data);
2776 u16PacketErrB = u8Data << 8;
2777 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x17*2, &u8Data);
2778 u16PacketErrB = u16PacketErrB | u8Data;
2779 *pu16PacketErr = u16PacketErrB;
2780 }
2781 else
2782 {
2783 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x21*2+1, &u8Data);
2784 u16PacketErrB = u8Data << 8;
2785 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x21*2, &u8Data);
2786 u16PacketErrB = u16PacketErrB | u8Data;
2787 *pu16PacketErr = u16PacketErrB;
2788 }
2789 break;
2790 case E_ISDBT_Layer_C:
2791 // [15:0] OUTER_UNCRT_PKT_NUM_PCKTPRD_C
2792 if (!bTbvaBypass && u8TbvaLayer == 2)
2793 {
2794 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x17*2+1, &u8Data);
2795 u16PacketErrC = u8Data << 8;
2796 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x17*2, &u8Data);
2797 u16PacketErrC = u16PacketErrC | u8Data;
2798 *pu16PacketErr = u16PacketErrC;
2799 }
2800 else
2801 {
2802 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x42*2+1, &u8Data);
2803 u16PacketErrC = u8Data << 8;
2804 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x42*2, &u8Data);
2805 u16PacketErrC = u16PacketErrC | u8Data;
2806 *pu16PacketErr = u16PacketErrC;
2807 }
2808 break;
2809 default:
2810 *pu16PacketErr = 0xFFFF;
2811 break;
2812 }
2813 #else
2814 switch(eLayerIndex)
2815 {
2816 case E_ISDBT_Layer_A:
2817 // [15:0] OUTER_UNCRT_PKT_NUM_PCKTPRD_A
2818 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x08*2+1, &u8Data);
2819 u16PacketErrA = u8Data << 8;
2820 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x08*2, &u8Data);
2821 u16PacketErrA = u16PacketErrA | u8Data;
2822 *pu16PacketErr = u16PacketErrA;
2823 break;
2824 case E_ISDBT_Layer_B:
2825 // [15:0] OUTER_UNCRT_PKT_NUM_PCKTPRD_B
2826 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x21*2+1, &u8Data);
2827 u16PacketErrB = u8Data << 8;
2828 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x21*2, &u8Data);
2829 u16PacketErrB = u16PacketErrB | u8Data;
2830 *pu16PacketErr = u16PacketErrB;
2831 break;
2832 case E_ISDBT_Layer_C:
2833 // [15:0] OUTER_UNCRT_PKT_NUM_PCKTPRD_C
2834 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x42*2+1, &u8Data);
2835 u16PacketErrC = u8Data << 8;
2836 bRet &= _MBX_ReadReg(ISDBT_OUTER_REG_BASE+0x42*2, &u8Data);
2837 u16PacketErrC = u16PacketErrC | u8Data;
2838 *pu16PacketErr = u16PacketErrC;
2839 break;
2840 default:
2841 *pu16PacketErr = 0xFFFF;
2842 break;
2843 }
2844 #endif
2845 // Unfreeze Packet error
2846 bRet &= _MBX_WriteReg(ISDBT_OUTER_REG_BASE+0x01*2+1, u8FrzData);
2847
2848 return bRet;
2849 }
2850
_HAL_INTERN_ISDBT_GetReg(MS_U16 u16Addr,MS_U8 * pu8Data)2851 static MS_BOOL _HAL_INTERN_ISDBT_GetReg(MS_U16 u16Addr, MS_U8 *pu8Data)
2852 {
2853 return _MBX_ReadReg(u16Addr, pu8Data);
2854 }
2855
_HAL_INTERN_ISDBT_SetReg(MS_U16 u16Addr,MS_U8 u8Data)2856 static MS_BOOL _HAL_INTERN_ISDBT_SetReg(MS_U16 u16Addr, MS_U8 u8Data)
2857 {
2858 return _MBX_WriteReg(u16Addr, u8Data);
2859 }
2860
2861 //-------------------------------------------------------------------------------------------------
2862 // Global Functions
2863 //-------------------------------------------------------------------------------------------------
HAL_INTERN_ISDBT_IOCTL_CMD(DMD_ISDBT_HAL_COMMAND eCmd,void * pArgs)2864 MS_BOOL HAL_INTERN_ISDBT_IOCTL_CMD(DMD_ISDBT_HAL_COMMAND eCmd, void *pArgs)
2865 {
2866 MS_BOOL bResult = TRUE;
2867
2868 switch(eCmd)
2869 {
2870 case DMD_ISDBT_HAL_CMD_Exit:
2871 bResult = _HAL_INTERN_ISDBT_Exit();
2872 break;
2873 case DMD_ISDBT_HAL_CMD_InitClk:
2874 _HAL_INTERN_ISDBT_InitClk();
2875 break;
2876 case DMD_ISDBT_HAL_CMD_Download:
2877 bResult = _HAL_INTERN_ISDBT_Download();
2878 break;
2879 case DMD_ISDBT_HAL_CMD_FWVERSION:
2880 _HAL_INTERN_ISDBT_FWVERSION();
2881 break;
2882 case DMD_ISDBT_HAL_CMD_SoftReset:
2883 bResult = _HAL_INTERN_ISDBT_SoftReset();
2884 break;
2885 case DMD_ISDBT_HAL_CMD_SetACICoef:
2886 bResult = _HAL_INTERN_ISDBT_SetACICoef();
2887 break;
2888 case DMD_ISDBT_HAL_CMD_SetISDBTMode:
2889 bResult = _HAL_INTERN_ISDBT_SetIsdbtMode();
2890 break;
2891 case DMD_ISDBT_HAL_CMD_SetModeClean:
2892 bResult = _HAL_INTERN_ISDBT_SetModeClean();
2893 break;
2894 case DMD_ISDBT_HAL_CMD_Active:
2895 break;
2896 case DMD_ISDBT_HAL_CMD_Check_FEC_Lock:
2897 bResult = _HAL_INTERN_ISDBT_Check_FEC_Lock();
2898 break;
2899 case DMD_ISDBT_HAL_CMD_Check_FSA_TRACK_Lock:
2900 bResult = _HAL_INTERN_ISDBT_Check_FSA_TRACK_Lock();
2901 break;
2902 case DMD_ISDBT_HAL_CMD_Check_PSYNC_Lock:
2903 bResult = _HAL_INTERN_ISDBT_Check_PSYNC_Lock();
2904 break;
2905 case DMD_ISDBT_HAL_CMD_Check_ICFO_CH_EXIST_Lock:
2906 bResult = _HAL_INTERN_ISDBT_Check_ICFO_CH_EXIST_Lock();
2907 break;
2908 case DMD_ISDBT_HAL_CMD_GetSignalCodeRate:
2909 bResult = _HAL_INTERN_ISDBT_GetSignalCodeRate((*((DMD_ISDBT_GET_CodeRate*)pArgs)).eIsdbtLayer, &((*((DMD_ISDBT_GET_CodeRate*)pArgs)).eCodeRate));
2910 break;
2911 case DMD_ISDBT_HAL_CMD_GetSignalGuardInterval:
2912 bResult = _HAL_INTERN_ISDBT_GetSignalGuardInterval((EN_ISDBT_GUARD_INTERVAL *)pArgs);
2913 break;
2914 case DMD_ISDBT_HAL_CMD_GetSignalTimeInterleaving:
2915 bResult = _HAL_INTERN_ISDBT_GetSignalTimeInterleaving((*((DMD_ISDBT_GET_TimeInterleaving*)pArgs)).eIsdbtLayer, &((*((DMD_ISDBT_GET_TimeInterleaving*)pArgs)).eTimeInterleaving));
2916 break;
2917 case DMD_ISDBT_HAL_CMD_GetSignalFFTValue:
2918 bResult = _HAL_INTERN_ISDBT_GetSignalFFTValue((EN_ISDBT_FFT_VAL *)pArgs);
2919 break;
2920 case DMD_ISDBT_HAL_CMD_GetSignalModulation:
2921 bResult = _HAL_INTERN_ISDBT_GetSignalModulation((*((DMD_ISDBT_GET_MODULATION*)pArgs)).eIsdbtLayer, &((*((DMD_ISDBT_GET_MODULATION*)pArgs)).eConstellation));
2922 break;
2923 case DMD_ISDBT_HAL_CMD_ReadIFAGC:
2924 *((MS_U16 *)pArgs) = _HAL_INTERN_ISDBT_ReadIFAGC();
2925 break;
2926 case DMD_ISDBT_HAL_CMD_GetFreqOffset:
2927 #ifdef UTPA2
2928 bResult = _HAL_INTERN_ISDBT_GetFreqOffset(&((*((DMD_ISDBT_CFO_DATA*)pArgs)).FFT_Mode), &((*((DMD_ISDBT_CFO_DATA*)pArgs)).TdCfoRegValue), &((*((DMD_ISDBT_CFO_DATA*)pArgs)).FdCfoRegValue), &((*((DMD_ISDBT_CFO_DATA*)pArgs)).IcfoRegValue));
2929 #else
2930 bResult = _HAL_INTERN_ISDBT_GetFreqOffset((float *)pArgs);
2931 #endif
2932 break;
2933 case DMD_ISDBT_HAL_CMD_GetSignalQuality:
2934 case DMD_ISDBT_HAL_CMD_GetSignalQualityOfLayerA:
2935 #ifndef UTPA2
2936 *((MS_U16*)pArgs) = _HAL_INTERN_ISDBT_GetSignalQualityOfLayerA();
2937 #endif
2938 break;
2939 case DMD_ISDBT_HAL_CMD_GetSignalQualityOfLayerB:
2940 #ifndef UTPA2
2941 *((MS_U16*)pArgs) = _HAL_INTERN_ISDBT_GetSignalQualityOfLayerB();
2942 #endif
2943 break;
2944 case DMD_ISDBT_HAL_CMD_GetSignalQualityOfLayerC:
2945 #ifndef UTPA2
2946 *((MS_U16*)pArgs) = _HAL_INTERN_ISDBT_GetSignalQualityOfLayerC();
2947 #endif
2948 break;
2949 case DMD_ISDBT_HAL_CMD_GetSignalQualityCombine:
2950 #ifndef UTPA2
2951 *((MS_U16*)pArgs) = _HAL_INTERN_ISDBT_GetSignalQualityOfLayerCombine();
2952 #endif
2953 break;
2954 case DMD_ISDBT_HAL_CMD_GetSNR:
2955 #ifdef UTPA2
2956 bResult = _HAL_INTERN_ISDBT_GetSNR(&((*((DMD_ISDBT_SNR_DATA*)pArgs)).RegSNR), &((*((DMD_ISDBT_SNR_DATA*)pArgs)).RegSnrObsNum));
2957 #else
2958 bResult = _HAL_INTERN_ISDBT_GetSNR((float *)pArgs);
2959 #endif
2960 break;
2961 case DMD_ISDBT_HAL_CMD_GetPreViterbiBer:
2962 #ifdef UTPA2
2963 bResult = _HAL_INTERN_ISDBT_GetPreViterbiBer((*((DMD_ISDBT_GET_BER_VALUE*)pArgs)).eIsdbtLayer, &((*((DMD_ISDBT_GET_BER_VALUE*)pArgs)).BerValue), &((*((DMD_ISDBT_GET_BER_VALUE*)pArgs)).BerPeriod));
2964 #else
2965 bResult = _HAL_INTERN_ISDBT_GetPreViterbiBer((*((DMD_ISDBT_GET_BER_VALUE*)pArgs)).eIsdbtLayer, &((*((DMD_ISDBT_GET_BER_VALUE*)pArgs)).fBerValue));
2966 #endif
2967 break;
2968 case DMD_ISDBT_HAL_CMD_GetPostViterbiBer:
2969 #ifdef UTPA2
2970 bResult = _HAL_INTERN_ISDBT_GetPostViterbiBer((*((DMD_ISDBT_GET_BER_VALUE*)pArgs)).eIsdbtLayer, &((*((DMD_ISDBT_GET_BER_VALUE*)pArgs)).BerValue), &((*((DMD_ISDBT_GET_BER_VALUE*)pArgs)).BerPeriod));
2971 #else
2972 bResult = _HAL_INTERN_ISDBT_GetPostViterbiBer((*((DMD_ISDBT_GET_BER_VALUE*)pArgs)).eIsdbtLayer, &((*((DMD_ISDBT_GET_BER_VALUE*)pArgs)).fBerValue));
2973 #endif
2974 break;
2975 case DMD_ISDBT_HAL_CMD_Read_PKT_ERR:
2976 bResult = _HAL_INTERN_ISDBT_Read_PKT_ERR((*((DMD_ISDBT_GET_PKT_ERR*)pArgs)).eIsdbtLayer, &((*((DMD_ISDBT_GET_PKT_ERR*)pArgs)).u16PacketErr));
2977 break;
2978 case DMD_ISDBT_HAL_CMD_TS_INTERFACE_CONFIG:
2979 break;
2980 case DMD_ISDBT_HAL_CMD_IIC_Bypass_Mode:
2981 break;
2982 case DMD_ISDBT_HAL_CMD_SSPI_TO_GPIO:
2983 break;
2984 case DMD_ISDBT_HAL_CMD_GPIO_GET_LEVEL:
2985 break;
2986 case DMD_ISDBT_HAL_CMD_GPIO_SET_LEVEL:
2987 break;
2988 case DMD_ISDBT_HAL_CMD_GPIO_OUT_ENABLE:
2989 break;
2990 case DMD_ISDBT_HAL_CMD_GET_REG:
2991 bResult = _HAL_INTERN_ISDBT_GetReg((*((DMD_ISDBT_REG_DATA *)pArgs)).u16Addr, &((*((DMD_ISDBT_REG_DATA *)pArgs)).u8Data));
2992 break;
2993 case DMD_ISDBT_HAL_CMD_SET_REG:
2994 bResult = _HAL_INTERN_ISDBT_SetReg((*((DMD_ISDBT_REG_DATA *)pArgs)).u16Addr, (*((DMD_ISDBT_REG_DATA *)pArgs)).u8Data);
2995 break;
2996 default:
2997 break;
2998 }
2999
3000 return bResult;
3001 }
3002
MDrv_DMD_ISDBT_Initial_Hal_Interface(void)3003 MS_BOOL MDrv_DMD_ISDBT_Initial_Hal_Interface(void)
3004 {
3005 return TRUE;
3006 }
3007
3008