1 //<MStar Software>
2 //******************************************************************************
3 // MStar Software
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76 //******************************************************************************
77 //<MStar Software>
78 ////////////////////////////////////////////////////////////////////////////////
79 //
80 // Copyright (c) 2006-2009 MStar Semiconductor, Inc.
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92 //
93 ////////////////////////////////////////////////////////////////////////////////
94
95
96 //-------------------------------------------------------------------------------------------------
97 // Include Files
98 //-------------------------------------------------------------------------------------------------
99
100 #ifndef MSOS_TYPE_LINUX_KERNEL
101 #include <stdio.h>
102 #include <math.h>
103 #endif
104
105 #include "drvDMD_ATSC.h"
106
107 //-------------------------------------------------------------------------------------------------
108 // Driver Compiler Options
109 //-------------------------------------------------------------------------------------------------
110
111 #define DMD_ATSC_CHIP_T3_T10 0x01
112 #define DMD_ATSC_CHIP_T7 0x02
113 #define DMD_ATSC_CHIP_T8_T9 0x03
114 #define DMD_ATSC_CHIP_A1 0x04
115 #define DMD_ATSC_CHIP_A3 0x05
116 #define DMD_ATSC_CHIP_A5 0x06
117 #define DMD_ATSC_CHIP_A7 0x07
118 #define DMD_ATSC_CHIP_A7P 0x08
119 #define DMD_ATSC_CHIP_AGATE 0x09
120 #define DMD_ATSC_CHIP_EDISON 0x0A
121 #define DMD_ATSC_CHIP_EINSTEIN 0x0B
122 #define DMD_ATSC_CHIP_EMERALD 0x0C
123 #define DMD_ATSC_CHIP_EIFFEL 0x0D
124 #define DMD_ATSC_CHIP_EDEN 0x0E
125 #define DMD_ATSC_CHIP_EINSTEIN3 0x0F
126 #define DMD_ATSC_CHIP_MONACO 0x10
127 #define DMD_ATSC_CHIP_MIAMI 0x11
128 #define DMD_ATSC_CHIP_MUJI 0x12
129 #define DMD_ATSC_CHIP_MUNICH 0x13
130 #define DMD_ATSC_CHIP_MAYA 0x14
131 #define DMD_ATSC_CHIP_MANHATTAN 0x15
132 #define DMD_ATSC_CHIP_WHISKY 0x16
133 #define DMD_ATSC_CHIP_MASERATI 0x17
134 #define DMD_ATSC_CHIP_MACAN 0x18
135 #define DMD_ATSC_CHIP_MUSTANG 0x19
136 #define DMD_ATSC_CHIP_MAXIM 0x1A
137 #define DMD_ATSC_CHIP_K3 0x80 //UTOF start from 0x80
138 #define DMD_ATSC_CHIP_KELTIC 0x81
139 #define DMD_ATSC_CHIP_KERES 0x82
140 #define DMD_ATSC_CHIP_KIRIN 0x83
141
142 #if defined(CHIP_A1)
143 #define DMD_ATSC_CHIP_VERSION DMD_ATSC_CHIP_A1
144 #elif defined(CHIP_A3)
145 #define DMD_ATSC_CHIP_VERSION DMD_ATSC_CHIP_A3
146 #elif defined(CHIP_A5)
147 #define DMD_ATSC_CHIP_VERSION DMD_ATSC_CHIP_A5
148 #elif defined(CHIP_A7)
149 #define DMD_ATSC_CHIP_VERSION DMD_ATSC_CHIP_A7
150 #elif defined(CHIP_AMETHYST)
151 #define DMD_ATSC_CHIP_VERSION DMD_ATSC_CHIP_A7P
152 #elif defined(CHIP_AGATE)
153 #define DMD_ATSC_CHIP_VERSION DMD_ATSC_CHIP_AGATE
154 #elif defined(CHIP_EDISON)
155 #define DMD_ATSC_CHIP_VERSION DMD_ATSC_CHIP_EDISON
156 #elif defined(CHIP_EINSTEIN)
157 #define DMD_ATSC_CHIP_VERSION DMD_ATSC_CHIP_EINSTEIN
158 #elif defined(CHIP_EINSTEIN3)
159 #define DMD_ATSC_CHIP_VERSION DMD_ATSC_CHIP_EINSTEIN3
160 #elif defined(CHIP_MONACO)
161 #define DMD_ATSC_CHIP_VERSION DMD_ATSC_CHIP_MONACO
162 #elif defined(CHIP_EMERALD)
163 #define DMD_ATSC_CHIP_VERSION DMD_ATSC_CHIP_EMERALD
164 #elif defined(CHIP_EIFFEL)
165 #define DMD_ATSC_CHIP_VERSION DMD_ATSC_CHIP_EIFFEL
166 #elif defined(CHIP_KAISER)
167 #define DMD_ATSC_CHIP_VERSION DMD_ATSC_CHIP_K3
168 #elif defined(CHIP_KELTIC)
169 #define DMD_ATSC_CHIP_VERSION DMD_ATSC_CHIP_KELTIC
170 #elif defined(CHIP_EDEN)
171 #define DMD_ATSC_CHIP_VERSION DMD_ATSC_CHIP_EDEN
172 #elif defined(CHIP_MIAMI)
173 #define DMD_ATSC_CHIP_VERSION DMD_ATSC_CHIP_MIAMI
174 #elif defined(CHIP_KERES)
175 #define DMD_ATSC_CHIP_VERSION DMD_ATSC_CHIP_KERES
176 #elif defined(CHIP_MUJI)
177 #define DMD_ATSC_CHIP_VERSION DMD_ATSC_CHIP_MUJI
178 #elif defined(CHIP_MUNICH)
179 #define DMD_ATSC_CHIP_VERSION DMD_ATSC_CHIP_MUNICH
180 #elif defined(CHIP_KIRIN)
181 #define DMD_ATSC_CHIP_VERSION DMD_ATSC_CHIP_KIRIN
182 #elif defined(CHIP_MAYA)
183 #define DMD_ATSC_CHIP_VERSION DMD_ATSC_CHIP_MAYA
184 #elif defined(CHIP_MANHATTAN)
185 #define DMD_ATSC_CHIP_VERSION DMD_ATSC_CHIP_MANHATTAN
186 #elif defined(CHIP_WHISKY)
187 #define DMD_ATSC_CHIP_VERSION DMD_ATSC_CHIP_WHISKY
188 #elif defined(CHIP_MASERATI)
189 #define DMD_ATSC_CHIP_VERSION DMD_ATSC_CHIP_MASERATI
190 #elif defined(CHIP_MACAN)
191 #define DMD_ATSC_CHIP_VERSION DMD_ATSC_CHIP_MACAN
192 #elif defined(CHIP_MUSTANG)
193 #define DMD_ATSC_CHIP_VERSION DMD_ATSC_CHIP_MUSTANG
194 #elif defined(CHIP_MAXIM)
195 #define DMD_ATSC_CHIP_VERSION DMD_ATSC_CHIP_MAXIM
196 #else
197 #define DMD_ATSC_CHIP_VERSION DMD_ATSC_CHIP_MACAN
198 #endif
199
200 //-------------------------------------------------------------------------------------------------
201 // Local Defines
202 //-------------------------------------------------------------------------------------------------
203
204 #define _RIU_READ_BYTE(addr) ( READ_BYTE(psDMD_ATSC_ResData->sDMD_ATSC_PriData.virtDMDBaseAddr + (addr) ) )
205 #define _RIU_WRITE_BYTE(addr, val) ( WRITE_BYTE(psDMD_ATSC_ResData->sDMD_ATSC_PriData.virtDMDBaseAddr + (addr), val) )
206
207 #define HAL_INTERN_ATSC_DBINFO(y) //y
208
209 #if (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_A1)
210 #ifndef MBRegBase
211 #define MBRegBase 0x112600UL
212 #endif
213 #ifndef MBRegBase_DMD1
214 #define MBRegBase_DMD1 0x112400UL
215 #endif
216 #else
217 #ifndef MBRegBase
218 #define MBRegBase 0x110500UL
219 #endif
220 #endif
221
222 #if (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_T3_T10)
223 #ifndef DMDMcuBase
224 #define DMDMcuBase 0x103460UL
225 #endif
226 #else
227 #ifndef DMDMcuBase
228 #define DMDMcuBase 0x103480UL
229 #endif
230 #endif
231
232 #if (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_K3)
233 #define INTERN_ATSC_OUTER_STATE 0xF0
234 #else
235 #define INTERN_ATSC_OUTER_STATE 0x80
236 #endif
237 #define INTERN_ATSC_VSB_TRAIN_SNR_LIMIT 0x05//0xBE//14.5dB
238 #define INTERN_ATSC_FEC_ENABLE 0x1F
239
240 #define VSB_ATSC 0x04
241 #define QAM256_ATSC 0x02
242
243 #define QAM16_J83ABC 0x00
244 #define QAM32_J83ABC 0x01
245 #define QAM64_J83ABC 0x02
246 #define QAM128_J83ABC 0x03
247 #define QAM256_J83ABC 0x04
248
249 //-------------------------------------------------------------------------------------------------
250 // Local Variables
251 //-------------------------------------------------------------------------------------------------
252
253 const MS_U8 INTERN_ATSC_table[] = {
254 #include "DMD_INTERN_ATSC.dat"
255 };
256
257 static MS_U16 u16Lib_size = sizeof(INTERN_ATSC_table);
258
259 #if (DMD_ATSC_CHIP_VERSION < DMD_ATSC_CHIP_K3)
260
261 #if (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_T7)
262 static MS_U8 Demod_Flow_register[17] = {0x52, 0x72, 0x52, 0x72, 0x5C, 0x5C, 0xA3, 0xEC, 0xEA,
263 0x05, 0x74, 0x1E, 0x38, 0x3A, 0x08, 0x70, 0x68};
264 #else
265 static MS_U8 Demod_Flow_register[21] = {0x52, 0x72, 0x52, 0x72, 0x5C, 0x5C, 0xA3, 0xEC, 0xEA,
266 0x05, 0x74, 0x1E, 0x38, 0x3A, 0x00, 0x00, 0x00, 0x00,
267 0x00, 0x00, 0x00};
268 #endif
269
270 #endif
271
272 #ifndef UTPA2
273 static const float _LogApproxTableX[80] =
274 { 1.00, 1.30, 1.69, 2.20, 2.86, 3.71, 4.83, 6.27, 8.16, 10.60, 13.79,
275 17.92, 23.30, 30.29, 39.37, 51.19, 66.54, 86.50, 112.46, 146.19,
276 190.05, 247.06, 321.18, 417.54, 542.80, 705.64, 917.33, 1192.53,
277 1550.29, 2015.38, 2620.00, 3405.99, 4427.79, 5756.13, 7482.97,
278 9727.86, 12646.22, 16440.08, 21372.11, 27783.74, 36118.86,
279 46954.52, 61040.88, 79353.15, 103159.09, 134106.82, 174338.86,
280 226640.52, 294632.68, 383022.48, 497929.22, 647307.99, 841500.39, 1093950.50,
281 1422135.65, 1848776.35, 2403409.25, 3124432.03, 4061761.64, 5280290.13,
282 6864377.17, 8923690.32, 11600797.42, 15081036.65, 19605347.64, 25486951.94,
283 33133037.52, 43072948.77, 55994833.40, 72793283.42, 94631268.45,
284 123020648.99, 159926843.68, 207904896.79, 270276365.82, 351359275.57,
285 456767058.24, 593797175.72, 771936328.43, 1003517226.96
286 };
287
288 static const float _LogApproxTableY[80] =
289 { 0.00, 0.11, 0.23, 0.34, 0.46, 0.57, 0.68, 0.80, 0.91, 1.03, 1.14, 1.25,
290 1.37, 1.48, 1.60, 1.71, 1.82, 1.94, 2.05, 2.16, 2.28, 2.39, 2.51, 2.62,
291 2.73, 2.85, 2.96, 3.08, 3.19, 3.30, 3.42, 3.53, 3.65, 3.76, 3.87, 3.99,
292 4.10, 4.22, 4.33, 4.44, 4.56, 4.67, 4.79, 4.90, 5.01, 5.13, 5.24, 5.36,
293 5.47, 5.58, 5.70, 5.81, 5.93, 6.04, 6.15, 6.27, 6.04, 6.15, 6.27, 6.38,
294 6.49, 6.61, 6.72, 6.84, 6.95, 7.06, 7.18, 7.29, 7.41, 7.52, 7.63, 7.75,
295 7.86, 7.98, 8.09, 8.20, 8.32, 8.43, 8.55, 8.66
296 };
297 #endif
298
299 //-------------------------------------------------------------------------------------------------
300 // Global Variables
301 //-------------------------------------------------------------------------------------------------
302
303 extern MS_U8 u8DMD_ATSC_DMD_ID;
304
305 extern DMD_ATSC_ResData *psDMD_ATSC_ResData;
306
307 //-------------------------------------------------------------------------------------------------
308 // Local Functions
309 //-------------------------------------------------------------------------------------------------
310 #ifndef UTPA2
311 #ifndef MSOS_TYPE_LINUX
Log10Approx(float flt_x)312 static float Log10Approx(float flt_x)
313 {
314 MS_U8 indx = 0;
315
316 do {
317 if (flt_x < _LogApproxTableX[indx])
318 break;
319 indx++;
320 }while (indx < 79); //stop at indx = 80
321
322 return _LogApproxTableY[indx];
323 }
324 #endif
325 #endif
326
_HAL_DMD_RIU_ReadByte(MS_U32 u32Addr)327 static MS_U8 _HAL_DMD_RIU_ReadByte(MS_U32 u32Addr)
328 {
329 return _RIU_READ_BYTE(((u32Addr) << 1) - ((u32Addr) & 1));
330 }
331
_HAL_DMD_RIU_WriteByte(MS_U32 u32Addr,MS_U8 u8Value)332 static void _HAL_DMD_RIU_WriteByte(MS_U32 u32Addr, MS_U8 u8Value)
333 {
334 _RIU_WRITE_BYTE(((u32Addr) << 1) - ((u32Addr) & 1), u8Value);
335 }
336
_HAL_DMD_RIU_WriteByteMask(MS_U32 u32Addr,MS_U8 u8Value,MS_U8 u8Mask)337 static void _HAL_DMD_RIU_WriteByteMask(MS_U32 u32Addr, MS_U8 u8Value, MS_U8 u8Mask)
338 {
339 _RIU_WRITE_BYTE((((u32Addr) <<1) - ((u32Addr) & 1)), (_RIU_READ_BYTE((((u32Addr) <<1) - ((u32Addr) & 1))) & ~(u8Mask)) | ((u8Value) & (u8Mask)));
340 }
_MBX_WriteReg(MS_U16 u16Addr,MS_U8 u8Data)341 static MS_BOOL _MBX_WriteReg(MS_U16 u16Addr, MS_U8 u8Data)
342 {
343 MS_U8 u8CheckCount;
344 MS_U8 u8CheckFlag = 0xFF;
345 MS_U32 u32MBRegBase = MBRegBase;
346
347 if (u8DMD_ATSC_DMD_ID == 0)
348 u32MBRegBase = MBRegBase;
349 else if (u8DMD_ATSC_DMD_ID == 1)
350 u32MBRegBase = MBRegBase_DMD1;
351
352 _HAL_DMD_RIU_WriteByte(u32MBRegBase + 0x00, (u16Addr&0xff));
353 _HAL_DMD_RIU_WriteByte(u32MBRegBase + 0x01, (u16Addr>>8));
354 _HAL_DMD_RIU_WriteByte(u32MBRegBase + 0x10, u8Data);
355 _HAL_DMD_RIU_WriteByte(u32MBRegBase + 0x1E, 0x01);
356
357 _HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, _HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)|0x02); // assert interrupt to VD MCU51
358 _HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, _HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)&(~0x02)); // de-assert interrupt to VD MCU51
359
360 for (u8CheckCount=0; u8CheckCount < 10; u8CheckCount++)
361 {
362 u8CheckFlag = _HAL_DMD_RIU_ReadByte(u32MBRegBase + 0x1E);
363 if ((u8CheckFlag&0x01)==0)
364 break;
365 MsOS_DelayTask(1);
366 }
367
368 if (u8CheckFlag&0x01)
369 {
370 printf("ERROR: ATSC INTERN DEMOD MBX WRITE TIME OUT!\n");
371 return FALSE;
372 }
373
374 return TRUE;
375 }
376
_MBX_ReadReg(MS_U16 u16Addr,MS_U8 * u8Data)377 static MS_BOOL _MBX_ReadReg(MS_U16 u16Addr, MS_U8 *u8Data)
378 {
379 MS_U8 u8CheckCount;
380 MS_U8 u8CheckFlag = 0xFF;
381 MS_U32 u32MBRegBase = MBRegBase;
382
383 if (u8DMD_ATSC_DMD_ID == 0)
384 u32MBRegBase = MBRegBase;
385 else if (u8DMD_ATSC_DMD_ID == 1)
386 u32MBRegBase = MBRegBase_DMD1;
387
388 _HAL_DMD_RIU_WriteByte(u32MBRegBase + 0x00, (u16Addr&0xff));
389 _HAL_DMD_RIU_WriteByte(u32MBRegBase + 0x01, (u16Addr>>8));
390 _HAL_DMD_RIU_WriteByte(u32MBRegBase + 0x1E, 0x02);
391
392 _HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, _HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)|0x02); // assert interrupt to VD MCU51
393 _HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, _HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)&(~0x02)); // de-assert interrupt to VD MCU51
394
395 for (u8CheckCount=0; u8CheckCount < 10; u8CheckCount++)
396 {
397 u8CheckFlag = _HAL_DMD_RIU_ReadByte(u32MBRegBase + 0x1E);
398 if ((u8CheckFlag&0x02)==0)
399 {
400 *u8Data = _HAL_DMD_RIU_ReadByte(u32MBRegBase + 0x10);
401 break;
402 }
403 MsOS_DelayTask(1);
404 }
405
406 if (u8CheckFlag&0x02)
407 {
408 printf("ERROR: ATSC INTERN DEMOD MBX READ TIME OUT!\n");
409 return FALSE;
410 }
411
412 return TRUE;
413 }
414
415 #if (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_K3)
_SEL_DMD(void)416 static MS_BOOL _SEL_DMD(void)
417 {
418 MS_U8 u8data = 0;
419
420 u8data = _HAL_DMD_RIU_ReadByte(0x101e3c);
421
422 if (u8DMD_ATSC_DMD_ID == 0) //select DMD0
423 u8data &= (~0x10);
424 else if (u8DMD_ATSC_DMD_ID == 1) //sel DMD1
425 u8data |= 0x10;
426
427 _HAL_DMD_RIU_WriteByte(0x101e3c, u8data);
428
429 return TRUE;
430 }
431 #endif
432
433 #if ((DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_A1) && (DMD_ATSC_CHIP_VERSION < DMD_ATSC_CHIP_K3))
_initTable(void)434 static void _initTable(void)
435 {
436 DMD_ATSC_ResData *pRes = psDMD_ATSC_ResData + u8DMD_ATSC_DMD_ID;
437
438 if (pRes->sDMD_ATSC_InitData.bTunerGainInvert)
439 Demod_Flow_register[12]=1;
440 else Demod_Flow_register[12]=0;
441
442 if (pRes->sDMD_ATSC_InitData.bIQSwap)
443 Demod_Flow_register[14] = 1;
444 else Demod_Flow_register[14] = 0;
445
446 Demod_Flow_register[15] = pRes->sDMD_ATSC_InitData.u16IF_KHZ&0xFF;
447 Demod_Flow_register[16] = (pRes->sDMD_ATSC_InitData.u16IF_KHZ)>>8;
448
449 printf("\n#### IF_KHz = [%d]\n", pRes->sDMD_ATSC_InitData.u16IF_KHZ);
450 printf("\n#### IQ_SWAP = [%d]\n", pRes->sDMD_ATSC_InitData.bIQSwap);
451 printf("\n#### Tuner Gain Invert = [%d]\n", pRes->sDMD_ATSC_InitData.bTunerGainInvert);
452 }
453 #endif
454
455 #if (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_T3_T10)
_HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)456 static void _HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)
457 {
458 HAL_INTERN_ATSC_DBINFO(printf("--------------DMD_ATSC_CHIP_T3_T10--------------\n"));
459
460 // MailBox
461 _HAL_DMD_RIU_WriteByte(0x100b44, 0x00); //clk mail box0 =xtal <<hk51 <--mail box 0--> aeon
462 _HAL_DMD_RIU_WriteByte(0x100b45, 0x00); //clk mail box0 =xtal <<hk51 <--mail box 1--> aeon
463
464 // Enable DMD MCU clock (108MHz)
465 if (_HAL_DMD_RIU_ReadByte(0x001ecf) == 0x00)
466 _HAL_DMD_RIU_WriteByte(0x100b42, 0x10);
467 else //after t3_u02
468 _HAL_DMD_RIU_WriteByte(0x100b42, 0x0D);
469
470 _HAL_DMD_RIU_WriteByte(0x100b43, 0x01); // Disable VD200 clock
471
472 _HAL_DMD_RIU_WriteByte(0x103314, 0x01); // Disable ADC clock
473
474 _HAL_DMD_RIU_WriteByte(0x103315, 0x01); // Disable DVB INNER clock
475
476 // Enable ATSC clock
477 _HAL_DMD_RIU_WriteByte(0x103302, 0x00);
478 _HAL_DMD_RIU_WriteByte(0x103303, 0x00);
479 _HAL_DMD_RIU_WriteByte(0x103304, 0x00);
480 _HAL_DMD_RIU_WriteByte(0x103305, 0x00);
481 _HAL_DMD_RIU_WriteByte(0x103306, 0x00);
482 _HAL_DMD_RIU_WriteByte(0x103307, 0x00);
483 _HAL_DMD_RIU_WriteByte(0x10330a, 0x08);
484
485 // Enable DVB INNERx1&2 clock
486 _HAL_DMD_RIU_WriteByte(0x10330c, 0x00);
487 _HAL_DMD_RIU_WriteByte(0x10330d, 0x00);
488
489 // Enable DVB SRAM0~SRAM3 clock
490 _HAL_DMD_RIU_WriteByte(0x103318, 0x00);
491 _HAL_DMD_RIU_WriteByte(0x103319, 0x00);
492
493 _HAL_DMD_RIU_WriteByte(0x103308, 0x00); // Enable ATSC TS clock
494 _HAL_DMD_RIU_WriteByte(0x103309, 0x01); // Disable DVB TS clock
495
496 _HAL_DMD_RIU_WriteByte(0x103300, 0x18); // Set DMD clock div
497 _HAL_DMD_RIU_WriteByte(0x103301, 0x04); // Enable DMD clock
498
499 MsOS_DelayTaskUs(1);
500
501 _HAL_DMD_RIU_WriteByte(0x103314, 0x00); // Enable ADC clock
502
503 _HAL_DMD_RIU_WriteByte(0x101e22, 0x02); // Set TS PAD
504 _HAL_DMD_RIU_WriteByte(0x101e23, 0x00);
505
506 _HAL_DMD_RIU_WriteByte(0x100b50, 0x08); // Enable TS0&1 clock
507 _HAL_DMD_RIU_WriteByte(0x100b51, 0x08);
508
509 if (bRFAGCTristateEnable)
510 _HAL_DMD_RIU_WriteByteMask(0x101e05, 0x20, 0x30); // Set IF&RF AGC output mode
511 else
512 _HAL_DMD_RIU_WriteByteMask(0x101e05, 0x00, 0x30); // Set IF&RF AGC output mode
513 }
514 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_T7)
_HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)515 static void _HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)
516 {
517 HAL_INTERN_ATSC_DBINFO(printf("--------------DMD_ATSC_CHIP_T7--------------\n"));
518
519 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10); // Enable DMD MCU clock (108MHz)
520
521 _HAL_DMD_RIU_WriteByte(0x103314, 0x01); // Disable ADC clock
522
523 _HAL_DMD_RIU_WriteByte(0x103315, 0x01); // Disable DVB INNER clock
524
525 // Enable ATSC clock
526 _HAL_DMD_RIU_WriteByte(0x103302, 0x00);
527 _HAL_DMD_RIU_WriteByte(0x103303, 0x00);
528 _HAL_DMD_RIU_WriteByte(0x103304, 0x00);
529 _HAL_DMD_RIU_WriteByte(0x103305, 0x00);
530 _HAL_DMD_RIU_WriteByte(0x103306, 0x00);
531 _HAL_DMD_RIU_WriteByte(0x103307, 0x00);
532 _HAL_DMD_RIU_WriteByte(0x10330a, 0x08);
533
534 // Enable DVB INNERx1&2&4 clock
535 _HAL_DMD_RIU_WriteByte(0x10330c, 0x00);
536 _HAL_DMD_RIU_WriteByte(0x10330d, 0x00);
537 _HAL_DMD_RIU_WriteByte(0x10330e, 0x00);
538
539 // Enable DVB OUTERx1&2&2_c clock
540 _HAL_DMD_RIU_WriteByte(0x103310, 0x00);
541 _HAL_DMD_RIU_WriteByte(0x103311, 0x00);
542 _HAL_DMD_RIU_WriteByte(0x103312, 0x00);
543
544 // Enable DVB EQx1&8c clock
545 _HAL_DMD_RIU_WriteByte(0x103316, 0x00);
546 _HAL_DMD_RIU_WriteByte(0x103317, 0x00);
547
548 // Enable DVB SRAM0~SRAM3 clock
549 _HAL_DMD_RIU_WriteByte(0x103318, 0x00);
550 _HAL_DMD_RIU_WriteByte(0x103319, 0x00);
551
552 _HAL_DMD_RIU_WriteByte(0x103308, 0x00); // Enable ATSC TS clock
553 _HAL_DMD_RIU_WriteByte(0x103309, 0x01); // Disable DVB TS clock
554
555 _HAL_DMD_RIU_WriteByte(0x103300, 0x18); // Set DMD clock div
556 _HAL_DMD_RIU_WriteByte(0x103301, 0x04); // Enable DMD clock
557
558 MsOS_DelayTaskUs(1);
559
560 _HAL_DMD_RIU_WriteByte(0x103314, 0x00); // Enable ADC clock
561
562 _HAL_DMD_RIU_WriteByte(0x101e22, 0x02); // Set TS PAD
563 _HAL_DMD_RIU_WriteByte(0x101e23, 0x00);
564
565 _HAL_DMD_RIU_WriteByte(0x100b50, 0x08); // Enable TS0&1 clock
566 _HAL_DMD_RIU_WriteByte(0x100b51, 0x08);
567
568 _HAL_DMD_RIU_WriteByteMask(0x101e9e, 0x00, 0xCF); // Set IF&RF AGC PAD and PWM AGC mode
569
570 if (bRFAGCTristateEnable)
571 _HAL_DMD_RIU_WriteByteMask(0x101e05, 0x20, 0x30); // Set IF&RF AGC output mode
572 else
573 _HAL_DMD_RIU_WriteByteMask(0x101e05, 0x00, 0x30); // Set IF&RF AGC output mode
574
575 _HAL_DMD_RIU_WriteByteMask(0x101ea1, 0x00, 0x80); // Set all pads (except SPI) as output
576
577 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x01);
578 _HAL_DMD_RIU_WriteByteMask(0x112003, 0x20, 0x20); // Release Ana misc resest
579 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x01, 0x01);
580
581 // Set DMD ANA
582 _HAL_DMD_RIU_WriteByte(0x112864, 0x00); // Set VCO first and second div
583 _HAL_DMD_RIU_WriteByte(0x112865, 0x00);
584
585 _HAL_DMD_RIU_WriteByte(0x11286C, 0x20); // Disable T&RF-AGC
586 _HAL_DMD_RIU_WriteByte(0x11286D, 0x00);
587
588 _HAL_DMD_RIU_WriteByte(0x112868, 0x00);
589 _HAL_DMD_RIU_WriteByte(0x112869, 0x80);
590
591 _HAL_DMD_RIU_WriteByte(0x112862, 0x00); // Set PLL first and second div
592 _HAL_DMD_RIU_WriteByte(0x112863, 0x00);
593
594 _HAL_DMD_RIU_WriteByte(0x112818, 0x03); // ADC I&Q pown down
595 _HAL_DMD_RIU_WriteByte(0x112819, 0x00);
596
597 MsOS_DelayTaskUs(2);
598
599 _HAL_DMD_RIU_WriteByte(0x11286A, 0x86); // Initial MPLL procedure
600 _HAL_DMD_RIU_WriteByte(0x11286B, 0x1E);
601 MsOS_DelayTaskUs(2);
602 _HAL_DMD_RIU_WriteByte(0x11286A, 0x06);
603 _HAL_DMD_RIU_WriteByte(0x11286B, 0x1E);
604 MsOS_DelayTaskUs(2);
605 _HAL_DMD_RIU_WriteByte(0x11286A, 0x06);
606 _HAL_DMD_RIU_WriteByte(0x11286B, 0x06);
607
608 MsOS_DelayTaskUs(2);
609
610 _HAL_DMD_RIU_WriteByte(0x112866, 0x01); // Set MPLL first and second div
611 _HAL_DMD_RIU_WriteByte(0x112867, 0x1d);
612
613 _HAL_DMD_RIU_WriteByte(0x112860, 0x00); // MPLL power up
614 _HAL_DMD_RIU_WriteByte(0x112861, 0x1c); // Set ADC output div
615
616 _HAL_DMD_RIU_WriteByte(0x112802, 0x40); // Set ADC I&Q
617 _HAL_DMD_RIU_WriteByte(0x112803, 0x04);
618
619 _HAL_DMD_RIU_WriteByte(0x112816, 0x05); // set PGA gain
620 _HAL_DMD_RIU_WriteByte(0x112817, 0x05);
621
622 _HAL_DMD_RIU_WriteByte(0x112818, 0x00); // ADC I&Q pown up
623 _HAL_DMD_RIU_WriteByte(0x112819, 0x00);
624
625 _HAL_DMD_RIU_WriteByte(0x112840, 0x00); // Disable SIF&VIF
626 _HAL_DMD_RIU_WriteByte(0x112841, 0x00);
627 }
628 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_T8_T9)
_HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)629 static void _HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)
630 {
631 HAL_INTERN_ATSC_DBINFO(printf("--------------DMD_ATSC_CHIP_T8_T9--------------\n"));
632
633 _HAL_DMD_RIU_WriteByte(0x10331E, 0x10); // Enable DMD MCU clock (108MHz)
634
635 _HAL_DMD_RIU_WriteByte(0x103314, 0x01); // Disable ADC clock
636
637 // Enable ATSC clock
638 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x08);
639 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
640 _HAL_DMD_RIU_WriteByte(0x111f02, 0x00);
641 _HAL_DMD_RIU_WriteByte(0x111f03, 0x00);
642 _HAL_DMD_RIU_WriteByte(0x111f04, 0x00);
643 _HAL_DMD_RIU_WriteByte(0x111f05, 0x00);
644 _HAL_DMD_RIU_WriteByte(0x111f06, 0x00);
645 _HAL_DMD_RIU_WriteByte(0x111f07, 0x00);
646
647 // Disable DVB INNERx1&2&4 clock
648 _HAL_DMD_RIU_WriteByte(0x111f0c, 0x01);
649 _HAL_DMD_RIU_WriteByte(0x111f0d, 0x01);
650 _HAL_DMD_RIU_WriteByte(0x111f0e, 0x01);
651
652 // Disable DVB OUTERx1&2&2_c clock
653 _HAL_DMD_RIU_WriteByte(0x111f10, 0x01);
654 _HAL_DMD_RIU_WriteByte(0x111f11, 0x01);
655 _HAL_DMD_RIU_WriteByte(0x111f12, 0x01);
656
657 // Disable DVB INNER clock
658 _HAL_DMD_RIU_WriteByte(0x111f15, 0x01);
659
660 // Disable DVB EQx1&8c clock
661 _HAL_DMD_RIU_WriteByte(0x111f16, 0x01);
662 _HAL_DMD_RIU_WriteByte(0x111f17, 0x01);
663
664 // Enable DVB SRAM0~SRAM3 clock
665 _HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
666 _HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
667
668 _HAL_DMD_RIU_WriteByte(0x103300, 0x11); // Set DMD clock div
669 _HAL_DMD_RIU_WriteByte(0x103301, 0x05); // Enable DMD clock
670
671 _HAL_DMD_RIU_WriteByte(0x103308, 0x00); // Enable ATSC TS clock
672 _HAL_DMD_RIU_WriteByte(0x103309, 0x01); // Disable DVB TS clock
673
674 // Disable VIF clock
675 _HAL_DMD_RIU_WriteByte(0x111f1c, 0x01);
676 _HAL_DMD_RIU_WriteByte(0x111f1d, 0x01);
677 _HAL_DMD_RIU_WriteByte(0x10331a, 0x01);
678 _HAL_DMD_RIU_WriteByte(0x10331b, 0x01);
679
680 MsOS_DelayTaskUs(1);
681
682 _HAL_DMD_RIU_WriteByte(0x103314, 0x00); // Enable ADC clock
683
684 _HAL_DMD_RIU_WriteByteMask(0x101eaf, 0x10, 0x18); // Set TS PAD
685
686 if (bRFAGCTristateEnable)
687 _HAL_DMD_RIU_WriteByteMask(0x101e05, 0x20, 0x30); // Set IF&RF AGC output mode
688 else
689 _HAL_DMD_RIU_WriteByteMask(0x101e05, 0x00, 0x30); // Set IF&RF AGC output mode
690
691 _HAL_DMD_RIU_WriteByteMask(0x101e9e, 0x00, 0xCF); // Set IF&RF AGC PAD and PWM AGC mode
692
693 _HAL_DMD_RIU_WriteByteMask(0x101ea0, 0x00, 0x03); // PWM2 uses PAD_PWM2 and PWM3 uses PAD_PWM3
694 _HAL_DMD_RIU_WriteByteMask(0x101ea1, 0x00, 0x80); // Set all pads (except SPI) as output
695
696 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
697 }
698 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_A1)
_HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)699 static void _HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)
700 {
701 HAL_INTERN_ATSC_DBINFO(printf("--------------DMD_ATSC_CHIP_A1--------------\n"));
702
703 //Set register at CLKGEN1
704 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
705 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10); // Denny: change 0x10!! 108M
706
707 _HAL_DMD_RIU_WriteByte(0x103314, 0x01); // Disable ADC clock
708
709 // set parallet ts clock
710 _HAL_DMD_RIU_WriteByte(0x103301, 0x05);
711 _HAL_DMD_RIU_WriteByte(0x103300, 0x11);
712
713 // enable atsc, DVBTC ts clock
714 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
715 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
716
717 // enable dvbc adc clock
718 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
719
720 // enable vif DAC clock
721 _HAL_DMD_RIU_WriteByte(0x10331b, 0x00);
722 _HAL_DMD_RIU_WriteByte(0x10331a, 0x00);
723
724 // Set register at CLKGEN_DMD
725 _HAL_DMD_RIU_WriteByte(0x111f03, 0x00);
726 _HAL_DMD_RIU_WriteByte(0x111f02, 0x00);
727 _HAL_DMD_RIU_WriteByte(0x111f05, 0x00);
728 _HAL_DMD_RIU_WriteByte(0x111f04, 0x00);
729 _HAL_DMD_RIU_WriteByte(0x111f07, 0x00);
730 _HAL_DMD_RIU_WriteByte(0x111f06, 0x00);
731
732 // enable clk_atsc_adcd_sync
733 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
734 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x08);
735
736 // enable dvbt inner clock
737 _HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
738 _HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
739
740 // enable dvbt inner clock
741 _HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
742 _HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
743
744 // enable dvbt inner clock
745 _HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
746 _HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
747
748 // enable dvbc outer clock
749 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
750 _HAL_DMD_RIU_WriteByte(0x111f12, 0x08);
751
752 // enable dvbc inner-c clock
753 _HAL_DMD_RIU_WriteByte(0x111f15, 0x00);
754 _HAL_DMD_RIU_WriteByte(0x111f14, 0x00);
755
756 // enable dvbc eq clock
757 _HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
758 _HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
759
760 // enable vif clock
761 _HAL_DMD_RIU_WriteByte(0x111f1d, 0x00);
762 _HAL_DMD_RIU_WriteByte(0x111f1c, 0x00);
763
764 // For ADC DMA Dump
765 _HAL_DMD_RIU_WriteByte(0x111f21, 0x00);
766 _HAL_DMD_RIU_WriteByte(0x111f20, 0x00);
767
768 // select clock
769 _HAL_DMD_RIU_WriteByte(0x111f23, 0x00);
770 _HAL_DMD_RIU_WriteByte(0x111f22, 0x00);
771
772 MsOS_DelayTaskUs(1);
773
774 _HAL_DMD_RIU_WriteByte(0x103314, 0x00); // Enable ADC clock
775
776 // Turn TSP
777 _HAL_DMD_RIU_WriteByte(0x100b55, 0x00);
778 _HAL_DMD_RIU_WriteByte(0x100b54, 0x00);
779
780 // set the ts0_clk from demod
781 _HAL_DMD_RIU_WriteByte(0x100b51, 0x00);
782 _HAL_DMD_RIU_WriteByte(0x100b50, 0x0C);
783 _HAL_DMD_RIU_WriteByte(0x101e22, 0x02);
784
785 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
786 }
787 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_A7)
_HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)788 static void _HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)
789 {
790 HAL_INTERN_ATSC_DBINFO(printf("--------------DMD_ATSC_CHIP_A7--------------\n"));
791
792 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
793 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
794
795 _HAL_DMD_RIU_WriteByte(0x103314, 0x01); // Disable ADC clock
796
797 _HAL_DMD_RIU_WriteByte(0x103301, 0x05);
798 _HAL_DMD_RIU_WriteByte(0x103300, 0x11);
799 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
800 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
801 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
802 _HAL_DMD_RIU_WriteByte(0x111f03, 0x00);
803 _HAL_DMD_RIU_WriteByte(0x111f02, 0x00);
804 _HAL_DMD_RIU_WriteByte(0x111f05, 0x00);
805 _HAL_DMD_RIU_WriteByte(0x111f04, 0x00);
806 _HAL_DMD_RIU_WriteByte(0x111f07, 0x00);
807 _HAL_DMD_RIU_WriteByte(0x111f06, 0x00);
808 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
809 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
810 _HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
811 _HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
812 _HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
813 _HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
814 _HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
815 _HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
816 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
817 _HAL_DMD_RIU_WriteByte(0x111f12, 0x08);
818 _HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
819 _HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
820 _HAL_DMD_RIU_WriteByte(0x111f25, 0x00);
821 _HAL_DMD_RIU_WriteByte(0x111f24, 0x00);
822 _HAL_DMD_RIU_WriteByte(0x111f23, 0x00);
823 _HAL_DMD_RIU_WriteByte(0x111f22, 0x00);
824
825 MsOS_DelayTaskUs(1);
826
827 _HAL_DMD_RIU_WriteByte(0x103314, 0x00); // Enable ADC clock
828
829 _HAL_DMD_RIU_WriteByteMask(0x000e13, 0x00, 0x04);
830
831 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
832 }
833 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_K3)
_HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)834 static void _HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)
835 {
836 DMD_ATSC_ResData *pRes = psDMD_ATSC_ResData + u8DMD_ATSC_DMD_ID;
837
838 HAL_INTERN_ATSC_DBINFO(printf("--------------DMD_ATSC_CHIP_K3--------------\n"));
839
840 if (pRes->sDMD_ATSC_InitData.u8IS_DUAL)
841 {
842 _HAL_DMD_RIU_WriteByte(0x101e39, 0x00);
843 _HAL_DMD_RIU_WriteByte(0x101e3d, 0x00);
844
845 /****************DMD0****************/
846
847 //set CLK_DMDMCU as 108M Hz
848 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
849
850 // set parallet ts clock
851 _HAL_DMD_RIU_WriteByte(0x103301, 0x07);
852 _HAL_DMD_RIU_WriteByte(0x103300, 0x11);
853
854 // enable DVBTC ts clock
855 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
856
857 // enable dvbc adc clock
858 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
859 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
860
861 // enable clk_atsc_adcd_sync
862 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
863 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x04);
864
865 // enable dvbt inner clock
866 _HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
867
868 // enable dvbt outer clock
869 _HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
870
871 // enable dvbc outer clock
872 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
873 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
874
875 // enable dvbc inner-c clock
876 _HAL_DMD_RIU_WriteByte(0x111f15, 0x04);
877
878 // enable dvbc eq clock
879 _HAL_DMD_RIU_WriteByte(0x111f17, 0x00);
880 _HAL_DMD_RIU_WriteByte(0x111f16, 0x00);
881
882 // For ADC DMA Dump
883 _HAL_DMD_RIU_WriteByte(0x111f22, 0x04);
884
885 // Turn TSP
886 //_HAL_DMD_RIU_WriteByte(0x000e13, 0x01);
887
888 //set reg_allpad_in
889 _HAL_DMD_RIU_WriteByte(0x101ea1, 0x00);
890 _HAL_DMD_RIU_WriteByte(0x101e04, 0x02);
891 _HAL_DMD_RIU_WriteByte(0x101e76, 0x03);
892
893 /****************DMD1****************/
894 _HAL_DMD_RIU_WriteByte(0x10331f, 0x10);
895
896 _HAL_DMD_RIU_WriteByte(0x103321, 0x07);
897 _HAL_DMD_RIU_WriteByte(0x103320, 0x11);
898
899 _HAL_DMD_RIU_WriteByte(0x103323, 0x00);
900 _HAL_DMD_RIU_WriteByte(0x103322, 0x00);
901
902 _HAL_DMD_RIU_WriteByte(0x11220b, 0x00);
903 _HAL_DMD_RIU_WriteByte(0x11220a, 0x04);
904
905 _HAL_DMD_RIU_WriteByte(0x11220c, 0x00);
906 _HAL_DMD_RIU_WriteByte(0x112211, 0x00);
907
908 _HAL_DMD_RIU_WriteByte(0x112213, 0x00);
909 _HAL_DMD_RIU_WriteByte(0x112212, 0x00);
910
911 _HAL_DMD_RIU_WriteByte(0x112215, 0x04);
912
913 _HAL_DMD_RIU_WriteByte(0x112217, 0x00);
914 _HAL_DMD_RIU_WriteByte(0x112216, 0x00);
915
916 _HAL_DMD_RIU_WriteByte(0x112222, 0x04);
917
918 _HAL_DMD_RIU_WriteByte(0x101e39, 0x03); //force ANA MISC controlled by DMD0
919 _HAL_DMD_RIU_WriteByte(0x101e3d, 0x01);
920 }
921 else
922 {
923 _HAL_DMD_RIU_WriteByte(0x101e39, 0x00);
924
925 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
926 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
927
928 _HAL_DMD_RIU_WriteByte(0x103301, 0x07);
929 _HAL_DMD_RIU_WriteByte(0x103300, 0x11);
930
931 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
932
933 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
934 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
935
936 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
937 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
938
939 _HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
940
941 _HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
942
943 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
944 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
945
946 _HAL_DMD_RIU_WriteByte(0x111f15, 0x00);
947
948 _HAL_DMD_RIU_WriteByte(0x111f17, 0x00);
949 _HAL_DMD_RIU_WriteByte(0x111f16, 0x00);
950
951 _HAL_DMD_RIU_WriteByte(0x111f22, 0x00);
952
953 _HAL_DMD_RIU_WriteByte(0x101ea1, 0x00);
954 _HAL_DMD_RIU_WriteByte(0x101e04, 0x02);
955 _HAL_DMD_RIU_WriteByte(0x101e76, 0x03);
956
957 _HAL_DMD_RIU_WriteByte(0x101e39, 0x03); //force ANA MISC controlled by DMD0
958 _HAL_DMD_RIU_WriteByte(0x101e3d, 0x01);
959 }
960 }
961 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_KELTIC)
_HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)962 static void _HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)
963 {
964 HAL_INTERN_ATSC_DBINFO(printf("--------------DMD_ATSC_CHIP_KELTIC--------------\n"));
965
966 _HAL_DMD_RIU_WriteByte(0x101e39, 0x00);
967
968 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
969 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
970
971 _HAL_DMD_RIU_WriteByte(0x103301, 0x07);
972 _HAL_DMD_RIU_WriteByte(0x103300, 0x11);
973
974 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
975
976 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
977 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
978
979 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
980 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x00);
981
982 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
983 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
984
985 _HAL_DMD_RIU_WriteByte(0x111f15, 0x00);
986
987 _HAL_DMD_RIU_WriteByte(0x111f17, 0x00);
988 _HAL_DMD_RIU_WriteByte(0x111f16, 0x00);
989
990 _HAL_DMD_RIU_WriteByte(0x111f22, 0x00);
991
992 _HAL_DMD_RIU_WriteByte(0x1120bc, 0x00);
993
994 _HAL_DMD_RIU_WriteByte(0x101ea1, 0x00);
995 _HAL_DMD_RIU_WriteByte(0x101e04, 0x02);
996
997 _HAL_DMD_RIU_WriteByte(0x101e39, 0x03);
998 }
999 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_KERES)
_HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)1000 static void _HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)
1001 {
1002 MS_U8 u8Val=0x00;
1003
1004 HAL_INTERN_ATSC_DBINFO(printf("--------------DMD_ATSC_CHIP_KERES--------------\n"));
1005
1006 u8Val = _HAL_DMD_RIU_ReadByte(0x101e39);
1007 _HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
1008
1009 _HAL_DMD_RIU_WriteByte(0x10331f,0x00);
1010 _HAL_DMD_RIU_WriteByte(0x10331e,0x10);
1011 _HAL_DMD_RIU_WriteByte(0x103301,0x07);
1012 _HAL_DMD_RIU_WriteByte(0x103300,0x11);
1013 _HAL_DMD_RIU_WriteByte(0x103309,0x00);
1014 _HAL_DMD_RIU_WriteByte(0x103315,0x00);
1015 _HAL_DMD_RIU_WriteByte(0x103314,0x00);
1016
1017 _HAL_DMD_RIU_WriteByte(0x111f0b,0x00);
1018 _HAL_DMD_RIU_WriteByte(0x111f0a,0x00);
1019 _HAL_DMD_RIU_WriteByte(0x111f0c,0x00);
1020 _HAL_DMD_RIU_WriteByte(0x111f11,0x00);
1021 _HAL_DMD_RIU_WriteByte(0x111f13,0x00);
1022 _HAL_DMD_RIU_WriteByte(0x111f12,0x00);
1023 _HAL_DMD_RIU_WriteByte(0x111f15,0x00);
1024 _HAL_DMD_RIU_WriteByte(0x111f17,0x00);
1025 _HAL_DMD_RIU_WriteByte(0x111f16,0x00);
1026 _HAL_DMD_RIU_WriteByte(0x111f22,0x00);
1027 _HAL_DMD_RIU_WriteByte(0x111f2b,0x00); //enable clk_rs
1028 _HAL_DMD_RIU_WriteByte(0x111f2a,0x10);
1029 //_HAL_DMD_RIU_WriteByte(0x000e13,0x01); // No need, it cause uart issue.
1030 _HAL_DMD_RIU_WriteByte(0x101ea1,0x00);
1031
1032 _HAL_DMD_RIU_WriteByte(0x101e04,0x02);
1033 _HAL_DMD_RIU_WriteByte(0x101e76,0x03);
1034
1035 u8Val = _HAL_DMD_RIU_ReadByte(0x101e39);
1036 _HAL_DMD_RIU_WriteByte(0x101e39, u8Val|0x03);
1037 }
1038 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_EDEN)
_HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)1039 static void _HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)
1040 {
1041 MS_U8 u8Val = 0x00;
1042
1043 HAL_INTERN_ATSC_DBINFO(printf("--------------DMD_ATSC_CHIP_EDEN--------------\n"));
1044
1045 u8Val = _HAL_DMD_RIU_ReadByte(0x101e39);
1046 _HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
1047
1048 _HAL_DMD_RIU_WriteByte(0x10331e,0x10);
1049 _HAL_DMD_RIU_WriteByte(0x103301,0x04);
1050 _HAL_DMD_RIU_WriteByte(0x103300,0x0B);
1051 _HAL_DMD_RIU_WriteByte(0x103309,0x00);
1052 _HAL_DMD_RIU_WriteByte(0x103308,0x00);
1053 _HAL_DMD_RIU_WriteByte(0x103315,0x00);
1054 _HAL_DMD_RIU_WriteByte(0x103314,0x04);
1055
1056 _HAL_DMD_RIU_WriteByte(0x111f03,0x00);
1057 _HAL_DMD_RIU_WriteByte(0x111f02,0x00);
1058 _HAL_DMD_RIU_WriteByte(0x111f05,0x00);
1059 _HAL_DMD_RIU_WriteByte(0x111f04,0x00);
1060 _HAL_DMD_RIU_WriteByte(0x111f07,0x00);
1061 _HAL_DMD_RIU_WriteByte(0x111f06,0x00);
1062 _HAL_DMD_RIU_WriteByte(0x111f0b,0x00);
1063 _HAL_DMD_RIU_WriteByte(0x111f0a,0x08);
1064
1065 _HAL_DMD_RIU_WriteByte(0x111f0d,0x00);
1066 _HAL_DMD_RIU_WriteByte(0x111f0c,0x00);
1067 _HAL_DMD_RIU_WriteByte(0x111f0f,0x00);
1068 _HAL_DMD_RIU_WriteByte(0x111f0e,0x00);
1069
1070 _HAL_DMD_RIU_WriteByte(0x111f11,0x00);
1071 _HAL_DMD_RIU_WriteByte(0x111f10,0x00);
1072 _HAL_DMD_RIU_WriteByte(0x111f13,0x00);
1073 _HAL_DMD_RIU_WriteByte(0x111f12,0x08);
1074 _HAL_DMD_RIU_WriteByte(0x111f19,0x00);
1075 _HAL_DMD_RIU_WriteByte(0x111f18,0x00);
1076 _HAL_DMD_RIU_WriteByte(0x111f23,0x40);
1077 _HAL_DMD_RIU_WriteByte(0x111f22,0x00);
1078
1079 u8Val = _HAL_DMD_RIU_ReadByte(0x101e39);
1080 _HAL_DMD_RIU_WriteByte(0x101e39, (u8Val|0x03));
1081 }
1082 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_EMERALD)
_HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)1083 static void _HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)
1084 {
1085 MS_U8 u8Val = 0x00;
1086
1087 HAL_INTERN_ATSC_DBINFO(printf("--------------DMD_ATSC_CHIP_EMERALD--------------\n"));
1088
1089 u8Val = _HAL_DMD_RIU_ReadByte(0x101e39);
1090 _HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
1091
1092 _HAL_DMD_RIU_WriteByte(0x10331f,0x00);//Different with EDEN!
1093 _HAL_DMD_RIU_WriteByte(0x10331e,0x10);
1094 _HAL_DMD_RIU_WriteByte(0x103301,0x05);//Different with EDEN!
1095 _HAL_DMD_RIU_WriteByte(0x103300,0x11);//Different with EDEN!
1096 _HAL_DMD_RIU_WriteByte(0x103309,0x00);
1097 _HAL_DMD_RIU_WriteByte(0x103308,0x00);
1098 _HAL_DMD_RIU_WriteByte(0x103315,0x00);
1099 _HAL_DMD_RIU_WriteByte(0x103314,0x00);//Different with EDEN!
1100
1101 _HAL_DMD_RIU_WriteByte(0x111f03,0x00);
1102 _HAL_DMD_RIU_WriteByte(0x111f02,0x00);
1103 _HAL_DMD_RIU_WriteByte(0x111f05,0x00);
1104 _HAL_DMD_RIU_WriteByte(0x111f04,0x00);
1105 _HAL_DMD_RIU_WriteByte(0x111f07,0x00);
1106 _HAL_DMD_RIU_WriteByte(0x111f06,0x00);
1107 _HAL_DMD_RIU_WriteByte(0x111f0b,0x00);
1108 _HAL_DMD_RIU_WriteByte(0x111f0a,0x08);
1109
1110 _HAL_DMD_RIU_WriteByte(0x111f0d,0x00);
1111 _HAL_DMD_RIU_WriteByte(0x111f0c,0x00);
1112 _HAL_DMD_RIU_WriteByte(0x111f0f,0x00);
1113 _HAL_DMD_RIU_WriteByte(0x111f0e,0x00);
1114
1115 _HAL_DMD_RIU_WriteByte(0x111f11,0x00);
1116 _HAL_DMD_RIU_WriteByte(0x111f10,0x00);
1117 _HAL_DMD_RIU_WriteByte(0x111f13,0x00);
1118 _HAL_DMD_RIU_WriteByte(0x111f12,0x08);
1119 _HAL_DMD_RIU_WriteByte(0x111f19,0x00);
1120 _HAL_DMD_RIU_WriteByte(0x111f18,0x00);
1121 _HAL_DMD_RIU_WriteByte(0x111f23,0x00);//Different with EDEN!
1122 _HAL_DMD_RIU_WriteByte(0x111f22,0x00);
1123
1124 _HAL_DMD_RIU_WriteByte(0x111f25,0x00);//Different with EDEN!
1125 _HAL_DMD_RIU_WriteByte(0x111f24,0x00);//Different with EDEN!
1126 _HAL_DMD_RIU_WriteByte(0x111f1E,0x00);//Different with EDEN!
1127 _HAL_DMD_RIU_WriteByte(0x111f09,0x00);//Different with EDEN!
1128
1129 u8Val = _HAL_DMD_RIU_ReadByte(0x000e13);
1130 _HAL_DMD_RIU_WriteByte(0x000e13, u8Val&0xFB);
1131
1132 u8Val = _HAL_DMD_RIU_ReadByte(0x101e39);
1133 _HAL_DMD_RIU_WriteByte(0x101e39, u8Val|0x03);
1134 }
1135 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_EINSTEIN)
_HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)1136 static void _HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)
1137 {
1138 MS_U8 u8Val = 0;
1139
1140 HAL_INTERN_ATSC_DBINFO(printf("--------------DMD_ATSC_CHIP_EINSTEIN--------------\n"));
1141
1142 u8Val = _HAL_DMD_RIU_ReadByte(0x101e39);
1143 _HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
1144
1145 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
1146 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10); //Denny: change 0x10!! 108M
1147 _HAL_DMD_RIU_WriteByte(0x103301, 0x05); //addy update 0809 MAdp_Demod_WriteReg(0x103301, 0x06);
1148 _HAL_DMD_RIU_WriteByte(0x103300, 0x11); //addy update 0809 MAdp_Demod_WriteReg(0x103300, 0x0B);
1149 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
1150 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
1151 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
1152 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
1153
1154 _HAL_DMD_RIU_WriteByte(0x111f28, 0x00); //dan add for nugget
1155 _HAL_DMD_RIU_WriteByte(0x111f03, 0x00);
1156 _HAL_DMD_RIU_WriteByte(0x111f02, 0x00);
1157 _HAL_DMD_RIU_WriteByte(0x111f05, 0x00);
1158 _HAL_DMD_RIU_WriteByte(0x111f04, 0x00);
1159 _HAL_DMD_RIU_WriteByte(0x111f07, 0x00);
1160 _HAL_DMD_RIU_WriteByte(0x111f06, 0x00);
1161 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
1162 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x08); // note enable clk_atsc_adcd_sync=25.41
1163
1164 _HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
1165 _HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
1166 _HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
1167 _HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
1168
1169 _HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
1170 _HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
1171 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
1172 _HAL_DMD_RIU_WriteByte(0x111f12, 0x08); //0406 update 0->8
1173 _HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
1174 _HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
1175
1176 _HAL_DMD_RIU_WriteByte(0x111f43, 0x00); //dan add for nugget
1177 _HAL_DMD_RIU_WriteByte(0x111f42, 0x00); //dan add for nugget
1178 _HAL_DMD_RIU_WriteByte(0x111f45, 0x00); //dan add for nugget
1179 _HAL_DMD_RIU_WriteByte(0x111f44, 0x00); //dan add for nugget
1180 _HAL_DMD_RIU_WriteByte(0x111f46, 0x01); //dan add for nugget
1181 _HAL_DMD_RIU_WriteByte(0x111f49, 0x00); //dan add for nugget
1182 _HAL_DMD_RIU_WriteByte(0x111f48, 0x00); //dan add for nugget
1183 _HAL_DMD_RIU_WriteByte(0x111f4b, 0x00); //dan add for nugget
1184 _HAL_DMD_RIU_WriteByte(0x111f4a, 0x00); //dan add for nugget
1185 _HAL_DMD_RIU_WriteByte(0x111f4c, 0x00); //dan add for nugget
1186
1187 _HAL_DMD_RIU_WriteByte(0x111f23, 0x00);
1188 _HAL_DMD_RIU_WriteByte(0x111f22, 0x00);//0x08); VT found some err.
1189
1190 u8Val = _HAL_DMD_RIU_ReadByte(0x101e39);
1191 _HAL_DMD_RIU_WriteByte(0x101e39, u8Val|0x03);
1192 }
1193 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_EINSTEIN3)
_HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)1194 static void _HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)
1195 {
1196 MS_U8 u8Val = 0;
1197
1198 HAL_INTERN_ATSC_DBINFO(printf("--------------DMD_ATSC_CHIP_EINSTEIN3--------------\n"));
1199
1200 u8Val = _HAL_DMD_RIU_ReadByte(0x101e39);
1201 _HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
1202
1203 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
1204 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);// Denny: change 0x10!! 108M
1205 _HAL_DMD_RIU_WriteByte(0x103301, 0x05);//addy update 0809 MAdp_Demod_WriteReg(0x103301, 0x06);
1206 _HAL_DMD_RIU_WriteByte(0x103300, 0x11);//addy update 0809 MAdp_Demod_WriteReg(0x103300, 0x0B);
1207 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
1208 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
1209 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
1210 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
1211
1212 _HAL_DMD_RIU_WriteByte(0x111f28, 0x00); //dan add for nugget
1213 _HAL_DMD_RIU_WriteByte(0x111f03, 0x00);
1214 _HAL_DMD_RIU_WriteByte(0x111f02, 0x00);
1215 _HAL_DMD_RIU_WriteByte(0x111f05, 0x00);
1216 _HAL_DMD_RIU_WriteByte(0x111f04, 0x00);
1217 _HAL_DMD_RIU_WriteByte(0x111f07, 0x00);
1218 _HAL_DMD_RIU_WriteByte(0x111f06, 0x00);
1219 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
1220 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x08); // note enable clk_atsc_adcd_sync=25.41
1221
1222 _HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
1223 _HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
1224 _HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
1225 _HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
1226
1227 _HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
1228 _HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
1229 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
1230 _HAL_DMD_RIU_WriteByte(0x111f12, 0x08);//0406 update 0->8
1231 _HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
1232 _HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
1233
1234 _HAL_DMD_RIU_WriteByte(0x111f43, 0x00); //dan add for nugget
1235 _HAL_DMD_RIU_WriteByte(0x111f42, 0x00); //dan add for nugget
1236 _HAL_DMD_RIU_WriteByte(0x111f45, 0x00); //dan add for nugget
1237 _HAL_DMD_RIU_WriteByte(0x111f44, 0x00); //dan add for nugget
1238 _HAL_DMD_RIU_WriteByte(0x111f46, 0x01); //dan add for nugget
1239 _HAL_DMD_RIU_WriteByte(0x111f49, 0x00); //dan add for nugget
1240 _HAL_DMD_RIU_WriteByte(0x111f48, 0x00); //dan add for nugget
1241 _HAL_DMD_RIU_WriteByte(0x111f4b, 0x00); //dan add for nugget
1242 _HAL_DMD_RIU_WriteByte(0x111f4a, 0x00); //dan add for nugget
1243 _HAL_DMD_RIU_WriteByte(0x111f4c, 0x00); //dan add for nugget
1244
1245 _HAL_DMD_RIU_WriteByte(0x111f23, 0x00);
1246 _HAL_DMD_RIU_WriteByte(0x111f22, 0x00);//0x08); VT found some err.
1247
1248 u8Val = _HAL_DMD_RIU_ReadByte(0x101e39);
1249 _HAL_DMD_RIU_WriteByte(0x101e39, u8Val|0x03);
1250 }
1251 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MONACO)
_HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)1252 static void _HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)
1253 {
1254 MS_U8 u8Val = 0;
1255
1256 HAL_INTERN_ATSC_DBINFO(printf("--------------DMD_ATSC_CHIP_MONACO--------------\n"));
1257
1258 u8Val = _HAL_DMD_RIU_ReadByte(0x101e39);
1259 _HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
1260
1261 // DMDMCU 108M
1262 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
1263 // Set parallel TS clock
1264 // [11] : reg_ckg_demod_test_in_en = 0
1265 // 0: select internal ADC CLK
1266 // 1: select external test-in clock
1267 // [10] : reg_ckg_dvbtm_ts_out_mode = 1
1268 // 0: select gated clock
1269 // 1: select free-run clock
1270 // [9] : reg_ckg_atsc_dvbtc_ts_inv = 0
1271 // 0: normal phase to pad
1272 // 1: invert phase to pad
1273 // [8] : reg_ckg_atsc_dvb_div_sel = 1
1274 // 0: select clk_dmplldiv5
1275 // 1: select clk_dmplldiv3
1276 // [4:0]: reg_ckg_dvbtm_ts_divnum = 17
1277 // => TS clock = (864/3)/(2*(17+1)) = 8MHz
1278 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h00, 2'b11, 16'h0511);
1279 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h00, 2'b11, 16'h0511);
1280 _HAL_DMD_RIU_WriteByte(0x103301, 0x05);
1281 _HAL_DMD_RIU_WriteByte(0x103300, 0x11);
1282 // Enable ATSC, DVBTC TS clock
1283 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
1284 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
1285 // Enable ADC clock in clkgen_demod
1286 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
1287 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
1288 // Enable VIF DAC clock in clkgen_demod
1289 _HAL_DMD_RIU_WriteByte(0x111f29, 0x00);
1290 _HAL_DMD_RIU_WriteByte(0x111f28, 0x00);
1291 // Enable ATSC clock
1292 _HAL_DMD_RIU_WriteByte(0x111f03, 0x00);
1293 _HAL_DMD_RIU_WriteByte(0x111f02, 0x00);
1294 _HAL_DMD_RIU_WriteByte(0x111f05, 0x00);
1295 _HAL_DMD_RIU_WriteByte(0x111f04, 0x00);
1296 _HAL_DMD_RIU_WriteByte(0x111f07, 0x00);
1297 _HAL_DMD_RIU_WriteByte(0x111f06, 0x00);
1298 // Enable clk_atsc_adcd_sync = 25.41
1299 // [3:0]: reg_ckg_atsc_adcd_sync
1300 // [0] : disable clock
1301 // [1] : invert clock
1302 // [3:2]: Select clock source
1303 // 00: clk_dmdadc_sync
1304 // 01: clk_atsc50_p
1305 // ^^^^^^^^^^^^
1306 // if(reg_atsc_adc_sel_mplldiv2) => clk_dmplldiv2_div7(49.7 MHz)
1307 // else => clk_dmplldiv17(50.82 MHz)
1308 // 10: clk_atsc25_p
1309 // ^^^^^^^^^^^^
1310 // if(reg_atsc_adc_sel_mplldiv2) => clk_dmplldiv2_div7_div2(24.85 MHz)
1311 // else => clk_dmplldiv17_div2(25.41 MHz)
1312 // 11: 1'b0
1313 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h05, 2'b11, 16'h0008);
1314 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h05, 2'b11, 16'h0008);
1315 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
1316 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x08);
1317 // Enable DVBT inner clock
1318 _HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
1319 _HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
1320 _HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
1321 _HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
1322 // Enable DVBT outer clock
1323 _HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
1324 _HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
1325 // Enable DVBC outer clock
1326 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
1327 _HAL_DMD_RIU_WriteByte(0x111f12, 0x08);
1328 // Enable SRAM clock
1329 _HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
1330 _HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
1331 // Enable ISDBT SRAM share clock and symbol rate clock
1332 _HAL_DMD_RIU_WriteByte(0x111f49, 0x44);
1333 _HAL_DMD_RIU_WriteByte(0x111f48, 0x00);
1334 // select clock
1335 _HAL_DMD_RIU_WriteByte(0x111f23, 0x00);
1336 _HAL_DMD_RIU_WriteByte(0x111f22, 0x00);
1337 // [3:0] : reg_ckg_dtmb_eq2x_inner2x_12x
1338 // [0] : disable clock
1339 // [1] : invert clock
1340 // [3:2]: Select clock source
1341 // 00: dtmb_clk288_buf(256 MHz)
1342 // 01: dtmb_eq_sram_clk36_buf(32 MHz)
1343 // 10: dtmb_eq_sram_clk216_buf(192 MHz)
1344 // 11: 1'b0
1345 // [7:4] : reg_ckg_dtmb_inner1x_dvbc_eq1x => CCI LMS 1x
1346 // ^^^^^^^^^^
1347 // [0] : disable clock
1348 // [1] : invert clock
1349 // [3:2]: Select clock source
1350 // 00: dtmb_clk18_buf(16 MHz) => DTMB
1351 // 01: clk_dmplldiv3_div16(18 MHz) => DVBC,ISDBT(>= (24/2=12))
1352 // 10: clk_dmplldiv10_div8(10.8 MHz)=> DVBT
1353 // 11: clk_cci_lms_1x_atsc_p_buf => ATSC
1354 // ^^^^^^^^^^^^^^^^^^^^^^^^^
1355 // if(reg_atsc_eq_sel_mplldiv2) => clk_dmplldiv2_div2_inv_div8(21.75 MHz)
1356 // else => clk_dmplldiv5_inv_div8(21.6 MHz)
1357 // [11:8] : reg_ckg_dtmb_inner4x_dvbc_eq4x => CCI LMS 4x
1358 // ^^^^^^^^^^
1359 // [0] : disable clock
1360 // [1] : invert clock
1361 // [3:2]: Select clock source
1362 // 00: dtmb_clk72_buf(64 MHz) => DTMB
1363 // 01: clk_dmplldiv3_div4(72 MHz) => DVBC,ISDBT(>= 48)
1364 // 10: clk_dmplldiv10_div2(43.2 MHz)=> DVBT
1365 // 11: clk_cci_lms_4x_atsc_p_buf => ATSC
1366 // ^^^^^^^^^^^^^^^^^^^^^^^^^
1367 // if(reg_atsc_eq_sel_mplldiv2) => clk_dmplldiv2_div2_inv_div2(87 MHz)
1368 // else => clk_dmplldiv5_inv_div2(86.4 MHz)
1369 // [15:12]: reg_ckg_dtmb_sram_dump
1370 // [0] : disable clock
1371 // [1] : invert clock
1372 // [3:2]: Select clock source
1373 // 00: dtmb_clk18_buf(16 MHz)
1374 // 01: dtmb_sram_dump_clk144_buf(128 MHz)
1375 // 10: dtmb_sram_dump_clk216_buf(192 MHz)
1376 // 11: dtmb_sram_dump_dmplldiv5_buf(153.6 MHz)
1377 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h38, 2'b11, 16'h1cc1);
1378 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h38, 2'b11, 16'h1cc1);
1379 _HAL_DMD_RIU_WriteByte(0x111f71, 0x1C);
1380 _HAL_DMD_RIU_WriteByte(0x111f70, 0xC1);
1381 // [4:0] : reg_ckg_dtmb_inner4x_sr1x => symbol rate FFT 1x
1382 // ^^^^^^^^^^^^^^^^^^
1383 // [0] : disable clock
1384 // [1] : invert clock
1385 // [4:2]: Select clock source
1386 // 000: adc_clk_buf
1387 // 001: clk_atsc25_p
1388 // ^^^^^^^^^^^^
1389 // if(reg_atsc_adc_sel_mplldiv2) => clk_dmplldiv2_div7_div2(24.85 MHz)
1390 // else => clk_dmplldiv17_div2(25.41 MHz)
1391 // 010: clk_atsc_eq25_p
1392 // ^^^^^^^^^^^^^^^
1393 // case({reg_eq25_sel_mplldiv3,reg_atsc_eq_sel_mplldiv2})
1394 // 2'b00: clk_dmplldiv5_inv_div8 (21.6 MHz)
1395 // 2'b01: clk_dmplldiv2_div2_inv_div8 (21.75 MHz)
1396 // 2'b10: clk_dmplldiv3_div16 (18 MHz)
1397 // 2'b11: 1'b0
1398 // endcase
1399 // 011: dtmb_clk72_buf(72 MHz)
1400 // 100: dtmb_clk18_buf(18 MHz)
1401 // 101: 1'b0
1402 // 110: 1'b0
1403 // 111: 1'b0
1404 // [12:8] : reg_ckg_dtmb_inner2x_sr0p5x => symbol rate FFT 0.5x
1405 // ^^^^^^^^^^^^^^^^^^^^
1406 // [0] : disable clock
1407 // [1] : invert clock
1408 // [4:2]: Select clock source
1409 // 000: clk_adc_div2_buf
1410 // 001: clk_frontend_d2_p0
1411 // ^^^^^^^^^^^^^^^^^^
1412 // if(reg_atsc_adc_sel_mplldiv2) => clk_dmplldiv2_div7_div4(12.43 MHz)
1413 // else => clk_dmplldiv17_div4(12.705 MHz)
1414 // 010: clk_atsc_eq25_div2_p
1415 // ^^^^^^^^^^^^^^^^^^^^
1416 // case({reg_eq25_sel_mplldiv3,reg_atsc_eq_sel_mplldiv2})
1417 // 2'b00: clk_dmplldiv5_inv_div8_div2 (10.8 MHz)
1418 // 2'b01: clk_dmplldiv2_div2_inv_div8_div2 (10.875 MHz)
1419 // 2'b10: clk_dmplldiv3_div32 (9 MHz)
1420 // 2'b11: 1'b0
1421 // endcase
1422 // 011: dtmb_clk36_buf(36 MHz)
1423 // 100: dtmb_clk9_buf(9 MHz)
1424 // 101: 1'b0
1425 // 110: 1'b0
1426 // 111: 1'b0
1427 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h3b, 2'b11, 16'h0404);
1428 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h3b, 2'b11, 16'h0404);
1429 _HAL_DMD_RIU_WriteByte(0x111f77, 0x04);
1430 _HAL_DMD_RIU_WriteByte(0x111f76, 0x04);
1431
1432 //Enable SRAM power saving
1433 _HAL_DMD_RIU_WriteByte(0x112091, 0x44);
1434 _HAL_DMD_RIU_WriteByte(0x112090, 0x00);
1435
1436 u8Val = _HAL_DMD_RIU_ReadByte(0x101e39);
1437 _HAL_DMD_RIU_WriteByte(0x101e39, u8Val|0x03);
1438 }
1439 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_EDISON)
_HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)1440 static void _HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)
1441 {
1442 MS_U8 u8Val = 0x00;
1443
1444 HAL_INTERN_ATSC_DBINFO(printf("--------------DMD_ATSC_CHIP_EDISON--------------\n"));
1445
1446 u8Val = _HAL_DMD_RIU_ReadByte(0x101e39);
1447 _HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
1448
1449 _HAL_DMD_RIU_WriteByte(0x10331f,0x00);//Different with EDEN!
1450 _HAL_DMD_RIU_WriteByte(0x10331e,0x10);
1451 _HAL_DMD_RIU_WriteByte(0x103301,0x06);//Different with EDEN!
1452 _HAL_DMD_RIU_WriteByte(0x103300,0x0B);//Different with EDEN!
1453 _HAL_DMD_RIU_WriteByte(0x103309,0x00);
1454 _HAL_DMD_RIU_WriteByte(0x103308,0x00);
1455 _HAL_DMD_RIU_WriteByte(0x103315,0x00);
1456 _HAL_DMD_RIU_WriteByte(0x103314,0x00);//Different with EDEN!
1457
1458 _HAL_DMD_RIU_WriteByte(0x111f03,0x00);
1459 _HAL_DMD_RIU_WriteByte(0x111f02,0x00);
1460 _HAL_DMD_RIU_WriteByte(0x111f05,0x00);
1461 _HAL_DMD_RIU_WriteByte(0x111f04,0x00);
1462 _HAL_DMD_RIU_WriteByte(0x111f07,0x00);
1463 _HAL_DMD_RIU_WriteByte(0x111f06,0x00);
1464 _HAL_DMD_RIU_WriteByte(0x111f0b,0x00);
1465 _HAL_DMD_RIU_WriteByte(0x111f0a,0x00);
1466
1467 _HAL_DMD_RIU_WriteByte(0x111f0d,0x00);
1468 _HAL_DMD_RIU_WriteByte(0x111f0c,0x00);
1469 _HAL_DMD_RIU_WriteByte(0x111f0f,0x00);
1470 _HAL_DMD_RIU_WriteByte(0x111f0e,0x00);
1471
1472 _HAL_DMD_RIU_WriteByte(0x111f11,0x00);
1473 _HAL_DMD_RIU_WriteByte(0x111f10,0x00);
1474 _HAL_DMD_RIU_WriteByte(0x111f13,0x00);
1475 _HAL_DMD_RIU_WriteByte(0x111f12,0x08);
1476 _HAL_DMD_RIU_WriteByte(0x111f19,0x00);
1477 _HAL_DMD_RIU_WriteByte(0x111f18,0x00);
1478 _HAL_DMD_RIU_WriteByte(0x111f23,0x00);//Different with EDEN!
1479 _HAL_DMD_RIU_WriteByte(0x111f22,0x00);
1480
1481 _HAL_DMD_RIU_WriteByte(0x111f25,0x00);
1482 _HAL_DMD_RIU_WriteByte(0x111f24,0x00);
1483
1484 _HAL_DMD_RIU_WriteByte(0x111F1E,0x00);
1485 _HAL_DMD_RIU_WriteByte(0x111F09,0x00);
1486
1487 u8Val = _HAL_DMD_RIU_ReadByte(0x000e13);
1488 _HAL_DMD_RIU_WriteByte(0x000e13, u8Val&0xFB);
1489
1490 u8Val = _HAL_DMD_RIU_ReadByte(0x101e39);
1491 _HAL_DMD_RIU_WriteByte(0x101e39, u8Val|0x03);
1492 }
1493 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_EIFFEL)
_HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)1494 static void _HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)
1495 {
1496 MS_U8 u8Val = 0x00;
1497
1498 HAL_INTERN_ATSC_DBINFO(printf("--------------DMD_ATSC_CHIP_EIFFEL--------------\n"));
1499
1500 u8Val = _HAL_DMD_RIU_ReadByte(0x101e39);
1501 _HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
1502
1503 _HAL_DMD_RIU_WriteByte(0x101e39 ,0x00);
1504 _HAL_DMD_RIU_WriteByte(0x10331f ,0x00);
1505 _HAL_DMD_RIU_WriteByte(0x10331e ,0x10);
1506 _HAL_DMD_RIU_WriteByte(0x103301 ,0x05);
1507 _HAL_DMD_RIU_WriteByte(0x103300 ,0x11);
1508 _HAL_DMD_RIU_WriteByte(0x103309 ,0x00);
1509 _HAL_DMD_RIU_WriteByte(0x103308 ,0x00);
1510 _HAL_DMD_RIU_WriteByte(0x103315 ,0x00);
1511 _HAL_DMD_RIU_WriteByte(0x103314 ,0x00);
1512 _HAL_DMD_RIU_WriteByte(0x111f28 ,0x00);
1513 // _HAL_DMD_RIU_WriteByte(0x112028 ,0x03);
1514 _HAL_DMD_RIU_WriteByte(0x111f03 ,0x00);
1515 _HAL_DMD_RIU_WriteByte(0x111f02 ,0x00);
1516 _HAL_DMD_RIU_WriteByte(0x111f05 ,0x00);
1517 _HAL_DMD_RIU_WriteByte(0x111f04 ,0x00);
1518 _HAL_DMD_RIU_WriteByte(0x111f07 ,0x00);
1519 _HAL_DMD_RIU_WriteByte(0x111f06 ,0x00);
1520 _HAL_DMD_RIU_WriteByte(0x111f0b ,0x00);
1521 _HAL_DMD_RIU_WriteByte(0x111f0a ,0x08);
1522 _HAL_DMD_RIU_WriteByte(0x111f0d ,0x00);
1523 _HAL_DMD_RIU_WriteByte(0x111f0c ,0x00);
1524 _HAL_DMD_RIU_WriteByte(0x111f0f ,0x00);
1525 _HAL_DMD_RIU_WriteByte(0x111f0e ,0x00);
1526 _HAL_DMD_RIU_WriteByte(0x111f11 ,0x00);
1527 _HAL_DMD_RIU_WriteByte(0x111f10 ,0x00);
1528 _HAL_DMD_RIU_WriteByte(0x111f13 ,0x00);
1529 _HAL_DMD_RIU_WriteByte(0x111f12 ,0x08);
1530 _HAL_DMD_RIU_WriteByte(0x111f19 ,0x00);
1531 _HAL_DMD_RIU_WriteByte(0x111f18 ,0x00);
1532 _HAL_DMD_RIU_WriteByte(0x111f23 ,0x00);
1533 _HAL_DMD_RIU_WriteByte(0x111f22 ,0x00);
1534
1535 u8Val = _HAL_DMD_RIU_ReadByte(0x000e61);
1536 _HAL_DMD_RIU_WriteByte(0x000e61, u8Val&0xFE);
1537
1538 u8Val = _HAL_DMD_RIU_ReadByte(0x101e39);
1539 _HAL_DMD_RIU_WriteByte(0x101e39, u8Val|0x03);
1540 }
1541 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MIAMI)
_HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)1542 stativ void _HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)
1543 {
1544 MS_U8 u8Val = 0;
1545
1546 HAL_INTERN_ATSC_DBINFO(printf("--------------DMD_ATSC_CHIP_MIAMI--------------\n"));
1547
1548 u8Val = _HAL_DMD_RIU_ReadByte(0x101e39);
1549 _HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
1550
1551 // DMDMCU 108M
1552 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
1553 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
1554 // Set parallel TS clock
1555 _HAL_DMD_RIU_WriteByte(0x103301, 0x05);
1556 _HAL_DMD_RIU_WriteByte(0x103300, 0x11);
1557 // Enable ATSC, DVBTC TS clock
1558 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
1559 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
1560 // Enable ADC clock in clkgen_demod
1561 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
1562 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
1563 // Select MPLLDIV17
1564 _HAL_DMD_RIU_WriteByte(0x111f28, 0x00);
1565 // Enable ATSC clock
1566 _HAL_DMD_RIU_WriteByte(0x111f03, 0x00);
1567 _HAL_DMD_RIU_WriteByte(0x111f02, 0x00);
1568 _HAL_DMD_RIU_WriteByte(0x111f05, 0x00);
1569 _HAL_DMD_RIU_WriteByte(0x111f04, 0x00);
1570 _HAL_DMD_RIU_WriteByte(0x111f07, 0x00);
1571 _HAL_DMD_RIU_WriteByte(0x111f06, 0x00);
1572 // enable clk_atsc_adcd_sync
1573 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
1574 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x08);
1575 // Enable DVBT inner clock
1576 _HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
1577 _HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
1578 _HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
1579 _HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
1580 // Enable DVBT outer clock
1581 _HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
1582 _HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
1583 // Enable DVBC outer clock
1584 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
1585 _HAL_DMD_RIU_WriteByte(0x111f12, 0x08);
1586 // Enable SRAM clock
1587 _HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
1588 _HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
1589 // enable clk_dvbtc_sram4_isdbt_inner4x & clk_adc1x_eq1x clock
1590 _HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
1591 _HAL_DMD_RIU_WriteByte(0x111f48, 0x00);
1592 // select clock
1593 _HAL_DMD_RIU_WriteByte(0x111f23, 0x00);
1594 _HAL_DMD_RIU_WriteByte(0x111f22, 0x00);
1595 // enable CCI LMS clock
1596 _HAL_DMD_RIU_WriteByte(0x111f51, 0x00);
1597 _HAL_DMD_RIU_WriteByte(0x111f50, 0xCC);
1598
1599 u8Val = _HAL_DMD_RIU_ReadByte(0x101e39);
1600 _HAL_DMD_RIU_WriteByte(0x101e39, u8Val|0x03);
1601 }
1602 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MUJI)
_HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)1603 static void _HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)
1604 {
1605 HAL_INTERN_ATSC_DBINFO(printf("--------------DMD_ATSC_CHIP_MUJI--------------\n"));
1606
1607 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
1608
1609 // DMDMCU 108M
1610 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
1611 // Set parallel TS clock
1612 // [11] : reg_ckg_demod_test_in_en = 0
1613 // 0: select internal ADC CLK
1614 // 1: select external test-in clock
1615 // [10] : reg_ckg_dvbtm_ts_out_mode = 1
1616 // 0: select gated clock
1617 // 1: select free-run clock
1618 // [9] : reg_ckg_atsc_dvbtc_ts_inv = 0
1619 // 0: normal phase to pad
1620 // 1: invert phase to pad
1621 // [8] : reg_ckg_atsc_dvb_div_sel = 1
1622 // 0: select clk_dmplldiv5
1623 // 1: select clk_dmplldiv3
1624 // [4:0]: reg_ckg_dvbtm_ts_divnum = 17
1625 // => TS clock = (864/3)/(2*(17+1)) = 8MHz
1626 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h00, 2'b11, 16'h0511);
1627 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h00, 2'b11, 16'h0511);
1628 _HAL_DMD_RIU_WriteByte(0x103301, 0x05);
1629 _HAL_DMD_RIU_WriteByte(0x103300, 0x11);
1630 // Enable ATSC, DVBTC TS clock
1631 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
1632 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
1633 // Enable ADC clock in clkgen_demod
1634 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
1635 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
1636 // Reset TS divider
1637 _HAL_DMD_RIU_WriteByte(0x103302, 0x01);
1638 _HAL_DMD_RIU_WriteByte(0x103302, 0x00);
1639 // Enable VIF DAC clock in clkgen_demod
1640 _HAL_DMD_RIU_WriteByte(0x111f29, 0x00);
1641 _HAL_DMD_RIU_WriteByte(0x111f28, 0x00);
1642 // Enable ATSC clock
1643 _HAL_DMD_RIU_WriteByte(0x111f03, 0x00);
1644 _HAL_DMD_RIU_WriteByte(0x111f02, 0x00);
1645 _HAL_DMD_RIU_WriteByte(0x111f05, 0x00);
1646 _HAL_DMD_RIU_WriteByte(0x111f04, 0x00);
1647 _HAL_DMD_RIU_WriteByte(0x111f07, 0x00);
1648 _HAL_DMD_RIU_WriteByte(0x111f06, 0x00);
1649 // Enable clk_atsc_adcd_sync = 25.41
1650 // [3:0]: reg_ckg_atsc_adcd_sync
1651 // [0] : disable clock
1652 // [1] : invert clock
1653 // [3:2]: Select clock source
1654 // 00: clk_dmdadc_sync
1655 // 01: clk_atsc50_p
1656 // ^^^^^^^^^^^^
1657 // if(reg_atsc_adc_sel_mplldiv2) => clk_dmplldiv2_div7(49.7 MHz)
1658 // else => clk_dmplldiv17(50.82 MHz)
1659 // 10: clk_atsc25_p
1660 // ^^^^^^^^^^^^
1661 // if(reg_atsc_adc_sel_mplldiv2) => clk_dmplldiv2_div7_div2(24.85 MHz)
1662 // else => clk_dmplldiv17_div2(25.41 MHz)
1663 // 11: 1'b0
1664 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h05, 2'b11, 16'h0008);
1665 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h05, 2'b11, 16'h0008);
1666 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
1667 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x08);
1668 // Enable DVBT inner clock
1669 _HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
1670 _HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
1671 _HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
1672 _HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
1673 // Enable DVBT outer clock
1674 _HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
1675 _HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
1676 // Enable DVBC outer clock
1677 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
1678 _HAL_DMD_RIU_WriteByte(0x111f12, 0x08);
1679 // Enable SRAM clock
1680 _HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
1681 _HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
1682 // Enable ISDBT SRAM share clock and symbol rate clock
1683 _HAL_DMD_RIU_WriteByte(0x111f49, 0x44);
1684 _HAL_DMD_RIU_WriteByte(0x111f48, 0x00);
1685 // select clock
1686 _HAL_DMD_RIU_WriteByte(0x111f23, 0x00);
1687 _HAL_DMD_RIU_WriteByte(0x111f22, 0x00);
1688 // [3:0] : reg_ckg_dtmb_eq2x_inner2x_12x
1689 // [0] : disable clock
1690 // [1] : invert clock
1691 // [3:2]: Select clock source
1692 // 00: dtmb_clk288_buf(256 MHz)
1693 // 01: dtmb_eq_sram_clk36_buf(32 MHz)
1694 // 10: dtmb_eq_sram_clk216_buf(192 MHz)
1695 // 11: 1'b0
1696 // [7:4] : reg_ckg_dtmb_inner1x_dvbc_eq1x => CCI LMS 1x
1697 // ^^^^^^^^^^
1698 // [0] : disable clock
1699 // [1] : invert clock
1700 // [3:2]: Select clock source
1701 // 00: dtmb_clk18_buf(16 MHz) => DTMB
1702 // 01: clk_dmplldiv3_div16(18 MHz) => DVBC,ISDBT(>= (24/2=12))
1703 // 10: clk_dmplldiv10_div8(10.8 MHz)=> DVBT
1704 // 11: clk_cci_lms_1x_atsc_p_buf => ATSC
1705 // ^^^^^^^^^^^^^^^^^^^^^^^^^
1706 // if(reg_atsc_eq_sel_mplldiv2) => clk_dmplldiv2_div2_inv_div8(21.75 MHz)
1707 // else => clk_dmplldiv5_inv_div8(21.6 MHz)
1708 // [11:8] : reg_ckg_dtmb_inner4x_dvbc_eq4x => CCI LMS 4x
1709 // ^^^^^^^^^^
1710 // [0] : disable clock
1711 // [1] : invert clock
1712 // [3:2]: Select clock source
1713 // 00: dtmb_clk72_buf(64 MHz) => DTMB
1714 // 01: clk_dmplldiv3_div4(72 MHz) => DVBC,ISDBT(>= 48)
1715 // 10: clk_dmplldiv10_div2(43.2 MHz)=> DVBT
1716 // 11: clk_cci_lms_4x_atsc_p_buf => ATSC
1717 // ^^^^^^^^^^^^^^^^^^^^^^^^^
1718 // if(reg_atsc_eq_sel_mplldiv2) => clk_dmplldiv2_div2_inv_div2(87 MHz)
1719 // else => clk_dmplldiv5_inv_div2(86.4 MHz)
1720 // [15:12]: reg_ckg_dtmb_sram_dump
1721 // [0] : disable clock
1722 // [1] : invert clock
1723 // [3:2]: Select clock source
1724 // 00: dtmb_clk18_buf(16 MHz)
1725 // 01: dtmb_sram_dump_clk144_buf(128 MHz)
1726 // 10: dtmb_sram_dump_clk216_buf(192 MHz)
1727 // 11: dtmb_sram_dump_dmplldiv5_buf(153.6 MHz)
1728 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h38, 2'b11, 16'h1cc1);
1729 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h38, 2'b11, 16'h1cc1);
1730 _HAL_DMD_RIU_WriteByte(0x111f71, 0x1C);
1731 _HAL_DMD_RIU_WriteByte(0x111f70, 0xC1);
1732 // [4:0] : reg_ckg_dtmb_inner4x_sr1x => symbol rate FFT 1x
1733 // ^^^^^^^^^^^^^^^^^^
1734 // [0] : disable clock
1735 // [1] : invert clock
1736 // [4:2]: Select clock source
1737 // 000: adc_clk_buf
1738 // 001: clk_atsc25_p
1739 // ^^^^^^^^^^^^
1740 // if(reg_atsc_adc_sel_mplldiv2) => clk_dmplldiv2_div7_div2(24.85 MHz)
1741 // else => clk_dmplldiv17_div2(25.41 MHz)
1742 // 010: clk_atsc_eq25_p
1743 // ^^^^^^^^^^^^^^^
1744 // case({reg_eq25_sel_mplldiv3,reg_atsc_eq_sel_mplldiv2})
1745 // 2'b00: clk_dmplldiv5_inv_div8 (21.6 MHz)
1746 // 2'b01: clk_dmplldiv2_div2_inv_div8 (21.75 MHz)
1747 // 2'b10: clk_dmplldiv3_div16 (18 MHz)
1748 // 2'b11: 1'b0
1749 // endcase
1750 // 011: dtmb_clk72_buf(72 MHz)
1751 // 100: dtmb_clk18_buf(18 MHz)
1752 // 101: 1'b0
1753 // 110: 1'b0
1754 // 111: 1'b0
1755 // [12:8] : reg_ckg_dtmb_inner2x_sr0p5x => symbol rate FFT 0.5x
1756 // ^^^^^^^^^^^^^^^^^^^^
1757 // [0] : disable clock
1758 // [1] : invert clock
1759 // [4:2]: Select clock source
1760 // 000: clk_adc_div2_buf
1761 // 001: clk_frontend_d2_p0
1762 // ^^^^^^^^^^^^^^^^^^
1763 // if(reg_atsc_adc_sel_mplldiv2) => clk_dmplldiv2_div7_div4(12.43 MHz)
1764 // else => clk_dmplldiv17_div4(12.705 MHz)
1765 // 010: clk_atsc_eq25_div2_p
1766 // ^^^^^^^^^^^^^^^^^^^^
1767 // case({reg_eq25_sel_mplldiv3,reg_atsc_eq_sel_mplldiv2})
1768 // 2'b00: clk_dmplldiv5_inv_div8_div2 (10.8 MHz)
1769 // 2'b01: clk_dmplldiv2_div2_inv_div8_div2 (10.875 MHz)
1770 // 2'b10: clk_dmplldiv3_div32 (9 MHz)
1771 // 2'b11: 1'b0
1772 // endcase
1773 // 011: dtmb_clk36_buf(36 MHz)
1774 // 100: dtmb_clk9_buf(9 MHz)
1775 // 101: 1'b0
1776 // 110: 1'b0
1777 // 111: 1'b0
1778 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h3b, 2'b11, 16'h0404);
1779 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h3b, 2'b11, 16'h0404);
1780 _HAL_DMD_RIU_WriteByte(0x111f77, 0x04);
1781 _HAL_DMD_RIU_WriteByte(0x111f76, 0x04);
1782
1783 // Muji
1784 // [1:0] : reg_ckg_isdbt_outer1x_dvbt_outer1x
1785 // [0] : disable clock
1786 // [1] : invert clock
1787 // [3:2]: Select clock source
1788 // vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
1789 // sel[0]= (reg_demod_isdbt_on & reg_ckg_isdbt_outer1x[2])
1790 // sel[1]= (~reg_demod_isdbt_on)
1791 // ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
1792 // 00: isdbt_clk6_lat(6 MHz)
1793 // 01: isdbt_clk8_lat(8 MHz)
1794 // 10: clk_dmplldiv10_div2(43.2 MHz)
1795 // 11: 1'b0
1796 // [6:4] : reg_ckg_miu_dvbtc_outer2x
1797 // [0] : disable clock
1798 // [1] : invert clock
1799 // [2] : Select clock source
1800 // 0: clk_miu_p
1801 // 1: clk_dmplldiv10(86.4 MHz)
1802 // [12:8] : reg_ckg_dvbtc_rs
1803 // [0] : disable clock
1804 // [1] : invert clock
1805 // [4:2]: Select clock source
1806 // 000: clk_dmplldiv10(86.4 MHz)
1807 // 001: clk_dmplldiv10_div2(43.2 MHz)
1808 // 010: clk_atsc50_p
1809 // ^^^^^^^^^^^^
1810 // if(reg_atsc_adc_sel_mplldiv2) => clk_dmplldiv2_div7(49.7 MHz)
1811 // else => clk_dmplldiv17(50.82 MHz)
1812 // 011: clk_dvbtc_rs_216_buf(216 MHz)
1813 // 100: clk_dvbtc_rs_172_buf(172 MHz)
1814 // 101: clk_dvbtc_rs_144_buf(144 MHz)
1815 // 110: 1'b0
1816 // 111: 1'b0
1817 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h27, 2'b10, 16'h0800);
1818 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h27, 2'b10, 16'h0800);
1819 _HAL_DMD_RIU_WriteByte(0x111f4f, 0x08);
1820
1821 //Enable SRAM power saving
1822 _HAL_DMD_RIU_WriteByte(0x112091, 0x44);
1823 _HAL_DMD_RIU_WriteByte(0x112090, 0x00);
1824
1825 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
1826 }
1827 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MUNICH)
_HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)1828 static void _HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)
1829 {
1830 MS_U8 u8Val = 0;
1831
1832 HAL_INTERN_ATSC_DBINFO(printf("--------------DMD_ATSC_CHIP_MUNICH--------------\n"));
1833
1834 u8Val = _HAL_DMD_RIU_ReadByte(0x101e39);
1835 _HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
1836
1837 // DMDMCU 108M
1838 _HAL_DMD_RIU_WriteByte(0x10331f, 0x00);
1839 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
1840 // Set parallel TS clock
1841 _HAL_DMD_RIU_WriteByte(0x103301, 0x05);
1842 _HAL_DMD_RIU_WriteByte(0x103300, 0x11);
1843 // Enable ATSC, DVBTC TS clock
1844 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
1845 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
1846 // Enable ADC clock in clkgen_demod
1847 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
1848 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
1849 // Select MPLLDIV17
1850 _HAL_DMD_RIU_WriteByte(0x111f28, 0x00);
1851 // Enable ATSC clock
1852 _HAL_DMD_RIU_WriteByte(0x111f03, 0x00);
1853 _HAL_DMD_RIU_WriteByte(0x111f02, 0x00);
1854 _HAL_DMD_RIU_WriteByte(0x111f05, 0x00);
1855 _HAL_DMD_RIU_WriteByte(0x111f04, 0x00);
1856 _HAL_DMD_RIU_WriteByte(0x111f07, 0x00);
1857 _HAL_DMD_RIU_WriteByte(0x111f06, 0x00);
1858 // enable clk_atsc_adcd_sync
1859 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
1860 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x08);
1861 // Enable DVBT inner clock
1862 _HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
1863 _HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
1864 _HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
1865 _HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
1866 // Enable DVBT outer clock
1867 _HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
1868 _HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
1869 // Enable DVBC outer clock
1870 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
1871 _HAL_DMD_RIU_WriteByte(0x111f12, 0x08);
1872 // Enable SRAM clock
1873 _HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
1874 _HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
1875 // enable clk_dvbtc_sram4_isdbt_inner4x & clk_adc1x_eq1x clock
1876 _HAL_DMD_RIU_WriteByte(0x111f49, 0x00);
1877 _HAL_DMD_RIU_WriteByte(0x111f48, 0x00);
1878 // select clock
1879 _HAL_DMD_RIU_WriteByte(0x111f23, 0x00);
1880 _HAL_DMD_RIU_WriteByte(0x111f22, 0x00);
1881 // enable CCI LMS clock
1882 _HAL_DMD_RIU_WriteByte(0x111f51, 0x00);
1883 _HAL_DMD_RIU_WriteByte(0x111f50, 0xCC);
1884
1885 u8Val = _HAL_DMD_RIU_ReadByte(0x101e39);
1886 _HAL_DMD_RIU_WriteByte(0x101e39, u8Val|0x03);
1887 }
1888 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_KIRIN)
_HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)1889 void _HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)
1890 {
1891 MS_U8 u8Val=0x00;
1892
1893 HAL_INTERN_ATSC_DBINFO(printf("--------------DMD_ATSC_CHIP_KIRIN--------------\n"));
1894
1895 u8Val = _HAL_DMD_RIU_ReadByte(0x101e39);
1896 _HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
1897
1898 _HAL_DMD_RIU_WriteByte(0x10331f,0x00);
1899 _HAL_DMD_RIU_WriteByte(0x10331e,0x10);
1900 _HAL_DMD_RIU_WriteByte(0x103301,0x07);
1901 _HAL_DMD_RIU_WriteByte(0x103300,0x11);
1902 _HAL_DMD_RIU_WriteByte(0x103309,0x00);
1903 _HAL_DMD_RIU_WriteByte(0x103315,0x00);
1904 _HAL_DMD_RIU_WriteByte(0x103314,0x00);
1905
1906 _HAL_DMD_RIU_WriteByte(0x111f0b,0x00);
1907 _HAL_DMD_RIU_WriteByte(0x111f0a,0x00);
1908 _HAL_DMD_RIU_WriteByte(0x111f0c,0x00);
1909 _HAL_DMD_RIU_WriteByte(0x111f11,0x00);
1910 _HAL_DMD_RIU_WriteByte(0x111f13,0x00);
1911 _HAL_DMD_RIU_WriteByte(0x111f12,0x00);
1912 _HAL_DMD_RIU_WriteByte(0x111f15,0x00);
1913 _HAL_DMD_RIU_WriteByte(0x111f17,0x00);
1914 _HAL_DMD_RIU_WriteByte(0x111f16,0x00);
1915 _HAL_DMD_RIU_WriteByte(0x111f22,0x00);
1916 _HAL_DMD_RIU_WriteByte(0x111f2b,0x00);
1917 _HAL_DMD_RIU_WriteByte(0x111f2a,0x10);
1918 _HAL_DMD_RIU_WriteByte(0x101ea1,0x00);
1919
1920 _HAL_DMD_RIU_WriteByte(0x101e04,0x02);
1921 _HAL_DMD_RIU_WriteByte(0x101e76,0x03);
1922
1923 u8Val = _HAL_DMD_RIU_ReadByte(0x101e39);
1924 _HAL_DMD_RIU_WriteByte(0x101e39,(u8Val| 0x03));
1925 }
1926 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MAYA)
_HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)1927 void _HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)
1928 {
1929 MS_U8 u8Val=0x00;
1930
1931 HAL_INTERN_ATSC_DBINFO(printf("--------------DMD_ATSC_CHIP_MAYA--------------\n"));
1932
1933 u8Val = _HAL_DMD_RIU_ReadByte(0x101e39);
1934 _HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
1935
1936 // DMDMCU 108M
1937 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
1938 // Set parallel TS clock
1939 _HAL_DMD_RIU_WriteByte(0x103301, 0x05);
1940 _HAL_DMD_RIU_WriteByte(0x103300, 0x11);
1941 // Enable ATSC, DVBTC TS clock
1942 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
1943 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
1944 // Enable ADC clock in clkgen_demod
1945 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
1946 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
1947 // Reset TS divider
1948 _HAL_DMD_RIU_WriteByte(0x103302, 0x01);
1949 _HAL_DMD_RIU_WriteByte(0x103302, 0x00);
1950 // ADC select MPLLDIV17 & EQ select MPLLDIV5
1951 _HAL_DMD_RIU_WriteByte(0x111f43, 0x00);
1952 _HAL_DMD_RIU_WriteByte(0x111f42, 0x00);
1953 // Enable ATSC clock
1954 _HAL_DMD_RIU_WriteByte(0x111f03, 0x00);
1955 _HAL_DMD_RIU_WriteByte(0x111f02, 0x00);
1956 // configure reg_ckg_atsc50, reg_ckg_atsc25, reg_ckg_atsc_eq25 and reg_ckg_atsc_ce25
1957 _HAL_DMD_RIU_WriteByte(0x111f04, 0x00);
1958 _HAL_DMD_RIU_WriteByte(0x111f07, 0x00);
1959 _HAL_DMD_RIU_WriteByte(0x111f06, 0x00);
1960 // enable clk_atsc_adcd_sync
1961 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
1962 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x08);
1963 // Enable DVBC outer clock
1964 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
1965 // Enable SRAM clock
1966 _HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
1967 _HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
1968 // select clock
1969 _HAL_DMD_RIU_WriteByte(0x111f23, 0x00);
1970 _HAL_DMD_RIU_WriteByte(0x111f22, 0x00);
1971 // enable CCI LMS clock
1972 _HAL_DMD_RIU_WriteByte(0x111f71, 0x00);
1973 _HAL_DMD_RIU_WriteByte(0x111f70, 0x00);
1974 // set symbol rate
1975 _HAL_DMD_RIU_WriteByte(0x111f77, 0x04);
1976 _HAL_DMD_RIU_WriteByte(0x111f76, 0x04);
1977 // reg_ckg_adc1x_eq1x
1978 _HAL_DMD_RIU_WriteByte(0x111f49, 0x04);
1979
1980 u8Val = _HAL_DMD_RIU_ReadByte(0x101e39);
1981 _HAL_DMD_RIU_WriteByte(0x101e39,(u8Val| 0x03));
1982 }
1983 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MANHATTAN)
_HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)1984 static void _HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)
1985 {
1986 MS_U8 u8Val = 0;
1987
1988 HAL_INTERN_ATSC_DBINFO(printf("--------------DMD_ATSC_CHIP_MANHATTAN--------------\n"));
1989
1990 u8Val = _HAL_DMD_RIU_ReadByte(0x101e39);
1991 _HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
1992
1993 // DMDMCU 108M
1994 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
1995 // Set parallel TS clock
1996 // [11] : reg_ckg_demod_test_in_en = 0
1997 // 0: select internal ADC CLK
1998 // 1: select external test-in clock
1999 // [10] : reg_ckg_dvbtm_ts_out_mode = 1
2000 // 0: select gated clock
2001 // 1: select free-run clock
2002 // [9] : reg_ckg_atsc_dvbtc_ts_inv = 0
2003 // 0: normal phase to pad
2004 // 1: invert phase to pad
2005 // [8] : reg_ckg_atsc_dvb_div_sel = 1
2006 // 0: select clk_dmplldiv5
2007 // 1: select clk_dmplldiv3
2008 // [4:0]: reg_ckg_dvbtm_ts_divnum = 17
2009 // => TS clock = (864/3)/(2*(17+1)) = 8MHz
2010 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h00, 2'b11, 16'h0511);
2011 // `RIU_W((`RIUBASE_CLKGEN1>>1)+7'h00, 2'b11, 16'h0511);
2012 _HAL_DMD_RIU_WriteByte(0x103301, 0x05);
2013 _HAL_DMD_RIU_WriteByte(0x103300, 0x11);
2014 // Enable ATSC, DVBTC TS clock
2015 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
2016 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
2017 // Enable ADC clock in clkgen_demod
2018 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
2019 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
2020 // Reset TS divider
2021 _HAL_DMD_RIU_WriteByte(0x103302, 0x01);
2022 _HAL_DMD_RIU_WriteByte(0x103302, 0x00);
2023 // Enable VIF DAC clock in clkgen_demod
2024 _HAL_DMD_RIU_WriteByte(0x111f29, 0x00);
2025 _HAL_DMD_RIU_WriteByte(0x111f28, 0x00);
2026 // Enable ATSC clock
2027 _HAL_DMD_RIU_WriteByte(0x111f03, 0x00);
2028 _HAL_DMD_RIU_WriteByte(0x111f02, 0x00);
2029 _HAL_DMD_RIU_WriteByte(0x111f05, 0x00);
2030 _HAL_DMD_RIU_WriteByte(0x111f04, 0x00);
2031 _HAL_DMD_RIU_WriteByte(0x111f07, 0x00);
2032 _HAL_DMD_RIU_WriteByte(0x111f06, 0x00);
2033 // Enable clk_atsc_adcd_sync = 25.41
2034 // [3:0]: reg_ckg_atsc_adcd_sync
2035 // [0] : disable clock
2036 // [1] : invert clock
2037 // [3:2]: Select clock source
2038 // 00: clk_dmdadc_sync
2039 // 01: clk_atsc50_p
2040 // ^^^^^^^^^^^^
2041 // if(reg_atsc_adc_sel_mplldiv2) => clk_dmplldiv2_div7(49.7 MHz)
2042 // else => clk_dmplldiv17(50.82 MHz)
2043 // 10: clk_atsc25_p
2044 // ^^^^^^^^^^^^
2045 // if(reg_atsc_adc_sel_mplldiv2) => clk_dmplldiv2_div7_div2(24.85 MHz)
2046 // else => clk_dmplldiv17_div2(25.41 MHz)
2047 // 11: 1'b0
2048 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h05, 2'b11, 16'h0008);
2049 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h05, 2'b11, 16'h0008);
2050 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
2051 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x08);
2052 // Enable DVBT inner clock
2053 _HAL_DMD_RIU_WriteByte(0x111f0d, 0x00);
2054 _HAL_DMD_RIU_WriteByte(0x111f0c, 0x00);
2055 _HAL_DMD_RIU_WriteByte(0x111f0f, 0x00);
2056 _HAL_DMD_RIU_WriteByte(0x111f0e, 0x00);
2057 // Enable DVBT outer clock
2058 _HAL_DMD_RIU_WriteByte(0x111f11, 0x00);
2059 _HAL_DMD_RIU_WriteByte(0x111f10, 0x00);
2060 // Enable DVBC outer clock
2061 _HAL_DMD_RIU_WriteByte(0x111f13, 0x00);
2062 _HAL_DMD_RIU_WriteByte(0x111f12, 0x08);
2063 // Enable SRAM clock
2064 _HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
2065 _HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
2066 // Enable ISDBT SRAM share clock and symbol rate clock
2067 _HAL_DMD_RIU_WriteByte(0x111f49, 0x44);
2068 _HAL_DMD_RIU_WriteByte(0x111f48, 0x00);
2069 // select clock
2070 _HAL_DMD_RIU_WriteByte(0x111f23, 0x00);
2071 _HAL_DMD_RIU_WriteByte(0x111f22, 0x00);
2072 // [3:0] : reg_ckg_dtmb_eq2x_inner2x_12x
2073 // [0] : disable clock
2074 // [1] : invert clock
2075 // [3:2]: Select clock source
2076 // 00: dtmb_clk288_buf(256 MHz)
2077 // 01: dtmb_eq_sram_clk36_buf(32 MHz)
2078 // 10: dtmb_eq_sram_clk216_buf(192 MHz)
2079 // 11: 1'b0
2080 // [7:4] : reg_ckg_dtmb_inner1x_dvbc_eq1x => CCI LMS 1x
2081 // ^^^^^^^^^^
2082 // [0] : disable clock
2083 // [1] : invert clock
2084 // [3:2]: Select clock source
2085 // 00: dtmb_clk18_buf(16 MHz) => DTMB
2086 // 01: clk_dmplldiv3_div16(18 MHz) => DVBC,ISDBT(>= (24/2=12))
2087 // 10: clk_dmplldiv10_div8(10.8 MHz)=> DVBT
2088 // 11: clk_cci_lms_1x_atsc_p_buf => ATSC
2089 // ^^^^^^^^^^^^^^^^^^^^^^^^^
2090 // if(reg_atsc_eq_sel_mplldiv2) => clk_dmplldiv2_div2_inv_div8(21.75 MHz)
2091 // else => clk_dmplldiv5_inv_div8(21.6 MHz)
2092 // [11:8] : reg_ckg_dtmb_inner4x_dvbc_eq4x => CCI LMS 4x
2093 // ^^^^^^^^^^
2094 // [0] : disable clock
2095 // [1] : invert clock
2096 // [3:2]: Select clock source
2097 // 00: dtmb_clk72_buf(64 MHz) => DTMB
2098 // 01: clk_dmplldiv3_div4(72 MHz) => DVBC,ISDBT(>= 48)
2099 // 10: clk_dmplldiv10_div2(43.2 MHz)=> DVBT
2100 // 11: clk_cci_lms_4x_atsc_p_buf => ATSC
2101 // ^^^^^^^^^^^^^^^^^^^^^^^^^
2102 // if(reg_atsc_eq_sel_mplldiv2) => clk_dmplldiv2_div2_inv_div2(87 MHz)
2103 // else => clk_dmplldiv5_inv_div2(86.4 MHz)
2104 // [15:12]: reg_ckg_dtmb_sram_dump
2105 // [0] : disable clock
2106 // [1] : invert clock
2107 // [3:2]: Select clock source
2108 // 00: dtmb_clk18_buf(16 MHz)
2109 // 01: dtmb_sram_dump_clk144_buf(128 MHz)
2110 // 10: dtmb_sram_dump_clk216_buf(192 MHz)
2111 // 11: dtmb_sram_dump_dmplldiv5_buf(153.6 MHz)
2112 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h38, 2'b11, 16'h1cc1);
2113 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h38, 2'b11, 16'h1cc1);
2114 _HAL_DMD_RIU_WriteByte(0x111f71, 0x1C);
2115 _HAL_DMD_RIU_WriteByte(0x111f70, 0xC1);
2116 // [4:0] : reg_ckg_dtmb_inner4x_sr1x => symbol rate FFT 1x
2117 // ^^^^^^^^^^^^^^^^^^
2118 // [0] : disable clock
2119 // [1] : invert clock
2120 // [4:2]: Select clock source
2121 // 000: adc_clk_buf
2122 // 001: clk_atsc25_p
2123 // ^^^^^^^^^^^^
2124 // if(reg_atsc_adc_sel_mplldiv2) => clk_dmplldiv2_div7_div2(24.85 MHz)
2125 // else => clk_dmplldiv17_div2(25.41 MHz)
2126 // 010: clk_atsc_eq25_p
2127 // ^^^^^^^^^^^^^^^
2128 // case({reg_eq25_sel_mplldiv3,reg_atsc_eq_sel_mplldiv2})
2129 // 2'b00: clk_dmplldiv5_inv_div8 (21.6 MHz)
2130 // 2'b01: clk_dmplldiv2_div2_inv_div8 (21.75 MHz)
2131 // 2'b10: clk_dmplldiv3_div16 (18 MHz)
2132 // 2'b11: 1'b0
2133 // endcase
2134 // 011: dtmb_clk72_buf(72 MHz)
2135 // 100: dtmb_clk18_buf(18 MHz)
2136 // 101: 1'b0
2137 // 110: 1'b0
2138 // 111: 1'b0
2139 // [12:8] : reg_ckg_dtmb_inner2x_sr0p5x => symbol rate FFT 0.5x
2140 // ^^^^^^^^^^^^^^^^^^^^
2141 // [0] : disable clock
2142 // [1] : invert clock
2143 // [4:2]: Select clock source
2144 // 000: clk_adc_div2_buf
2145 // 001: clk_frontend_d2_p0
2146 // ^^^^^^^^^^^^^^^^^^
2147 // if(reg_atsc_adc_sel_mplldiv2) => clk_dmplldiv2_div7_div4(12.43 MHz)
2148 // else => clk_dmplldiv17_div4(12.705 MHz)
2149 // 010: clk_atsc_eq25_div2_p
2150 // ^^^^^^^^^^^^^^^^^^^^
2151 // case({reg_eq25_sel_mplldiv3,reg_atsc_eq_sel_mplldiv2})
2152 // 2'b00: clk_dmplldiv5_inv_div8_div2 (10.8 MHz)
2153 // 2'b01: clk_dmplldiv2_div2_inv_div8_div2 (10.875 MHz)
2154 // 2'b10: clk_dmplldiv3_div32 (9 MHz)
2155 // 2'b11: 1'b0
2156 // endcase
2157 // 011: dtmb_clk36_buf(36 MHz)
2158 // 100: dtmb_clk9_buf(9 MHz)
2159 // 101: 1'b0
2160 // 110: 1'b0
2161 // 111: 1'b0
2162 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h3b, 2'b11, 16'h0404);
2163 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h3b, 2'b11, 16'h0404);
2164 _HAL_DMD_RIU_WriteByte(0x111f77, 0x04);
2165 _HAL_DMD_RIU_WriteByte(0x111f76, 0x04);
2166
2167 // Muji
2168 // [1:0] : reg_ckg_isdbt_outer1x_dvbt_outer1x
2169 // [0] : disable clock
2170 // [1] : invert clock
2171 // [3:2]: Select clock source
2172 // vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
2173 // sel[0]= (reg_demod_isdbt_on & reg_ckg_isdbt_outer1x[2])
2174 // sel[1]= (~reg_demod_isdbt_on)
2175 // ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
2176 // 00: isdbt_clk6_lat(6 MHz)
2177 // 01: isdbt_clk8_lat(8 MHz)
2178 // 10: clk_dmplldiv10_div2(43.2 MHz)
2179 // 11: 1'b0
2180 // [6:4] : reg_ckg_miu_dvbtc_outer2x
2181 // [0] : disable clock
2182 // [1] : invert clock
2183 // [2] : Select clock source
2184 // 0: clk_miu_p
2185 // 1: clk_dmplldiv10(86.4 MHz)
2186 // [12:8] : reg_ckg_dvbtc_rs
2187 // [0] : disable clock
2188 // [1] : invert clock
2189 // [4:2]: Select clock source
2190 // 000: clk_dmplldiv10(86.4 MHz)
2191 // 001: clk_dmplldiv10_div2(43.2 MHz)
2192 // 010: clk_atsc50_p
2193 // ^^^^^^^^^^^^
2194 // if(reg_atsc_adc_sel_mplldiv2) => clk_dmplldiv2_div7(49.7 MHz)
2195 // else => clk_dmplldiv17(50.82 MHz)
2196 // 011: clk_dvbtc_rs_216_buf(216 MHz)
2197 // 100: clk_dvbtc_rs_172_buf(172 MHz)
2198 // 101: clk_dvbtc_rs_144_buf(144 MHz)
2199 // 110: 1'b0
2200 // 111: 1'b0
2201 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h27, 2'b10, 16'h0800);
2202 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h27, 2'b10, 16'h0800);
2203 _HAL_DMD_RIU_WriteByte(0x111f4f, 0x08);
2204
2205 // ================================================================
2206 // ISDBT SRAM pool clock enable
2207 // ================================================================
2208 // [3:0] : reg_ckg_share_dtmb_inner12x_isdbt_inner2x
2209 // [0] : disable clock
2210 // [1] : invert clock
2211 // [3:2] : 0 : clk_dmplldiv10_div2 \_________________> clk_isdbt_inner2x_dvbt_inner2x, *sel[0] = (reg_demod_isdbt_on) | TEST_CLK_EN
2212 // 1 : clk_isdbt_inner2x_p /
2213 // 2 : clk_dtmb_inner12x_4x_dvbtc_rs_mux --------> clk_dtmb_inner12x_4x_dvbtc_rs
2214 // 3 : 1'b0
2215 // [7:4] : reg_ckg_share_dtmb_inner8x_rs_isdbt_inner2x
2216 // [0] : disable clock
2217 // [1] : invert clock
2218 // [3:2] : 0 : clk_dmplldiv10_div2 \_________________> clk_isdbt_inner2x_dvbt_inner2x, *sel[0] = (reg_demod_isdbt_on) | TEST_CLK_EN
2219 // : 1 : clk_isdbt_inner2x_p /
2220 // : 2 : dtmb_clk144_buf \_________________> clk_dtmb_inner8x_dvbtc_rs, *sel[0] = reg_ckg_dtmb_inner8x_dvbtc_rs[2] | TEST_CLK_EN
2221 // : 3 : clk_dvbtc_rs_mux /
2222 // [11:8] : reg_ckg_share_dtmb_inner8x_isdbt_inner2x
2223 // [0] : disable clock
2224 // [1] : invert clock
2225 // [3:2] : 0 : clk_dmplldiv10_div2 \_________________> clk_isdbt_inner2x_dvbt_inner2x, *sel[0] = (reg_demod_isdbt_on) | TEST_CLK_EN
2226 // : 1 : clk_isdbt_inner2x_p /
2227 // : 2 : dtmb_clk144_buf ------------------> clk_dtmb_inner8x
2228 // : 3 : 1'b0
2229 // [15:12] : reg_ckg_share_dtmb_outer2x_isdbt_inner2x
2230 // [0] : disable clock
2231 // [1] : invert clock
2232 // [3:2] : 0 : clk_dmplldiv10_div2 \_________________> clk_isdbt_inner2x_dvbt_inner2x, *sel[0] = (reg_demod_isdbt_on) | TEST_CLK_EN
2233 // : 1 : clk_isdbt_inner2x_p /
2234 // : 2 : dtmb_eq_clk36_buf ------------------> clk_dtmb_outer2x
2235 // : 3 : 1'b0
2236 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h40, 2'b11, 16'h0000);
2237 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h40, 2'b11, 16'h0000);
2238 _HAL_DMD_RIU_WriteByte(0x111f81, 0x00);
2239 _HAL_DMD_RIU_WriteByte(0x111f80, 0x00);
2240
2241
2242 // [3:0] : reg_ckg_share_dtmb_inner2x_isdbt_inner2x
2243 // [0] : disable clock
2244 // [1] : invert clock
2245 // [3:2] : 0 : clk_dmplldiv10_div2 \_________________> clk_isdbt_inner2x_dvbt_inner2x, *sel[0] = (reg_demod_isdbt_on) | TEST_CLK_EN
2246 // : 1 : clk_isdbt_inner2x_p /
2247 // : 2 : dtmb_clk36_buf ------------------> clk_dtmb_inner2x
2248 // : 3 : 1'b0
2249 // [7:4] : reg_ckg_share_dtmb_inner12x_isdbt_inner4x
2250 // [0] : disable clock
2251 // [1] : invert clock
2252 // [3:2] : 0 : clk_dvbtc_sram4_p \_________________> clk_dvbtc_sram4_isdbt_inner4x, *sel[0] = reg_demod_isdbt_on | TEST_CLK_EN;
2253 // : 1 : clk_isdbt_inner4x_p /
2254 // : 2 : clk_dtmb_inner12x_4x_dvbtc_rs_mux --------> clk_dtmb_inner12x_4x_dvbtc_rs,
2255 // : 3 : 1'b0
2256 // [11:8] : reg_ckg_share_dtmb_eq2x_isdbt_outer6x
2257 // [0] : disable clock
2258 // [1] : invert clock
2259 // [3:2] : 0 : isdbt_clk36_lat \_________________> clk_isdbt_outer6x, *sel[0] = reg_ckg_isdbt_outer6x[2] | TEST_CLK_EN
2260 // : 1 : isdbt_clk48_lat /
2261 // : 2 : clk_dtmb_eq2x_inner12x_mux ---------------> clk_dtmb_eq2x_inner12x
2262 // : 3 : 1'b0
2263 // [15:12] : reg_ckg_share_dtmb_eq0p5x_isdbt_sram0
2264 // [0] : disable clock
2265 // [1] : invert clock
2266 // [3:2] : 0 : clk_dvbtc_sram0_p \_________________> clk_sram0, *sel[0] = reg_demod_isdbt_on | TEST_CLK_EN
2267 // : 1 : clk_isdbt_inner4x_p /
2268 // : 2 : dtmb_eq_clk72_buf \_________________> clk_dtmb_eq0p5x_inner4x *sel[0] = reg_ckg_dtmb_eq0p5x_inner4x[2] | extmd
2269 // : 3 : dtmb_clk72_buf /
2270 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h41, 2'b11, 16'h0000);
2271 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h41, 2'b11, 16'h0000);
2272 _HAL_DMD_RIU_WriteByte(0x111f83, 0x00);
2273 _HAL_DMD_RIU_WriteByte(0x111f82, 0x00);
2274
2275
2276 // [3:0] : reg_ckg_share_dtmb_eq2x_isdbt_sram1
2277 // [0] : disable clock
2278 // [1] : invert clock
2279 // [3:2] : 0 : clk_dvbtc_sram1_p \_________________> clk_sram1, *sel[0] = reg_demod_isdbt_on | TEST_CLK_EN
2280 // : 1 : clk_isdbt_inner4x_p /
2281 // : 2 : clk_dtmb_eq2x_inner2x_12x_mux ------------> clk_dtmb_eq2x_inner2x_12x
2282 // : 3 : 1'b0
2283 // [7:4] : reg_ckg_share_dtmb_inner6x_isdbt_sram3
2284 // [0] : disable clock
2285 // [1] : invert clock
2286 // [3:2] : 0 : clk_dvbtc_sram3_p \_________________> clk_sram3, *sel[0] = ((~reg_fed_srd_on) & reg_demod_isdbt_on) | TEST_CLK_EN
2287 // : 1 : clk_isdbt_inner2x_p /
2288 // : 2 : dtmb_clk108_buf ------------------> clk_dtmb_inner6x
2289 // : 3 : 1'b0
2290 // [11:8] : reg_ckg_share_dtmb_eq2x_isdbt_sram3
2291 // [0] : disable clock
2292 // [1] : invert clock
2293 // [3:2] : 0 : clk_dvbtc_sram3_p \_________________> clk_sram3, *sel[0] = ((~reg_fed_srd_on) & reg_demod_isdbt_on) | TEST_CLK_EN
2294 // : 1 : clk_isdbt_inner2x_p /
2295 // : 2 : clk_dtmb_eq2x_inner12x_mux ---------------> clk_dtmb_eq2x_inner12x
2296 // : 3 : 1'b0
2297 // [15:12] : reg_ckg_share_dtmb_inner12x_isdbt_sram4
2298 // [0] : disable clock
2299 // [1] : invert clock
2300 // [3:2] : 0 : clk_dvbtc_sram4_p \_________________> clk_sram4, *sel[0] = ((~reg_fed_srd_on) & reg_demod_isdbt_on) | TEST_CLK_EN
2301 // : 1 : clk_isdbt_inner2x_p /
2302 // : 2 : dtmb_clk216_buf ------------------> clk_dtmb_inner12x
2303 // : 3 : 1'b0
2304 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h42, 2'b11, 16'h0000);
2305 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h42, 2'b11, 16'h0000);
2306 _HAL_DMD_RIU_WriteByte(0x111f85, 0x00);
2307 _HAL_DMD_RIU_WriteByte(0x111f84, 0x00);
2308
2309
2310 // [3:0] : reg_ckg_share_dtmb_inner12x_eq0p5x_isdbt_sram4
2311 // [0] : disable clock
2312 // [1] : invert clock
2313 // [3:2] : 0 : clk_dvbtc_sram4_p \_________________> clk_sram4, *sel[0] = ((~reg_fed_srd_on) & reg_demod_isdbt_on) | TEST_CLK_EN
2314 // : 1 : clk_isdbt_inner2x_p /
2315 // : 2 : dtmb_clk216_buf \_________________> clk_dtmb_inner12x_eq0p5x, *sel[0] = reg_ckg_dtmb_inner12x_eq0p5x[2] | extmd
2316 // : 3 : dtmb_eq_clk72_buf /
2317 // [7:4] : reg_ckg_share_dtmb_eq0p25x_isdbt_sram4
2318 // [0] : disable clock
2319 // [1] : invert clock
2320 // [3:2] : 0 : clk_dvbtc_sram4_p \_________________> clk_sram4, *sel[0] = ((~reg_fed_srd_on) & reg_demod_isdbt_on) | TEST_CLK_EN
2321 // : 1 : clk_isdbt_inner2x_p /
2322 // : 2 : dtmb_eq_clk36_buf ------------------> clk_dtmb_eq0p25x
2323 // : 3 : 1'b0
2324 // [11:8] : reg_ckg_share_dtmb_inner2x_isdbt_sram4
2325 // [0] : disable clock
2326 // [1] : invert clock
2327 // [3:2] : 0 : clk_dvbtc_sram4_p \_________________> clk_sram4, *sel[0] = ((~reg_fed_srd_on) & reg_demod_isdbt_on) | TEST_CLK_EN
2328 // : 1 : clk_isdbt_inner2x_p /
2329 // : 2 : dtmb_clk36_buf \_________________> clk_dtmb_inner2x_dvbtc_rs, *sel[0] = reg_ckg_dtmb_inner2x_dvbtc_rs[2] | TEST_CLK_EN
2330 // : 3 : clk_dvbtc_rs_mux /
2331 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h43, 2'b11, 16'h0000);
2332 // `RIU_W((`RIUBASE_CLKGEN_DMD>>1)+7'h43, 2'b11, 16'h0000);
2333 _HAL_DMD_RIU_WriteByte(0x111f87, 0x00);
2334 _HAL_DMD_RIU_WriteByte(0x111f86, 0x00);
2335
2336 u8Val = _HAL_DMD_RIU_ReadByte(0x101e39);
2337 _HAL_DMD_RIU_WriteByte(0x101e39, u8Val|0x03);
2338 }
2339 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_WHISKY)
_HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)2340 void _HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)
2341 {
2342 MS_U8 u8Val=0x00;
2343
2344 HAL_INTERN_ATSC_DBINFO(printf("--------------DMD_ATSC_CHIP_WHISKY--------------\n"));
2345
2346 u8Val = _HAL_DMD_RIU_ReadByte(0x101e39);
2347 _HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
2348
2349 // DMDMCU 108M
2350 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
2351 // Set parallel TS clock
2352 _HAL_DMD_RIU_WriteByte(0x103301, 0x05);
2353 _HAL_DMD_RIU_WriteByte(0x103300, 0x11);
2354 // Enable ATSC, DVBTC TS clock
2355 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
2356 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
2357 // Enable ADC clock in clkgen_demod
2358 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
2359 _HAL_DMD_RIU_WriteByte(0x103314, 0x00);
2360 // Reset TS divider
2361 _HAL_DMD_RIU_WriteByte(0x103302, 0x01);
2362 _HAL_DMD_RIU_WriteByte(0x103302, 0x00);
2363 // ADC select MPLLDIV17 & EQ select MPLLDIV5
2364 _HAL_DMD_RIU_WriteByte(0x111f43, 0x00);
2365 _HAL_DMD_RIU_WriteByte(0x111f42, 0x00);
2366 // Enable ATSC clock
2367 _HAL_DMD_RIU_WriteByte(0x111f03, 0x00);
2368 _HAL_DMD_RIU_WriteByte(0x111f02, 0x00);
2369 // configure reg_ckg_atsc50, reg_ckg_atsc25, reg_ckg_atsc_eq25 and reg_ckg_atsc_ce25
2370 _HAL_DMD_RIU_WriteByte(0x111f04, 0x00);
2371 _HAL_DMD_RIU_WriteByte(0x111f07, 0x00);
2372 _HAL_DMD_RIU_WriteByte(0x111f06, 0x00);
2373 // enable clk_atsc_adcd_sync
2374 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
2375 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x08);
2376 // Enable DVBC outer clock
2377 _HAL_DMD_RIU_WriteByte(0x111f12, 0x00);
2378 // Enable SRAM clock
2379 _HAL_DMD_RIU_WriteByte(0x111f19, 0x00);
2380 _HAL_DMD_RIU_WriteByte(0x111f18, 0x00);
2381 // select clock
2382 _HAL_DMD_RIU_WriteByte(0x111f23, 0x00);
2383 _HAL_DMD_RIU_WriteByte(0x111f22, 0x00);
2384 // enable CCI LMS clock
2385 _HAL_DMD_RIU_WriteByte(0x111f71, 0x00);
2386 _HAL_DMD_RIU_WriteByte(0x111f70, 0x00);
2387 // set symbol rate
2388 _HAL_DMD_RIU_WriteByte(0x111f77, 0x04);
2389 _HAL_DMD_RIU_WriteByte(0x111f76, 0x04);
2390 // reg_ckg_adc1x_eq1x
2391 _HAL_DMD_RIU_WriteByte(0x111f49, 0x04);
2392
2393 u8Val = _HAL_DMD_RIU_ReadByte(0x101e39);
2394 _HAL_DMD_RIU_WriteByte(0x101e39,(u8Val| 0x03));
2395 }
2396 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MASERATI || DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MACAN)
_HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)2397 static void _HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)
2398 {
2399 //MS_U8 u8Val = 0;
2400
2401 #if DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MASERATI
2402 HAL_INTERN_ATSC_DBINFO(printf("--------------DMD_ATSC_CHIP_MASERATI--------------\n"));
2403 #else
2404 HAL_INTERN_ATSC_DBINFO(printf("--------------DMD_ATSC_CHIP_MACAN--------------\n"));
2405 #endif
2406
2407 //u8Val = _HAL_DMD_RIU_ReadByte(0x101e39);
2408 //_HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
2409 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
2410
2411 _HAL_DMD_RIU_WriteByte(0x1128d0, 0x01);
2412
2413 _HAL_DMD_RIU_WriteByte(0x10331e, 0x10);
2414
2415 _HAL_DMD_RIU_WriteByte(0x103301, 0x05);
2416 _HAL_DMD_RIU_WriteByte(0x103300, 0x11);
2417
2418 _HAL_DMD_RIU_WriteByte(0x103309, 0x00);
2419 _HAL_DMD_RIU_WriteByte(0x103308, 0x00);
2420
2421 _HAL_DMD_RIU_WriteByte(0x103302, 0x01);
2422 _HAL_DMD_RIU_WriteByte(0x103302, 0x00);
2423
2424 _HAL_DMD_RIU_WriteByte(0x111f0b, 0x00);
2425 _HAL_DMD_RIU_WriteByte(0x111f0a, 0x08);
2426
2427 _HAL_DMD_RIU_WriteByte(0x103315, 0x00);
2428 _HAL_DMD_RIU_WriteByte(0x103314, 0x08);
2429
2430 _HAL_DMD_RIU_WriteByte(0x1128d0, 0x00);
2431
2432 _HAL_DMD_RIU_WriteByte(0x152928, 0x00);
2433
2434 _HAL_DMD_RIU_WriteByte(0x152903, 0x00);
2435 _HAL_DMD_RIU_WriteByte(0x152902, 0x00);
2436
2437 _HAL_DMD_RIU_WriteByte(0x152905, 0x00);
2438 _HAL_DMD_RIU_WriteByte(0x152904, 0x00);
2439
2440 _HAL_DMD_RIU_WriteByte(0x152907, 0x00);
2441 _HAL_DMD_RIU_WriteByte(0x152906, 0x00);
2442
2443
2444
2445 _HAL_DMD_RIU_WriteByte(0x111f21, 0x44);
2446 _HAL_DMD_RIU_WriteByte(0x111f20, 0x40);
2447
2448 _HAL_DMD_RIU_WriteByte(0x111f23, 0x10);
2449 _HAL_DMD_RIU_WriteByte(0x111f22, 0x44);
2450
2451 _HAL_DMD_RIU_WriteByte(0x111f3b, 0x08);
2452 _HAL_DMD_RIU_WriteByte(0x111f3a, 0x08);
2453
2454 _HAL_DMD_RIU_WriteByte(0x111f71, 0x00);
2455 _HAL_DMD_RIU_WriteByte(0x111f70, 0x00);
2456
2457 _HAL_DMD_RIU_WriteByte(0x111f73, 0x00);
2458 _HAL_DMD_RIU_WriteByte(0x111f72, 0x00);
2459
2460 _HAL_DMD_RIU_WriteByte(0x111f79, 0x11);
2461 _HAL_DMD_RIU_WriteByte(0x111f78, 0x18);
2462
2463 _HAL_DMD_RIU_WriteByte(0x152991, 0x88);
2464 _HAL_DMD_RIU_WriteByte(0x152990, 0x88);
2465
2466 _HAL_DMD_RIU_WriteByte(0x111f69, 0x44);
2467 _HAL_DMD_RIU_WriteByte(0x111f68, 0x00);
2468
2469 _HAL_DMD_RIU_WriteByte(0x111f75, 0x81);
2470 _HAL_DMD_RIU_WriteByte(0x111f74, 0x11);
2471
2472 _HAL_DMD_RIU_WriteByte(0x111f77, 0x81);
2473 _HAL_DMD_RIU_WriteByte(0x111f76, 0x88);
2474
2475 _HAL_DMD_RIU_WriteByte(0x15298f, 0x11);
2476 _HAL_DMD_RIU_WriteByte(0x15298e, 0x88);
2477
2478 _HAL_DMD_RIU_WriteByte(0x152923, 0x00);
2479 _HAL_DMD_RIU_WriteByte(0x152922, 0x00);
2480
2481 _HAL_DMD_RIU_WriteByte(0x111f25, 0x10);
2482 _HAL_DMD_RIU_WriteByte(0x111f24, 0x11);
2483
2484 _HAL_DMD_RIU_WriteByte(0x152971, 0x1c);
2485 _HAL_DMD_RIU_WriteByte(0x152970, 0xc1);
2486
2487 _HAL_DMD_RIU_WriteByte(0x152977, 0x04);
2488 _HAL_DMD_RIU_WriteByte(0x152976, 0x04);
2489
2490 _HAL_DMD_RIU_WriteByte(0x111f6f, 0x11);
2491 _HAL_DMD_RIU_WriteByte(0x111f6e, 0x00);
2492
2493 _HAL_DMD_RIU_WriteByte(0x111feb, 0x18);
2494
2495 _HAL_DMD_RIU_WriteByte(0x111f7f, 0x10);
2496 _HAL_DMD_RIU_WriteByte(0x111f7e, 0x11);
2497
2498 _HAL_DMD_RIU_WriteByte(0x111f31, 0x14);
2499
2500 _HAL_DMD_RIU_WriteByte(0x152981, 0x00);
2501 _HAL_DMD_RIU_WriteByte(0x152980, 0x00);
2502
2503 _HAL_DMD_RIU_WriteByte(0x152983, 0x00);
2504 _HAL_DMD_RIU_WriteByte(0x152982, 0x00);
2505
2506 _HAL_DMD_RIU_WriteByte(0x152985, 0x00);
2507 _HAL_DMD_RIU_WriteByte(0x152984, 0x00);
2508
2509 _HAL_DMD_RIU_WriteByte(0x152987, 0x00);
2510 _HAL_DMD_RIU_WriteByte(0x152986, 0x00);
2511
2512 _HAL_DMD_RIU_WriteByte(0x152979, 0x11);
2513 _HAL_DMD_RIU_WriteByte(0x152978, 0x14);
2514
2515 _HAL_DMD_RIU_WriteByte(0x15298d, 0x81);
2516 _HAL_DMD_RIU_WriteByte(0x15298c, 0x44);
2517
2518 //u8Val = _HAL_DMD_RIU_ReadByte(0x101e39);
2519 //_HAL_DMD_RIU_WriteByte(0x101e39, u8Val|0x03);
2520 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
2521 }
2522 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MUSTANG )
_HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)2523 static void _HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)
2524 {
2525 //MS_U8 u8Val = 0;
2526
2527 HAL_INTERN_ATSC_DBINFO(printf("--------------DMD_ATSC_CHIP_MUSTANG--------------\n"));
2528
2529 //u8Val = _HAL_DMD_RIU_ReadByte(0x101e39);
2530 //_HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
2531 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
2532
2533
2534 _HAL_DMD_RIU_WriteByte(0x101e39,0x00);
2535
2536 _HAL_DMD_RIU_WriteByte(0x10331e,0x10);
2537
2538
2539 _HAL_DMD_RIU_WriteByte(0x103301,0x05);
2540 _HAL_DMD_RIU_WriteByte(0x103300,0x11);
2541
2542
2543 _HAL_DMD_RIU_WriteByte(0x103309,0x00);
2544 _HAL_DMD_RIU_WriteByte(0x103308,0x00);
2545
2546
2547 _HAL_DMD_RIU_WriteByte(0x103315,0x00);
2548 _HAL_DMD_RIU_WriteByte(0x103314,0x08);
2549
2550 _HAL_DMD_RIU_WriteByte(0x103302,0x01);
2551 _HAL_DMD_RIU_WriteByte(0x103302,0x00);
2552
2553
2554 _HAL_DMD_RIU_WriteByte(0x152928,0x00);
2555
2556
2557 _HAL_DMD_RIU_WriteByte(0x152903,0x00);
2558 _HAL_DMD_RIU_WriteByte(0x152902,0x00);
2559
2560 _HAL_DMD_RIU_WriteByte(0x152905,0x00);
2561 _HAL_DMD_RIU_WriteByte(0x152904,0x00);
2562
2563 _HAL_DMD_RIU_WriteByte(0x152907,0x00);
2564 _HAL_DMD_RIU_WriteByte(0x152906,0x00);
2565
2566 _HAL_DMD_RIU_WriteByte(0x111f0b,0x00);
2567 _HAL_DMD_RIU_WriteByte(0x111f0a,0x08);
2568
2569 _HAL_DMD_RIU_WriteByte(0x111f21,0x44);
2570 _HAL_DMD_RIU_WriteByte(0x111f20,0x40);
2571
2572
2573 _HAL_DMD_RIU_WriteByte(0x111f23,0x10);
2574 _HAL_DMD_RIU_WriteByte(0x111f22,0x44);
2575
2576 _HAL_DMD_RIU_WriteByte(0x111f3b,0x08);
2577 _HAL_DMD_RIU_WriteByte(0x111f3a,0x08);
2578
2579 _HAL_DMD_RIU_WriteByte(0x111f71,0x00);
2580 _HAL_DMD_RIU_WriteByte(0x111f70,0x00);
2581 _HAL_DMD_RIU_WriteByte(0x111f73,0x00);
2582 _HAL_DMD_RIU_WriteByte(0x111f72,0x00);
2583
2584 _HAL_DMD_RIU_WriteByte(0x111f79,0x11);
2585 _HAL_DMD_RIU_WriteByte(0x111f78,0x18);
2586
2587 _HAL_DMD_RIU_WriteByte(0x152991,0x88);
2588 _HAL_DMD_RIU_WriteByte(0x152990,0x88);
2589
2590
2591 _HAL_DMD_RIU_WriteByte(0x111f69,0x44);
2592 _HAL_DMD_RIU_WriteByte(0x111f68,0x00);
2593
2594 _HAL_DMD_RIU_WriteByte(0x111f75,0x81);
2595 _HAL_DMD_RIU_WriteByte(0x111f74,0x11);
2596
2597
2598 _HAL_DMD_RIU_WriteByte(0x111f77,0x81);
2599 _HAL_DMD_RIU_WriteByte(0x111f76,0x88);
2600
2601
2602 _HAL_DMD_RIU_WriteByte(0x15298f,0x11);
2603 _HAL_DMD_RIU_WriteByte(0x15298e,0x88);
2604
2605 _HAL_DMD_RIU_WriteByte(0x152923,0x00);
2606 _HAL_DMD_RIU_WriteByte(0x152922,0x00);
2607
2608 _HAL_DMD_RIU_WriteByte(0x111f25,0x10);
2609 _HAL_DMD_RIU_WriteByte(0x111f24,0x11);
2610
2611 _HAL_DMD_RIU_WriteByte(0x152971,0x1c);
2612 _HAL_DMD_RIU_WriteByte(0x152970,0xc1);
2613
2614
2615 _HAL_DMD_RIU_WriteByte(0x152977,0x04);
2616 _HAL_DMD_RIU_WriteByte(0x152976,0x04);
2617
2618
2619 _HAL_DMD_RIU_WriteByte(0x111f6f,0x11);
2620 _HAL_DMD_RIU_WriteByte(0x111f6e,0x00);
2621
2622 _HAL_DMD_RIU_WriteByte(0x111feb,0x18);
2623 _HAL_DMD_RIU_WriteByte(0x111f7f,0x10);
2624 _HAL_DMD_RIU_WriteByte(0x111f7e,0x11);
2625 _HAL_DMD_RIU_WriteByte(0x111f31,0x14);
2626
2627
2628 _HAL_DMD_RIU_WriteByte(0x152981,0x00);
2629 _HAL_DMD_RIU_WriteByte(0x152980,0x00);
2630
2631
2632
2633 _HAL_DMD_RIU_WriteByte(0x152983,0x00);
2634 _HAL_DMD_RIU_WriteByte(0x152982,0x00);
2635
2636
2637
2638 _HAL_DMD_RIU_WriteByte(0x152985,0x00);
2639 _HAL_DMD_RIU_WriteByte(0x152984,0x00);
2640
2641
2642 _HAL_DMD_RIU_WriteByte(0x152987,0x00);
2643 _HAL_DMD_RIU_WriteByte(0x152986,0x00);
2644
2645 _HAL_DMD_RIU_WriteByte(0x152979,0x11);
2646 _HAL_DMD_RIU_WriteByte(0x152978,0x14);
2647
2648
2649 _HAL_DMD_RIU_WriteByte(0x15298d,0x81);
2650 _HAL_DMD_RIU_WriteByte(0x15298c,0x44);
2651
2652
2653
2654
2655 //u8Val = _HAL_DMD_RIU_ReadByte(0x101e39);
2656 //_HAL_DMD_RIU_WriteByte(0x101e39, u8Val|0x03);
2657 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
2658 }
2659 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MAXIM )
_HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)2660 static void _HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)
2661 {
2662 //MS_U8 u8Val = 0;
2663
2664 HAL_INTERN_ATSC_DBINFO(printf("--------------DMD_ATSC_CHIP_MAXIM--------------\n"));
2665
2666 //u8Val = _HAL_DMD_RIU_ReadByte(0x101e39);
2667 //_HAL_DMD_RIU_WriteByte(0x101e39, u8Val&(~0x03));
2668 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x00, 0x03);
2669
2670 _HAL_DMD_RIU_WriteByte(0x10331e,0x10);
2671
2672 _HAL_DMD_RIU_WriteByte(0x103301,0x05);
2673 _HAL_DMD_RIU_WriteByte(0x103300,0x11);
2674
2675
2676 _HAL_DMD_RIU_WriteByte(0x103309,0x00);
2677 _HAL_DMD_RIU_WriteByte(0x103308,0x00);
2678
2679 _HAL_DMD_RIU_WriteByte(0x103315,0x00);
2680 _HAL_DMD_RIU_WriteByte(0x103314,0x08);
2681
2682
2683 _HAL_DMD_RIU_WriteByte(0x103302,0x01);
2684
2685 _HAL_DMD_RIU_WriteByte(0x103302,0x00);
2686
2687
2688 _HAL_DMD_RIU_WriteByte(0x103321,0x00);
2689 _HAL_DMD_RIU_WriteByte(0x103320,0x08);
2690
2691
2692 _HAL_DMD_RIU_WriteByte(0x152928,0x00);
2693
2694
2695 _HAL_DMD_RIU_WriteByte(0x152903,0x00);
2696 _HAL_DMD_RIU_WriteByte(0x152902,0x00);
2697
2698
2699 _HAL_DMD_RIU_WriteByte(0x152905,0x00);
2700 _HAL_DMD_RIU_WriteByte(0x152904,0x00);
2701
2702
2703 _HAL_DMD_RIU_WriteByte(0x152907,0x00);
2704 _HAL_DMD_RIU_WriteByte(0x152906,0x00);
2705
2706
2707 _HAL_DMD_RIU_WriteByte(0x111f0b,0x00);
2708 _HAL_DMD_RIU_WriteByte(0x111f0a,0x08);
2709
2710
2711 _HAL_DMD_RIU_WriteByte(0x111f21,0x44);
2712 _HAL_DMD_RIU_WriteByte(0x111f20,0x40);
2713
2714
2715 _HAL_DMD_RIU_WriteByte(0x111f23,0x10);
2716 _HAL_DMD_RIU_WriteByte(0x111f22,0x44);
2717
2718 _HAL_DMD_RIU_WriteByte(0x111f3b,0x08);
2719 _HAL_DMD_RIU_WriteByte(0x111f3a,0x08);
2720
2721 _HAL_DMD_RIU_WriteByte(0x111f71,0x00);
2722 _HAL_DMD_RIU_WriteByte(0x111f70,0x00);
2723 _HAL_DMD_RIU_WriteByte(0x111f73,0x00);
2724 _HAL_DMD_RIU_WriteByte(0x111f72,0x00);
2725
2726 _HAL_DMD_RIU_WriteByte(0x111f79,0x11);
2727 _HAL_DMD_RIU_WriteByte(0x111f78,0x18);
2728
2729 _HAL_DMD_RIU_WriteByte(0x152991,0x88);
2730 _HAL_DMD_RIU_WriteByte(0x152990,0x88);
2731
2732 _HAL_DMD_RIU_WriteByte(0x111f69,0x44);
2733 _HAL_DMD_RIU_WriteByte(0x111f68,0x00);
2734
2735 _HAL_DMD_RIU_WriteByte(0x111f75,0x81);
2736 _HAL_DMD_RIU_WriteByte(0x111f74,0x11);
2737
2738 _HAL_DMD_RIU_WriteByte(0x111f77,0x81);
2739 _HAL_DMD_RIU_WriteByte(0x111f76,0x88);
2740
2741 _HAL_DMD_RIU_WriteByte(0x15298f,0x11);
2742 _HAL_DMD_RIU_WriteByte(0x15298e,0x88);
2743
2744 _HAL_DMD_RIU_WriteByte(0x152923,0x00);
2745 _HAL_DMD_RIU_WriteByte(0x152922,0x00);
2746
2747 _HAL_DMD_RIU_WriteByte(0x111f25,0x10);
2748 _HAL_DMD_RIU_WriteByte(0x111f24,0x11);
2749
2750 _HAL_DMD_RIU_WriteByte(0x152971,0x1c);
2751 _HAL_DMD_RIU_WriteByte(0x152970,0xc1);
2752
2753
2754 _HAL_DMD_RIU_WriteByte(0x152977,0x04);
2755 _HAL_DMD_RIU_WriteByte(0x152976,0x04);
2756
2757
2758 _HAL_DMD_RIU_WriteByte(0x111f6f,0x11);
2759 _HAL_DMD_RIU_WriteByte(0x111f6e,0x00);
2760
2761 _HAL_DMD_RIU_WriteByte(0x111feb,0x18);
2762
2763 _HAL_DMD_RIU_WriteByte(0x111f7f,0x10);
2764 _HAL_DMD_RIU_WriteByte(0x111f7e,0x11);
2765
2766 _HAL_DMD_RIU_WriteByte(0x111f31,0x14);
2767
2768 _HAL_DMD_RIU_WriteByte(0x152981,0x00);
2769 _HAL_DMD_RIU_WriteByte(0x152980,0x00);
2770
2771
2772 _HAL_DMD_RIU_WriteByte(0x152983,0x00);
2773 _HAL_DMD_RIU_WriteByte(0x152982,0x00);
2774
2775
2776 _HAL_DMD_RIU_WriteByte(0x152985,0x00);
2777 _HAL_DMD_RIU_WriteByte(0x152984,0x00);
2778
2779
2780
2781 _HAL_DMD_RIU_WriteByte(0x152987,0x00);
2782 _HAL_DMD_RIU_WriteByte(0x152986,0x00);
2783
2784 _HAL_DMD_RIU_WriteByte(0x152979,0x11);
2785 _HAL_DMD_RIU_WriteByte(0x152978,0x14);
2786
2787 _HAL_DMD_RIU_WriteByte(0x15298d,0x81);
2788 _HAL_DMD_RIU_WriteByte(0x15298c,0x44);
2789
2790 _HAL_DMD_RIU_WriteByteMask(0x101e39, 0x03, 0x03);
2791 }
2792
2793 #else
_HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)2794 static void _HAL_INTERN_ATSC_InitClk(MS_BOOL bRFAGCTristateEnable)
2795 {
2796 printf("--------------DMD_ATSC_CHIP_NONE--------------\n");
2797 }
2798 #endif
2799
_HAL_INTERN_ATSC_Download(void)2800 static MS_BOOL _HAL_INTERN_ATSC_Download(void)
2801 {
2802 DMD_ATSC_ResData *pRes = psDMD_ATSC_ResData + u8DMD_ATSC_DMD_ID;
2803
2804 MS_U8 udata = 0x00;
2805 MS_U16 i=0;
2806 MS_U16 fail_cnt=0;
2807 #if (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_K3)
2808 MS_U8 u8TmpData;
2809 MS_U16 u16AddressOffset;
2810 #endif
2811
2812 #if (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_T3_T10)
2813 if (_HAL_DMD_RIU_ReadByte(0x101E3E) != 0x08) HAL_PWS_Stop_VDMCU();
2814 else
2815 {
2816 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x01); // reset VD_MCU
2817 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x00);
2818 MsOS_DelayTask(20);
2819 return TRUE;
2820 }
2821 #else
2822 if (pRes->sDMD_ATSC_PriData.bDownloaded)
2823 {
2824 #if (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MUSTANG)
2825 udata=_HAL_DMD_RIU_ReadByte(DMDMcuBase+0x00);
2826 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, (udata|0x02)); // reset RIU remapping reset
2827 udata=_HAL_DMD_RIU_ReadByte(DMDMcuBase+0x00);
2828 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, (udata|0x01)); // reset VD_MCU
2829 #else
2830 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x01); // reset MCU, madison patch
2831 #endif
2832 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x00);
2833 MsOS_DelayTask(20);
2834 return TRUE;
2835 }
2836 #endif
2837
2838 #if (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MUSTANG)
2839 udata=_HAL_DMD_RIU_ReadByte(DMDMcuBase+0x00);
2840 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, (udata|0x02)); // reset RIU remapping reset
2841 udata=_HAL_DMD_RIU_ReadByte(DMDMcuBase+0x00);
2842 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, (udata|0x01)); // reset VD_MCU
2843 #else
2844 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x01); // reset MCU, madison patch
2845 #endif
2846 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x01, 0x00); // disable SRAM
2847 #if (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MUSTANG)
2848 udata=_HAL_DMD_RIU_ReadByte(DMDMcuBase+0x00);
2849 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, (udata&(~0x01))); // release MCU, madison patch
2850 #else
2851 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x00);// release MCU, madison patchs
2852 #endif
2853 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x50); // enable "vdmcu51_if"
2854 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x51); // enable auto-increase
2855 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x04, 0x00); // sram address low byte
2856 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x05, 0x00); // sram address high byte
2857
2858 //// Load code thru VDMCU_IF ////
2859 HAL_INTERN_ATSC_DBINFO(printf(">Load Code...\n"));
2860
2861 for (i = 0; i < u16Lib_size; i++)
2862 {
2863 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, INTERN_ATSC_table[i]); // write data to VD MCU 51 code sram
2864 }
2865
2866 //// Content verification ////
2867 HAL_INTERN_ATSC_DBINFO(printf(">Verify Code...\n"));
2868
2869 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x04, 0x00); // sram address low byte
2870 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x05, 0x00); // sram address high byte
2871
2872 for (i = 0; i < u16Lib_size; i++)
2873 {
2874 udata = _HAL_DMD_RIU_ReadByte(DMDMcuBase+0x10); // read sram data
2875
2876 if (udata != INTERN_ATSC_table[i])
2877 {
2878 HAL_INTERN_ATSC_DBINFO(printf(">fail add = 0x%x\n", i));
2879 HAL_INTERN_ATSC_DBINFO(printf(">code = 0x%x\n", INTERN_ATSC_table[i]));
2880 HAL_INTERN_ATSC_DBINFO(printf(">data = 0x%x\n", udata));
2881
2882 if (fail_cnt++ > 10)
2883 {
2884 HAL_INTERN_ATSC_DBINFO(printf(">DSP Loadcode fail!"));
2885 return FALSE;
2886 }
2887 }
2888 }
2889
2890 #if (DMD_ATSC_CHIP_VERSION < DMD_ATSC_CHIP_K3)
2891 #if (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_A1)
2892 _initTable();
2893 #endif
2894
2895 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x04, 0x80); // sram address low byte
2896 #if (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_T8_T9 || DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_A1)
2897 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x05, 0x6B); // sram address high byte
2898 #else
2899 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x05, 0x5B); // sram address high byte
2900 #endif
2901
2902 for (i = 0; i < sizeof(Demod_Flow_register); i++)
2903 {
2904 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, Demod_Flow_register[i]);
2905 }
2906 #else // #if (DMD_ATSC_CHIP_VERSION < DMD_ATSC_CHIP_K3)
2907 u16AddressOffset = (INTERN_ATSC_table[0x400] << 8)|INTERN_ATSC_table[0x401];
2908
2909 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x04, (u16AddressOffset&0xFF)); // sram address low byte
2910 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x05, (u16AddressOffset>>8)); // sram address high byte
2911
2912 u8TmpData = (MS_U8)pRes->sDMD_ATSC_InitData.u16IF_KHZ;
2913 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
2914 u8TmpData = (MS_U8)(pRes->sDMD_ATSC_InitData.u16IF_KHZ >> 8);
2915 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
2916 u8TmpData = (MS_U8)pRes->sDMD_ATSC_InitData.bIQSwap;
2917 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
2918 u8TmpData = (MS_U8)pRes->sDMD_ATSC_InitData.u16AGC_REFERENCE;
2919 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
2920 u8TmpData = (MS_U8)(pRes->sDMD_ATSC_InitData.u16AGC_REFERENCE >> 8);
2921 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
2922 u8TmpData = (MS_U8)pRes->sDMD_ATSC_InitData.u8IS_DUAL;
2923 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
2924 u8TmpData = (MS_U8)u8DMD_ATSC_DMD_ID;
2925 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x0C, u8TmpData); // write data to VD MCU 51 code sram
2926 #endif // #if (DMD_ATSC_CHIP_VERSION < DMD_ATSC_CHIP_K3)
2927
2928 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x50); // diable auto-increase
2929 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x03, 0x00); // disable "vdmcu51_if"
2930
2931 #if (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MUSTANG)
2932 udata=_HAL_DMD_RIU_ReadByte(DMDMcuBase+0x00);
2933 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, (udata|0x01)); // reset VD_MCU
2934 #else
2935 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x01); // reset MCU, madison patch
2936 #endif
2937 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x01, 0x01); // enable SRAM
2938 _HAL_DMD_RIU_WriteByte(DMDMcuBase+0x00, 0x00); // release VD_MCU
2939
2940 #if (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_T3_T10)
2941 _HAL_DMD_RIU_WriteByte(0x101E3E, 0x08); // ATSC = BIT3 -> 0x08
2942 _HAL_DMD_RIU_WriteByte(0x11051C, 0x00);
2943 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_T7)
2944 _HAL_DMD_RIU_WriteByte(0x11261C, 0x00);
2945 pRes->sDMD_ATSC_PriData.bDownloaded = true;
2946 #else
2947 pRes->sDMD_ATSC_PriData.bDownloaded = true;
2948 #endif
2949
2950 MsOS_DelayTask(20);
2951
2952 HAL_INTERN_ATSC_DBINFO(printf(">DSP Loadcode done.\n"));
2953
2954 return TRUE;
2955 }
2956
_HAL_INTERN_ATSC_FWVERSION(void)2957 static void _HAL_INTERN_ATSC_FWVERSION(void)
2958 {
2959 MS_U8 data1,data2,data3;
2960
2961 #if (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_K3)
2962 _MBX_ReadReg(0x20C4, &data1);
2963 _MBX_ReadReg(0x20C5, &data2);
2964 _MBX_ReadReg(0x20C6, &data3);
2965 #else
2966 _MBX_ReadReg(0x20C4, &data1);
2967 _MBX_ReadReg(0x20CF, &data2);
2968 _MBX_ReadReg(0x20D0, &data3);
2969 #endif
2970
2971 printf("INTERN_ATSC_FW_VERSION:%x.%x.%x\n", data1, data2, data3);
2972 }
2973
_HAL_INTERN_ATSC_Exit(void)2974 static MS_BOOL _HAL_INTERN_ATSC_Exit(void)
2975 {
2976 MS_U8 u8CheckCount = 0;
2977
2978 _HAL_DMD_RIU_WriteByte(MBRegBase + 0x1C, 0x01);
2979
2980 _HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, _HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)|0x02); // assert interrupt to VD MCU51
2981 _HAL_DMD_RIU_WriteByte(DMDMcuBase + 0x03, _HAL_DMD_RIU_ReadByte(DMDMcuBase + 0x03)&(~0x02)); // de-assert interrupt to VD MCU51
2982
2983 while ((_HAL_DMD_RIU_ReadByte(MBRegBase + 0x1C)&0x02) != 0x02)
2984 {
2985 MsOS_DelayTaskUs(10);
2986
2987 if (u8CheckCount++ == 0xFF)
2988 {
2989 printf(">> ATSC Exit Fail!\n");
2990 return FALSE;
2991 }
2992 }
2993
2994 printf(">> ATSC Exit Ok!\n");
2995
2996 return TRUE;
2997 }
2998
_HAL_INTERN_ATSC_SoftReset(void)2999 static MS_BOOL _HAL_INTERN_ATSC_SoftReset(void)
3000 {
3001 MS_U8 u8Data = 0xFF;
3002
3003 //Reset FSM
3004 if (_MBX_WriteReg(0x20C0, 0x00)==FALSE) return FALSE;
3005
3006 #if (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_K3)
3007 while (u8Data != 0x02)
3008 #else
3009 while (u8Data != 0x00)
3010 #endif
3011 {
3012 if (_MBX_ReadReg(0x20C1, &u8Data)==FALSE) return FALSE;
3013 }
3014
3015 #if (DMD_ATSC_CHIP_VERSION < DMD_ATSC_CHIP_K3)
3016 //Execute demod top reset
3017 _MBX_ReadReg(0x2002, &u8Data);
3018 _MBX_WriteReg(0x2002, (u8Data|0x10));
3019 return _MBX_WriteReg(0x2002, (u8Data&(~0x10)));
3020 #else
3021 return TRUE;
3022 #endif
3023 }
3024
_HAL_INTERN_ATSC_SetVsbMode(void)3025 static MS_BOOL _HAL_INTERN_ATSC_SetVsbMode(void)
3026 {
3027 return _MBX_WriteReg(0x20C0, 0x08);
3028 }
3029
_HAL_INTERN_ATSC_Set64QamMode(void)3030 static MS_BOOL _HAL_INTERN_ATSC_Set64QamMode(void)
3031 {
3032 #if (DMD_ATSC_CHIP_VERSION < DMD_ATSC_CHIP_K3)
3033 if (_MBX_WriteReg(0x20C3, 0x00)==FALSE) return FALSE;
3034 #endif
3035 return _MBX_WriteReg(0x20C0, 0x04);
3036 }
3037
_HAL_INTERN_ATSC_Set256QamMode(void)3038 static MS_BOOL _HAL_INTERN_ATSC_Set256QamMode(void)
3039 {
3040 #if (DMD_ATSC_CHIP_VERSION < DMD_ATSC_CHIP_K3)
3041 if (_MBX_WriteReg(0x20C3, 0x01)==FALSE) return FALSE;
3042 #endif
3043 return _MBX_WriteReg(0x20C0, 0x04);
3044 }
3045
_HAL_INTERN_ATSC_SetModeClean(void)3046 static MS_BOOL _HAL_INTERN_ATSC_SetModeClean(void)
3047 {
3048 return _MBX_WriteReg(0x20C0, 0x00);
3049 }
3050
_HAL_INTERN_ATSC_Check8VSB64_256QAM(void)3051 static DMD_ATSC_DEMOD_TYPE _HAL_INTERN_ATSC_Check8VSB64_256QAM(void)
3052 {
3053 MS_U8 mode = 0;
3054
3055 #if (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_K3)
3056 _MBX_ReadReg(0x2A02, &mode); //EQ mode check
3057
3058 mode &= 0x07;
3059
3060 if (mode == QAM16_J83ABC) return DMD_ATSC_DEMOD_ATSC_16QAM;
3061 else if (mode == QAM32_J83ABC) return DMD_ATSC_DEMOD_ATSC_32QAM;
3062 else if (mode == QAM64_J83ABC) return DMD_ATSC_DEMOD_ATSC_64QAM;
3063 else if (mode == QAM128_J83ABC) return DMD_ATSC_DEMOD_ATSC_128QAM;
3064 else if (mode == QAM256_J83ABC) return DMD_ATSC_DEMOD_ATSC_256QAM;
3065 else return DMD_ATSC_DEMOD_ATSC_256QAM;
3066 #else
3067 #if (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MASERATI || DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MACAN \
3068 || DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MAXIM)
3069 _MBX_ReadReg(0x1700, &mode); //mode check
3070 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MUSTANG)
3071 _MBX_ReadReg(0x0400, &mode); //mode check (atsc_dmd)
3072 #else
3073 _MBX_ReadReg(0x2900, &mode); //mode check
3074 #endif
3075
3076 if ((mode&VSB_ATSC) == VSB_ATSC) return DMD_ATSC_DEMOD_ATSC_VSB;
3077 else if ((mode & QAM256_ATSC) == QAM256_ATSC) return DMD_ATSC_DEMOD_ATSC_256QAM;
3078 else return DMD_ATSC_DEMOD_ATSC_64QAM;
3079 #endif
3080 }
3081
_HAL_INTERN_ATSC_Vsb_QAM_AGCLock(void)3082 static MS_BOOL _HAL_INTERN_ATSC_Vsb_QAM_AGCLock(void)
3083 {
3084 MS_U8 data1 = 0;
3085
3086 #if (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_A1)
3087 #if (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MASERATI || DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MACAN \
3088 || DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MUSTANG || DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MAXIM)
3089 _MBX_ReadReg(0x2829, &data1); //AGC_LOCK
3090 #else
3091 _MBX_ReadReg(0x271D, &data1); //AGC_LOCK
3092 #endif
3093 #else
3094 _MBX_ReadReg(0x293A, &data1); //AGC_LOCK
3095 #endif
3096
3097 if(data1&0x01)
3098 {
3099 return TRUE;
3100 }
3101 else
3102 {
3103 return FALSE;
3104 }
3105 }
3106
_HAL_INTERN_ATSC_Vsb_PreLock(void)3107 static MS_BOOL _HAL_INTERN_ATSC_Vsb_PreLock(void)
3108 {
3109 MS_U8 data1 = 0;
3110 MS_U8 data2 = 0;
3111 MS_U16 checkValue;
3112
3113 _MBX_ReadReg(0x20C2, &data1); //<0>TR_LOCK, <1>PTK_LOCK
3114
3115 if ((data1&0x02) == 0x02)
3116 {
3117 #if (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MASERATI || DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MACAN \
3118 || DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MAXIM)
3119 _MBX_ReadReg(0x18EA, &data1);
3120 _MBX_ReadReg(0x18EB, &data2);
3121 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MUSTANG)
3122 _MBX_ReadReg(0x05EA, &data1); //atsc_dmdext
3123 _MBX_ReadReg(0x05EB, &data2); //atsc_dmdext
3124 #else
3125 _MBX_ReadReg(0x2AEA, &data1);
3126 _MBX_ReadReg(0x2AEB, &data2);
3127 #endif
3128
3129 checkValue = data1 << 8;
3130 checkValue |= data2;
3131
3132 HAL_INTERN_ATSC_DBINFO(printf("Internal Pre Locking time :[%d]ms\n",checkValue));
3133
3134 return TRUE;
3135 }
3136 else
3137 {
3138 HAL_INTERN_ATSC_DBINFO(printf("\nPreLock - FALSE"));
3139
3140 return FALSE;
3141 }
3142 }
3143
_HAL_INTERN_ATSC_Vsb_FSync_Lock(void)3144 static MS_BOOL _HAL_INTERN_ATSC_Vsb_FSync_Lock(void)
3145 {
3146 MS_U8 data1 = 0;
3147 MS_U8 data2 = 0;
3148 MS_U16 checkValue;
3149
3150 #if (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MASERATI || DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MACAN \
3151 || DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MAXIM)
3152 _MBX_ReadReg(0x1824, &data1); //<4>1:Field Sync lock = Fsync lock
3153 #else
3154 _MBX_ReadReg(0x2A24, &data1); //<4>1:Field Sync lock = Fsync lock
3155 #endif
3156
3157 if ((data1&0x10) == 0x10)
3158 {
3159 #if (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MASERATI || DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MACAN \
3160 || DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MAXIM)
3161 _MBX_ReadReg(0x18EE, &data1);
3162 _MBX_ReadReg(0x18EF, &data2);
3163 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MUSTANG)
3164 _MBX_ReadReg(0x05EE, &data1); //atsc_dmdext
3165 _MBX_ReadReg(0x05EF, &data2); //atsc_dmdext
3166 #else
3167 _MBX_ReadReg(0x2AEE, &data1);
3168 _MBX_ReadReg(0x2AEF, &data2);
3169 #endif
3170
3171 checkValue = data1 << 8;
3172 checkValue |= data2;
3173
3174 HAL_INTERN_ATSC_DBINFO(printf("Internal Fsync Locking time :[%d]ms\n",checkValue));
3175
3176 return TRUE;
3177 }
3178 else
3179 {
3180 HAL_INTERN_ATSC_DBINFO(printf("\nFsync Lock - FALSE"));
3181
3182 return FALSE;
3183 }
3184 }
3185
_HAL_INTERN_ATSC_Vsb_CE_Lock(void)3186 static MS_BOOL _HAL_INTERN_ATSC_Vsb_CE_Lock(void)
3187 {
3188 #if (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_A1)
3189 return TRUE;
3190 #else
3191 MS_U8 data1 = 0;
3192
3193 _MBX_ReadReg(0x20C2, &data1); //<4>1:CE Search Fail
3194
3195 if((data1&0x10) == 0)
3196 {
3197 HAL_INTERN_ATSC_DBINFO(printf("\nCE Lock"));
3198 return TRUE;
3199 }
3200 else
3201 {
3202 HAL_INTERN_ATSC_DBINFO(printf("\nCE unLock"));
3203 return FALSE;
3204 }
3205 #endif
3206 }
3207
_HAL_INTERN_ATSC_Vsb_FEC_Lock(void)3208 static MS_BOOL _HAL_INTERN_ATSC_Vsb_FEC_Lock(void)
3209 {
3210 MS_U8 data1=0, data2=0, data3=0, data4=0, data5=0;
3211 #if (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_A1)
3212 MS_U8 data6 =0, data7 = 0;
3213 #endif
3214
3215 #if (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_A1)
3216 _MBX_ReadReg(0x20C1, &data1);
3217 #if (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MASERATI || DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MACAN \
3218 || DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MAXIM)
3219 _MBX_ReadReg(0x1A17, &data2);//AD_NOISE_PWR_TRAIN1
3220 #else
3221 _MBX_ReadReg(0x2C17, &data2);//AD_NOISE_PWR_TRAIN1
3222 #endif
3223 _MBX_ReadReg(0x20C2, &data3);//<0>TR_LOCK, <1>PTK_LOCK
3224 #if (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MASERATI || DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MACAN \
3225 || DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MAXIM)
3226 _MBX_ReadReg(0x1901, &data4);//FEC_EN_CTL
3227 _MBX_ReadReg(0x1C67, &data5);//addy
3228 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MUSTANG)
3229 _MBX_ReadReg(0x0601, &data4);//FEC_EN_CTL (atsc_fec)
3230 _MBX_ReadReg(0x2D67, &data5);//addy (atsc_eqext)
3231 #else
3232 _MBX_ReadReg(0x2B01, &data4);//FEC_EN_CTL
3233 _MBX_ReadReg(0x2D67, &data5);//addy
3234 #endif
3235 _MBX_ReadReg(0x1F01, &data6);
3236 _MBX_ReadReg(0x1F40, &data7);
3237
3238 //Driver update 0426 :suggestion for field claim
3239 if (data1==INTERN_ATSC_OUTER_STATE &&
3240 ((data2<=INTERN_ATSC_VSB_TRAIN_SNR_LIMIT) || (data5 <= INTERN_ATSC_VSB_TRAIN_SNR_LIMIT)) &&
3241 ((data3&0x02)==0x02) &&
3242 ((data4&INTERN_ATSC_FEC_ENABLE)==INTERN_ATSC_FEC_ENABLE) &&
3243 ((data6&0x10) == 0x10) && ((data7&0x01) == 0x01))
3244 {
3245 HAL_INTERN_ATSC_DBINFO(printf("\nFEC Lock"));
3246 return TRUE;
3247 }
3248 else
3249 {
3250 HAL_INTERN_ATSC_DBINFO(printf("\nFEC unLock"));
3251 return FALSE;
3252 }
3253 #else
3254 _MBX_ReadReg(0x20C1, &data1);
3255 _MBX_ReadReg(0x2C17, &data2); //AD_NOISE_PWR_TRAIN1 (DFS)
3256 _MBX_ReadReg(0x20C2, &data3); //<0>TR_LOCK, <1>PTK_LOCK
3257 _MBX_ReadReg(0x2B01, &data4); //FEC_EN_CTL
3258 _MBX_ReadReg(0x2C15, &data5); //AD_NOISE_PWR_TRAIN1 (DSS)
3259
3260 if ((data1 == INTERN_ATSC_OUTER_STATE) &&
3261 ((data2 <= INTERN_ATSC_VSB_TRAIN_SNR_LIMIT) || (data5 <= INTERN_ATSC_VSB_TRAIN_SNR_LIMIT)) &&
3262 ((data3&0x02)==0x02) &&
3263 ((data4&INTERN_ATSC_FEC_ENABLE) == INTERN_ATSC_FEC_ENABLE))
3264 {
3265 HAL_INTERN_ATSC_DBINFO(printf("\nFEC Lock"));
3266 return TRUE;
3267 }
3268 else
3269 {
3270 HAL_INTERN_ATSC_DBINFO(printf("\nFEC unLock"));
3271 return FALSE;
3272 }
3273 #endif
3274 }
3275
_HAL_INTERN_ATSC_QAM_PreLock(void)3276 static MS_BOOL _HAL_INTERN_ATSC_QAM_PreLock(void)
3277 {
3278 MS_U8 data1 = 0;
3279
3280 #if (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_K3)
3281 _MBX_ReadReg(0x2950, &data1); //TR_LOCK
3282 #elif (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_A1)
3283 #if (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MASERATI || DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MACAN \
3284 || DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MAXIM)
3285 _MBX_ReadReg(0x1B15, &data1); //TR_LOCK
3286 #else
3287 _MBX_ReadReg(0x2615, &data1); //TR_LOCK
3288 #endif
3289 #else
3290 _MBX_ReadReg(0x2921, &data1); //TR_LOCK
3291 #endif
3292
3293 #if (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_K3)
3294 if (data1&0x01)
3295 {
3296 HAL_INTERN_ATSC_DBINFO(printf(" QAM preLock OK \n"));
3297 return TRUE;
3298 }
3299 else
3300 {
3301 HAL_INTERN_ATSC_DBINFO(printf(" QAM preLock NOT OK \n"));
3302 return FALSE;
3303 }
3304 #else
3305 if((data1&0x10) == 0x10)
3306 {
3307 HAL_INTERN_ATSC_DBINFO(printf(" QAM preLock OK \n"));
3308 return TRUE;
3309 }
3310 else
3311 {
3312 HAL_INTERN_ATSC_DBINFO(printf(" QAM preLock NOT OK \n"));
3313 return FALSE;
3314 }
3315 #endif
3316 }
3317
_HAL_INTERN_ATSC_QAM_Main_Lock(void)3318 static MS_BOOL _HAL_INTERN_ATSC_QAM_Main_Lock(void)
3319 {
3320 #if DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_A1
3321 MS_U8 data1=0, data2=0, data3=0, data4=0, data5=0, data6=0;
3322 #else
3323 MS_U8 data1=0, data4=0, data5=0, data6=0;
3324 #endif
3325
3326 #if (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_K3)
3327 _MBX_ReadReg(0x20C1, &data1);
3328 _MBX_ReadReg(0x2B18, &data2); //boundary detected
3329 _MBX_ReadReg(0x2950, &data3); //TR_LOCK
3330 _MBX_ReadReg(0x2B01, &data4); //FEC_EN_CTL
3331 _MBX_ReadReg(0x2101, &data5); //RS_backend
3332 _MBX_ReadReg(0x2140, &data6); //RS_backend
3333
3334 if (data1==INTERN_ATSC_OUTER_STATE && (data2&0x01)==0x01 &&
3335 data4==INTERN_ATSC_FEC_ENABLE && (data3&0x01) ==0x01 &&
3336 ((data5&0x10) == 0x10) && ((data6&0x01) == 0x01))
3337 {
3338 return TRUE;
3339 }
3340 else
3341 {
3342 return FALSE;
3343 }
3344 #elif (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_A1)
3345 _MBX_ReadReg(0x20C1, &data1);
3346 #if (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MASERATI || DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MACAN \
3347 || DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MAXIM)
3348 _MBX_ReadReg(0x1918, &data2); //boundary detected
3349 _MBX_ReadReg(0x1B15, &data3); //TR_LOCK
3350 _MBX_ReadReg(0x1901, &data4); //FEC_EN_CTL
3351 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MUSTANG)
3352 _MBX_ReadReg(0x0618, &data2); //boundary detected (atsc_fec)
3353 _MBX_ReadReg(0x2615, &data3); //TR_LOCK (dmd_tr)
3354 _MBX_ReadReg(0x0601, &data4); //FEC_EN_CTL (atsc_fec)
3355 #else
3356 _MBX_ReadReg(0x2B18, &data2); //boundary detected
3357 _MBX_ReadReg(0x2615, &data3); //TR_LOCK
3358 _MBX_ReadReg(0x2B01, &data4); //FEC_EN_CTL
3359 #endif
3360 _MBX_ReadReg(0x1F01, &data5);
3361 _MBX_ReadReg(0x1F40, &data6);
3362
3363 if (data1==INTERN_ATSC_OUTER_STATE && (data2&0x01)==0x01 &&
3364 data4==INTERN_ATSC_FEC_ENABLE && (data3&0x10)==0x10 &&
3365 ((data5&0x10) == 0x10) && ((data6&0x01) == 0x01))
3366 {
3367 return TRUE;
3368 }
3369 else
3370 {
3371 return FALSE;
3372 }
3373 #else
3374 _MBX_ReadReg(0x2B18, &data4); //boundary detected
3375 _MBX_ReadReg(0x2B01, &data5); //FEC_EN_CTL
3376 _MBX_ReadReg(0x2921, &data6); //TR_LOCK
3377 _MBX_ReadReg(0x20C1, &data1);
3378
3379 if (data1==INTERN_ATSC_OUTER_STATE && (data4&0x01) == 0x01 &&
3380 (data5&INTERN_ATSC_FEC_ENABLE) == INTERN_ATSC_FEC_ENABLE &&
3381 (data6&0x10) == 0x10)
3382 {
3383 return TRUE;
3384 }
3385 else
3386 {
3387 return FALSE;
3388 }
3389 #endif
3390 }
3391
_HAL_INTERN_ATSC_ReadIFAGC(void)3392 static MS_U8 _HAL_INTERN_ATSC_ReadIFAGC(void)
3393 {
3394 MS_U16 data = 0;
3395
3396 #if (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_K3)
3397 _MBX_ReadReg(0x2726, ((MS_U8*)(&data))+1); //reg_frontend
3398 _MBX_ReadReg(0x2727, (MS_U8*)(&data));
3399 #elif (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_A1)
3400 #if (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MASERATI || DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MACAN \
3401 || DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MUSTANG|| DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MAXIM)
3402 _MBX_ReadReg(0x280E, ((MS_U8*)(&data))+1);
3403 _MBX_ReadReg(0x280F, (MS_U8*)(&data));
3404 #else
3405 _MBX_ReadReg(0x2944, ((MS_U8*)(&data))+1);
3406 _MBX_ReadReg(0x2945, (MS_U8*)(&data));
3407 #endif
3408 #endif
3409
3410 return data;
3411 }
3412
_HAL_INTERN_ATSC_CheckSignalCondition(DMD_ATSC_SIGNAL_CONDITION * pstatus)3413 static void _HAL_INTERN_ATSC_CheckSignalCondition(DMD_ATSC_SIGNAL_CONDITION* pstatus)
3414 {
3415 DMD_ATSC_DEMOD_TYPE eMode;
3416 #if (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_K3)
3417 MS_U8 u8NoisePowerH = 0, u8NoisePowerL = 0;
3418 static MS_U8 u8NoisePowerL_Last = 0xff;
3419 #else
3420 MS_U8 u8NoisePowerH=0;
3421 #endif
3422 static MS_U8 u8NoisePowerH_Last = 0xff;
3423
3424 eMode = _HAL_INTERN_ATSC_Check8VSB64_256QAM();
3425
3426 #if (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_K3)
3427 _MBX_ReadReg(0x2ABE, &u8NoisePowerL); //DVBC_EQ
3428 _MBX_ReadReg(0x2ABF, &u8NoisePowerH);
3429 #else
3430 #if (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MASERATI || DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MACAN \
3431 || DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MAXIM)
3432 _MBX_ReadReg(0x1A15, &u8NoisePowerH);
3433 #else
3434 _MBX_ReadReg(0x2C15, &u8NoisePowerH); //(atsc_eq)
3435 #endif
3436 #endif
3437
3438 if (eMode == DMD_ATSC_DEMOD_ATSC_VSB) //VSB mode//SNR=10*log10((1344<<10)/noisepower)
3439 {
3440 if (!_HAL_INTERN_ATSC_Vsb_FEC_Lock()) u8NoisePowerH=0xFF;
3441 else if (abs(u8NoisePowerH_Last-u8NoisePowerH) > 5)
3442 u8NoisePowerH_Last = u8NoisePowerH;
3443 else u8NoisePowerH = u8NoisePowerH_Last;
3444
3445 if (u8NoisePowerH > 0xBE) //SNR<14.5
3446 *pstatus=DMD_ATSC_SIGNAL_NO;
3447 else if (u8NoisePowerH > 0x4D) //SNR<18.4
3448 *pstatus=DMD_ATSC_SIGNAL_WEAK;
3449 else if (u8NoisePowerH > 0x23) //SNR<21.8
3450 *pstatus=DMD_ATSC_SIGNAL_MODERATE;
3451 else if (u8NoisePowerH > 0x0A) //SNR<26.9
3452 *pstatus=DMD_ATSC_SIGNAL_STRONG;
3453 else
3454 *pstatus=DMD_ATSC_SIGNAL_VERY_STRONG;
3455 }
3456 else //QAM MODE
3457 {
3458 #if (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_K3)
3459 if (!_HAL_INTERN_ATSC_QAM_Main_Lock() || u8NoisePowerH) u8NoisePowerL=0xFF;
3460 else if (abs(u8NoisePowerL_Last-u8NoisePowerL) > 5)
3461 u8NoisePowerL_Last = u8NoisePowerL;
3462 else u8NoisePowerL = u8NoisePowerL_Last;
3463
3464 //SNR=10*log10(65536/noisepower)
3465 if (eMode == DMD_ATSC_DEMOD_ATSC_256QAM)
3466 {
3467 if (u8NoisePowerL > 0x71) //SNR<27.6
3468 *pstatus=DMD_ATSC_SIGNAL_NO;
3469 else if (u8NoisePowerL > 0x31) //SNR<31.2
3470 *pstatus=DMD_ATSC_SIGNAL_WEAK;
3471 else if (u8NoisePowerL > 0x25) //SNR<32.4
3472 *pstatus=DMD_ATSC_SIGNAL_MODERATE;
3473 else if (u8NoisePowerL > 0x17) //SNR<34.4
3474 *pstatus=DMD_ATSC_SIGNAL_STRONG;
3475 else
3476 *pstatus=DMD_ATSC_SIGNAL_VERY_STRONG;
3477 }
3478 else
3479 {
3480 if (u8NoisePowerL > 0x1D) //SNR<21.5
3481 *pstatus=DMD_ATSC_SIGNAL_NO;
3482 else if (u8NoisePowerL > 0x14) //SNR<25.4
3483 *pstatus=DMD_ATSC_SIGNAL_WEAK;
3484 else if (u8NoisePowerL > 0x0F) //SNR<27.8
3485 *pstatus=DMD_ATSC_SIGNAL_MODERATE;
3486 else if (u8NoisePowerL > 0x0B) //SNR<31.4
3487 *pstatus=DMD_ATSC_SIGNAL_STRONG;
3488 else
3489 *pstatus=DMD_ATSC_SIGNAL_VERY_STRONG;
3490 }
3491 #else
3492 if (!_HAL_INTERN_ATSC_QAM_Main_Lock()) u8NoisePowerH=0xFF;
3493 else if (abs(u8NoisePowerH_Last-u8NoisePowerH) > 5)
3494 u8NoisePowerH_Last = u8NoisePowerH;
3495 else u8NoisePowerH = u8NoisePowerH_Last;
3496
3497 if (eMode == DMD_ATSC_DEMOD_ATSC_256QAM) //256QAM//SNR=10*log10((2720<<10)/noisepower)
3498 {
3499 if (u8NoisePowerH > 0x13) //SNR<27.5
3500 *pstatus=DMD_ATSC_SIGNAL_NO;
3501 else if (u8NoisePowerH > 0x08) //SNR<31.2
3502 *pstatus=DMD_ATSC_SIGNAL_WEAK;
3503 else if (u8NoisePowerH > 0x06) //SNR<32.4
3504 *pstatus=DMD_ATSC_SIGNAL_MODERATE;
3505 else if (u8NoisePowerH > 0x04) //SNR<34.2
3506 *pstatus=DMD_ATSC_SIGNAL_STRONG;
3507 else
3508 *pstatus=DMD_ATSC_SIGNAL_VERY_STRONG;
3509 }
3510 else //64QAM//SNR=10*log10((2688<<10)/noisepower)
3511 {
3512 if (u8NoisePowerH > 0x4C) //SNR<21.5
3513 *pstatus=DMD_ATSC_SIGNAL_NO;
3514 else if (u8NoisePowerH > 0x1F) //SNR<25.4
3515 *pstatus=DMD_ATSC_SIGNAL_WEAK;
3516 else if (u8NoisePowerH > 0x11) //SNR<27.8
3517 *pstatus=DMD_ATSC_SIGNAL_MODERATE;
3518 else if (u8NoisePowerH > 0x07) //SNR<31.4
3519 *pstatus=DMD_ATSC_SIGNAL_STRONG;
3520 else
3521 *pstatus=DMD_ATSC_SIGNAL_VERY_STRONG;
3522 }
3523 #endif
3524 }
3525 }
3526
_HAL_INTERN_ATSC_ReadSNRPercentage(void)3527 static MS_U8 _HAL_INTERN_ATSC_ReadSNRPercentage(void)
3528 {
3529 DMD_ATSC_DEMOD_TYPE eMode;
3530 MS_U8 u8NoisePowerH = 0, u8NoisePowerL = 0;
3531 MS_U16 u16NoisePower;
3532
3533 eMode = _HAL_INTERN_ATSC_Check8VSB64_256QAM();
3534
3535 #if (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_K3)
3536 _MBX_ReadReg(0x2ABE, &u8NoisePowerL); //DVBC_EQ
3537 _MBX_ReadReg(0x2ABF, &u8NoisePowerH);
3538 #else
3539 #if (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MASERATI || DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MACAN \
3540 || DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MAXIM)
3541 _MBX_ReadReg(0x1A14, &u8NoisePowerL);
3542 _MBX_ReadReg(0x1A15, &u8NoisePowerH);
3543 #else
3544 _MBX_ReadReg(0x2C14, &u8NoisePowerL); //atsc_eq
3545 _MBX_ReadReg(0x2C15, &u8NoisePowerH);
3546 #endif
3547 #endif
3548
3549 u16NoisePower = (u8NoisePowerH<<8) | u8NoisePowerL;
3550
3551 if (eMode == DMD_ATSC_DEMOD_ATSC_VSB) //VSB mode//SNR=10*log10((1344<<10)/noisepower)
3552 {
3553 if (!_HAL_INTERN_ATSC_Vsb_FEC_Lock())
3554 return 0;//SNR=0;
3555 else if (u16NoisePower<=0x008A)//SNR>=40dB
3556 return 100;//SNR=MAX_SNR;
3557 else if (u16NoisePower<=0x0097)//SNR>=39.6dB
3558 return 99;//
3559 else if (u16NoisePower<=0x00A5)//SNR>=39.2dB
3560 return 98;//
3561 else if (u16NoisePower<=0x00B5)//SNR>=38.8dB
3562 return 97;//
3563 else if (u16NoisePower<=0x00C7)//SNR>=38.4dB
3564 return 96;//
3565 else if (u16NoisePower<=0x00DA)//SNR>=38.0dB
3566 return 95;//
3567 else if (u16NoisePower<=0x00EF)//SNR>=37.6dB
3568 return 94;//
3569 else if (u16NoisePower<=0x0106)//SNR>=37.2dB
3570 return 93;//
3571 else if (u16NoisePower<=0x0120)//SNR>=36.8dB
3572 return 92;//
3573 else if (u16NoisePower<=0x013B)//SNR>=36.4dB
3574 return 91;//
3575 else if (u16NoisePower<=0x015A)//SNR>=36.0dB
3576 return 90;//
3577 else if (u16NoisePower<=0x017B)//SNR>=35.6dB
3578 return 89;//
3579 else if (u16NoisePower<=0x01A0)//SNR>=35.2dB
3580 return 88;//
3581 else if (u16NoisePower<=0x01C8)//SNR>=34.8dB
3582 return 87;//
3583 else if (u16NoisePower<=0x01F4)//SNR>=34.4dB
3584 return 86;//
3585 else if (u16NoisePower<=0x0224)//SNR>=34.0dB
3586 return 85;//
3587 else if (u16NoisePower<=0x0259)//SNR>=33.6dB
3588 return 84;//
3589 else if (u16NoisePower<=0x0293)//SNR>=33.2dB
3590 return 83;//
3591 else if (u16NoisePower<=0x02D2)//SNR>=32.8dB
3592 return 82;//
3593 else if (u16NoisePower<=0x0318)//SNR>=32.4dB
3594 return 81;//
3595 else if (u16NoisePower<=0x0364)//SNR>=32.0dB
3596 return 80;//
3597 else if (u16NoisePower<=0x03B8)//SNR>=31.6dB
3598 return 79;//
3599 else if (u16NoisePower<=0x0414)//SNR>=31.2dB
3600 return 78;//
3601 else if (u16NoisePower<=0x0479)//SNR>=30.8dB
3602 return 77;//
3603 else if (u16NoisePower<=0x04E7)//SNR>=30.4dB
3604 return 76;//
3605 else if (u16NoisePower<=0x0560)//SNR>=30.0dB
3606 return 75;//
3607 else if (u16NoisePower<=0x05E5)//SNR>=29.6dB
3608 return 74;//
3609 else if (u16NoisePower<=0x0677)//SNR>=29.2dB
3610 return 73;//
3611 else if (u16NoisePower<=0x0716)//SNR>=28.8dB
3612 return 72;//
3613 else if (u16NoisePower<=0x07C5)//SNR>=28.4dB
3614 return 71;//
3615 else if (u16NoisePower<=0x0885)//SNR>=28.0dB
3616 return 70;//
3617 else if (u16NoisePower<=0x0958)//SNR>=27.6dB
3618 return 69;//
3619 else if (u16NoisePower<=0x0A3E)//SNR>=27.2dB
3620 return 68;//
3621 else if (u16NoisePower<=0x0B3B)//SNR>=26.8dB
3622 return 67;//
3623 else if (u16NoisePower<=0x0C51)//SNR>=26.4dB
3624 return 66;//
3625 else if (u16NoisePower<=0x0D81)//SNR>=26.0dB
3626 return 65;//
3627 else if (u16NoisePower<=0x0ECF)//SNR>=25.6dB
3628 return 64;//
3629 else if (u16NoisePower<=0x103C)//SNR>=25.2dB
3630 return 63;//
3631 else if (u16NoisePower<=0x11CD)//SNR>=24.8dB
3632 return 62;//
3633 else if (u16NoisePower<=0x1385)//SNR>=24.4dB
3634 return 61;//
3635 else if (u16NoisePower<=0x1567)//SNR>=24.0dB
3636 return 60;//
3637 else if (u16NoisePower<=0x1778)//SNR>=23.6dB
3638 return 59;//
3639 else if (u16NoisePower<=0x19BB)//SNR>=23.2dB
3640 return 58;//
3641 else if (u16NoisePower<=0x1C37)//SNR>=22.8dB
3642 return 57;//
3643 else if (u16NoisePower<=0x1EF0)//SNR>=22.4dB
3644 return 56;//
3645 else if (u16NoisePower<=0x21EC)//SNR>=22.0dB
3646 return 55;//
3647 else if (u16NoisePower<=0x2531)//SNR>=21.6dB
3648 return 54;//
3649 else if (u16NoisePower<=0x28C8)//SNR>=21.2dB
3650 return 53;//
3651 else if (u16NoisePower<=0x2CB7)//SNR>=20.8dB
3652 return 52;//
3653 else if (u16NoisePower<=0x3108)//SNR>=20.4dB
3654 return 51;//
3655 else if (u16NoisePower<=0x35C3)//SNR>=20.0dB
3656 return 50;//
3657 else if (u16NoisePower<=0x3AF2)//SNR>=19.6dB
3658 return 49;//
3659 else if (u16NoisePower<=0x40A2)//SNR>=19.2dB
3660 return 48;//
3661 else if (u16NoisePower<=0x46DF)//SNR>=18.8dB
3662 return 47;//
3663 else if (u16NoisePower<=0x4DB5)//SNR>=18.4dB
3664 return 46;//
3665 else if (u16NoisePower<=0x5534)//SNR>=18.0dB
3666 return 45;//
3667 else if (u16NoisePower<=0x5D6D)//SNR>=17.6dB
3668 return 44;//
3669 else if (u16NoisePower<=0x6670)//SNR>=17.2dB
3670 return 43;//
3671 else if (u16NoisePower<=0x7052)//SNR>=16.8dB
3672 return 42;//
3673 else if (u16NoisePower<=0x7B28)//SNR>=16.4dB
3674 return 41;//
3675 else if (u16NoisePower<=0x870A)//SNR>=16.0dB
3676 return 40;//
3677 else if (u16NoisePower<=0x9411)//SNR>=15.6dB
3678 return 39;//
3679 else if (u16NoisePower<=0xA25A)//SNR>=15.2dB
3680 return 38;//
3681 else if (u16NoisePower<=0xB204)//SNR>=14.8dB
3682 return 37;//
3683 else if (u16NoisePower<=0xC331)//SNR>=14.4dB
3684 return 36;//
3685 else if (u16NoisePower<=0xD606)//SNR>=14.0dB
3686 return 35;//
3687 else if (u16NoisePower<=0xEAAC)//SNR>=13.6dB
3688 return 34;//
3689 else// if (u16NoisePower>=0xEAAC)//SNR<13.6dB
3690 return 33;//
3691 }
3692 else //QAM MODE
3693 {
3694 if( eMode == DMD_ATSC_DEMOD_ATSC_256QAM ) //256QAM//SNR=10*log10((2720<<10)/noisepower)
3695 {
3696 if (!_HAL_INTERN_ATSC_QAM_Main_Lock())
3697 return 0;//SNR=0;
3698 else if (u16NoisePower<=0x0117)//SNR>=40dB
3699 return 100;//
3700 else if (u16NoisePower<=0x0131)//SNR>=39.6dB
3701 return 99;//
3702 else if (u16NoisePower<=0x014F)//SNR>=39.2dB
3703 return 98;//
3704 else if (u16NoisePower<=0x016F)//SNR>=38.8dB
3705 return 97;//
3706 else if (u16NoisePower<=0x0193)//SNR>=38.4dB
3707 return 96;//
3708 else if (u16NoisePower<=0x01B9)//SNR>=38.0dB
3709 return 95;//
3710 else if (u16NoisePower<=0x01E4)//SNR>=37.6dB
3711 return 94;//
3712 else if (u16NoisePower<=0x0213)//SNR>=37.2dB
3713 return 93;//
3714 else if (u16NoisePower<=0x0246)//SNR>=36.8dB
3715 return 92;//
3716 else if (u16NoisePower<=0x027E)//SNR>=36.4dB
3717 return 91;//
3718 else if (u16NoisePower<=0x02BC)//SNR>=36.0dB
3719 return 90;//
3720 else if (u16NoisePower<=0x02FF)//SNR>=35.6dB
3721 return 89;//
3722 else if (u16NoisePower<=0x0349)//SNR>=35.2dB
3723 return 88;//
3724 else if (u16NoisePower<=0x039A)//SNR>=34.8dB
3725 return 87;//
3726 else if (u16NoisePower<=0x03F3)//SNR>=34.4dB
3727 return 86;//
3728 else if (u16NoisePower<=0x0455)//SNR>=34.0dB
3729 return 85;//
3730 else if (u16NoisePower<=0x04C0)//SNR>=33.6dB
3731 return 84;//
3732 else if (u16NoisePower<=0x0535)//SNR>=33.2dB
3733 return 83;//
3734 else if (u16NoisePower<=0x05B6)//SNR>=32.8dB
3735 return 82;//
3736 else if (u16NoisePower<=0x0643)//SNR>=32.4dB
3737 return 81;//
3738 else if (u16NoisePower<=0x06DD)//SNR>=32.0dB
3739 return 80;//
3740 else if (u16NoisePower<=0x0787)//SNR>=31.6dB
3741 return 79;//
3742 else if (u16NoisePower<=0x0841)//SNR>=31.2dB
3743 return 78;//
3744 else if (u16NoisePower<=0x090D)//SNR>=30.8dB
3745 return 77;//
3746 else if (u16NoisePower<=0x09EC)//SNR>=30.4dB
3747 return 76;//
3748 else if (u16NoisePower<=0x0AE1)//SNR>=30.0dB
3749 return 75;//
3750 else if (u16NoisePower<=0x0BEE)//SNR>=29.6dB
3751 return 74;//
3752 else if (u16NoisePower<=0x0D15)//SNR>=29.2dB
3753 return 73;//
3754 else if (u16NoisePower<=0x0E58)//SNR>=28.8dB
3755 return 72;//
3756 else if (u16NoisePower<=0x0FBA)//SNR>=28.4dB
3757 return 71;//
3758 else if (u16NoisePower<=0x113E)//SNR>=28.0dB
3759 return 70;//
3760 else if (u16NoisePower<=0x12E8)//SNR>=27.6dB
3761 return 69;//
3762 else if (u16NoisePower<=0x14BB)//SNR>=27.2dB
3763 return 68;//
3764 else if (u16NoisePower<=0x16BB)//SNR>=26.8dB
3765 return 67;//
3766 else if (u16NoisePower<=0x18ED)//SNR>=26.4dB
3767 return 66;//
3768 else if (u16NoisePower<=0x1B54)//SNR>=26.0dB
3769 return 65;//
3770 else if (u16NoisePower<=0x1DF7)//SNR>=25.6dB
3771 return 64;//
3772 else if (u16NoisePower<=0x20DB)//SNR>=25.2dB
3773 return 63;//
3774 else if (u16NoisePower<=0x2407)//SNR>=24.8dB
3775 return 62;//
3776 else if (u16NoisePower<=0x2781)//SNR>=24.4dB
3777 return 61;//
3778 else if (u16NoisePower<=0x2B50)//SNR>=24.0dB
3779 return 60;//
3780 else if (u16NoisePower<=0x2F7E)//SNR>=23.6dB
3781 return 59;//
3782 else if (u16NoisePower<=0x3413)//SNR>=23.2dB
3783 return 58;//
3784 else if (u16NoisePower<=0x3919)//SNR>=22.8dB
3785 return 57;//
3786 else if (u16NoisePower<=0x3E9C)//SNR>=22.4dB
3787 return 56;//
3788 else if (u16NoisePower<=0x44A6)//SNR>=22.0dB
3789 return 55;//
3790 else if (u16NoisePower<=0x4B45)//SNR>=21.6dB
3791 return 54;//
3792 else if (u16NoisePower<=0x5289)//SNR>=21.2dB
3793 return 53;//
3794 else if (u16NoisePower<=0x5A7F)//SNR>=20.8dB
3795 return 52;//
3796 else if (u16NoisePower<=0x633A)//SNR>=20.4dB
3797 return 51;//
3798 else if (u16NoisePower<=0x6CCD)//SNR>=20.0dB
3799 return 50;//
3800 else if (u16NoisePower<=0x774C)//SNR>=19.6dB
3801 return 49;//
3802 else if (u16NoisePower<=0x82CE)//SNR>=19.2dB
3803 return 48;//
3804 else if (u16NoisePower<=0x8F6D)//SNR>=18.8dB
3805 return 47;//
3806 else if (u16NoisePower<=0x9D44)//SNR>=18.4dB
3807 return 46;//
3808 else if (u16NoisePower<=0xAC70)//SNR>=18.0dB
3809 return 45;//
3810 else if (u16NoisePower<=0xBD13)//SNR>=17.6dB
3811 return 44;//
3812 else if (u16NoisePower<=0xCF50)//SNR>=17.2dB
3813 return 43;//
3814 else if (u16NoisePower<=0xE351)//SNR>=16.8dB
3815 return 42;//
3816 else if (u16NoisePower<=0xF93F)//SNR>=16.4dB
3817 return 41;//
3818 else// if (u16NoisePower>=0xF93F)//SNR<16.4dB
3819 return 40;//
3820 }
3821 else //64QAM//SNR=10*log10((2688<<10)/noisepower)
3822 {
3823 if (!_HAL_INTERN_ATSC_QAM_Main_Lock())
3824 return 0;//SNR=0;
3825 else if (u16NoisePower<=0x0113)//SNR>=40dB
3826 return 100;//
3827 else if (u16NoisePower<=0x012E)//SNR>=39.6dB
3828 return 99;//
3829 else if (u16NoisePower<=0x014B)//SNR>=39.2dB
3830 return 98;//
3831 else if (u16NoisePower<=0x016B)//SNR>=38.8dB
3832 return 97;//
3833 else if (u16NoisePower<=0x018E)//SNR>=38.4dB
3834 return 96;//
3835 else if (u16NoisePower<=0x01B4)//SNR>=38.0dB
3836 return 95;//
3837 else if (u16NoisePower<=0x01DE)//SNR>=37.6dB
3838 return 94;//
3839 else if (u16NoisePower<=0x020C)//SNR>=37.2dB
3840 return 93;//
3841 else if (u16NoisePower<=0x023F)//SNR>=36.8dB
3842 return 92;//
3843 else if (u16NoisePower<=0x0277)//SNR>=36.4dB
3844 return 91;//
3845 else if (u16NoisePower<=0x02B3)//SNR>=36.0dB
3846 return 90;//
3847 else if (u16NoisePower<=0x02F6)//SNR>=35.6dB
3848 return 89;//
3849 else if (u16NoisePower<=0x033F)//SNR>=35.2dB
3850 return 88;//
3851 else if (u16NoisePower<=0x038F)//SNR>=34.8dB
3852 return 87;//
3853 else if (u16NoisePower<=0x03E7)//SNR>=34.4dB
3854 return 86;//
3855 else if (u16NoisePower<=0x0448)//SNR>=34.0dB
3856 return 85;//
3857 else if (u16NoisePower<=0x04B2)//SNR>=33.6dB
3858 return 84;//
3859 else if (u16NoisePower<=0x0525)//SNR>=33.2dB
3860 return 83;//
3861 else if (u16NoisePower<=0x05A5)//SNR>=32.8dB
3862 return 82;//
3863 else if (u16NoisePower<=0x0630)//SNR>=32.4dB
3864 return 81;//
3865 else if (u16NoisePower<=0x06C9)//SNR>=32.0dB
3866 return 80;//
3867 else if (u16NoisePower<=0x0770)//SNR>=31.6dB
3868 return 79;//
3869 else if (u16NoisePower<=0x0828)//SNR>=31.2dB
3870 return 78;//
3871 else if (u16NoisePower<=0x08F1)//SNR>=30.8dB
3872 return 77;//
3873 else if (u16NoisePower<=0x09CE)//SNR>=30.4dB
3874 return 76;//
3875 else if (u16NoisePower<=0x0AC1)//SNR>=30.0dB
3876 return 75;//
3877 else if (u16NoisePower<=0x0BCA)//SNR>=29.6dB
3878 return 74;//
3879 else if (u16NoisePower<=0x0CED)//SNR>=29.2dB
3880 return 73;//
3881 else if (u16NoisePower<=0x0E2D)//SNR>=28.8dB
3882 return 72;//
3883 else if (u16NoisePower<=0x0F8B)//SNR>=28.4dB
3884 return 71;//
3885 else if (u16NoisePower<=0x110A)//SNR>=28.0dB
3886 return 70;//
3887 else if (u16NoisePower<=0x12AF)//SNR>=27.6dB
3888 return 69;//
3889 else if (u16NoisePower<=0x147D)//SNR>=27.2dB
3890 return 68;//
3891 else if (u16NoisePower<=0x1677)//SNR>=26.8dB
3892 return 67;//
3893 else if (u16NoisePower<=0x18A2)//SNR>=26.4dB
3894 return 66;//
3895 else if (u16NoisePower<=0x1B02)//SNR>=26.0dB
3896 return 65;//
3897 else if (u16NoisePower<=0x1D9D)//SNR>=25.6dB
3898 return 64;//
3899 else if (u16NoisePower<=0x2078)//SNR>=25.2dB
3900 return 63;//
3901 else if (u16NoisePower<=0x239A)//SNR>=24.8dB
3902 return 62;//
3903 else if (u16NoisePower<=0x270A)//SNR>=24.4dB
3904 return 61;//
3905 else if (u16NoisePower<=0x2ACE)//SNR>=24.0dB
3906 return 60;//
3907 else if (u16NoisePower<=0x2EEF)//SNR>=23.6dB
3908 return 59;//
3909 else if (u16NoisePower<=0x3376)//SNR>=23.2dB
3910 return 58;//
3911 else if (u16NoisePower<=0x386D)//SNR>=22.8dB
3912 return 57;//
3913 else if (u16NoisePower<=0x3DDF)//SNR>=22.4dB
3914 return 56;//
3915 else if (u16NoisePower<=0x43D7)//SNR>=22.0dB
3916 return 55;//
3917 else if (u16NoisePower<=0x4A63)//SNR>=21.6dB
3918 return 54;//
3919 else if (u16NoisePower<=0x5190)//SNR>=21.2dB
3920 return 53;//
3921 else if (u16NoisePower<=0x596E)//SNR>=20.8dB
3922 return 52;//
3923 else if (u16NoisePower<=0x620F)//SNR>=20.4dB
3924 return 51;//
3925 else if (u16NoisePower<=0x6B85)//SNR>=20.0dB
3926 return 50;//
3927 else if (u16NoisePower<=0x75E5)//SNR>=19.6dB
3928 return 49;//
3929 else if (u16NoisePower<=0x8144)//SNR>=19.2dB
3930 return 48;//
3931 else if (u16NoisePower<=0x8DBD)//SNR>=18.8dB
3932 return 47;//
3933 else if (u16NoisePower<=0x9B6A)//SNR>=18.4dB
3934 return 46;//
3935 else if (u16NoisePower<=0xAA68)//SNR>=18.0dB
3936 return 45;//
3937 else if (u16NoisePower<=0xBAD9)//SNR>=17.6dB
3938 return 44;//
3939 else if (u16NoisePower<=0xCCE0)//SNR>=17.2dB
3940 return 43;//
3941 else if (u16NoisePower<=0xE0A4)//SNR>=16.8dB
3942 return 42;//
3943 else if (u16NoisePower<=0xF650)//SNR>=16.4dB
3944 return 41;//
3945 else// if (u16NoisePower>=0xF650)//SNR<16.4dB
3946 return 40;//
3947 }
3948 }
3949 }
3950
3951 #ifdef UTPA2
_HAL_INTERN_ATSC_GET_QAM_SNR(MS_U16 * pNoisepower,MS_U32 * pSym_num)3952 static MS_BOOL _HAL_INTERN_ATSC_GET_QAM_SNR(MS_U16 *pNoisepower, MS_U32 *pSym_num)
3953 #else
3954 static MS_BOOL _HAL_INTERN_ATSC_GET_QAM_SNR(float *f_snr)
3955 #endif
3956 {
3957 MS_U8 u8Data = 0;
3958 MS_U16 noisepower = 0;
3959
3960 if (_HAL_INTERN_ATSC_QAM_Main_Lock())
3961 {
3962 // latch
3963 _MBX_WriteReg(0x2905, 0x80);
3964 // read noise power
3965 _MBX_ReadReg(0x2A45, &u8Data);
3966 noisepower = u8Data;
3967 _MBX_ReadReg(0x2A44, &u8Data);
3968 noisepower = (noisepower<<8)|u8Data;
3969 // unlatch
3970 _MBX_WriteReg(0x2905, 0x00);
3971
3972 if (noisepower == 0x0000)
3973 noisepower = 0x0001;
3974
3975 #ifdef UTPA2
3976 *pNoisepower = noisepower;
3977 *pSym_num = 65536;
3978 #else
3979 #ifdef MSOS_TYPE_LINUX
3980 *f_snr = 10.0f*log10f(65536.0f/(float)noisepower);
3981 #else
3982 *f_snr = 10.0f*Log10Approx(65536.0f/(float)noisepower);
3983 #endif
3984 #endif
3985 }
3986 else
3987 {
3988 #ifdef UTPA2
3989 *pNoisepower = 0;
3990 *pSym_num = 0;
3991 #else
3992 *f_snr = 0.0f;
3993 #endif
3994 }
3995
3996 return TRUE;
3997 }
3998
_HAL_INTERN_ATSC_ReadPKTERR(void)3999 static MS_U16 _HAL_INTERN_ATSC_ReadPKTERR(void)
4000 {
4001 MS_U16 data = 0;
4002 MS_U8 reg = 0;
4003 DMD_ATSC_DEMOD_TYPE eMode;
4004
4005 eMode = _HAL_INTERN_ATSC_Check8VSB64_256QAM();
4006
4007 if (eMode == DMD_ATSC_DEMOD_ATSC_VSB)
4008 {
4009 if (!_HAL_INTERN_ATSC_Vsb_FEC_Lock()) data = 0;
4010 else
4011 {
4012 #if (DMD_ATSC_CHIP_VERSION < DMD_ATSC_CHIP_A1)
4013 _MBX_ReadReg(0x2B20, ®);
4014 data = reg;
4015 _MBX_ReadReg(0x2B21, ®);
4016 data = (data << 8)|reg;
4017 #else
4018 _MBX_ReadReg(0x1F67, ®);
4019 data = reg;
4020 _MBX_ReadReg(0x1F66, ®);
4021 data = (data << 8)|reg;
4022 #endif
4023 }
4024 }
4025 else
4026 {
4027 if (!_HAL_INTERN_ATSC_QAM_Main_Lock()) data = 0;
4028 else
4029 {
4030 #if (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_K3)
4031 _MBX_ReadReg(0x2166, ®);
4032 data = reg;
4033 _MBX_ReadReg(0x2167, ®);
4034 data = (data << 8)|reg;
4035 #elif (DMD_ATSC_CHIP_VERSION < DMD_ATSC_CHIP_A1)
4036 _MBX_ReadReg(0x2B20, ®);
4037 data = reg;
4038 _MBX_ReadReg(0x2B21, ®);
4039 data = (data << 8)|reg;
4040 #else
4041 _MBX_ReadReg(0x1F66, ®);
4042 data = reg;
4043 _MBX_ReadReg(0x1F67, ®);
4044 data = (data << 8)|reg;
4045 #endif
4046 }
4047 }
4048
4049 return data;
4050 }
4051
4052 #ifdef UTPA2
_HAL_INTERN_ATSC_ReadBER(MS_U32 * pBitErr,MS_U16 * pError_window,MS_U32 * pWin_unit)4053 static MS_BOOL _HAL_INTERN_ATSC_ReadBER(MS_U32 *pBitErr, MS_U16 *pError_window, MS_U32 *pWin_unit)
4054 #else
4055 static MS_BOOL _HAL_INTERN_ATSC_ReadBER(float *pBer)
4056 #endif
4057 {
4058 MS_BOOL status = true;
4059 MS_U8 reg = 0, reg_frz = 0;
4060 MS_U16 BitErrPeriod;
4061 MS_U32 BitErr;
4062 DMD_ATSC_DEMOD_TYPE eMode;
4063
4064 eMode = _HAL_INTERN_ATSC_Check8VSB64_256QAM();
4065
4066 if (eMode == DMD_ATSC_DEMOD_ATSC_VSB)
4067 {
4068 if (!_HAL_INTERN_ATSC_Vsb_FEC_Lock())
4069 {
4070 #ifdef UTPA2
4071 *pBitErr = 0;
4072 *pError_window = 0;
4073 *pWin_unit = 0;
4074 #else
4075 *pBer = 0;
4076 #endif
4077 }
4078 else
4079 {
4080 _MBX_ReadReg(0x1F03, ®_frz);
4081 _MBX_WriteReg(0x1F03, reg_frz|0x03);
4082
4083 _MBX_ReadReg(0x1F47, ®);
4084 BitErrPeriod = reg;
4085 _MBX_ReadReg(0x1F46, ®);
4086 BitErrPeriod = (BitErrPeriod << 8)|reg;
4087
4088 status &= _MBX_ReadReg(0x1F6d, ®);
4089 BitErr = reg;
4090 status &= _MBX_ReadReg(0x1F6c, ®);
4091 BitErr = (BitErr << 8)|reg;
4092 status &= _MBX_ReadReg(0x1F6b, ®);
4093 BitErr = (BitErr << 8)|reg;
4094 status &= _MBX_ReadReg(0x1F6a, ®);
4095 BitErr = (BitErr << 8)|reg;
4096
4097 reg_frz=reg_frz&(~0x03);
4098 _MBX_WriteReg(0x1F03, reg_frz);
4099
4100 if (BitErrPeriod == 0 ) //protect 0
4101 BitErrPeriod = 1;
4102
4103 #ifdef UTPA2
4104 *pBitErr = BitErr;
4105 *pError_window = BitErrPeriod;
4106 *pWin_unit = 8*187*128;
4107 #else
4108 if (BitErr <=0 )
4109 *pBer = 0.5f / ((float)BitErrPeriod*8*187*128);
4110 else
4111 *pBer = (float)BitErr / ((float)BitErrPeriod*8*187*128);
4112 #endif
4113 }
4114 }
4115 else
4116 {
4117 if (!_HAL_INTERN_ATSC_QAM_Main_Lock())
4118 {
4119 #ifdef UTPA2
4120 *pBitErr = 0;
4121 *pError_window = 0;
4122 *pWin_unit = 0;
4123 #else
4124 *pBer = 0;
4125 #endif
4126 }
4127 else
4128 {
4129 #if (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_K3)
4130 _MBX_ReadReg(0x2103, ®_frz);
4131 _MBX_WriteReg(0x2103, reg_frz|0x03);
4132
4133 _MBX_ReadReg(0x2147, ®);
4134 BitErrPeriod = reg;
4135 _MBX_ReadReg(0x2146, ®);
4136 BitErrPeriod = (BitErrPeriod << 8)|reg;
4137
4138 status &= _MBX_ReadReg(0x216d, ®);
4139 BitErr = reg;
4140 status &= _MBX_ReadReg(0x216c, ®);
4141 BitErr = (BitErr << 8)|reg;
4142 status &= _MBX_ReadReg(0x216b, ®);
4143 BitErr = (BitErr << 8)|reg;
4144 status &= _MBX_ReadReg(0x216a, ®);
4145 BitErr = (BitErr << 8)|reg;
4146
4147 reg_frz=reg_frz&(~0x03);
4148 _MBX_WriteReg(0x2103, reg_frz);
4149
4150 if (BitErrPeriod == 0) //protect 0
4151 BitErrPeriod = 1;
4152
4153 #ifdef UTPA2
4154 *pBitErr = BitErr;
4155 *pError_window = BitErrPeriod;
4156 *pWin_unit = 8*188*128;
4157 #else
4158 if (BitErr <=0)
4159 *pBer = 0.5f / ((float)BitErrPeriod*8*188*128);
4160 else
4161 *pBer = (float)BitErr / ((float)BitErrPeriod*8*188*128);
4162 #endif
4163 #else // #if (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_K3)
4164 _MBX_ReadReg(0x1F03, ®_frz);
4165 _MBX_WriteReg(0x1F03, reg_frz|0x03);
4166
4167 _MBX_ReadReg(0x1F47, ®);
4168 BitErrPeriod = reg;
4169 _MBX_ReadReg(0x1F46, ®);
4170 BitErrPeriod = (BitErrPeriod << 8)|reg;
4171
4172 BitErr = reg;
4173 status &= _MBX_ReadReg(0x1F6c, ®);
4174 BitErr = (BitErr << 8)|reg;
4175 status &= _MBX_ReadReg(0x1F6b, ®);
4176 BitErr = (BitErr << 8)|reg;
4177 status &= _MBX_ReadReg(0x1F6a, ®);
4178 BitErr = (BitErr << 8)|reg;
4179
4180 reg_frz=reg_frz&(~0x03);
4181 _MBX_WriteReg(0x1F03, reg_frz);
4182
4183 if (BitErrPeriod == 0 ) //protect 0
4184 BitErrPeriod = 1;
4185
4186 #ifdef UTPA2
4187 *pBitErr = BitErr;
4188 *pError_window = BitErrPeriod;
4189 *pWin_unit = 7*122*128;
4190 #else
4191 if (BitErr <=0 )
4192 *pBer = 0.5f / ((float)BitErrPeriod*7*122*128);
4193 else
4194 *pBer = (float)BitErr / ((float)BitErrPeriod*7*122*128);
4195 #endif
4196 #endif // #if (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_K3)
4197 }
4198 }
4199
4200 return status;
4201 }
4202
4203 #ifdef UTPA2
_HAL_INTERN_ATSC_ReadFrequencyOffset(MS_U8 * pMode,MS_S16 * pFF,MS_S16 * pRate)4204 static MS_BOOL _HAL_INTERN_ATSC_ReadFrequencyOffset(MS_U8 *pMode, MS_S16 *pFF, MS_S16 *pRate)
4205 #else
4206 static MS_S16 _HAL_INTERN_ATSC_ReadFrequencyOffset(void)
4207 #endif
4208 {
4209 DMD_ATSC_DEMOD_TYPE eMode;
4210 MS_U8 u8PTK_LOOP_FF_R3=0, u8PTK_LOOP_FF_R2=0;
4211 MS_U8 u8PTK_RATE_2=0;
4212 MS_U8 u8AD_CRL_LOOP_VALUE0=0, u8AD_CRL_LOOP_VALUE1=0;
4213 MS_U8 u8MIX_RATE_0=0, u8MIX_RATE_1=0, u8MIX_RATE_2=0;
4214 MS_S16 PTK_LOOP_FF;
4215 MS_S16 AD_CRL_LOOP_VALUE;
4216 MS_S16 MIX_RATE;
4217 #ifndef UTPA2
4218 MS_S16 FreqOffset = 0; //kHz
4219 #endif
4220
4221 eMode = _HAL_INTERN_ATSC_Check8VSB64_256QAM();
4222
4223 #ifdef UTPA2
4224 *pMode = eMode;
4225 #endif
4226
4227 if (eMode == DMD_ATSC_DEMOD_ATSC_VSB) //VSB mode//
4228 {
4229 #if (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MASERATI || DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MACAN \
4230 || DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MAXIM)
4231 _MBX_WriteReg(0x177E, 0x01);
4232 _MBX_WriteReg(0x17E6, 0xff);
4233 _MBX_ReadReg(0x177C, &u8PTK_LOOP_FF_R2);
4234 _MBX_ReadReg(0x177D, &u8PTK_LOOP_FF_R3);
4235 _MBX_WriteReg(0x177E, 0x00);
4236 _MBX_WriteReg(0x17E6, 0xff);
4237 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MUSTANG)
4238 _MBX_WriteReg(0x047E, 0x01); //atsc_dmd
4239 _MBX_WriteReg(0x04E6, 0xff);
4240 _MBX_ReadReg(0x047C, &u8PTK_LOOP_FF_R2);
4241 _MBX_ReadReg(0x047D, &u8PTK_LOOP_FF_R3);
4242 _MBX_WriteReg(0x047E, 0x00);
4243 _MBX_WriteReg(0x04E6, 0xff);
4244 #else
4245 _MBX_WriteReg(0x297E, 0x01);
4246 _MBX_WriteReg(0x29E6, 0xff);
4247 _MBX_ReadReg(0x297C, &u8PTK_LOOP_FF_R2);
4248 _MBX_ReadReg(0x297D, &u8PTK_LOOP_FF_R3);
4249 _MBX_WriteReg(0x297E, 0x00);
4250 _MBX_WriteReg(0x29E6, 0xff);
4251 #endif
4252
4253 PTK_LOOP_FF = (u8PTK_LOOP_FF_R3<<8) | u8PTK_LOOP_FF_R2;
4254 #ifdef UTPA2
4255 *pFF = PTK_LOOP_FF;
4256 #else
4257 FreqOffset = (float)(-PTK_LOOP_FF*0.04768);
4258 #endif
4259
4260 #if (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MASERATI || DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MACAN \
4261 || DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MAXIM)
4262 _MBX_ReadReg(0x1782, &u8PTK_RATE_2);
4263 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MUSTANG)
4264 _MBX_ReadReg(0x0482, &u8PTK_RATE_2); //atsc_dmd
4265 #else
4266 _MBX_ReadReg(0x2982, &u8PTK_RATE_2);
4267 #endif
4268
4269 #ifdef UTPA2
4270 *pRate = u8PTK_RATE_2;
4271 #else
4272 if (u8PTK_RATE_2 == 0x07)
4273 FreqOffset = FreqOffset-100;
4274 else if (u8PTK_RATE_2 == 0x08)
4275 FreqOffset = FreqOffset-500;
4276 #endif
4277 }
4278 else //QAM MODE
4279 {
4280 #if (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_K3)
4281 _MBX_ReadReg(0x2A40, &u8AD_CRL_LOOP_VALUE0);
4282 _MBX_ReadReg(0x2A41, &u8AD_CRL_LOOP_VALUE1);
4283 _MBX_ReadReg(0x2758, &u8MIX_RATE_0);
4284 _MBX_ReadReg(0x2759, &u8MIX_RATE_1);
4285 _MBX_ReadReg(0x275A, &u8MIX_RATE_2);
4286
4287 AD_CRL_LOOP_VALUE = (u8AD_CRL_LOOP_VALUE1 << 8) | u8AD_CRL_LOOP_VALUE0;
4288 MIX_RATE = ((u8MIX_RATE_2 << 16) | (u8MIX_RATE_1 << 8) | u8MIX_RATE_0) >> 4;
4289
4290 #ifdef UTPA2
4291 *pMode |= 0x80;
4292 *pFF = AD_CRL_LOOP_VALUE;
4293 *pRate = MIX_RATE;
4294 #else
4295 if (eMode == DMD_ATSC_DEMOD_ATSC_256QAM) //256QAM//
4296 {
4297 FreqOffset = (float)(AD_CRL_LOOP_VALUE*0.0000199); //5.360537E6/2^28*1000
4298 }
4299 else if (eMode == DMD_ATSC_DEMOD_ATSC_64QAM)//64QAM//
4300 {
4301 FreqOffset = (float)(AD_CRL_LOOP_VALUE*0.0000188); //5.056941E6/2^21*1000
4302 }
4303
4304 FreqOffset = FreqOffset+(float)(MIX_RATE-0x3A07)/330.13018; //(0.001/25.41*2^27/16)???
4305 #endif
4306 #else // #if (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_K3)
4307 #if (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MASERATI || DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MACAN \
4308 || DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MAXIM)
4309 _MBX_ReadReg(0x1A04, &u8AD_CRL_LOOP_VALUE0);
4310 _MBX_ReadReg(0x1A05, &u8AD_CRL_LOOP_VALUE1);
4311 #else
4312 _MBX_ReadReg(0x2C04, &u8AD_CRL_LOOP_VALUE0);
4313 _MBX_ReadReg(0x2C05, &u8AD_CRL_LOOP_VALUE1);
4314 #endif
4315
4316 AD_CRL_LOOP_VALUE = (u8AD_CRL_LOOP_VALUE1<<8) | u8AD_CRL_LOOP_VALUE0;
4317
4318 #if (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MASERATI || DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MACAN \
4319 || DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MAXIM)
4320 _MBX_ReadReg(0x1704, &u8MIX_RATE_0);
4321 _MBX_ReadReg(0x1705, &u8MIX_RATE_1);
4322 _MBX_ReadReg(0x1706, &u8MIX_RATE_2);
4323 #elif (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_MUSTANG)
4324 _MBX_ReadReg(0x0404, &u8MIX_RATE_0); //atsc_dmd
4325 _MBX_ReadReg(0x0405, &u8MIX_RATE_1);
4326 _MBX_ReadReg(0x0406, &u8MIX_RATE_2);
4327 #else
4328 _MBX_ReadReg(0x2904, &u8MIX_RATE_0);
4329 _MBX_ReadReg(0x2905, &u8MIX_RATE_1);
4330 _MBX_ReadReg(0x2906, &u8MIX_RATE_2);
4331 #endif
4332
4333 MIX_RATE = (u8MIX_RATE_2<<12)|(u8MIX_RATE_1<<4)|(u8MIX_RATE_0>>4);
4334
4335 #ifdef UTPA2
4336 *pFF = AD_CRL_LOOP_VALUE;
4337 *pRate = MIX_RATE;
4338 #else
4339 if (eMode == DMD_ATSC_DEMOD_ATSC_256QAM) //256QAM//
4340 {
4341 FreqOffset = (float)(AD_CRL_LOOP_VALUE*0.0025561); //5.360537E6/2^21*1000
4342 }
4343 else if (eMode == DMD_ATSC_DEMOD_ATSC_64QAM)//64QAM//
4344 {
4345 FreqOffset = (float)(AD_CRL_LOOP_VALUE*0.00241134); //5.056941E6/2^21*1000
4346 }
4347
4348 FreqOffset = FreqOffset+(float)(MIX_RATE-0x3D70)/2.62144; //(0.001/25*2^20/16)
4349 #endif
4350 #endif // #if (DMD_ATSC_CHIP_VERSION >= DMD_ATSC_CHIP_K3)
4351 }
4352
4353 #ifdef UTPA2
4354 return TRUE;
4355 #else
4356 return FreqOffset;
4357 #endif
4358 }
4359
_HAL_INTERN_ATSC_GetReg(MS_U16 u16Addr,MS_U8 * pu8Data)4360 static MS_BOOL _HAL_INTERN_ATSC_GetReg(MS_U16 u16Addr, MS_U8 *pu8Data)
4361 {
4362 return _MBX_ReadReg(u16Addr, pu8Data);
4363 }
4364
_HAL_INTERN_ATSC_SetReg(MS_U16 u16Addr,MS_U8 u8Data)4365 static MS_BOOL _HAL_INTERN_ATSC_SetReg(MS_U16 u16Addr, MS_U8 u8Data)
4366 {
4367 return _MBX_WriteReg(u16Addr, u8Data);
4368 }
4369
4370 //-------------------------------------------------------------------------------------------------
4371 // Global Functions
4372 //-------------------------------------------------------------------------------------------------
HAL_INTERN_ATSC_IOCTL_CMD(DMD_ATSC_HAL_COMMAND eCmd,void * pArgs)4373 MS_BOOL HAL_INTERN_ATSC_IOCTL_CMD(DMD_ATSC_HAL_COMMAND eCmd, void *pArgs)
4374 {
4375 MS_BOOL bResult = TRUE;
4376
4377 #if (DMD_ATSC_CHIP_VERSION == DMD_ATSC_CHIP_K3)
4378 _SEL_DMD();
4379 #endif
4380
4381 switch(eCmd)
4382 {
4383 case DMD_ATSC_HAL_CMD_Exit:
4384 bResult = _HAL_INTERN_ATSC_Exit();
4385 break;
4386 case DMD_ATSC_HAL_CMD_InitClk:
4387 _HAL_INTERN_ATSC_InitClk(false);
4388 break;
4389 case DMD_ATSC_HAL_CMD_Download:
4390 bResult = _HAL_INTERN_ATSC_Download();
4391 break;
4392 case DMD_ATSC_HAL_CMD_FWVERSION:
4393 _HAL_INTERN_ATSC_FWVERSION();
4394 break;
4395 case DMD_ATSC_HAL_CMD_SoftReset:
4396 bResult = _HAL_INTERN_ATSC_SoftReset();
4397 break;
4398 case DMD_ATSC_HAL_CMD_SetVsbMode:
4399 bResult = _HAL_INTERN_ATSC_SetVsbMode();
4400 break;
4401 case DMD_ATSC_HAL_CMD_Set64QamMode:
4402 bResult = _HAL_INTERN_ATSC_Set64QamMode();
4403 break;
4404 case DMD_ATSC_HAL_CMD_Set256QamMode:
4405 bResult = _HAL_INTERN_ATSC_Set256QamMode();
4406 break;
4407 case DMD_ATSC_HAL_CMD_SetModeClean:
4408 bResult = _HAL_INTERN_ATSC_SetModeClean();
4409 break;
4410 case DMD_ATSC_HAL_CMD_Set_QAM_SR:
4411 break;
4412 case DMD_ATSC_HAL_CMD_Active:
4413 break;
4414 case DMD_ATSC_HAL_CMD_Check8VSB64_256QAM:
4415 *((DMD_ATSC_DEMOD_TYPE *)pArgs) = _HAL_INTERN_ATSC_Check8VSB64_256QAM();
4416 break;
4417 case DMD_ATSC_HAL_CMD_AGCLock:
4418 bResult = _HAL_INTERN_ATSC_Vsb_QAM_AGCLock();
4419 break;
4420 case DMD_ATSC_HAL_CMD_Vsb_PreLock:
4421 bResult = _HAL_INTERN_ATSC_Vsb_PreLock();
4422 break;
4423 case DMD_ATSC_HAL_CMD_Vsb_FSync_Lock:
4424 bResult = _HAL_INTERN_ATSC_Vsb_FSync_Lock();
4425 break;
4426 case DMD_ATSC_HAL_CMD_Vsb_CE_Lock:
4427 bResult = _HAL_INTERN_ATSC_Vsb_CE_Lock();
4428 break;
4429 case DMD_ATSC_HAL_CMD_Vsb_FEC_Lock:
4430 bResult = _HAL_INTERN_ATSC_Vsb_FEC_Lock();
4431 break;
4432 case DMD_ATSC_HAL_CMD_QAM_PreLock:
4433 bResult = _HAL_INTERN_ATSC_QAM_PreLock();
4434 break;
4435 case DMD_ATSC_HAL_CMD_QAM_Main_Lock:
4436 bResult = _HAL_INTERN_ATSC_QAM_Main_Lock();
4437 break;
4438 case DMD_ATSC_HAL_CMD_ReadIFAGC:
4439 *((MS_U16 *)pArgs) = _HAL_INTERN_ATSC_ReadIFAGC();
4440 break;
4441 case DMD_ATSC_HAL_CMD_CheckSignalCondition:
4442 _HAL_INTERN_ATSC_CheckSignalCondition((DMD_ATSC_SIGNAL_CONDITION *)pArgs);
4443 break;
4444 case DMD_ATSC_HAL_CMD_ReadSNRPercentage:
4445 *((MS_U8 *)pArgs) = _HAL_INTERN_ATSC_ReadSNRPercentage();
4446 break;
4447 case DMD_ATSC_HAL_CMD_GET_QAM_SNR:
4448 #ifdef UTPA2
4449 bResult = _HAL_INTERN_ATSC_GET_QAM_SNR(&((*((DMD_ATSC_SNR_DATA *)pArgs)).noisepower), &((*((DMD_ATSC_SNR_DATA *)pArgs)).sym_num));
4450 #else
4451 bResult = _HAL_INTERN_ATSC_GET_QAM_SNR((float *)pArgs);
4452 #endif
4453 break;
4454 case DMD_ATSC_HAL_CMD_ReadPKTERR:
4455 *((MS_U16 *)pArgs) = _HAL_INTERN_ATSC_ReadPKTERR();
4456 break;
4457 case DMD_ATSC_HAL_CMD_GetPreViterbiBer:
4458 break;
4459 case DMD_ATSC_HAL_CMD_GetPostViterbiBer:
4460 #ifdef UTPA2
4461 bResult = _HAL_INTERN_ATSC_ReadBER(&((*((DMD_ATSC_BER_DATA *)pArgs)).BitErr), &((*((DMD_ATSC_BER_DATA *)pArgs)).Error_window), &((*((DMD_ATSC_BER_DATA *)pArgs)).Win_unit));
4462 #else
4463 bResult = _HAL_INTERN_ATSC_ReadBER((float *)pArgs);
4464 #endif
4465 break;
4466 case DMD_ATSC_HAL_CMD_ReadFrequencyOffset:
4467 #ifdef UTPA2
4468 bResult = _HAL_INTERN_ATSC_ReadFrequencyOffset(&((*((DMD_ATSC_CFO_DATA *)pArgs)).Mode), &((*((DMD_ATSC_CFO_DATA *)pArgs)).FF), &((*((DMD_ATSC_CFO_DATA *)pArgs)).Rate));
4469 #else
4470 *((MS_S16 *)pArgs) = _HAL_INTERN_ATSC_ReadFrequencyOffset();
4471 #endif
4472 break;
4473 case DMD_ATSC_HAL_CMD_TS_INTERFACE_CONFIG:
4474 break;
4475 case DMD_ATSC_HAL_CMD_IIC_Bypass_Mode:
4476 break;
4477 case DMD_ATSC_HAL_CMD_SSPI_TO_GPIO:
4478 break;
4479 case DMD_ATSC_HAL_CMD_GPIO_GET_LEVEL:
4480 break;
4481 case DMD_ATSC_HAL_CMD_GPIO_SET_LEVEL:
4482 break;
4483 case DMD_ATSC_HAL_CMD_GPIO_OUT_ENABLE:
4484 break;
4485 case DMD_ATSC_HAL_CMD_GET_REG:
4486 bResult = _HAL_INTERN_ATSC_GetReg((*((DMD_ATSC_REG_DATA *)pArgs)).u16Addr, &((*((DMD_ATSC_REG_DATA *)pArgs)).u8Data));
4487 break;
4488 case DMD_ATSC_HAL_CMD_SET_REG:
4489 bResult = _HAL_INTERN_ATSC_SetReg((*((DMD_ATSC_REG_DATA *)pArgs)).u16Addr, (*((DMD_ATSC_REG_DATA *)pArgs)).u8Data);
4490 break;
4491 default:
4492 break;
4493 }
4494
4495 return bResult;
4496 }
4497
MDrv_DMD_ATSC_Initial_Hal_Interface(void)4498 MS_BOOL MDrv_DMD_ATSC_Initial_Hal_Interface(void)
4499 {
4500 return TRUE;
4501 }
4502