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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 #ifndef _INTERN_DVBT2_H_ 96 #define _INTERN_DVBT2_H_ 97 98 #ifdef _INTERN_DVBT2_C_ 99 #define EXTSEL 100 #else 101 #define EXTSEL extern 102 #endif 103 104 105 //-------------------------------------------------------------------- 106 107 // #define DEMOD_DYNAMIC_SLAVE_ID_1 0x32 108 // #define DEMOD_DYNAMIC_SLAVE_ID_2 0x72 109 // #define DEMOD_DYNAMIC_SLAVE_ID_3 0xB2 110 // #define DEMOD_DYNAMIC_SLAVE_ID_4 0xF2 111 112 #define DEMOD_ADDR_H 0x00 113 #define DEMOD_ADDR_L 0x01 114 #define DEMOD_WRITE_REG 0x02 115 #define DEMOD_WRITE_REG_EX 0x03 116 #define DEMOD_READ_REG 0x04 117 #define DEMOD_RAM_CONTROL 0x05 118 119 #if 0//DTV_SCAN_AUTO_FINE_TUNE_ENABLE 120 //INTERN_DVBT2_ Capture Range fix to 500K 121 #define DEMOD_CAPTURE_RANGE_500_K 500 122 #define DEMOD_CAPTURE_RANGE_SIZE DEMOD_CAPTURE_RANGE_500_K 123 #endif 124 125 #define MDrv_ReadByte(x) HAL_DMD_RIU_ReadByte(x) 126 #define MDrv_WriteByte(x,y) HAL_DMD_RIU_WriteByte(x,y) 127 128 #if 1 129 #define U8 MAPI_U8 130 #define U16 MAPI_U16 131 #define U32 MAPI_U32 132 #define BOOL MAPI_BOOL 133 #define BOOLEAN MAPI_BOOL 134 #if 0 135 #define BIT0 0x01 136 #define BIT1 0x02 137 #define BIT2 0x04 138 #define BIT3 0x08 139 #define BIT4 0x10 140 #define BIT5 0x20 141 #define BIT6 0x40 142 #define BIT7 0x80 143 #endif 144 #define BYTE MAPI_U8 145 146 #define WORD MAPI_WORD 147 #define E_RESULT_SUCCESS MAPI_TRUE 148 #define E_RESULT_FAILURE MAPI_FALSE 149 #define FUNCTION_RESULT MAPI_BOOL 150 151 152 153 154 #define INTERN_DVBT2_TS_SERIAL_INVERSION 0 155 #define INTERN_DVBT2_TS_PARALLEL_INVERSION 1 156 #define INTERN_DVBT2_DTV_DRIVING_LEVEL 1 157 #define INTERN_DVBT2_WEAK_SIGNAL_PICTURE_FREEZE_ENABLE 1 158 #endif 159 160 161 //-------------------------------------------------------------------- 162 typedef enum 163 { 164 E_SYS_UNKOWN = -1, 165 E_SYS_DVBT, 166 E_SYS_DVBC, 167 E_SYS_ATSC, 168 E_SYS_VIF, 169 E_SYS_DVBT2, 170 171 E_SYS_NUM 172 }E_SYSTEM; 173 174 typedef enum 175 { 176 CMD_SYSTEM_INIT = 0, 177 CMD_DAC_CALI, 178 CMD_DVBT_CONFIG, 179 CMD_DVBC_CONFIG, 180 CMD_VIF_CTRL, 181 CMD_FSM_CTRL, 182 CMD_INDIR_RREG, 183 CMD_INDIR_WREG, 184 CMD_GET_INFO, 185 CMD_TS_CTRL, 186 CMD_TUNED_VALUE, 187 CMD_DVBT2_CONFIG, 188 189 CMD_MAX_NUM 190 }E_CMD_CODE; 191 192 typedef enum 193 { 194 pc_system = 0, 195 196 SYS_PARAM_MAX_NUM 197 }E_SYS_PARAM; 198 199 typedef enum 200 { 201 TS_PARALLEL = 0, 202 TS_SERIAL = 1, 203 204 TS_MODE_MAX_NUM 205 }E_TS_MODE; 206 207 typedef enum 208 { 209 agc_ref_small, 210 agc_ref_large, 211 agc_ref_aci, 212 ripple_switch_th_l, 213 ripple_switch_th_h, 214 215 TUNED_PARAM_MAX_NUM 216 }E_TUNED_PARAM; 217 218 //@@++ Arki 20100125 219 typedef enum 220 { 221 TS_MODUL_MODE, 222 TS_FFX_VALUE, 223 TS_GUARD_INTERVAL, 224 TS_CODE_RATE, 225 226 TS_PARAM_MAX_NUM 227 }E_SIGNAL_TYPE; 228 //@@-- Arki 20100125 229 230 typedef struct 231 { 232 MS_U8 cmd_code; 233 MS_U8 param[64]; 234 } S_CMDPKTREG; 235 #if 0 236 typedef enum 237 { 238 // fw version, check sum 239 T2_CHECK_SUM_L = 0x00, 240 E_T2_CHECK_SUM_H, 241 E_T2_FW_VER_0, 242 E_T2_FW_VER_1, 243 E_T2_FW_VER_2, 244 245 // operation mode 246 E_T2_ZIF_EN = 0x20, 247 E_T2_RF_AGC_EN, 248 E_T2_HUM_DET_EN, 249 E_T2_DCR_EN, 250 E_T2_IQB_EN, 251 E_T2_IIS_EN, 252 E_T2_CCI_EN, 253 E_T2_LOW_PWR_DET_EN, 254 E_T2_ACI_DET_EN, 255 E_T2_TD_MOTION_EN, 256 E_T2_FD_MOTION_EN, 257 258 // channel tuning param 259 E_T2_BW = 0x40, 260 E_T2_FC_L = 0x41, 261 E_T2_FC_H = 0x42, 262 E_T2_FS_L, 263 E_T2_FS_H, 264 E_T2_ZIF, 265 E_T2_GI, 266 E_T2_ACI_DET_TYPE, 267 E_T2_AGC_REF, //0x48 268 E_T2_RSSI_REF, 269 E_T2_SNR_TIME_L, 270 E_T2_SNR_TIME_H, 271 E_T2_BER_CMP_TIME_L, 272 E_T2_BER_CMP_TIME_H, 273 E_T2_SFO_CFO_NUM, 274 E_T2_CCI, 275 E_T2_ACI_DET_TH_L, //0x50 276 E_T2_ACI_DET_TH_H, 277 E_T2_TS_SERIAL = 0x52, 278 E_T2_TS_CLK_RATE = 0x53, 279 E_T2_TS_OUT_INV = 0x54, 280 E_T2_TS_DATA_SWAP = 0x55, 281 E_T2_TDP_CCI_KP, 282 E_T2_CCI_FSWEEP, //0x57 283 E_T2_TS_ERR_POL, //0x58 284 E_T2_IF_AGC_INV_PWM_EN, // 0x59 285 286 E_T2_TOTAL_CFO_0 = 0x85, 287 E_T2_TOTAL_CFO_1, 288 289 // dvbt2 lock history 290 E_T2_DVBT2_LOCK_HIS = 0xF0, 291 E_T2_FEF_DET_IND, 292 E_T2_MPLP_NO_COMMON_IND, 293 E_T2_SNR_L, // 0xf3 294 E_T2_SNR_H, // 0xf4 295 E_T2_DOPPLER_DET_FLAG, // 0xf5 296 E_T2_DOPPLER_DET_TH_L, // 0xf6 297 E_T2_DOPPLER_DET_TH_H, // 0xf7 298 299 // splp, mplp releted 300 E_T2_PLP_ID_ARR = 0x100, 301 E_T2_L1_FLAG = 0x120, 302 E_T2_PLP_ID, 303 E_T2_GROUP_ID, 304 E_T2_PARAM_NUM, 305 } E_DVBT2_PARAM; 306 #endif 307 /* 308 // Move to Tuner_SSI.h 309 typedef enum 310 { 311 _QPSK = 0x0, 312 _16QAM = 0x1, 313 _64QAM = 0x2, 314 }E_CONSTEL; 315 316 typedef enum 317 { 318 _CR1Y2 = 0x0, 319 _CR2Y3 = 0x1, 320 _CR3Y4 = 0x2, 321 _CR5Y6 = 0x3, 322 _CR7Y8 = 0x4, 323 }E_CODERATE; 324 325 326 typedef struct 327 { 328 U8 constel; 329 U8 code_rate; 330 float cn_ref; 331 }S_SQI_CN_NORDIGP1_INTERN_DVBT2; 332 333 typedef struct 334 { 335 float power_db; 336 U8 sar3_val; 337 }S_INTERN_DVBT2_RFAGC_SSI; 338 339 typedef struct 340 { 341 float power_db; 342 U8 agc_val; 343 }S_INTERN_DVBT2_IFAGC_SSI; 344 345 typedef struct 346 { 347 U8 constel; 348 U8 code_rate; 349 float p_ref; 350 }S_INTERN_DVBT2_SSI_PREF; 351 352 typedef struct 353 { 354 float attn_db; 355 U8 agc_err; 356 }S_INTERN_DVBT2_IFAGC_ERR; 357 */ 358 //-------------------------------------------------------------------- 359 360 //-------------------------------------------------------------------- 361 MS_BOOL INTERN_DVBT2_Reset ( void ); 362 MS_BOOL INTERN_DVBT2_SoftReset ( void ); 363 MS_BOOL INTERN_DVBT2_Active(MS_BOOL bEnable); 364 MS_BOOL INTERN_DVBT2_Exit ( void ); 365 MS_BOOL INTERN_DVBT2_Power_On_Initialization(MS_BOOL bRFAGCTristateEnable, MS_U8 u8ADCIQMode, MS_U8 u8PadSel, MS_BOOL bPGAEnable, MS_U8 u8PGAGain, const MS_U8 *u8DMD_DVBT_DSPRegInitExt, MS_U8 u8DMD_DVBT_DSPRegInitSize); 366 MS_BOOL INTERN_DVBT2_DSPReg_Init(const MS_U8 *u8DVBT_DSPReg, MS_U8 u8Size); 367 MS_BOOL INTERN_DVBT2_Serial_Control(MS_BOOL bEnable, MS_U8 u8TSClk); 368 MS_BOOL INTERN_DVBT2_Config(DMD_DVBT2_RF_CHANNEL_BANDWIDTH BW, MS_BOOL bSerialTS, MS_U8 u8TSClk, MS_U32 u32IFFreq, MS_U8 u8PlpID); 369 DMD_T2_LOCK_STATUS INTERN_DVBT2_Lock(MS_U16 u16DMD_DVBT2_P1_Timeout, MS_U16 u16DMD_DVBT2_FEC_Timeout); 370 MS_BOOL INTERN_DVBT2_GetLock(DMD_DVBT2_GETLOCK_TYPE eStatus); 371 //MS_BOOL INTERN_DVBT2_GetSignalStrength(MS_U16 *strength, const DMD_DVBT2_InitData *sDMD_DVBT2_InitData, MS_U8 u8SarValue, float fRFPowerDbm); 372 //MS_BOOL INTERN_DVBT2_GetSignalQuality(MS_U16 *quality, const DMD_DVBT2_InitData *sDMD_DVBT2_InitData, MS_U8 u8SarValue, float fRFPowerDbm); 373 //MS_BOOL INTERN_DVBT2_GetPostLdpcBer(float *ber); 374 MS_BOOL INTERN_DVBT2_GetPostLdpcBer(MS_U32 *BitErr_reg, MS_U16 *BitErrPeriod_reg, MS_U16 *FecType); 375 376 //MS_BOOL INTERN_DVBT2_GetPreLdpcBer(float *ber); 377 MS_BOOL INTERN_DVBT2_GetPreLdpcBer(MS_U32 *BitErr_reg, MS_U16 *BitErrPeriod_reg, MS_U16 *FecType); 378 379 MS_BOOL INTERN_DVBT2_GetPacketErr(MS_U16 *u16PktErr); 380 //MS_BOOL INTERN_DVBT2_Get_FreqOffset(float *pFreqOff, MS_U8 u8BW); 381 MS_BOOL INTERN_DVBT2_Get_FreqOffset(MS_U32 *CfoTd_reg, MS_U32 *CfoFd_reg, MS_U32 *Icfo_reg, MS_U8 *fft_reg); 382 383 MS_BOOL INTERN_DVBT2_Get_L1_Parameter( MS_U16 * pu16L1_parameter, DMD_DVBT2_SIGNAL_INFO eSignalType); 384 //float INTERN_DVBT2_GetSNR (void); 385 MS_BOOL INTERN_DVBT2_GetSNR (MS_U16 *u16_snr100, MS_U8 *snr_cali, MS_U8 *u8_gi); 386 387 MS_BOOL INTERN_DVBT2_Version(MS_U16 *ver); 388 MS_BOOL INTERN_DVBT2_Show_Modulation_info(void); 389 MS_BOOL INTERN_DVBT2_Show_Demod_Info(void); 390 MS_BOOL INTERN_DVBT2_Show_Lock_Info(void); 391 MS_BOOL INTERN_DVBT2_Show_PRESFO_Info(void); 392 MS_BOOL INTERN_DVBT2_Show_Lock_Time_Info(void); 393 MS_BOOL INTERN_DVBT2_Show_BER_Info(void); 394 MS_BOOL INTERN_DVBT2_Show_AGC_Info(void); 395 //MS_BOOL INTERN_DVBT2_NORDIG_SSI_Table_Write(DMD_T2_CONSTEL constel, DMD_T2_CODERATE code_rate, float write_value); 396 //MS_BOOL INTERN_DVBT2_NORDIG_SSI_Table_Read(DMD_T2_CONSTEL constel, DMD_T2_CODERATE code_rate, float *read_value); 397 MS_BOOL INTERN_DVBT2_GetPlpBitMap(MS_U8* u8PlpBitMap); 398 MS_BOOL INTERN_DVBT2_GetPlpGroupID(MS_U8 u8PlpID, MS_U8* u8GroupID); 399 MS_BOOL INTERN_DVBT2_SetPlpGroupID(MS_U8 u8PlpID, MS_U8 u8GroupID); 400 401 //-------------------------------------------------------------------- 402 403 #define INTERN_DVBT2_LOAD_FW_FROM_CODE_MEMORY 404 405 #undef EXTSEL 406 #endif