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93 ////////////////////////////////////////////////////////////////////////////////
94
95 ///////////////////////////////////////////////////////////////////////////////////////////////////
96 ///
97 /// file drvAVD.c
98 /// @brief AVD Driver Interface
99 /// @author MStar Semiconductor Inc.
100 ///////////////////////////////////////////////////////////////////////////////////////////////////
101
102
103 //-------------------------------------------------------------------------------------------------
104 // Include Files
105 //-------------------------------------------------------------------------------------------------
106 // Common Definition
107 #include <string.h>
108 #include "MsCommon.h"
109 #include "MsVersion.h"
110 #include "MsOS.h"
111
112 // Internal Definition
113 //#include "regCHIP.h"
114 //#include "regAVD.h"
115 //#include "mapi_tuner.h"
116 #include "drvSYS.h"
117 //#include "drvDMD_VD_MBX.h"
118 #include "drvDMD_EXTERN_MSB124x.h"
119 #include "include/drvDMD_common.h"
120 #include "include/drvSAR.h"
121 #include "drvMMIO.h"
122 //-------------------------------------------------------------------------------------------------
123 // Driver Compiler Options
124 //-------------------------------------------------------------------------------------------------
125 #define ERR_DEMOD_MSB(x) x
126 #ifdef MS_DEBUG
127 #define DBG_DEMOD_MSB(x) x
128 #define DBG_DEMOD_FLOW(x) x
129 #define DBG_GET_SIGNAL(x) // x
130 #define DBG_DEMOD_LOAD_I2C(x) x
131 #define DBG_DEMOD_CHECKSUM(x) // x
132 #define DBG_FLASH_WP(x) // x
133 #endif
134 #define DBG_KIRIN_BOND(x) //x
135
136 //-------------------------------------------------------------------------------------------------
137 // Local Defines
138 //-------------------------------------------------------------------------------------------------
139 #define PRINTE(p) printf p
140
141 #define LOAD_CODE_I2C_BLOCK_NUM 0x400//0x80
142 #define REG_MB_CNTL 0x0C80
143 #define REG_MB_ADDR_L 0x0C84
144 #define REG_MB_ADDR_H 0x0C82
145 #define REG_MB_DATA 0x0C86
146 #define REG_FSM_EN 0x0CB8
147
148 #define resetDemodTime 50
149 #define waitFlashTime 50
150
151 #define SDRAM_DATA_CHECK 0
152 #define SRAM_DATA_CHECK 0
153 #define SDRAM_BASE 0x5000
154 #define SRAM_BASE 0x8000
155 #define SPI_DEVICE_BUFFER_SIZE 256
156 #define MAX_MSB124X_LIB_LEN 131072
157
158 #define MSB124X_BOOT 0x01
159 #define MSB124X_DVBT2 0x02
160 #define MSB124X_DVBT 0x04
161 #define MSB124X_DVBC 0x08
162 #define MSB124X_DVBS2 0x10
163 #define MSB124X_ALL 0x0F
164
165 #define MSB124X_BOOT_START_ADDR 0x00000
166 #define MSB124X_BOOT_END_ADDR 0x007FF
167 #define MSB124X_DVBT2_P1_START_ADDR 0x00800
168 #define MSB124X_DVBT2_P1_END_ADDR 0x087FF
169 #define MSB124X_DVBT2_P2_START_ADDR 0x08800
170 #define MSB124X_DVBT2_P2_END_ADDR 0x0FFFF
171 #define MSB124X_DVBT_START_ADDR 0x10000
172 #define MSB124X_DVBT_END_ADDR 0x17FFF
173 #define MSB124X_DVBC_START_ADDR 0x18000
174 #define MSB124X_DVBC_END_ADDR 0x1FFFF
175 #define MSB124X_DVBS2_P1_START_ADDR 0x20000
176 #define MSB124X_DVBS2_P1_END_ADDR 0x27FFF
177 #define MSB124X_DVBS2_P2_START_ADDR 0x28000
178 #define MSB124X_DVBS2_P2_END_ADDR 0x28FFF
179
180
181 #define MSB124X_WINDOWS_BASE 0x100
182 #define MSB124X_BOOT_WINDOWS_OFFSET MSB124X_WINDOWS_BASE
183 #define MSB124X_DVBT2_P2_WINDOWS_OFFSET (MSB124X_WINDOWS_BASE + 0x08)
184 #define MSB124X_DVBT2_P1_WINDOWS_OFFSET (MSB124X_DVBT2_P2_WINDOWS_OFFSET + 0x08)
185 #define MSB124X_DVBT_WINDOWS_OFFSET (MSB124X_DVBT2_P1_WINDOWS_OFFSET + 0x08)
186 #define MSB124X_DVBC_WINDOWS_OFFSET (MSB124X_DVBT_WINDOWS_OFFSET + 0x08)
187 #define MSB124X_DVBS2_P2_WINDOWS_OFFSET (MSB124X_DVBC_WINDOWS_OFFSET + 0x08)
188 #define MSB124X_DVBS2_P1_WINDOWS_OFFSET (MSB124X_DVBS2_P2_WINDOWS_OFFSET + 0x08)
189
190 #define MSB124X_MAX_FLASH_ON_RETRY_NUM 3
191
192 #define UNUSED(x) (x=x)
193
194 /////////////// CONSTANT /////////////////
195 #define PAGE_WRITE_SIZE 256
196 #define VERSION_CODE_ADDR 0xFC0
197 #define VERSION_CODE_SIZE 32
198
199
200 //kirin bonding option
201 #define DRV_RIU_ReadByte(_u32addr) (*(volatile MS_U32*)(_u32addr) )
202 //-------------------------------------------------------------------------------------------------
203 // Local Structurs
204 //-------------------------------------------------------------------------------------------------
205
206 //-------------------------------------------------------------------------------------------------
207 // Global Variables
208 //-------------------------------------------------------------------------------------------------
209 #if 1
210
211 #define DMD_LOCK() _Lock()
212 #define DMD_UNLOCK() _UnLock()
213
214 #else
215 #define DMD_LOCK() \
216 do{ \
217 MS_ASSERT(MsOS_In_Interrupt() == FALSE); \
218 if (eDMD_MSB124X_DbgLevel == E_DMD_MSB124X_DBGLV_DEBUG) printf("%s lock mutex\n", __FUNCTION__);\
219 MsOS_ObtainMutex(pDemod->_s32DMD_Mutex, MSOS_WAIT_FOREVER);\
220 }while(0)
221
222 #define DMD_UNLOCK() \
223 do{ \
224 MsOS_ReleaseMutex(pDemod->_s32DMD_Mutex);\
225 if (eDMD_MSB124X_DbgLevel == E_DMD_MSB124X_DBGLV_DEBUG) printf("%s unlock mutex\n", __FUNCTION__); \
226 }while(0)
227 #endif
228 //-------------------------------------------------------------------------------------------------
229 // Local Variables
230 //-------------------------------------------------------------------------------------------------
231 #if 1
232 static MSIF_Version _drv_dmd_msb124x_extern_version = {
233 .MW = { DMD_MSB124X_EXTERN_VER, },
234 };
235 #else
236 static MSIF_Version _drv_dmd_msb123x_extern_version;
237 #endif
238
239 #define DEMOD_MAX_INSTANCE 2
240 #define DEMOD_GET_ACTIVE_NODE() &_gDemodNode[_gActiveInstanceIndex]
241
242
243 #if (defined CONFIG_EXT_DVBS_DISABLE) && (CONFIG_EXT_DVBS_DISABLE==1)
244 MS_U8 MSB124X_LIB[]={
245 #include "msb124x_dvbt.dat"
246 };
247 #else
248 MS_U8 MSB124X_LIB[]={
249 #include "msb124x_dvbs_s2_t_t2.dat"
250 };
251 #endif
252
253 MS_U8 MSB1245_LIB[]=
254 {
255 #include "msb1245_dvbs.dat"
256 };
257 //configure
258 //--------------------------------------------------------------------- for DVB-T2
259 // BW: 0->1.7M, 1->5M, 2->6M, 3->7M, 4->8M, 5->10M
260 #define T2_BW_VAL 0x04
261
262 // FC: FC = FS = 4800 = 0x12C0 (4.80MHz IF)
263 #define T2_FC_L_VAL 0xC0 // 4.80M
264 #define T2_FC_H_VAL 0x12
265 #define T2_TS_SERIAL_VAL 0x00
266 #define T2_TS_CLK_RATE_VAL 0x06
267 #define T2_TS_OUT_INV_VAL 0x01
268 #define T2_TS_DATA_SWAP_VAL 0x00
269 #define T2_TS_ERR_POL_VAL 0x00
270
271 #define T2_TS_SPREAD_SPAN 0x00 //Unit: kHz (0: disable; default: 40 kHz)
272 #define T2_TS_SPREAD_STEP_SIZE 0x00 //Unit: percent(%) (0: disable; default: 3.0 %)
273
274 #define T2_TS_PHASE_TUNING_EN 0x00 //0: disable; 1: enable
275 #define T2_TS_PHASE_TUNING_NUM 0x00 //Unit: degree <range: 0x00 ~ 0x1F>
276
277
278 MS_U8 MSB124X_DVBT2_DSPREG_TABLE[] =
279 {
280 T2_BW_VAL, T2_FC_L_VAL, T2_FC_H_VAL, T2_TS_SERIAL_VAL, T2_TS_CLK_RATE_VAL,
281 T2_TS_OUT_INV_VAL, T2_TS_DATA_SWAP_VAL, T2_TS_ERR_POL_VAL,
282 T2_TS_SPREAD_SPAN,T2_TS_SPREAD_STEP_SIZE,T2_TS_PHASE_TUNING_EN,T2_TS_PHASE_TUNING_NUM
283 };
284
285 //--------------------------------------------------------------------- for DVB-T
286 //operation
287
288 //configure
289 #define T_FC_L 0xc0
290 #define T_FC_H 0x12
291 #define T_FS_L 0x80
292 #define T_FS_H 0x70
293 #define T_BW 0x03
294 #define T_IQ_SWAP 0x00
295 #define T_SERIAL_TS 0x00
296 #define T_TS_CLK_SEL 0x06
297 #define T_TS_OUT_INV 0x01
298 #define T_TS_DATA_SWAP 0x00
299 #define T_IF_INV_PWM_OUT_EN 0x00
300
301 #define T_TS_SPREAD_SPAN 0x00 //Unit: kHz (0: disable; default: 40 kHz)
302 #define T_TS_SPREAD_STEP_SIZE 0x00 //Unit: percent(%) (0: disable; default: 3.0 %)
303
304 #define T_TS_PHASE_TUNING_EN 0x00 //0: disable; 1: enable
305 #define T_TS_PHASE_TUNING_NUM 0x00 //Unit: degree <range: 0x00 ~ 0x1F>
306
307 MS_U8 MSB124X_DVBT_DSPREG_TABLE[] =
308 {
309 T_BW, T_FC_L, T_FC_H, T_SERIAL_TS, T_TS_CLK_SEL, T_TS_OUT_INV, T_TS_DATA_SWAP,
310 T_IQ_SWAP, T_IF_INV_PWM_OUT_EN,
311 T_TS_SPREAD_SPAN,T_TS_SPREAD_STEP_SIZE,T_TS_PHASE_TUNING_EN,T_TS_PHASE_TUNING_NUM
312 };
313
314 //--------------------------------------------------------------------- for DVB-C
315 #define C_AUTO_SCAN_SYM_RATE 1
316 #define C_AUTO_SCAN_QAM 1
317 #define C_IF_INV_PWM_OUT_EN 0
318 #define C_ZIF 0
319 #define C_FC_L 0x88
320 #define C_FC_H 0x13
321 #define C_FS_L 0xC0
322 #define C_FS_H 0x5D
323 #define C_BW_L 0xDB
324 #define C_BW_H 0x1A
325 #define C_BW1_L 0xF4
326 #define C_BW1_H 0x1A
327 #define C_BW2_L 0xDB
328 #define C_BW2_H 0x1A
329 #define C_BW3_L 0x58
330 #define C_BW3_H 0x1B
331 #define C_QAM 2
332 #define C_CCI 0
333 #define C_TS_SERIAL 0
334 #define C_TS_CLK_RATE 6
335 #define C_TS_OUT_INV 1
336 #define C_TS_DATA_SWAP 0
337 #define C_IQ_SWAP 0
338 #define C_TS_SPREAD_SPAN 0x00 //Unit: kHz (0: disable; default: 40 kHz)
339 #define C_TS_SPREAD_STEP_SIZE 0x00 //Unit: percent(%) (0: disable; default: 3.0 %)
340
341 #define C_TS_PHASE_TUNING_EN 0x00 //0: disable; 1: enable
342 #define C_TS_PHASE_TUNING_NUM 0x00 //Unit: degree <range: 0x00 ~ 0x1F>
343
344 MS_U8 MSB124X_DVBC_DSPREG_TABLE[] =
345 {
346 C_AUTO_SCAN_SYM_RATE, //0x20
347 C_AUTO_SCAN_QAM,
348 C_IF_INV_PWM_OUT_EN,
349 C_ZIF,
350 C_FC_L,
351 C_FC_H,
352 C_FS_L,
353 C_FS_H,
354
355 C_BW_L, //0x28
356 C_BW_H,
357 C_BW1_L,
358 C_BW1_H,
359 C_BW2_L,
360 C_BW2_H,
361 C_BW3_L,
362 C_BW3_H,
363
364 C_QAM, //0x30
365 C_CCI,
366 C_TS_SERIAL,
367 C_TS_CLK_RATE,
368 C_TS_OUT_INV,
369 C_TS_DATA_SWAP,
370 C_IQ_SWAP,
371 };
372
373 typedef struct xMSB124XData
374 {
375 MS_BOOL Active;
376 MS_BOOL bDMD_MSB124X_Power_init_en;
377 MS_U8 u8DMD_MSB124X_PowerOnInitialization_Flow;
378 MS_U8 u8DMD_MSB124X_Sdram_Code;
379 MS_U8 u8DMD_MSB124X_Sram_Code;
380 sDMD_MSB124X_InitData _sDMD_MSB124X_InitData;
381 eDMD_MSB124X_DemodulatorType eDMD_MSB124X_CurrentDemodulatorType;
382 MS_BOOL bDemodRest;
383 MS_U8 DVBT2_DSP_REG[sizeof(MSB124X_DVBT2_DSPREG_TABLE)];
384 MS_U8 DVBT_DSP_REG[sizeof(MSB124X_DVBT_DSPREG_TABLE)];
385 MS_U8 DVBC_DSP_REG[sizeof(MSB124X_DVBC_DSPREG_TABLE)];
386 }tMSB124XData;
387
388 static MS_S32 _gActiveInstanceIndex = 0;
389 static eDMD_MSB124X_DbgLv eDMD_MSB124X_DbgLevel=E_DMD_MSB124X_DBGLV_NONE;
390 static tMSB124XData _gDemodNode[DEMOD_MAX_INSTANCE]=
391 {
392 {FALSE, FALSE, 0, 0, 0, {0}, E_DMD_MSB124X_DEMOD_DVBT,TRUE,{0},{0},{0}},
393 {FALSE, FALSE, 0, 0, 0, {0}, E_DMD_MSB124X_DEMOD_DVBT,TRUE,{0},{0},{0}},
394 };
395
396 //-------------------------------------------------------------------------------------------------
397 // Debug Functions
398 //-------------------------------------------------------------------------------------------------
399 #ifdef MS_DEBUG
400 #define DMD_DBG(x) (x)
401 #else
402 #define DMD_DBG(x) //(x)
403 #endif
404 //-------------------------------------------------------------------------------------------------
405 // Local Functions
406 //-------------------------------------------------------------------------------------------------
407 static MS_S32 _s32DMD_Mutex = -1;
408 static MS_S32 _s32LockOwner = -1;
409 static MS_S32 _sLockCount = 0;
_Lock(void)410 static void _Lock(void)
411 {
412 MS_S32 s32CurTaskId = MsOS_GetOSThreadID();
413
414 if(_s32DMD_Mutex == -1)
415 {
416 return;
417 }
418
419 if (_s32LockOwner == s32CurTaskId)
420 {
421 _sLockCount++;
422 }
423 else
424 {
425
426 MsOS_ObtainMutex(_s32DMD_Mutex, MSOS_WAIT_FOREVER);
427 //printf("m_CircularMutex lock\n");
428 _sLockCount = 1;
429 _s32LockOwner = s32CurTaskId;
430 }
431 }
_UnLock(void)432 static void _UnLock(void)
433 {
434 MS_S32 s32CurTaskId = MsOS_GetOSThreadID();
435
436 if(_s32DMD_Mutex == -1)
437 {
438 return;
439 }
440 if (s32CurTaskId == _s32LockOwner)
441 {
442 if (--_sLockCount == 0)
443 {
444 _s32LockOwner = -1;
445 //printf("m_CircularMutex unlock\n");
446 MsOS_ReleaseMutex(_s32DMD_Mutex);
447 }
448 }
449
450 }
451
452 //-------------------------------------------------------------------------------------------------
453 // Global Functions
454 //-------------------------------------------------------------------------------------------------
455 #define INDEX_TO_HANDLE(x) ((x)+1)
456 #define HANDLE_TO_INDEX(x) ((x)-1)
457 //If using legacy API, mutex is created in Init and deleted in Exit
458 //If using New API(EX API), mutex is created in CreateNode and deleted in DeleteNode
459 //Add _CreateMutex, called in Init and CreateNode
_CreateMutex(void)460 static MS_BOOL _CreateMutex(void)
461 {
462 if (_s32DMD_Mutex == -1)
463 {
464 _sLockCount = 0;
465 _s32LockOwner = -1;
466 _s32DMD_Mutex = MsOS_CreateMutex(E_MSOS_FIFO, "_utopia_124x", MSOS_PROCESS_SHARED);
467 if (_s32DMD_Mutex == -1)
468 {
469 DMD_DBG(printf(" Create Mutex Fail\n"));
470 return FALSE;
471 }
472 }
473 return TRUE;
474 }
475 //Add _DeleteMutex, called in Exit and DeleteNode
476
_DeleteMutex(void)477 static MS_BOOL _DeleteMutex(void)
478 {
479 int i=0;
480 for(i=0; i<DEMOD_MAX_INSTANCE; i++)
481 {
482 //still having active instance, no need to DeleteMutex
483 if(_gDemodNode[i].Active == TRUE)
484 {
485 return TRUE;
486 }
487 }
488 if (_s32DMD_Mutex != -1)
489 {
490 MsOS_DeleteMutex(_s32DMD_Mutex);
491 _s32DMD_Mutex = -1;
492 _sLockCount = 0;
493 _s32LockOwner = -1;
494 }
495 return TRUE;
496 }
497
MDrv_DMD_MSB124X_SwitchHandle(MS_S32 s32Handle)498 extern MS_BOOL MDrv_DMD_MSB124X_SwitchHandle(MS_S32 s32Handle)
499 {
500 MS_S32 s32Index = HANDLE_TO_INDEX(s32Handle);
501 if(s32Index>=DEMOD_MAX_INSTANCE)
502 return FALSE;
503 if(s32Index<0)
504 return FALSE;
505 _gActiveInstanceIndex =s32Index;
506 return TRUE;
507 }
MDrv_DMD_MSB124X_GetCurrentHandle(void)508 extern MS_S32 MDrv_DMD_MSB124X_GetCurrentHandle(void)
509 {
510 return INDEX_TO_HANDLE(_gActiveInstanceIndex);
511 }
MDrv_MDM_MSB124X_CreateNode(MS_S32 * s32Handle)512 extern MS_BOOL MDrv_MDM_MSB124X_CreateNode(MS_S32 *s32Handle)
513 {
514 int i=0;
515 if(_CreateMutex() == FALSE)
516 {
517 return FALSE;
518 }
519 for(i=0; i<DEMOD_MAX_INSTANCE; i++)
520 {
521 if(_gDemodNode[i].Active == FALSE)
522 {
523 _gDemodNode[i].Active = TRUE;
524 *s32Handle = INDEX_TO_HANDLE(i);
525 return TRUE;
526 }
527 }
528 printf("Slot Full\n");
529 return FALSE;
530 }
MDrv_MDM_MSB124X_DeleteNode(MS_S32 s32Handle)531 extern MS_BOOL MDrv_MDM_MSB124X_DeleteNode(MS_S32 s32Handle)
532 {
533 MS_S32 s32Index = HANDLE_TO_INDEX(s32Handle);
534 if(s32Index>=DEMOD_MAX_INSTANCE)
535 return FALSE;
536 if(s32Index<0)
537 return FALSE;
538 if(_gDemodNode[s32Index].Active == TRUE)
539 {
540 _gDemodNode[s32Index].Active = FALSE;
541 _DeleteMutex();
542 return TRUE;
543 }
544 return FALSE;
545 }
546
547
MDrv_DMD_MSB124X_Init(sDMD_MSB124X_InitData * pDMD_MSB124X_InitData,MS_U32 u32InitDataLen)548 MS_BOOL MDrv_DMD_MSB124X_Init(sDMD_MSB124X_InitData *pDMD_MSB124X_InitData, MS_U32 u32InitDataLen)
549 {
550 //char pDMD_MSB124X_MutexString[16], pDMD_MSB124X_MutexString_RegRW[16], pDMD_MSB124X_MutexString_DSPRegRW[16];
551 //char pDMD_MSB124X_MutexString[16];
552 tMSB124XData *pDemod = DEMOD_GET_ACTIVE_NODE();
553
554 //if (NULL == strncpy(pDMD_MSB124X_MutexString,"Mutex DMD DVB",16))
555 //{
556 // DMD_DBG(printf("MDrv_DMD_MSB124X_Init strcpy Fail\n"));
557 //return FALSE;
558 //}
559
560 if(_CreateMutex() == FALSE)
561 {
562 DMD_DBG(printf("MDrv_DMD_MSB124X_Init Create Mutex Fail\n"));
563 return FALSE;
564 }
565
566 DMD_LOCK();
567 if ( sizeof(sDMD_MSB124X_InitData) == u32InitDataLen)
568 {
569 memcpy(&pDemod->_sDMD_MSB124X_InitData, pDMD_MSB124X_InitData, u32InitDataLen);
570 }
571 else
572 {
573 DMD_DBG(printf("MDrv_DMD_MSB124X_Init input data structure incorrect\n"));
574 DMD_UNLOCK();
575 return FALSE;
576 }
577
578 if (pDemod->_sDMD_MSB124X_InitData.pDVBC_DSP_REG!= NULL)
579 {
580 printf("MDrv_DMD_MSB124X_Init Init DVBC DSP Table By Device Driver ... \n");
581 #if 1
582
583 memcpy (&pDemod->DVBC_DSP_REG[0],
584 pDemod->_sDMD_MSB124X_InitData.pDVBC_DSP_REG ,
585 sizeof(MSB124X_DVBC_DSPREG_TABLE));
586 #else
587 memcpy (&MSB124X_DVBC_DSPREG_TABLE[0],
588 pDemod->_sDMD_MSB124X_InitData.pDVBC_DSP_REG ,
589 sizeof(MSB124X_DVBC_DSPREG_TABLE));
590 #endif
591 }
592 else
593 {
594 #if 1
595
596 memcpy (&pDemod->DVBC_DSP_REG[0],
597 MSB124X_DVBC_DSPREG_TABLE ,
598 sizeof(MSB124X_DVBC_DSPREG_TABLE));
599 #endif
600 printf("MDrv_DMD_MSB124X_Init Init DVBC DSP Table By Device Driver ... \n");
601 }
602
603 if (pDemod->_sDMD_MSB124X_InitData.pDVBT_DSP_REG!= NULL)
604 {
605 printf("MDrv_DMD_MSB124X_Init Init DVBT DSP Table By Device Driver ... \n");
606 #if 1
607 memcpy (&pDemod->DVBT_DSP_REG[0],
608 pDemod->_sDMD_MSB124X_InitData.pDVBT_DSP_REG ,
609 sizeof(MSB124X_DVBT_DSPREG_TABLE));
610 #else
611 memcpy (&MSB124X_DVBT_DSPREG_TABLE[0],
612 pDemod->_sDMD_MSB124X_InitData.pDVBT_DSP_REG ,
613 sizeof(MSB124X_DVBT_DSPREG_TABLE));
614 #endif
615 }
616 else
617 {
618 #if 1
619 memcpy (&pDemod->DVBT_DSP_REG[0],
620 MSB124X_DVBT_DSPREG_TABLE ,
621 sizeof(MSB124X_DVBT_DSPREG_TABLE));
622 #endif
623 printf("MDrv_DMD_MSB124X_Init Init DVBT DSP Table By Device Driver ... \n");
624 }
625
626 if (pDemod->_sDMD_MSB124X_InitData.pDVBT2_DSP_REG!= NULL)
627 {
628 printf("MDrv_DMD_MSB124X_Init Init DVBT2 DSP Table By Device Driver ... \n");
629
630 #if 1
631 memcpy (&pDemod->DVBT2_DSP_REG[0],
632 pDemod->_sDMD_MSB124X_InitData.pDVBT2_DSP_REG ,
633 sizeof(MSB124X_DVBT2_DSPREG_TABLE));
634 #else
635 memcpy (&MSB124X_DVBT2_DSPREG_TABLE[0],
636 pDemod->_sDMD_MSB124X_InitData.pDVBT2_DSP_REG ,
637 sizeof(MSB124X_DVBT2_DSPREG_TABLE));
638 #endif
639 }
640 else
641 {
642 #if 1
643 memcpy (&pDemod->DVBT2_DSP_REG[0],
644 MSB124X_DVBT2_DSPREG_TABLE,
645 sizeof(MSB124X_DVBT2_DSPREG_TABLE));
646 #endif
647 printf("MDrv_DMD_MSB124X_Init Init DVBT2 DSP Table By Device Driver ... \n");
648 }
649
650 if (pDemod->_sDMD_MSB124X_InitData.bEnableSPILoadCode &&
651 pDemod->_sDMD_MSB124X_InitData.fpMSB124x_SPIPAD_En != NULL)
652 {
653 if (!MDrv_DMD_SSPI_Init(0))
654 {
655 printf("MDrv_DMD_MSB124x_Init Init MDrv_DMD_SSPI_Init Fail \n");
656 }
657 }
658 else
659 {
660 pDemod->_sDMD_MSB124X_InitData.bEnableSPILoadCode = FALSE;
661 }
662
663 //eDMD_MSB124X_DbgLevel = E_DMD_MSB124X_DBGLV_DEBUG;
664 #ifdef MS_DEBUG
665 if (eDMD_MSB124X_DbgLevel >= E_DMD_MSB124X_DBGLV_INFO)
666 {
667 printf("MDrv_DMD_MSB124X_Init %d\n", _gActiveInstanceIndex);
668 }
669 #endif
670
671 DMD_UNLOCK();
672 return TRUE;
673 }
674
MDrv_DMD_MSB124X_Exit(void)675 MS_BOOL MDrv_DMD_MSB124X_Exit(void)
676 {
677 tMSB124XData *pDemod = DEMOD_GET_ACTIVE_NODE();
678 #ifdef MS_DEBUG
679 if (eDMD_MSB124X_DbgLevel >= E_DMD_MSB124X_DBGLV_DEBUG)
680 {
681 printf("MDrv_DMD_MSB124X_Exit %d\n", _gActiveInstanceIndex);
682 }
683 #endif
684 pDemod->bDMD_MSB124X_Power_init_en = FALSE;
685 pDemod->u8DMD_MSB124X_PowerOnInitialization_Flow = 0;
686 pDemod->u8DMD_MSB124X_Sdram_Code = 0x0;
687 pDemod->u8DMD_MSB124X_Sram_Code = 0x0;
688 pDemod->bDemodRest = TRUE;
689 _DeleteMutex();
690 return TRUE;
691 }
692
MDrv_DMD_MSB124X_SetDbgLevel(eDMD_MSB124X_DbgLv u8DbgLevel)693 MS_BOOL MDrv_DMD_MSB124X_SetDbgLevel(eDMD_MSB124X_DbgLv u8DbgLevel)
694 {
695 //DMD_LOCK();
696 eDMD_MSB124X_DbgLevel = u8DbgLevel;
697 //DMD_UNLOCK();
698 return TRUE;
699 }
700
701
MDrv_DMD_MSB124X_GetLibVer(const MSIF_Version ** ppVersion)702 MS_BOOL MDrv_DMD_MSB124X_GetLibVer(const MSIF_Version **ppVersion)
703 {
704 //tMSB124XData *pDemod = DEMOD_GET_ACTIVE_NODE();
705 //DMD_LOCK();
706 if (!ppVersion)
707 {
708 // DMD_UNLOCK();
709 return FALSE;
710 }
711
712 *ppVersion = &_drv_dmd_msb124x_extern_version;
713 //DMD_UNLOCK();
714 return TRUE;
715 }
716
MDrv_DMD_MSB124X_GetFWVer(MS_U16 * ver)717 MS_BOOL MDrv_DMD_MSB124X_GetFWVer(MS_U16 *ver)
718 {
719
720 MS_BOOL bRet=TRUE;
721
722 //DMD_LOCK();
723 //printf("MDrv_DMD_DVBT_GetFWVer %x\n",*ver);
724 //DMD_UNLOCK();
725
726 return bRet;
727
728 }
729
_MDrv_DMD_MSB124X_GetReg(MS_U16 u16Addr,MS_U8 * pu8Data)730 static MS_BOOL _MDrv_DMD_MSB124X_GetReg(MS_U16 u16Addr, MS_U8 *pu8Data)
731 {
732 MS_BOOL bRet=TRUE;
733 MS_U8 u8MsbData[6];
734 tMSB124XData *pDemod = DEMOD_GET_ACTIVE_NODE();
735
736 u8MsbData[0] = 0x10;
737 u8MsbData[1] = 0x00;
738 u8MsbData[2] = 0x00;
739 u8MsbData[3] = (u16Addr >> 8) &0xff;
740 u8MsbData[4] = u16Addr & 0xff;
741
742 u8MsbData[0] = 0x35;
743 (pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB124X_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, u8MsbData);
744
745 u8MsbData[0] = 0x10;
746 (pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB124X_DEMOD_I2C_WRITE_BYTES, 0, NULL, 5, u8MsbData);
747 (pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB124X_DEMOD_I2C_READ_BYTES, 0, NULL, 1, pu8Data);
748
749 u8MsbData[0] = 0x34;
750 bRet=(pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB124X_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, u8MsbData);
751
752 #ifdef MS_DEBUG
753 if (eDMD_MSB124X_DbgLevel >= E_DMD_MSB124X_DBGLV_DEBUG)
754 {
755 printf("_MDrv_DMD_MSB124X_GetReg %x %x\n", u16Addr, *pu8Data);
756 }
757 #endif
758
759 return bRet;
760 }
761
MDrv_DMD_MSB124X_GetReg(MS_U16 u16Addr,MS_U8 * pu8Data)762 MS_BOOL MDrv_DMD_MSB124X_GetReg(MS_U16 u16Addr, MS_U8 *pu8Data)
763 {
764 MS_BOOL bRet=TRUE;
765
766 DMD_LOCK();
767 bRet = _MDrv_DMD_MSB124X_GetReg(u16Addr, pu8Data);
768 DMD_UNLOCK();
769
770 return bRet;
771 }
772
_MDrv_DMD_MSB124X_SetReg(MS_U16 u16Addr,MS_U8 u8Data)773 static MS_BOOL _MDrv_DMD_MSB124X_SetReg(MS_U16 u16Addr, MS_U8 u8Data)
774 {
775 MS_BOOL bRet=TRUE;
776 MS_U8 u8MsbData[6];
777 tMSB124XData *pDemod = DEMOD_GET_ACTIVE_NODE();
778 #ifdef MS_DEBUG
779 if (eDMD_MSB124X_DbgLevel >= E_DMD_MSB124X_DBGLV_DEBUG)
780 {
781 printf("_MDrv_DMD_MSB124X_SetReg %x %x\n", u16Addr, u8Data);
782 }
783 #endif
784
785 u8MsbData[0] = 0x10;
786 u8MsbData[1] = 0x00;
787 u8MsbData[2] = 0x00;
788 u8MsbData[3] = (u16Addr >> 8) &0xff;
789 u8MsbData[4] = u16Addr &0xff;
790 u8MsbData[5] = u8Data;
791
792 u8MsbData[0] = 0x35;
793 (pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB124X_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, u8MsbData);
794
795 u8MsbData[0] = 0x10;
796 (pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB124X_DEMOD_I2C_WRITE_BYTES, 0, NULL, 6, u8MsbData);
797
798 u8MsbData[0] = 0x34;
799 bRet=(pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB124X_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, u8MsbData);
800 return bRet;
801 }
802
MDrv_DMD_MSB124X_SetReg(MS_U16 u16Addr,MS_U8 u8Data)803 MS_BOOL MDrv_DMD_MSB124X_SetReg(MS_U16 u16Addr, MS_U8 u8Data)
804 {
805 MS_BOOL bRet=TRUE;
806
807 DMD_LOCK();
808 bRet = _MDrv_DMD_MSB124X_SetReg(u16Addr, u8Data);
809 DMD_UNLOCK();
810
811 return bRet;
812 }
813
814
_MDrv_DMD_MSB124X_SetRegs(MS_U16 u16Addr,MS_U8 * u8pData,MS_U16 data_size)815 static MS_BOOL _MDrv_DMD_MSB124X_SetRegs(MS_U16 u16Addr, MS_U8* u8pData, MS_U16 data_size)
816 {
817 MS_BOOL bRet=TRUE;
818 MS_U8 u8MsbDataValue[LOAD_CODE_I2C_BLOCK_NUM + 5];
819 MS_U16 idx = 0;
820 tMSB124XData *pDemod = DEMOD_GET_ACTIVE_NODE();
821 #ifdef MS_DEBUG
822 if (eDMD_MSB124X_DbgLevel >= E_DMD_MSB124X_DBGLV_DEBUG)
823 {
824 printf("_MDrv_DMD_MSB124X_SetRegs %x %x\n", u16Addr, data_size);
825 }
826 #endif
827
828 u8MsbDataValue[0] = 0x10;
829 u8MsbDataValue[1] = 0x00;
830 u8MsbDataValue[2] = 0x00;
831 u8MsbDataValue[3] = (u16Addr >> 8) &0xff;
832 u8MsbDataValue[4] = u16Addr & 0xff;
833 // u8MsbDataValue[5] = 0x00;
834
835 for(idx = 0; idx < data_size ; idx++)
836 {
837 u8MsbDataValue[5+idx] = u8pData[idx];
838 }
839
840 u8MsbDataValue[0] = 0x35;
841 bRet &= (pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB124X_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, u8MsbDataValue);
842
843 u8MsbDataValue[0] = 0x10;
844 bRet &= (pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB124X_DEMOD_I2C_WRITE_BYTES, 0, NULL, 5 + data_size, u8MsbDataValue);
845
846 u8MsbDataValue[0] = 0x34;
847 bRet &= (pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB124X_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, u8MsbDataValue);
848
849 return bRet;
850 }
851
MDrv_DMD_MSB124X_SetRegs(MS_U16 u16Addr,MS_U8 * u8pData,MS_U16 data_size)852 MS_BOOL MDrv_DMD_MSB124X_SetRegs(MS_U16 u16Addr, MS_U8* u8pData, MS_U16 data_size)
853 {
854 MS_BOOL bRet=TRUE;
855
856 DMD_LOCK();
857 bRet = _MDrv_DMD_MSB124X_SetRegs(u16Addr, u8pData, data_size);
858 DMD_UNLOCK();
859
860 return bRet;
861 }
862
_MDrv_DMD_MSB124X_SetReg2Bytes(MS_U16 u16Addr,MS_U16 u16Data)863 static MS_BOOL _MDrv_DMD_MSB124X_SetReg2Bytes(MS_U16 u16Addr, MS_U16 u16Data)
864 {
865 MS_BOOL bRet=TRUE;
866
867 #ifdef MS_DEBUG
868 if (eDMD_MSB124X_DbgLevel >= E_DMD_MSB124X_DBGLV_DEBUG)
869 {
870 printf("_MDrv_DMD_MSB124X_SetReg2Bytes %x %x\n", u16Addr, u16Data);
871 }
872 #endif
873
874 bRet &= _MDrv_DMD_MSB124X_SetReg(u16Addr, (MS_U8)u16Data&0x00ff);
875 bRet &= _MDrv_DMD_MSB124X_SetReg(u16Addr + 0x0001, (MS_U8)(u16Data>>8)&0x00ff);
876
877 return bRet;
878 }
879
MDrv_DMD_MSB124X_SetReg2Bytes(MS_U16 u16Addr,MS_U16 u16Data)880 MS_BOOL MDrv_DMD_MSB124X_SetReg2Bytes(MS_U16 u16Addr, MS_U16 u16Data)
881 {
882 MS_BOOL bRet=TRUE;
883
884 DMD_LOCK();
885 bRet = _MDrv_DMD_MSB124X_SetReg2Bytes(u16Addr, u16Data);
886 DMD_UNLOCK();
887
888 return bRet;
889 }
890
891
_MDrv_DMD_MSB124X_GetDSPReg(MS_U16 u16Addr,MS_U8 * pu8Data)892 MS_BOOL _MDrv_DMD_MSB124X_GetDSPReg(MS_U16 u16Addr, MS_U8 *pu8Data)
893 {
894 MS_BOOL bRet=TRUE;
895 MS_U8 u8Cntl = 0x00;
896 MS_U16 u16Cntr = 0x00;
897
898 bRet &= _MDrv_DMD_MSB124X_SetReg(REG_MB_ADDR_H, (MS_U8)(u16Addr >> 8));
899 bRet &= _MDrv_DMD_MSB124X_SetReg(REG_MB_ADDR_L, (MS_U8)(u16Addr));
900 bRet &= _MDrv_DMD_MSB124X_SetReg(REG_MB_CNTL, 0x03);
901
902 do
903 {
904 bRet &= _MDrv_DMD_MSB124X_GetReg(REG_MB_CNTL, &u8Cntl);
905 if (u16Cntr++ > 0x7ff)
906 {
907 #ifdef MS_DEBUG
908 //if (eDMD_MSB124X_DbgLevel >= E_DMD_MSB124X_DBGLV_DEBUG)
909 {
910 printf("MSB124X_MB_READ_FAILURE\n");
911 }
912 #endif
913 return FALSE;
914 }
915 }
916 while(u8Cntl != 0xff);
917
918 bRet &= _MDrv_DMD_MSB124X_GetReg(REG_MB_DATA, pu8Data);
919
920 #ifdef MS_DEBUG
921 if (eDMD_MSB124X_DbgLevel >= E_DMD_MSB124X_DBGLV_DEBUG)
922 {
923 printf("MDrv_DMD_MSB124X_GetDSPReg %x %x\n", u16Addr, *pu8Data);
924 }
925 #endif
926
927 return bRet;
928 }
929
MDrv_DMD_MSB124X_GetDSPReg(MS_U16 u16Addr,MS_U8 * pu8Data)930 MS_BOOL MDrv_DMD_MSB124X_GetDSPReg(MS_U16 u16Addr, MS_U8 *pu8Data)
931 {
932 MS_BOOL bRet=TRUE;
933
934 DMD_LOCK();
935 bRet = _MDrv_DMD_MSB124X_GetDSPReg(u16Addr, pu8Data);
936 DMD_UNLOCK();
937
938 return bRet;
939 }
940
_MDrv_DMD_MSB124X_SetDSPReg(MS_U16 u16Addr,MS_U8 u8Data)941 MS_BOOL _MDrv_DMD_MSB124X_SetDSPReg(MS_U16 u16Addr, MS_U8 u8Data)
942 {
943 MS_BOOL bRet=TRUE;
944 MS_U8 u8Cntl = 0x00;
945 MS_U16 u16Cntr = 0x00;
946
947 #ifdef MS_DEBUG
948 if (eDMD_MSB124X_DbgLevel >= E_DMD_MSB124X_DBGLV_DEBUG)
949 {
950 printf("MDrv_DMD_MSB124X_SetDSPReg %x %x\n", u16Addr, u8Data);
951 }
952 #endif
953
954 bRet &= _MDrv_DMD_MSB124X_SetReg(REG_MB_DATA, u8Data);
955 bRet &= _MDrv_DMD_MSB124X_SetReg(REG_MB_ADDR_H, (MS_U8)(u16Addr >> 8));
956 bRet &= _MDrv_DMD_MSB124X_SetReg(REG_MB_ADDR_L, (MS_U8)(u16Addr));
957 bRet &= _MDrv_DMD_MSB124X_SetReg(REG_MB_CNTL, 0x04);
958
959 do
960 {
961 bRet &= _MDrv_DMD_MSB124X_GetReg(REG_MB_CNTL, &u8Cntl);
962 if (u16Cntr++ > 0x7ff)
963 {
964 #ifdef MS_DEBUG
965 //if (eDMD_MSB124X_DbgLevel >= E_DMD_MSB124X_DBGLV_DEBUG)
966 {
967 printf("MSB124X_MB_WRITE_FAILURE\n");
968 }
969 #endif
970 return false;
971 }
972 }
973 while(u8Cntl != 0xff);
974 return bRet;
975 }
976
MDrv_DMD_MSB124X_SetDSPReg(MS_U16 u16Addr,MS_U8 u8Data)977 MS_BOOL MDrv_DMD_MSB124X_SetDSPReg(MS_U16 u16Addr, MS_U8 u8Data)
978 {
979 MS_BOOL bRet=TRUE;
980
981 DMD_LOCK();
982 bRet = _MDrv_DMD_MSB124X_SetDSPReg(u16Addr, u8Data);
983 DMD_UNLOCK();
984
985 return bRet;
986 }
987
_MSB124X_I2C_CH_Reset(MS_U8 ch_num)988 static MS_BOOL _MSB124X_I2C_CH_Reset(MS_U8 ch_num)
989 {
990 MS_BOOL bRet=TRUE;
991 //MAPI_U8 addr[4] = {0x00, 0x00, 0x00, 0x00};
992 MS_U8 u8data[5] = {0x53, 0x45, 0x52, 0x44, 0x42};
993 tMSB124XData *pDemod = DEMOD_GET_ACTIVE_NODE();
994
995 #ifdef MS_DEBUG
996 printf("[msb124x][beg]I2C_CH_Reset, CH=0x%x\n",ch_num);
997 #endif
998 //DMD_LOCK_REG_RW();
999
1000 // 8'hb2(SRID)->8,h53(PWD1)->8,h45(PWD2)->8,h52(PWD3)->8,h44(PWD4)->8,h42(PWD5)
1001 //u8data[0] = 0x53;
1002 //bRet &= (*_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB124X_DEMOD_I2C_WRITE_BYTES, 0, NULL, 5, u8data);
1003 if (pDemod->bDemodRest)
1004 {
1005 pDemod->bDemodRest = FALSE;
1006 // 8'hb2(SRID)->8,h53(PWD1)->8,h45(PWD2)->8,h52(PWD3)->8,h44(PWD4)->8,h42(PWD5)
1007 u8data[0] = 0x53;
1008 // Don't check Ack because this passward only ack one time for the first time.
1009 bRet &= (pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB124X_DEMOD_I2C_WRITE_BYTES, 0, NULL, 5, u8data);
1010 }
1011 // 8'hb2(SRID)->8,h71(CMD) //TV.n_iic_
1012 u8data[0] = 0x71;
1013 bRet &= (pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB124X_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, u8data);
1014
1015 // 8'hb2(SRID)->8,h81(CMD) //TV.n_iic_sel_b0
1016 u8data[0] = ((ch_num & 0x01) != 0)? 0x81 : 0x80;
1017 bRet &= (pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB124X_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, u8data);
1018
1019 // 8'hb2(SRID)->8,h83(CMD) //TV.n_iic_sel_b1
1020 u8data[0] = ((ch_num & 0x02) != 0)? 0x83 : 0x82;
1021 bRet &= (pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB124X_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, u8data);
1022
1023 // 8'hb2(SRID)->8,h84(CMD) //TV.n_iic_sel_b2
1024 u8data[0] = ((ch_num & 0x04) != 0)? 0x85 : 0x84;
1025 bRet &= (pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB124X_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, u8data);
1026
1027 // 8'hb2(SRID)->8,h53(CMD) //TV.n_iic_ad_byte_en2, 32bit read/write
1028 u8data[0] = 0x53;
1029 bRet &= (pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB124X_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, u8data);
1030
1031 // 8'hb2(SRID)->8,h7f(CMD) //TV.n_iic_sel_use_cfg
1032 u8data[0] = 0x7f;
1033 bRet &= (pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB124X_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, u8data);
1034
1035 /*
1036 // 8'hb2(SRID)->8,h35(CMD) //TV.n_iic_use
1037 data[0] = 0x35;
1038 iptr->WriteBytes(0, NULL, 1, data);
1039
1040 // 8'hb2(SRID)->8,h71(CMD) //TV.n_iic_Re-shape
1041 data[0] = 0x71;
1042 iptr->WriteBytes(0, NULL, 1, data);
1043 */
1044 //DMD_UNLOCK_REG_RW();
1045 #ifdef MS_DEBUG
1046 DBG_DEMOD_LOAD_I2C(printf("[msb124x][end]I2C_CH_Reset, CH=0x%x\n",ch_num));
1047 #endif
1048 return bRet;
1049 }
1050
_MSB124X_HW_init(void)1051 static MS_BOOL _MSB124X_HW_init(void)
1052 {
1053 MS_BOOL bRet = true;
1054 MS_U8 u8_tmp = 0;
1055 MS_U8 u8_timeout = 0;
1056
1057 #ifdef MS_DEBUG
1058 printf("[msb124x][beg]MSB124X_HW_init\n");
1059 #endif
1060 //DMD_LOCK();
1061
1062 // ASIC INIT for WDM DVB-T2
1063 // -------------------------------------------------------------------
1064 // Initialize DMD_ANA_MISC
1065 // -------------------------------------------------------------------
1066 // [0] reg_tst_ldo25i
1067 // [1] reg_tst_ldo25q
1068 // [5:4] reg_tst_ldo25i_selfb
1069 // [7:6] reg_tst_ldo25q_selfb
1070 // [8] reg_pd_dm2p5ldoi = 1'b0
1071 // [9] reg_pd_dm2p5ldoq = 1'b0
1072 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x0A00+(0x4f)*2, 0x0000);
1073
1074 // [0] reg_tst_ldo11_clk
1075 // [1] reg_tst_ldo26
1076 // [2] reg_tst_ldo11_cmp
1077 // [3] reg_pd_dm1p1ldo_clk = 1'b0
1078 // [4] reg_pd_dm1p1ldo_cmp = 1'b0
1079 // [6] reg_tst_ldo26_selfb
1080 // [7] reg_pd_dm2p6ldo = 1'b0
1081 // [9:8] reg_tst_ldo11_cmp_selfb
1082 // [11:10] reg_tst_ldo11_clk_selfb
1083 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x0A00+(0x4e)*2, 0x0000);
1084
1085 // [1:0] reg_mpll_loop_div_first feedback divider 00:div by 1 01:div by 2 10:div by 4 11:div by 8
1086 // [15:8] reg_mpll_loop_div_second feedback divider, div by binary data number
1087 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x0A00+(0x33)*2, 0x1201);
1088
1089 // [2:0] reg_mpll_ictrl charge pump current control
1090 // [3] reg_mpll_in_sel 1.8V or 3.3V reference clock domain select (1'b0=0==>3.3 V reference clock domain)
1091 // [4] reg_mpll_xtal2adc_sel select the XTAL clock bypass to MPLL_ADC_CLK
1092 // [5] reg_mpll_xtal2next_pll_sel crystal clock bypass to next PLL select
1093 // [6] reg_mpll_vco_offset set VCO initial offset frequency
1094 // [7] reg_mpll_pd gated reference clock and power down PLL analog_3v: 1=power down
1095 // [8] reg_xtal_en XTAL enable register; 1: enable
1096 // [10:9] reg_xtal_sel XTAL driven strength select.
1097 // [11] reg_mpll_porst MPLL input power on reset, connect to reg as MPLL_RESET
1098 // [12] reg_mpll_reset PLL software reset; 1:reset
1099 // [13] reg_pd_dmpll_clk XTAL to MPLL clock reference power down
1100 // [14] reg_pd_3p3_1 XTAL to CLK_24M_3P3_1 power down
1101 // [15] reg_pd_3p3_2 XTAL to CLK_24M_3P3_2 power down
1102 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x0A00+(0x35)*2, 0x1803);
1103 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x0A00+(0x35)*2, 0x0003);
1104
1105 // [0] reg_mpll_clk_dp_pd dummy
1106 // [1] reg_adc_clk_pd ADC output clock power down
1107 // [2] reg_mpll_div2_pd MPLL_DIV2 power down
1108 // [3] reg_mpll_div3_pd MPLL_DIV3 power down
1109 // [4] reg_mpll_div4_pd MPLL_DIV4 power down
1110 // [5] reg_mpll_div8_pd MPLL_DIV8 power down
1111 // [6] reg_mpll_div10_pd MPLL_DIV10 power down
1112 // `RIU_W((`RIUBASE_ADCPLL>>1)+7'h30, 2'b11, 16'h2400); // divide ADC clock to 24Mhz = 24*36/36
1113 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x0A00+(0x30)*2, 0x2400);
1114
1115 // $display("--------------------------------------");
1116 // $display("Initialize ADC I/Q");
1117 // $display("--------------------------------------");
1118
1119 // [0] Q channel ADC power down
1120 // [1] I channel ADC power down
1121 // [2] Q channel clamp enable. 0:enable, 1:disable
1122 // [3] I channel clamp enable. 0:enable, 1:disable
1123 // [6:4] I channel input mux control;
1124 // 3'b000=I channel ADC calibration mode input
1125 // 3'b001=VIF signal from VIFPGA
1126 // 3'b100=DVB or ATSC mode input from PAD_I(Q)P(M)
1127 // all the other combination are only for test mode, don't use without understanding.
1128 // [10:8] Q channel input mux control;
1129 // 3'b000=Q channel ADC calibration mode input
1130 // 3'b001=VIF signal from VIFPGA 3'b010 = SSIF signal from PAD_SIFP(M)
1131 // 3'b100=DVB or ATSC mode input from PAD_I(Q)P(M)
1132 // all the other combination are only for test mode, don't use without understanding.
1133 // [12] ADC I,Q swap enable; 1: swap
1134 // [13] ADC clock out select; 1: ADC_CLKQ
1135 // [14] ADC linear calibration bypass enable; 1:enable
1136 // [15] ADC internal 1.2v regulator control always 0 in T3
1137 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x0A00+(0x01)*2, 0x0440);
1138
1139 // [2:0] reg_imuxs_s
1140 // [6:4] reg_qmuxs_s
1141 // [9:8] reg_iclpstr_s
1142 // [13:12] reg_qclpstr_s
1143 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x0A00+(0x45)*2, 0x0000);
1144
1145 //bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x0A00+(0x51)*2, 0x0021);
1146
1147 // [0] Channel I ADC power down: 1=power dwon
1148 // [1] Channel Q ADC power down: 1=power dwon
1149 // [2] power down clamp buffer for test mode
1150 // [3] change ADC reference voltage for SSIF
1151 // [6:4] ADC source bias current control
1152 // [9:8] XTAL receiver amp gain
1153 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x0A00+(0x0c)*2, 0x0002);
1154
1155 // [0] reg_linear_cal_start_q 0 0 1
1156 // [1] reg_linear_cal_mode_q 0 0 1
1157 // [2] reg_linear_cal_en_q 0 0 1
1158 // [3] reg_linear_cal_code0_oren_q 0 0 1
1159 // [6:4] reg_linear_cal_status_sel_q 2 0 3
1160 // [7] reg_pwdn_vcalbuf 0 0 1
1161 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x0A00+(0x0f)*2, 0x0000);
1162
1163 // [3:0] clamp voltage control
1164 // 3'b000 = 0.7v
1165 // 3'b001 = 0.75v
1166 // 3'b010 = 0.5v
1167 // 3'b011 = 0.4v
1168 // 3'b100 = 0.8v
1169 // 3'b101 = 0.9v
1170 // 3'b110 = 0.65v
1171 // 3'b111 = 0.60v
1172 // [4] REFERENCE power down
1173 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x0A00+(0x20)*2, 0x0000);
1174
1175 // Set ADC gain is 1
1176 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x0A00+(0x0b)*2, 0x0909);
1177
1178 // Disable ADC Sign bit
1179 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x0A00+(0x2e)*2, 0x0000);
1180
1181 // ADC I channel offset
1182 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x0A00+(0x2a)*2, 0x0c00);
1183
1184 // ADC Q channel offset
1185 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x0A00+(0x2b)*2, 0x0c00);
1186
1187 // [2:0]reg_acl_ref
1188 // [5:4]reg_acl_isel
1189 // [8] reg_xtal_pm_isel
1190 // [9] reg_bond_mode
1191 // [10] reg_clk_bond_mode
1192 // [11] reg_clk_usb_3p3_en
1193 // [13:12] reg_iq_ctrl = 2'd1
1194 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x0A00+(0x19)*2, 0x1e00);
1195
1196 // [ 4:0]reg_ckg_bist[4:0]
1197 // [11:8]reg_ckg_adcd_d2[3:0]
1198 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x0900+(0x1c)*2, 0x0000);
1199
1200 // [ 4:0]reg_ckg_dvbtm_sram_t11x_t22x[4:0]
1201 // [12:8]reg_ckg_dvbtm_sram_t11x_t24x[4:0]
1202 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x0900+(0x1e)*2, 0x0000);
1203
1204
1205 // -------------------------------------------------------------------
1206 // Release clock gating
1207 // -------------------------------------------------------------------
1208
1209 // [0] reg_xtal_en
1210 // [9:8] reg_clk_pd_iic
1211 // [10] reg_clk_pd_all
1212 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x0900+(0x09)*2, 0x0101);
1213
1214 // [3:0] reg_ckg_adcd
1215 // [7:4] reg_ckg_sadc
1216 // [11:8] reg_ckg_iicm
1217 // [13:12] reg_ckg_sbus
1218 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x0900+(0x0a)*2, 0x0000);
1219
1220 // [5:0] reg_ckg_mcu
1221 // [6] reg_ckg_live
1222 // [11:8] reg_ckg_inner
1223 // bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x0900+(0x0b)*2, 0x0030);
1224 //set MCU ckg to 108MHz by jason
1225 // reg_ckg_mcu[4:2] = 0x0
1226 // reg_ckg_mcu[5] = 0x0
1227 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x0900+(0x0b)*2, 0x0020);
1228 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x0900+(0x0b)*2, 0x0000);
1229
1230 // @0x0910
1231 // [3:0] reg_ckg_dvbtm_adc
1232 // [6:4] reg_ckg_dvbt_inner1x
1233 // [10:8] reg_ckg_dvbt_inner2x
1234 // [14:12] reg_ckg_dvbt_inner4x
1235 //DVBT2
1236 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x0900+(0x10)*2, 0x1110);
1237
1238 // @0x0911
1239 // [2:0] reg_ckg_dvbt_outer1x
1240 // [6:4] reg_ckg_dvbt_outer2x
1241 // [11:8] reg_ckg_dvbtc_outer2x
1242 //DVBT2
1243 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x0900+(0x11)*2, 0x0111);
1244
1245 // @0x0912
1246 // [3:0] reg_ckg_dvbtm_ts
1247 // [4] reg_dvbtm_ts_out_mode
1248 // [5] reg_dvbtm_ts_clk_pol
1249 // [15:8] reg_dvbtm_ts_clk_divnum
1250 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x0900+(0x12)*2, 0x1418);
1251
1252 // @0x0913
1253 // [5:0] reg_ckg_spi
1254 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x0900+(0x13)*2, 0x0020);
1255
1256 // @0x0914
1257 // [12:8] reg_ckg_dvbtm_sram_t1o2x_t22x
1258 //DVBT2
1259 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x0900+(0x14)*2, 0x0000);
1260
1261 // @0x0915
1262 // [3:0] reg_ckg_dvbc_inner
1263 // [6:4] reg_ckg_dvbc_eq
1264 // [10:8] reg_ckg_dvbc_eq8x
1265 //DVBT2
1266 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x0900+(0x15)*2, 0x0111);
1267
1268 // @0x0916
1269 // [8:4] reg_ckg_dvbtm_sram_adc_t22x
1270 //DVBT2
1271 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x0900+(0x16)*2, 0x0001);
1272
1273 // @0x0917
1274 // [4:0] reg_ckg_dvbtm_sram_t12x_t22x
1275 // [12:8] reg_ckg_dvbtm_sram_t12x_t24x
1276 //DVBT2
1277 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x0900+(0x17)*2, 0x0000);
1278
1279 // @0x0918
1280 // [4:0] reg_ckg_dvbtm_sram_t14x_t24x
1281 // [12:8] reg_ckg_dvbtm_ts_in
1282 //DVBT2
1283 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x0900+(0x18)*2, 0x0400);
1284
1285 // @0x0919
1286 // [2:0] reg_ckg_tdp_jl_inner1x
1287 // [6:4] reg_ckg_tdp_jl_inner4x
1288 // [15:8] reg_ckg_miu
1289 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x0900+(0x19)*2, 0x3c00);
1290
1291 // @0x091a
1292 // [6:4] reg_ckg_dvbt2_inner1x
1293 // [10:8] reg_ckg_dvbt2_inner2x
1294 // [14:12] reg_ckg_dvbt2_inner4x
1295 //DVBT2
1296 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x0900+(0x1a)*2, 0x0000);
1297
1298 // @0x090e
1299 // [3:0] reg_ckg_dvbs2_ldpc_inner_sram
1300 // [7:4] reg_ckg_dvbs_viterbi_sram
1301 //DVBT2
1302 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x0900+(0x0e)*2, 0x0000);
1303
1304 // @0x091b
1305 // [2:0] reg_ckg_dvbt2_outer1x
1306 // [6:4] reg_ckg_dvbt2_outer2x
1307 // [10:8] reg_ckg_syn_miu
1308 // [14:12] reg_ckg_syn_ts
1309 //DVBT2
1310 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x0900+(0x1b)*2, 0x0000);
1311
1312 // @0x091c
1313 // [4:0] reg_ckg_bist
1314 // [11:8] reg_ckg_adcd_d2
1315 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x0900+(0x1c)*2, 0x0000);
1316
1317 // @0x091d
1318 // [3:0] reg_ckg_dvbtm_adc_eq_1x
1319 // [7:4] reg_ckg_dvbtm_adc_eq_0p5x
1320 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x0900+(0x1d)*2, 0x0000);
1321
1322 // @0x0921
1323 // [2:0] reg_ckg_tdp_teq_inner1x
1324 // [14:12] reg_ckg_tdp_teq_inner2x
1325 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x0900+(0x21)*2, 0x0000);
1326
1327 // @0x0922
1328 // [3:0] reg_ckg_dvbt_t2_inner0p5x_dvbc_eq1x
1329 // [7:4] reg_ckg_dvbt_t2_inner2x_dvbc_eq4x
1330 // [11:8] reg_ckg_dvbt_t2_inner1x
1331 //DVBT2
1332 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x0900+(0x22)*2, 0x0000);
1333
1334 // [1:0] reg_iicm_pad_sel
1335 // [4] reg_i2c_sbpm_en
1336 // [12:8] reg_i2c_sbpm_idle_num
1337 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x0900+(0x08)*2, 0x0a01);
1338
1339 // [8] reg_turn_off_pad
1340 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x0900+(0x28)*2, 0x0000);
1341
1342 // @0x0970
1343 // [3:0] reg_ckg_dvbt_inner2x_srd0p5x
1344 // [7:4] reg_ckg_dvbt2_inner2x_srd0p5x
1345 // [12:8] reg_ckg_dvbtm_sram_t1outer1x_t24x
1346 //DVBT2
1347 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x0900+(0x70)*2, 0x0000);
1348
1349 // @0x0971
1350 // [4:0] reg_ckg_dvbtm_sram_t12x_t24x_srd1x
1351 // [12:8] reg_ckg_dvbtm_sram_t14x_t24x_srd1x
1352 //DVBT2
1353 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x0900+(0x71)*2, 0x0000);
1354
1355 // @0x0972
1356 // [6:0] reg_ckg_dvbt2_s2_bch_out
1357 // [12:8] reg_ckg_dvbt2_outer2x
1358 //DVBT2
1359 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x0900+(0x72)*2, 0x0000);
1360
1361 // @0x0973
1362 // [3:0] reg_ckg_dvbt2_inner4x_s2_inner
1363 //DVBT2
1364 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x0900+(0x73)*2, 0x0000);
1365
1366 // @0x0974
1367 // [4:0] reg_ckg_dvbtm_sram_t12x_t24x_s2inner
1368 // [12:8] reg_ckg_dvbtm_sram_t14x_t24x_s2inner
1369 //DVBT2
1370 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x0900+(0x74)*2, 0x0000);
1371
1372 // @0x0975
1373 // [4:0] reg_ckg_dvbtc_rs
1374 // [11:8] reg_ckg_dvbs_outer2x_dvbt_outer2x
1375 // [15:12] reg_ckg_dvbs_outer2x_dvbt_outer2x_miu
1376 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x0900+(0x75)*2, 0xc101);
1377
1378 // @0x0976
1379 // [4:0] reg_ckg_dvbs_outer2x_dvbt_outer2x_dvbt2_inner2x
1380 //DVBT2
1381 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x0900+(0x76)*2, 0x000c);
1382
1383 // @0x0977
1384 // [3:0] reg_ckg_dvbt2_inner4x_dvbtc_rs
1385 // [8:4] reg_ckg_dvbtm_sram_adc_t22x_dvbtc_rs
1386 //DVBT2
1387 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x0900+(0x77)*2, 0x0000);
1388
1389 // $display("--------------------------------------");
1390 // $display("Initialize Transport Stream synthesizer and APLL");
1391 // $display("--------------------------------------");
1392
1393 // [15:0] reg_synth_set[15: 0]
1394 // [ 7:0] reg_synth_set[23:16]
1395 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x0900+(0x51)*2, 0x0000);
1396 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x0900+(0x52)*2, 0x0040);
1397
1398
1399 // [0] reg_synth_reset
1400 // [1] reg_synth_ssc_en
1401 // [2] reg_synth_ssc_mode
1402 // [4] reg_synth_sld
1403 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x0900+(0x50)*2, 0x0010);
1404
1405 // [1:0] reg_apll_loop_div_first
1406 // [15:8] reg_apll_loop_div_second
1407 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x0900+(0x57)*2, 0x0000);
1408
1409 // [0] reg_apll_pd
1410 // [1] reg_apll_reset
1411 // [2] reg_apll_porst
1412 // [3] reg_apll_vco_offset
1413 // [4] reg_apll_en_ts
1414 // [5] reg_apll_endcc
1415 // [6] reg_apll_clkin_sel
1416 // [8] reg_apll_ts_mode
1417 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x0900+(0x55)*2, 0x0100);
1418 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x0900+(0x55)*2, 0x0110);
1419
1420 // [16:0] reg_apll_test
1421 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x0900+(0x59)*2, 0x0000);
1422
1423 // 0x0920
1424 // [3:0] reg_ckg_ts_apll_div[2:0]
1425 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x0900+(0x20)*2, 0x0004);
1426
1427 //if(_sDMD_MSB124X_InitData.u8WO_Sdram==0)
1428 {
1429 // -------------------------------------------------------------------
1430 // initialize MIU
1431 // -------------------------------------------------------------------
1432 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x1200+(0x0f)*2, 0x0000);
1433 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x1200+(0x0f)*2, 0x0000);
1434 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x1200+(0x0f)*2, 0x0000);
1435 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x1200+(0x0f)*2, 0x0c01);
1436 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x1200+(0x0f)*2, 0x0c00);
1437
1438
1439 // set frequence 180MHz
1440 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x1200+(0x11)*2, 0x60cc);
1441 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x1200+(0x11)*2, 0x00cc);
1442 //bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x1200+(0x11)*2, 0x0066);
1443 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x1200+(0x11)*2, 0x004c); // 133Mhz
1444 //bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x1200+(0x10)*2, 0x2666);
1445 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x1200+(0x10)*2, 0x33f8); // 133Mhz
1446 // yihao 20130925 for new apll model
1447 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x1200+(0x12)*2, 0x0000);
1448 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x1200+(0x13)*2, 0x0000);
1449 // yihao 20130925 for new apll model
1450 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x1200+(0x16)*2, 0x0000);
1451 //bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x1200+(0x1c)*2, 0x0080);
1452 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x1200+(0x1c)*2, 0x00b0); //fine tune by Yihao Lo
1453
1454 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x1200+(0x01)*2, 0x8100);
1455 // cke : [0]
1456 // reg_self_refresh : [1]
1457 // reg_dynamic_cke : [2]
1458 // reg_dynamic_ck_odt : [3]
1459 // reg_dram_bus : [5:4] 00: 16b, 01: 32b, 10: 64b
1460 // reg_dram_type : [7:6] 00: sdr, 01: ddr, 10: ddr2
1461 // reg_4ba : [8] 0: 2bk, 1: 4bk
1462 // reg_col_size : [10:9]
1463 // reg_cke_oenz : [12]
1464 // reg_dq_oenz : [13]
1465 // reg_adr_oenz : [14]
1466 // reg_cs_z : [15]
1467 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x1200+(0x01)*2, 0xe100);
1468 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x1200+(0x01)*2, 0x8100);
1469 //bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x1200+(0x02)*2, 0x0360);
1470 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x1200+(0x02)*2, 0x0371); //fine tune by Yihao Lo
1471 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x1200+(0x03)*2, 0x0030);
1472 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x1200+(0x04)*2, 0x33c9);
1473 // reg_tRAS : [3:0] 9
1474 // reg_tRC : [7:4] c
1475 // reg_tRCD : [11:8] 3
1476 // reg_tRP : [15:12] 3
1477 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x1200+(0x05)*2, 0x4232);
1478 // reg_tRRD : [3:0] 2
1479 // tWR : [7:4] 3
1480 // reg_tMRD : [11:8] 2
1481 // reg_tRTP : [15:12] 4
1482 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x1200+(0x06)*2, 0x5532);
1483 // reg_w2r_dly(tWTR) : [3:0] 2
1484 // reg_w2r_oen_dly : [7:4] 3
1485 // reg_r2w_dly(tRTW) : [11:8] 5
1486 // reg_r2w_oen_dly : [15:12] 5
1487 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x1200+(0x07)*2, 0x400c);
1488 // tRFC : [5:0] c
1489 // reg_tRAS[4] : [6] 0
1490 // reg_tRC[4] : [7] 0
1491 // reg_write_latency : [10:8] 0
1492 // reg_tCCD : [15:14] 1
1493 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x1200+(0x0e)*2, 0x1800);
1494
1495 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x1200+(0x23)*2, 0x7ffe);
1496
1497 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x1200+(0x20)*2, 0xc001);
1498
1499 //delay 1
1500 MsOS_DelayTaskUs(100);
1501
1502 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x1200+(0x0f)*2, 0x0c01);
1503 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x1200+(0x0f)*2, 0x0c00);
1504 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x1200+(0x0f)*2, 0x0c01);
1505 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x1200+(0x0f)*2, 0x0c00);
1506
1507 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x1200+(0x01)*2, 0x010d);
1508
1509
1510 // $display("--------Initial DRAM start here!!!");
1511 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x1200+(0x00)*2, 0x0001);
1512
1513 // wait(test_chip_top.dut.i_dig_top.miu_inst.miu_reg_0.init_done);
1514 bRet &= _MDrv_DMD_MSB124X_GetReg(0x1201, &u8_tmp);
1515 //printf(("[MSB124X]MIU wait init done, u8_tmp=0x%x, bRet=0x%x\n", u8_tmp, bRet));
1516 while (u8_tmp != 0x80)
1517 {
1518 if (u8_timeout++ > 200)
1519 {
1520 printf(("[MSB124X][err]MIU init failure...\n"));
1521 return FALSE;
1522 }
1523 // 10us delay
1524 MsOS_DelayTaskUs(10);
1525 bRet &= _MDrv_DMD_MSB124X_GetReg(0x1201, &u8_tmp);
1526 }
1527 //printf(("[MSB124X]MIU init done, u8_tmp=0x%x, bRet=0x%x\n", u8_tmp, bRet));
1528
1529 // $display("--------Initial Done");
1530 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x1200+(0x08)*2, 0x0001);
1531
1532 // $display("-------------------------");
1533 // $display("-- miu self test start --");
1534 // $display("-------------------------");
1535 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x1200+(0x71)*2, 0x0000);
1536 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x1200+(0x72)*2, 0x0010);
1537 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x1200+(0x74)*2, 0x5aa5);
1538 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x1200+(0x70)*2, 0x0001);
1539
1540 // #10000;
1541 //delay 1
1542 MsOS_DelayTaskUs(100);
1543
1544 //wait test_finish
1545 bRet &= _MDrv_DMD_MSB124X_GetReg((0x1200 + (0x70) * 2 + 1), &u8_tmp);
1546 //printf(("[MSB124X]MIU wait test done, u8_tmp=0x%x,bRet=0x%x\n", u8_tmp, bRet));
1547 while ((u8_tmp & 0x80) != 0x80)
1548 {
1549 if (u8_timeout++ > 200)
1550 {
1551 printf(("[MSB124X][err]MIU self test NOT finished...\n"));
1552 return FALSE;
1553 }
1554 // 10us delay
1555 MsOS_DelayTaskUs(10);
1556 bRet &= _MDrv_DMD_MSB124X_GetReg((0x1200 + (0x70) * 2 + 1), &u8_tmp);
1557 }
1558
1559 // #10000;
1560 //delay 1
1561 MsOS_DelayTaskUs(100);
1562
1563 // MIU self test FAIL let program stuck in this while loop
1564 bRet &= _MDrv_DMD_MSB124X_GetReg((0x1200 + (0x70) * 2 + 1), &u8_tmp);
1565
1566 if (u8_tmp == 0x40)
1567 {
1568 printf(("@MSB124X, error, MIU self test fail !!!!\n"));
1569 bRet = FALSE;
1570 }
1571 else
1572 {
1573 printf(("@MSB124X, MIU self test successful.\n"));
1574 }
1575
1576 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x1200+(0x23)*2, 0x0000);
1577
1578 // -------------------------------------------------------------------
1579 // initialize MIU finish
1580 // -------------------------------------------------------------------
1581 }
1582 // -------------------------------------------------------------------
1583 // Turn on pads
1584 // -------------------------------------------------------------------
1585
1586 // ------Turn off all pad in
1587 // [0] reg_set_pad_low
1588 // [1] reg_set_pad_high
1589 // [2] reg_set_i2cs_pad_low
1590 // [3] reg_set_i2cs_pad_high
1591 // [8] reg_turn_off_pad
1592 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x0900+(0x28)*2, 0x0000);
1593
1594 // ------I2CM pad on
1595 // [1:0] reg_iicm_pad_sel[1:0] 1:iicm enable 2:UART enable
1596 // [4] reg_i2c_sbpm_en 1: enable I2CS bypass to I2CM function
1597 // [12:8] reg_i2c_sbpm_idle_num[4:0] a: default
1598 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x0900+(0x08)*2, 0x0a01);
1599
1600 // ------Transport Stream pad on (except TS ERR pad)
1601 // [15:0] reg_en_ts_pad[15:0] 0x00ff:normal TS location 0xff00:reverse TS location
1602 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x0900+(0x2d)*2, 0x00ff);
1603
1604 // ------Transport Stream pad on (TS ERR pad)
1605 // [0] reg_en_ts_err_pad 1: enable
1606 // [4] reg_ts_err_pol 1: inverse 0:normal
1607 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x0900+(0x2e)*2, 0x0000);
1608
1609 // ------AGC pad on
1610 // [0] reg_ifagc_t_enable
1611 // [1] reg_ifagc_t_odmode
1612 // [2] reg_ifagc_t_data_sel
1613 // [4] reg_ifagc_t_force_enable
1614 // [5] reg_ifagc_t_force_value
1615 // [8] reg_ifagc_s_enable
1616 // [9] reg_ifagc_s_odmode
1617 // [10] reg_ifagc_s_data_sel
1618 // [12] reg_ifagc_s_force_enable
1619 // [13] reg_ifagc_s_force_value
1620 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x0a00+(0x18)*2, 0x0001);
1621
1622 //DMD_UNLOCK();
1623 #ifdef MS_DEBUG
1624 printf("[msb124x][end]MSB124X_HW_init, bRet=0x%x\n",bRet);
1625 #endif
1626 return bRet;
1627 }
1628
_Load2Sdram(MS_U8 * u8_ptr,MS_U16 data_length,MS_U16 sdram_win_offset_base)1629 static MS_BOOL _Load2Sdram(MS_U8 *u8_ptr, MS_U16 data_length, MS_U16 sdram_win_offset_base)
1630 {
1631 MS_BOOL bRet = true;
1632 MS_U16 sdram_win_offset = sdram_win_offset_base;
1633 MS_U16 x_data_offset = 0;
1634 MS_U16 y_cir_addr = 0;
1635 #ifdef MS_DEBUG
1636 MS_U32 u32tmm_3 = 0, u32tmm_4 = 0;
1637 #endif
1638 tMSB124XData *pDemod = DEMOD_GET_ACTIVE_NODE();
1639
1640 #ifdef MS_DEBUG
1641 DBG_DEMOD_FLOW(printf("%s(),%d\n",__func__,__LINE__));
1642 DBG_DEMOD_LOAD_I2C(printf("[msb124x][beg]Load2Sdram, len=0x%x, win_offset=0x%x\n",data_length,sdram_win_offset_base));
1643 u32tmm_3 = MsOS_GetSystemTime();
1644 #endif
1645
1646 // mask miu access for all and mcu
1647 bRet &= _MDrv_DMD_MSB124X_SetReg(0x1200+(0x23)*2 + 1,0x0f);
1648 bRet &= _MDrv_DMD_MSB124X_SetReg(0x1200+(0x23)*2,0xf0);
1649 // 10us delay
1650 MsOS_DelayTaskUs(10);
1651
1652 // Disable MCU
1653 bRet &= _MDrv_DMD_MSB124X_SetReg(0x0b00+(0x19)*2, 0x03);
1654
1655 if (pDemod->_sDMD_MSB124X_InitData.bEnableSPILoadCode)
1656 {
1657 MS_U32 u32Addr = 0;
1658
1659 u32Addr = (MS_U32)sdram_win_offset_base * 0x1000; // unit: 4K
1660 bRet &= MDrv_DMD_SSPI_MIU_Writes(u32Addr, u8_ptr, data_length);
1661 #ifdef MS_DEBUG
1662 DBG_DEMOD_LOAD_I2C(printf("[msb124x]u32Addr=%08lx\n",u32Addr));
1663 #endif
1664
1665 #if (SDRAM_DATA_CHECK == 1)
1666 #ifdef MS_DEBUG
1667 DBG_DEMOD_LOAD_I2C(printf("[msb124x]SDRAM data check...\n"));
1668 #endif
1669 MS_U16 i = 0, j = 0, index = 0;
1670 MS_U8 buf[SPI_DEVICE_BUFFER_SIZE]= {0};
1671
1672 if((data_length % SPI_DEVICE_BUFFER_SIZE) == 0)
1673 index = data_length / SPI_DEVICE_BUFFER_SIZE;
1674 else
1675 index = data_length / SPI_DEVICE_BUFFER_SIZE + 1;
1676
1677 for (i=0; i<index; i++)
1678 {
1679 memset(buf, 0x00, SPI_DEVICE_BUFFER_SIZE);
1680
1681 bRet &= MDrv_DMD_SSPI_MIU_Reads(u32Addr+SPI_DEVICE_BUFFER_SIZE*i, buf, SPI_DEVICE_BUFFER_SIZE);
1682 for (j=0; j<SPI_DEVICE_BUFFER_SIZE; j++)
1683 {
1684 if (buf[j] != u8_ptr[SPI_DEVICE_BUFFER_SIZE*i+j])
1685 {
1686 printf("[msb124x]error, u32Addr=0x%08lx, y=0x%x, x=0x%x\n",u32Addr+SPI_DEVICE_BUFFER_SIZE*i+j, buf[j] , u8_ptr[j]);
1687 }
1688 }
1689 }
1690 #ifdef MS_DEBUG
1691 DBG_DEMOD_LOAD_I2C(printf("[msb124x]SDRAM data check...Done\n"));
1692 #endif
1693 #endif
1694 }
1695 else
1696 {
1697 // Change CH from 3 to 0
1698 if (_MSB124X_I2C_CH_Reset(0) == FALSE)
1699 {
1700 printf(">>>MSB124X CH0 Reset:Fail\n");
1701 return FALSE;
1702 }
1703 else
1704 {
1705
1706 // set xData map upper and low bound for 64k DRAM window
1707 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x2B00+(0x63)*2, 0x3F24);
1708
1709 // set xData map offset for 64k DRAM window, 64kbytes alignment
1710 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x2B00+(0x64)*2, 0x0000);
1711
1712 // set xData map upper and low bound for 4k DRAM window
1713 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x2B00+(0x65)*2, 0x2014);
1714
1715 // set xData map offset for 4k DRAM window, 4kbytes alignment
1716 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x2B00+(0x66)*2, sdram_win_offset++);
1717
1718 // enable xData map for DRAM
1719 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x2B00+(0x62)*2, 0x0007);
1720
1721 for(x_data_offset = 0, y_cir_addr = SDRAM_BASE; x_data_offset < data_length;)
1722 {
1723 if (y_cir_addr == 0x6000)
1724 {
1725 //set xData map offset for 4k DRAM window, 4kbytes alignment
1726 // 0x1000, 4096 bytes
1727 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x2B00+(0x66)*2, sdram_win_offset++);
1728 y_cir_addr = SDRAM_BASE;
1729 }
1730
1731 // max 0x200, error above.....
1732
1733 if((data_length - x_data_offset) >= LOAD_CODE_I2C_BLOCK_NUM)
1734 {
1735 bRet &= _MDrv_DMD_MSB124X_SetRegs(y_cir_addr, (u8_ptr + x_data_offset),LOAD_CODE_I2C_BLOCK_NUM);
1736 y_cir_addr += LOAD_CODE_I2C_BLOCK_NUM;
1737 x_data_offset += LOAD_CODE_I2C_BLOCK_NUM;
1738 }
1739 else
1740 {
1741 bRet &= _MDrv_DMD_MSB124X_SetRegs(y_cir_addr, (u8_ptr + x_data_offset),data_length - x_data_offset);
1742 y_cir_addr += (data_length - x_data_offset);
1743 x_data_offset += (data_length - x_data_offset);
1744 }
1745 }
1746 #ifdef MS_DEBUG
1747 DBG_DEMOD_LOAD_I2C(printf("[msb124x]x_data_offset=%d,y_cir_addr=%d,z_block_num=%d\n",x_data_offset,y_cir_addr,sdram_win_offset));
1748 #endif
1749 #if (SDRAM_DATA_CHECK == 1)
1750 // beg data check.
1751 #ifdef MS_DEBUG
1752 DBG_DEMOD_LOAD_I2C(printf("[msb124x]SDRAM data check...\n"));
1753 #endif
1754
1755 sdram_win_offset = sdram_win_offset_base;
1756
1757 // set xData map offset for 4k DRAM window, 4kbytes alignment
1758 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x2B00+(0x66)*2, sdram_win_offset++);
1759
1760 for(x_data_offset = 0, y_cir_addr = SDRAM_BASE; x_data_offset < data_length;)
1761 {
1762 MS_U8 u8_tmp;
1763 if (y_cir_addr == 0x6000)
1764 {
1765 //set xData map offset for 4k DRAM window, 4kbytes alignment
1766 // 0x1000, 4096 bytes
1767 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x2B00+(0x66)*2, sdram_win_offset++);
1768 y_cir_addr = SDRAM_BASE;
1769 }
1770
1771 bRet &= _MDrv_DMD_MSB124X_GetReg(y_cir_addr++, &u8_tmp);
1772 if(u8_tmp != *(u8_ptr + x_data_offset++))
1773 {
1774 printf("[msb124x]error, idx=0x%x, y=0x%x, x=0x%x\n",y_cir_addr-1, u8_tmp, *(u8_ptr + x_data_offset-1));
1775 }
1776 }
1777
1778 #ifdef MS_DEBUG
1779 DBG_DEMOD_LOAD_I2C(printf("[msb124x]SDRAM data check...Done\n"));
1780 #endif
1781
1782 // end data check
1783 #endif
1784 // Release xData map for SDRAM
1785 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x2B00+(0x62)*2, 0x0000);
1786
1787 // Channel changed from CH 0x00 to CH 0x03
1788 if (_MSB124X_I2C_CH_Reset(3) == FALSE)
1789 {
1790 ERR_DEMOD_MSB(printf(">>>MSB124X CH3 Reset:Fail\n"));
1791 return FALSE;
1792 }
1793 }
1794 }
1795 #ifdef MS_DEBUG
1796 u32tmm_4 = MsOS_GetSystemTime();
1797 printf("[tmm2]t4-t3 = %ld (%ld - %ld)\n",u32tmm_4-u32tmm_3,u32tmm_4,u32tmm_3);
1798 DBG_DEMOD_LOAD_I2C(printf("[msb124x][end]Load2Sdram, len=0x%x, win_offset=0x%x\n",data_length,sdram_win_offset_base));
1799 if (!bRet) printf("%s %d Error\n",__func__, __LINE__);
1800 #endif
1801
1802 return bRet;
1803 }
1804
1805 //no sdram case
_Load2Sram(MS_U8 * u8_ptr,MS_U16 data_length,MS_U16 sram_win_offset_base)1806 static MS_BOOL _Load2Sram(MS_U8 *u8_ptr, MS_U16 data_length, MS_U16 sram_win_offset_base)
1807 {
1808 MS_BOOL bRet = TRUE;
1809 MS_U16 sram_win_offset = sram_win_offset_base;
1810 MS_U16 x_data_offset = 0;
1811 MS_U16 y_cir_addr = 0;
1812 MS_U8 u8data;
1813 #ifdef MS_DEBUG
1814 MS_U32 u32tmm_3 = 0, u32tmm_4 = 0;
1815 #endif
1816
1817 tMSB124XData *pDemod = DEMOD_GET_ACTIVE_NODE();
1818
1819 UNUSED(sram_win_offset);
1820
1821 #ifdef MS_DEBUG
1822 DBG_DEMOD_FLOW(printf("%s(),%d\n",__func__,__LINE__));
1823 u32tmm_3 = MsOS_GetSystemTime();
1824 #endif
1825
1826 if (pDemod->_sDMD_MSB124X_InitData.bEnableSPILoadCode)
1827 {
1828 MS_U32 u32Addr = 0;
1829 // mask miu access for all and mcu
1830 bRet &= _MDrv_DMD_MSB124X_SetReg(0x1200+(0x23)*2 + 1,0x0f);
1831 bRet &= _MDrv_DMD_MSB124X_SetReg(0x1200+(0x23)*2,0xf0);
1832 // 10us delay
1833 MsOS_DelayTaskUs(10);
1834
1835 // Disable MCU
1836 bRet &= _MDrv_DMD_MSB124X_SetReg(0x0b00+(0x19)*2, 0x03);
1837
1838 // Enable sspi to sram
1839 //[4:4]reg_sspi2sram_en;
1840 bRet &= _MDrv_DMD_MSB124X_GetReg(0x0900 + (0x3a) * 2, &u8data);
1841 bRet &= _MDrv_DMD_MSB124X_SetReg(0x0900 + (0x3a) * 2, u8data|0x10);
1842
1843 //address[31:31] 1:direct to sram, 0:direct to sdram
1844 u32Addr = 0x80000000;//SRAM_BASE<<16;
1845 bRet &= MDrv_DMD_SSPI_MIU_Writes(u32Addr, u8_ptr, data_length);
1846 //debug only, must remove
1847 printf(" @@@ sram download by SPI \n");
1848
1849 #ifdef MS_DEBUG
1850 DBG_DEMOD_LOAD_I2C(printf("[msb124x]u32Addr=%08lx\n",u32Addr));
1851 #endif
1852
1853 #if (SRAM_DATA_CHECK == 1)
1854 #ifdef MS_DEBUG
1855 DBG_DEMOD_LOAD_I2C(printf("[msb124x]SRAM data check...\n"));
1856 #endif
1857 MS_U16 i = 0, j = 0, index = 0;
1858 MS_U8 buf[SPI_DEVICE_BUFFER_SIZE]= {0};
1859
1860 if((data_length % SPI_DEVICE_BUFFER_SIZE) == 0)
1861 index = data_length / SPI_DEVICE_BUFFER_SIZE;
1862 else
1863 index = data_length / SPI_DEVICE_BUFFER_SIZE + 1;
1864
1865 for (i=0; i<index; i++)
1866 {
1867 memset(buf, 0x00, SPI_DEVICE_BUFFER_SIZE);
1868
1869 bRet &= MDrv_DMD_SSPI_MIU_Reads(u32Addr+SPI_DEVICE_BUFFER_SIZE*i, buf, SPI_DEVICE_BUFFER_SIZE);
1870 for (j=0; j<SPI_DEVICE_BUFFER_SIZE; j++)
1871 {
1872 if (buf[j] != u8_ptr[SPI_DEVICE_BUFFER_SIZE*i+j])
1873 {
1874 printf("[msb124x]error, u32Addr=0x%08lx, y=0x%x, x=0x%x\n",u32Addr+SPI_DEVICE_BUFFER_SIZE*i+j, buf[j] , u8_ptr[j]);
1875 }
1876 }
1877 }
1878 #ifdef MS_DEBUG
1879 DBG_DEMOD_LOAD_I2C(printf("[msb124x]SRAM data check...Done\n"));
1880 #endif
1881 #endif
1882
1883 // Disable sspi to sram
1884 //[4:4]reg_sspi2sram_en
1885 bRet &= _MDrv_DMD_MSB124X_GetReg(0x0900 + (0x3a) * 2, &u8data);
1886 bRet &= _MDrv_DMD_MSB124X_SetReg(0x0900 + (0x3a) * 2, u8data&(~0x10));
1887
1888 }
1889 else
1890 {
1891 //
1892
1893 //---------------------------------------------------
1894 if (_MSB124X_I2C_CH_Reset(3) == TRUE)
1895 {
1896 // Start MCU reset
1897 bRet &= _MDrv_DMD_MSB124X_SetReg(0x0b32, 0x01);
1898
1899 // Disable Watch-Dog
1900 bRet &= _MSB124X_I2C_CH_Reset(0) ;
1901 bRet &= _MDrv_DMD_MSB124X_SetReg(0x3008, 0x00);
1902 bRet &= _MDrv_DMD_MSB124X_SetReg(0x3009, 0x00);
1903 bRet &= _MDrv_DMD_MSB124X_SetReg(0x300A, 0x00);
1904 bRet &= _MDrv_DMD_MSB124X_SetReg(0x300B, 0x00);
1905 }
1906 else
1907 {
1908 ERR_DEMOD_MSB( printf(" _MSB124X_I2C_CH_Reset(3) failed \n"));
1909 return FALSE;
1910 }
1911
1912 if (_MSB124X_I2C_CH_Reset(3) == FALSE)
1913 {
1914 ERR_DEMOD_MSB(printf(">>>MSB124X CH3 Reset:Fail\n"));
1915 return FALSE;
1916 }
1917 else
1918 {
1919 //--------------------------------------------------------------------------
1920 // Set xData map for Program SRAM
1921 //--------------------------------------------------------------------------
1922 //set lower bound "xb_eram_hb[5:0]"
1923 bRet &= _MDrv_DMD_MSB124X_SetReg(0x10e1, 0x20);
1924 //set upper bound "xb_eram_lb[5:0]"
1925 bRet &= _MDrv_DMD_MSB124X_SetReg(0x10e0, 0x3f);
1926 //set "reg_xd2eram_hk_mcu_psram_en"
1927 bRet &= _MDrv_DMD_MSB124X_SetReg(0x10e6, 0x08);
1928
1929 if (_MSB124X_I2C_CH_Reset(0) == TRUE)
1930 {
1931 for (x_data_offset = 0, y_cir_addr = SRAM_BASE; x_data_offset < data_length;)
1932 {
1933 if ((data_length - x_data_offset) >= LOAD_CODE_I2C_BLOCK_NUM)
1934 {
1935 bRet &= _MDrv_DMD_MSB124X_SetRegs(y_cir_addr, (u8_ptr + x_data_offset), LOAD_CODE_I2C_BLOCK_NUM);
1936 y_cir_addr += LOAD_CODE_I2C_BLOCK_NUM;
1937 x_data_offset += LOAD_CODE_I2C_BLOCK_NUM;
1938 }
1939 else
1940 {
1941 bRet &= _MDrv_DMD_MSB124X_SetRegs(y_cir_addr, (u8_ptr + x_data_offset), data_length - x_data_offset);
1942 y_cir_addr += (data_length - x_data_offset);
1943 x_data_offset += (data_length - x_data_offset);
1944 }
1945 }
1946
1947 }
1948 else
1949 {
1950 ERR_DEMOD_MSB( printf(" _MSB124X_I2C_CH_Reset(0) failed \n"));
1951 return FALSE;
1952 }
1953
1954
1955 //--------------------------------------------------------------------------
1956 // Release xData map for Program SRAM
1957 //--------------------------------------------------------------------------
1958 //clear "reg_xd2eram_hk_mcu_psram_en"
1959 // `DBG.iic_write( 2, (`RIUBASE_MCU + 8'he6), 8'h00)
1960
1961 if (_MSB124X_I2C_CH_Reset(3) == TRUE)
1962 {
1963 bRet &= _MDrv_DMD_MSB124X_SetReg(0x10e6, 0x00);
1964 }
1965 else
1966 {
1967 ERR_DEMOD_MSB( printf("_MSB124X_I2C_CH_Reset(3) failed \n"));
1968 return FALSE;
1969 }
1970
1971 // Set Inst map for Program SRAM
1972 //set lower bound "SRAM_A_START_ADDR"
1973 bRet &= _MDrv_DMD_MSB124X_SetReg(0x1004, 0x00);
1974 bRet &= _MDrv_DMD_MSB124X_SetReg(0x1005, 0x00);
1975 bRet &= _MDrv_DMD_MSB124X_SetReg(0x1000, 0x00);
1976 //set upper bound "SRAM_A_END_ADDR"
1977 bRet &= _MDrv_DMD_MSB124X_SetReg(0x1006, 0x7F);
1978 bRet &= _MDrv_DMD_MSB124X_SetReg(0x1007, 0xFF);
1979 bRet &= _MDrv_DMD_MSB124X_SetReg(0x1002, 0x00);
1980 // Enable Program SRAM
1981 bRet &= _MDrv_DMD_MSB124X_SetReg(0x1018, 0x01);
1982
1983 // End MCU reset
1984 bRet &= _MDrv_DMD_MSB124X_SetReg(0x0b32, 0x00);
1985
1986 }
1987 }
1988
1989 #ifdef MS_DEBUG
1990 u32tmm_4 = MsOS_GetSystemTime();
1991 printf("[tmm2]t4-t3 = %ld (%ld - %ld)\n",u32tmm_4-u32tmm_3,u32tmm_4,u32tmm_3);
1992 DBG_DEMOD_LOAD_I2C(printf("[msb124x][end]Load2Sram, len=0x%x, win_offset=0x%x\n",data_length,sram_win_offset_base));
1993 if (!bRet) printf("%s %d Error\n",__func__, __LINE__);
1994 #endif
1995
1996 return bRet;
1997
1998 }
1999
_LoadDspCodeToSDRAM_Boot(void)2000 static MS_BOOL _LoadDspCodeToSDRAM_Boot(void)
2001 {
2002 MS_BOOL bRet = true;
2003 MS_U16 code_size, win_offset;
2004 MS_U8 *data_ptr;
2005 tMSB124XData *pDemod = DEMOD_GET_ACTIVE_NODE();
2006
2007 #ifdef MS_DEBUG
2008 DBG_DEMOD_FLOW(printf("%s(),%d\n",__func__,__LINE__));
2009 DBG_DEMOD_LOAD_I2C(printf("[msb124x][beg]LoadDspCodeToSDRAM_Boot\n"));
2010 #endif
2011
2012 if(!(pDemod->u8DMD_MSB124X_Sdram_Code&MSB124X_BOOT))
2013 {
2014 if(sizeof(MSB124X_LIB) > MSB124X_BOOT_START_ADDR)
2015 {
2016 // boot code
2017 data_ptr = MSB124X_LIB + MSB124X_BOOT_START_ADDR;
2018 code_size = MSB124X_BOOT_END_ADDR - MSB124X_BOOT_START_ADDR + 1;
2019 win_offset = MSB124X_BOOT_WINDOWS_OFFSET;
2020 bRet &= _Load2Sdram(data_ptr,code_size,win_offset);
2021 if(bRet == true)
2022 {
2023 pDemod->u8DMD_MSB124X_Sdram_Code |= MSB124X_BOOT;
2024 }
2025 }
2026 else
2027 {
2028 printf("@msb124x, boot code is unavailable!!!\n");
2029 }
2030 }
2031 #ifdef MS_DEBUG
2032 DBG_DEMOD_LOAD_I2C(printf("[msb124x][end]LoadDspCodeToSDRAM_Boot\n"));
2033 #endif
2034 return bRet;
2035 }
2036
_LoadDspCodeToSDRAM_dvbt2(void)2037 static MS_BOOL _LoadDspCodeToSDRAM_dvbt2(void)
2038 {
2039 MS_BOOL bRet = true;
2040 MS_U16 code_size, win_offset;
2041 MS_U8 *data_ptr;
2042 tMSB124XData *pDemod = DEMOD_GET_ACTIVE_NODE();
2043
2044 #ifdef MS_DEBUG
2045 DBG_DEMOD_FLOW(printf("%s(),%d\n",__func__,__LINE__));
2046 DBG_DEMOD_LOAD_I2C(printf("[msb124x][beg]LoadDspCodeToSDRAM_dvbt2\n"));
2047 #endif
2048
2049 if( !(pDemod->u8DMD_MSB124X_Sdram_Code&MSB124X_DVBT2) )
2050 {
2051 if(sizeof(MSB124X_LIB) > MSB124X_DVBT2_P1_START_ADDR)
2052 {
2053 // dvbt2_p2
2054 data_ptr = MSB124X_LIB + MSB124X_DVBT2_P2_START_ADDR;
2055 code_size = MSB124X_DVBT2_P2_END_ADDR - MSB124X_DVBT2_P2_START_ADDR + 1;
2056 win_offset = MSB124X_DVBT2_P2_WINDOWS_OFFSET;
2057 bRet &= _Load2Sdram(data_ptr,code_size,win_offset);
2058
2059 // dvbt2_p1
2060 data_ptr = MSB124X_LIB + MSB124X_DVBT2_P1_START_ADDR;
2061 code_size = MSB124X_DVBT2_P1_END_ADDR - MSB124X_DVBT2_P1_START_ADDR + 1;
2062 win_offset = MSB124X_DVBT2_P1_WINDOWS_OFFSET;
2063 bRet &= _Load2Sdram(data_ptr,code_size,win_offset);
2064
2065 if(bRet == true)
2066 {
2067 pDemod->u8DMD_MSB124X_Sdram_Code |= MSB124X_DVBT2;
2068 }
2069 }
2070 else
2071 {
2072 ERR_DEMOD_MSB(printf("@msb124x, dvbt2 code is unavailable!!!\n"));
2073 }
2074 }
2075 #ifdef MS_DEBUG
2076 DBG_DEMOD_LOAD_I2C(printf("[msb124x][end]LoadDspCodeToSDRAM_dvbt2\n"));
2077 #endif
2078 return bRet;
2079 }
2080
_LoadDspCodeToSDRAM_dvbs2(void)2081 static MS_BOOL _LoadDspCodeToSDRAM_dvbs2(void)
2082 {
2083 MS_BOOL bRet = true;
2084 MS_U16 code_size, win_offset;
2085 MS_U8 *data_ptr;
2086 tMSB124XData *pDemod = DEMOD_GET_ACTIVE_NODE();
2087
2088 #ifdef MS_DEBUG
2089 DBG_DEMOD_FLOW(printf("%s(),%d\n",__func__,__LINE__));
2090 DBG_DEMOD_LOAD_I2C(printf("[msb124x][beg]LoadDspCodeToSDRAM_dvbs2\n"));
2091 #endif
2092 printf("[msb124x][beg]LoadDspCodeToSDRAM_dvbs2\n");
2093
2094 if(!(pDemod->u8DMD_MSB124X_Sdram_Code&MSB124X_DVBS2))
2095 {
2096 // dvbt code
2097 if(sizeof(MSB124X_LIB) > MSB124X_DVBS2_P1_START_ADDR)
2098 {
2099 // dvbs2_p2
2100 data_ptr = MSB124X_LIB + MSB124X_DVBS2_P2_START_ADDR;
2101 code_size = MSB124X_DVBS2_P2_END_ADDR - MSB124X_DVBS2_P2_START_ADDR + 1;
2102 win_offset = MSB124X_DVBS2_P2_WINDOWS_OFFSET;
2103 bRet &= _Load2Sdram(data_ptr,code_size,win_offset);
2104
2105 // dvbs2_p1
2106 data_ptr = MSB124X_LIB + MSB124X_DVBS2_P1_START_ADDR;
2107 code_size = MSB124X_DVBS2_P1_END_ADDR - MSB124X_DVBS2_P1_START_ADDR + 1;
2108 win_offset = MSB124X_DVBS2_P1_WINDOWS_OFFSET;
2109 bRet &= _Load2Sdram(data_ptr,code_size,win_offset);
2110 if(bRet == true)
2111 {
2112 pDemod->u8DMD_MSB124X_Sdram_Code |= MSB124X_DVBS2;
2113 }
2114 }
2115 else
2116 {
2117 printf("@msb124x, dvbs2 code is unavailable!!!\n");
2118 }
2119 }
2120 #ifdef MS_DEBUG
2121 DBG_DEMOD_LOAD_I2C(printf("[msb124x][end]LoadDspCodeToSDRAM_dvbs2\n"));
2122 #endif
2123 return bRet;
2124 }
2125
2126 //no sdram case -- DVBS
_LoadDspCodeToSRAM_dvbs2(void)2127 static MS_BOOL _LoadDspCodeToSRAM_dvbs2(void)
2128 {
2129 MS_BOOL bRet = true;
2130 MS_U16 code_size, win_offset;
2131 MS_U8 *data_ptr;
2132
2133 tMSB124XData *pDemod = DEMOD_GET_ACTIVE_NODE();
2134
2135 #ifdef MS_DEBUG
2136 DBG_DEMOD_FLOW(printf("%s(),%d\n",__func__,__LINE__));
2137 DBG_DEMOD_LOAD_I2C(printf("[msb124x][beg]LoadDspCodeToSRAM_dvbs2\n"));
2138 #endif
2139
2140
2141 if(!(pDemod->u8DMD_MSB124X_Sram_Code&MSB124X_DVBS2))
2142 {
2143 // dvbs code
2144 if(sizeof(MSB124X_LIB) > MSB124X_DVBS2_P1_START_ADDR)
2145 {
2146 data_ptr = MSB124X_LIB + MSB124X_DVBS2_P1_START_ADDR;
2147 code_size = MSB124X_DVBS2_P1_END_ADDR - MSB124X_DVBS2_P1_START_ADDR + 1;
2148 win_offset = MSB124X_DVBS2_P1_WINDOWS_OFFSET;
2149 bRet &= _Load2Sram(data_ptr,code_size,win_offset);
2150 if(bRet == true)
2151 {
2152 pDemod->u8DMD_MSB124X_Sram_Code |= MSB124X_DVBS2;
2153 }
2154 }
2155 else
2156 {
2157 printf("@msb124x, dvbs2 code is unavailable!!!\n");
2158 }
2159 }
2160 #ifdef MS_DEBUG
2161 DBG_DEMOD_LOAD_I2C(printf("[msb124x][end]LoadDspCodeToSRAM_dvbs2\n"));
2162 #endif
2163 return bRet;
2164 }
2165
2166
_LoadDspCodeToSDRAM_dvbt(void)2167 static MS_BOOL _LoadDspCodeToSDRAM_dvbt(void)
2168 {
2169 MS_BOOL bRet = true;
2170 MS_U16 code_size, win_offset;
2171 MS_U8 *data_ptr;
2172 tMSB124XData *pDemod = DEMOD_GET_ACTIVE_NODE();
2173
2174 #ifdef MS_DEBUG
2175 DBG_DEMOD_FLOW(printf("%s(),%d\n",__func__,__LINE__));
2176 DBG_DEMOD_LOAD_I2C(printf("[msb124x][beg]LoadDspCodeToSDRAM_dvbt\n"));
2177 #endif
2178
2179 if(!(pDemod->u8DMD_MSB124X_Sdram_Code&MSB124X_DVBT))
2180 {
2181 // dvbt code
2182 if(sizeof(MSB124X_LIB) > MSB124X_DVBT_START_ADDR)
2183 {
2184 data_ptr = MSB124X_LIB + MSB124X_DVBT_START_ADDR;
2185 code_size = MSB124X_DVBT_END_ADDR - MSB124X_DVBT_START_ADDR + 1;
2186 win_offset = MSB124X_DVBT_WINDOWS_OFFSET;
2187 bRet &= _Load2Sdram(data_ptr,code_size,win_offset);
2188 if(bRet == true)
2189 {
2190 pDemod->u8DMD_MSB124X_Sdram_Code |= MSB124X_DVBT;
2191 }
2192 }
2193 else
2194 {
2195 printf("@msb124x, dvbt code is unavailable!!!\n");
2196 }
2197 }
2198 #ifdef MS_DEBUG
2199 DBG_DEMOD_LOAD_I2C(printf("[msb124x][end]LoadDspCodeToSDRAM_dvbt\n"));
2200 #endif
2201 return bRet;
2202 }
2203
2204 //no sdram case
_LoadDspCodeToSRAM_dvbt(void)2205 static MS_BOOL _LoadDspCodeToSRAM_dvbt(void)
2206 {
2207 MS_BOOL bRet = true;
2208 MS_U16 code_size, win_offset;
2209 MS_U8 *data_ptr;
2210 tMSB124XData *pDemod = DEMOD_GET_ACTIVE_NODE();
2211
2212 #ifdef MS_DEBUG
2213 DBG_DEMOD_FLOW(printf("%s(),%d\n",__func__,__LINE__));
2214 DBG_DEMOD_LOAD_I2C(printf("[msb124x][beg]LoadDspCodeToSRAM_dvbt\n"));
2215 #endif
2216
2217 if(!(pDemod->u8DMD_MSB124X_Sram_Code&MSB124X_DVBT))
2218 {
2219 // dvbt code
2220 if(sizeof(MSB124X_LIB) > MSB124X_DVBT_START_ADDR)
2221 {
2222 data_ptr = MSB124X_LIB + MSB124X_DVBT_START_ADDR;
2223 code_size = MSB124X_DVBT_END_ADDR - MSB124X_DVBT_START_ADDR + 1;
2224 win_offset = MSB124X_DVBT_WINDOWS_OFFSET;
2225 bRet &= _Load2Sram(data_ptr,code_size,win_offset);
2226 if(bRet == true)
2227 {
2228 pDemod->u8DMD_MSB124X_Sram_Code |= MSB124X_DVBT;
2229 }
2230 }
2231 else
2232 {
2233 printf("@msb124x, dvbt code is unavailable!!!\n");
2234 }
2235 }
2236 #ifdef MS_DEBUG
2237 DBG_DEMOD_LOAD_I2C(printf("[msb124x][end]LoadDspCodeToSRAM_dvbt\n"));
2238 #endif
2239 return bRet;
2240 }
2241
_LoadDspCodeToSDRAM_dvbc(void)2242 static MS_BOOL _LoadDspCodeToSDRAM_dvbc(void)
2243 {
2244 MS_BOOL bRet = true;
2245 MS_U16 code_size, win_offset;
2246 MS_U8 *data_ptr;
2247 tMSB124XData *pDemod = DEMOD_GET_ACTIVE_NODE();
2248
2249 #ifdef MS_DEBUG
2250 DBG_DEMOD_FLOW(printf("%s(),%d\n",__func__,__LINE__));
2251 DBG_DEMOD_LOAD_I2C(printf("[msb124x][beg]LoadDspCodeToSDRAM_dvbc\n"));
2252 #endif
2253
2254 if(!(pDemod->u8DMD_MSB124X_Sdram_Code&MSB124X_DVBC))
2255 {
2256 // dvbc code
2257 if(sizeof(MSB124X_LIB) > MSB124X_DVBC_START_ADDR)
2258 {
2259 data_ptr = MSB124X_LIB + MSB124X_DVBC_START_ADDR;
2260 code_size = MSB124X_DVBC_END_ADDR - MSB124X_DVBC_START_ADDR + 1;
2261 win_offset = MSB124X_DVBC_WINDOWS_OFFSET;
2262 bRet &= _Load2Sdram(data_ptr,code_size,win_offset);
2263 if(bRet == true)
2264 {
2265 pDemod->u8DMD_MSB124X_Sdram_Code |= MSB124X_DVBC;
2266 }
2267 }
2268 else
2269 {
2270 printf("@msb124x, dvbc code is unavailable!!!\n");
2271 }
2272 }
2273 #ifdef MS_DEBUG
2274 DBG_DEMOD_LOAD_I2C(printf("[msb124x][end]LoadDspCodeToSDRAM_dvbc\n"));
2275 #endif
2276 return bRet;
2277 }
2278
2279 //no sdram case
_LoadDspCodeToSRAM_dvbc(void)2280 static MS_BOOL _LoadDspCodeToSRAM_dvbc(void)
2281 {
2282 MS_BOOL bRet = true;
2283 MS_U16 code_size, win_offset;
2284 MS_U8 *data_ptr;
2285 tMSB124XData *pDemod = DEMOD_GET_ACTIVE_NODE();
2286
2287 #ifdef MS_DEBUG
2288 DBG_DEMOD_FLOW(printf("%s(),%d\n",__func__,__LINE__));
2289 DBG_DEMOD_LOAD_I2C(printf("[msb124x][beg]LoadDspCodeToSRAM_dvbc\n"));
2290 #endif
2291
2292 if(!(pDemod->u8DMD_MSB124X_Sram_Code&MSB124X_DVBC))
2293 {
2294 // dvbc code
2295 if(sizeof(MSB124X_LIB) > MSB124X_DVBC_START_ADDR)
2296 {
2297 data_ptr = MSB124X_LIB + MSB124X_DVBC_START_ADDR;
2298 code_size = MSB124X_DVBC_END_ADDR - MSB124X_DVBC_START_ADDR + 1;
2299 win_offset = MSB124X_DVBC_WINDOWS_OFFSET;
2300 bRet &= _Load2Sram(data_ptr,code_size,win_offset);
2301 if(bRet == true)
2302 {
2303 pDemod->u8DMD_MSB124X_Sram_Code |= MSB124X_DVBC;
2304 }
2305 }
2306 else
2307 {
2308 printf("@msb124x, dvbc code is unavailable!!!\n");
2309 }
2310 }
2311 #ifdef MS_DEBUG
2312 DBG_DEMOD_LOAD_I2C(printf("[msb124x][end]LoadDspCodeToSRAM_dvbc\n"));
2313 #endif
2314 return bRet;
2315 }
2316
_LoadDspCodeToSDRAM(MS_U8 code_n)2317 static MS_BOOL _LoadDspCodeToSDRAM(MS_U8 code_n)
2318 {
2319 MS_BOOL bRet = true;
2320 #ifdef MS_DEBUG
2321 MS_U32 u32tmm_7 = 0, u32tmm_8 = 0;
2322 #endif
2323 tMSB124XData *pDemod = DEMOD_GET_ACTIVE_NODE();
2324 MS_U8 u8Data;
2325 #ifdef MS_DEBUG
2326 DBG_DEMOD_FLOW(printf("%s(),%d\n",__func__,__LINE__));
2327 DBG_DEMOD_LOAD_I2C(printf("[msb124x][beg]LoadDspCodeToSDRAM, code_n=0x%x\n",code_n));
2328 u32tmm_7 = MsOS_GetSystemTime();
2329 #endif
2330
2331 if (pDemod->_sDMD_MSB124X_InitData.bEnableSPILoadCode)
2332 {
2333 (pDemod->_sDMD_MSB124X_InitData.fpMSB124x_SPIPAD_En)(TRUE);
2334 // ------enable to use TS_PAD as SSPI_PAD
2335 // [0:0] reg_en_sspi_pad
2336 // [1:1] reg_ts_sspi_en, 1: use TS_PAD as SSPI_PAD
2337 _MDrv_DMD_MSB124X_SetReg2Bytes(0x0900 + (0x3b) * 2, 0x0002);
2338 // ------- MSPI protocol setting
2339 // [8] cpha
2340 // [9] cpol
2341 _MDrv_DMD_MSB124X_GetReg(0x0900+(0x3a)*2+1,&u8Data);
2342 u8Data &= 0xFC;
2343 _MDrv_DMD_MSB124X_SetReg(0x0900+(0x3a)*2+1, u8Data);
2344 // ------- MSPI driving setting
2345 _MDrv_DMD_MSB124X_SetReg2Bytes(0x0900+(0x2c)*2, 0x07ff);
2346 }
2347
2348 switch(code_n)
2349 {
2350 case MSB124X_BOOT:
2351 {
2352 // boot code
2353 bRet &= _LoadDspCodeToSDRAM_Boot();
2354 }
2355 break;
2356 case MSB124X_DVBT2:
2357 {
2358 // dvbt2 code
2359 bRet &= _LoadDspCodeToSDRAM_dvbt2();
2360 }
2361 break;
2362 case MSB124X_DVBT:
2363 {
2364 // dvbt
2365 bRet &= _LoadDspCodeToSDRAM_dvbt();
2366 }
2367 break;
2368 case MSB124X_DVBC:
2369 {
2370 // dvbtc
2371 bRet &= _LoadDspCodeToSDRAM_dvbc();
2372 }
2373 break;
2374 case MSB124X_DVBS2:
2375 {
2376 // dvbtc
2377 bRet &= _LoadDspCodeToSDRAM_dvbs2();
2378 }
2379 break;
2380
2381 case MSB124X_ALL:
2382 default:
2383 {
2384 // boot+dvbt2+dvbt+dvbc
2385 // boot code
2386 bRet &= _LoadDspCodeToSDRAM_Boot();
2387 // dvbt2
2388 bRet &= _LoadDspCodeToSDRAM_dvbt2();
2389 // dvbt
2390 bRet &= _LoadDspCodeToSDRAM_dvbt();
2391 // dvbtc
2392 bRet &= _LoadDspCodeToSDRAM_dvbc();
2393 bRet &= _LoadDspCodeToSDRAM_dvbs2();
2394 }
2395 break;
2396 }
2397
2398 if (pDemod->_sDMD_MSB124X_InitData.bEnableSPILoadCode)
2399 {
2400 // ------disable to use TS_PAD as SSPI_PAD after load code
2401 // [0:0] reg_en_sspi_pad
2402 // [1:1] reg_ts_sspi_en, 1: use TS_PAD as SSPI_PAD
2403 _MDrv_DMD_MSB124X_SetReg2Bytes(0x0900 + (0x3b) * 2, 0x0001);
2404 (pDemod->_sDMD_MSB124X_InitData.fpMSB124x_SPIPAD_En)(FALSE);
2405 }
2406
2407 #ifdef MS_DEBUG
2408 u32tmm_8 = MsOS_GetSystemTime();
2409 printf("[tmm4]t8-t7 = %ld (%ld - %ld)\n",u32tmm_8-u32tmm_7,u32tmm_8,u32tmm_7);
2410 DBG_DEMOD_LOAD_I2C(printf("[msb124x][end]LoadDspCodeToSDRAM, code_n=0x%x, bRet=0x%x\n",code_n,bRet));
2411 #endif
2412
2413 return bRet;
2414 }
2415
2416 //no sdram case
_LoadDspCodeToSRAM(MS_U8 code_n)2417 static MS_BOOL _LoadDspCodeToSRAM(MS_U8 code_n)
2418 {
2419 MS_BOOL bRet = true;
2420 #ifdef MS_DEBUG
2421 // MS_U32 u32tmm_7 = 0, u32tmm_8 = 0;
2422 #endif
2423 tMSB124XData *pDemod = DEMOD_GET_ACTIVE_NODE();
2424
2425 #ifdef MS_DEBUG
2426 DBG_DEMOD_FLOW(printf("%s(),%d\n",__func__,__LINE__));
2427 DBG_DEMOD_LOAD_I2C(printf("[msb124x][beg]LoadDspCodeToSRAM, code_n=0x%x\n",code_n));
2428 // u32tmm_7 = MsOS_GetSystemTime();
2429 #endif
2430
2431 if(code_n == pDemod->u8DMD_MSB124X_Sram_Code)
2432 {
2433 #ifdef MS_DEBUG
2434 printf("[msb124x]LoadDspCodeToSRAM, code is available.\n");
2435 #endif
2436 return bRet;
2437 }
2438
2439 if (pDemod->_sDMD_MSB124X_InitData.bEnableSPILoadCode)
2440 {
2441 (pDemod->_sDMD_MSB124X_InitData.fpMSB124x_SPIPAD_En)(TRUE);
2442 // ------enable to use TS_PAD as SSPI_PAD
2443 // [0:0] reg_en_sspi_pad
2444 // [1:1] reg_ts_sspi_en, 1: use TS_PAD as SSPI_PAD
2445 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x0900 + (0x3b) * 2, 0x0002);
2446 //[4:4]reg_sspi2sram_en;
2447 //bRet &= _MDrv_DMD_MSB124X_GetReg(0x0900 + (0x3a) * 2, &u8data);
2448 //bRet &= _MDrv_DMD_MSB124X_SetReg(0x0900 + (0x3a) * 2, u8data|0x10);
2449
2450 }
2451
2452 switch(code_n)
2453 {
2454 case MSB124X_DVBT:
2455 {
2456 // dvbt
2457 bRet &= _LoadDspCodeToSRAM_dvbt();
2458 }
2459 break;
2460 case MSB124X_DVBC:
2461 {
2462 // dvbtc
2463 bRet &= _LoadDspCodeToSRAM_dvbc();
2464 }
2465 break;
2466 case MSB124X_DVBS2:
2467 {
2468 // dvbs/s2
2469 bRet &= _LoadDspCodeToSRAM_dvbs2();
2470 }
2471 break;
2472 default:
2473 {
2474 // boot code
2475 bRet &= _LoadDspCodeToSRAM_dvbt();
2476 }
2477 break;
2478 }
2479
2480
2481 if (pDemod->_sDMD_MSB124X_InitData.bEnableSPILoadCode)
2482 {
2483 // ------disable to use TS_PAD as SSPI_PAD after load code
2484 // [0:0] reg_en_sspi_pad
2485 // [1:1] reg_ts_sspi_en, 1: use TS_PAD as SSPI_PAD
2486 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x0900 + (0x3b) * 2, 0x0001);
2487 //[4:4]reg_sspi2sram_en
2488 //bRet &= _MDrv_DMD_MSB124X_GetReg(0x0900 + (0x3a) * 2, &u8data);
2489 //bRet &= _MDrv_DMD_MSB124X_SetReg(0x0900 + (0x3a) * 2, u8data&(~0x10));
2490
2491 (pDemod->_sDMD_MSB124X_InitData.fpMSB124x_SPIPAD_En)(FALSE);
2492 }
2493
2494 #ifdef MS_DEBUG
2495 //u32tmm_8 = MsOS_GetSystemTime();
2496 //printf("[tmm4]t8-t7 = %ld (%ld - %ld)\n",u32tmm_8-u32tmm_7,u32tmm_8,u32tmm_7);
2497 DBG_DEMOD_LOAD_I2C(printf("[msb124x][end]LoadDspCodeToSRAM, code_n=0x%x, bRet=0x%x\n",code_n,bRet));
2498 #endif
2499
2500 return bRet;
2501 }
2502
2503
2504
_MSB124X_MEM_switch(MS_U8 mem_type)2505 static MS_BOOL _MSB124X_MEM_switch(MS_U8 mem_type)
2506 {
2507 MS_BOOL bRet = true;
2508 MS_U8 u8_tmp = 0;
2509 MS_U8 u8Data = 0;
2510 MS_U16 timeout = 0;
2511 #ifdef MS_DEBUG
2512 MS_U32 u32tmm_15 = 0, u32tmm_16 = 0;
2513 #endif
2514 tMSB124XData *pDemod = DEMOD_GET_ACTIVE_NODE();
2515
2516 #ifdef MS_DEBUG
2517 DBG_DEMOD_FLOW(printf("%s(),%d\n",__func__,__LINE__));
2518 DBG_DEMOD_LOAD_I2C(printf("[msb124x][beg]MSB124X_MEM_switch, mem_type=0x%x\n",mem_type));
2519 u32tmm_15 = MsOS_GetSystemTime();
2520 #endif
2521
2522 switch(pDemod->eDMD_MSB124X_CurrentDemodulatorType)
2523 {
2524 case E_DMD_MSB124X_DEMOD_DVBT2:
2525 u8Data=1;
2526 break;
2527 case E_DMD_MSB124X_DEMOD_DVBT:
2528 u8Data=2;
2529 break;
2530 case E_DMD_MSB124X_DEMOD_DVBC:
2531 u8Data=3;
2532 break;
2533 case E_DMD_MSB124X_DEMOD_DVBS2:
2534 u8Data=4;
2535 break;
2536 default:
2537 u8Data=2;
2538 return FALSE;
2539 }
2540
2541 if(mem_type == 1)
2542 {
2543
2544 bRet &= _MDrv_DMD_MSB124X_SetReg(0x2B80,0x10);
2545
2546 // SRAM_START_ADDR 0x0000
2547 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x1000,0x0000);
2548 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x1004,0x0000);
2549
2550 // SRAM_END_ADDR 0x7FFF
2551 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x1002,0x0000);
2552 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x1006,0x7FFF);
2553
2554 if(u8Data == 4)
2555 {//DVBS
2556
2557 // Offset to 1M +128 KB
2558 bRet &= _MDrv_DMD_MSB124X_SetReg(0x2B80,0x12);//Uint : 64 KB
2559
2560 // DRAM_START_ADDR 0x28000
2561 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x1008,0x0000);
2562 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x100C,0x8000);
2563
2564 // DRAM_END_ADDR 0x2FFFF
2565 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x100A,0x0000);
2566 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x100E,0xFFFF);
2567 }
2568 else
2569 {//DVBT2,DVBT,DVBC
2570
2571 bRet &= _MDrv_DMD_MSB124X_SetReg(0x2B80,0x10);// Offset to 1M
2572
2573 // DRAM_START_ADDR 0x8000
2574 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x1008,0x0000);
2575 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x100C,0x8000);
2576
2577
2578 // DRAM_END_ADDR 0xFFFF
2579 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x100A,0x0000);
2580 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x100E,0xFFFF);
2581
2582 //Disable romA_en & romB_en
2583 bRet &= _MDrv_DMD_MSB124X_SetReg(0x1038,0x00);
2584 }
2585 // Enable SRAM&SDRAM memory map
2586 bRet &= _MDrv_DMD_MSB124X_SetReg(0x1018,0x05);
2587
2588 // Wait memory map to be enabled
2589 do
2590 {
2591 bRet &= _MDrv_DMD_MSB124X_GetReg(0x1018,&u8_tmp);
2592 if(timeout++ > 500)
2593 {
2594 printf("@msb124x, D+S memory mapping failure.!!!\n");
2595 return FALSE;
2596 }
2597 }
2598 while(u8_tmp != 0x05);
2599 }
2600 else if(mem_type == 0)
2601 {
2602 // Enable SRAM&SDRAM memory map
2603
2604 bRet &= _MDrv_DMD_MSB124X_SetReg(0x2B80,0x10);
2605
2606 // DRAM_START_ADDR 0x8000
2607 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x1008,0x0000);
2608 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x100C,0x0000);
2609
2610
2611 // DRAM_END_ADDR 0xFFFF
2612 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x100A,0x0000);
2613 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x100E,0x7FFF);
2614
2615 // Enable SRAM&SDRAM memory map
2616 bRet &= _MDrv_DMD_MSB124X_SetReg(0x1018,0x04);
2617
2618 // Wait memory map to be enabled
2619 do
2620 {
2621 bRet &= _MDrv_DMD_MSB124X_GetReg(0x1018,&u8_tmp);
2622 if(timeout++ > 500)
2623 {
2624 printf("@msb124x, D memory mapping failure.!!!\n");
2625 return FALSE;
2626 }
2627 }
2628 while(u8_tmp != 0x04);
2629 }
2630 else
2631 {
2632 printf("@msb124x, invalid mem type mapping.\n");
2633 return FALSE;
2634 }
2635
2636 #ifdef MS_DEBUG
2637 u32tmm_16 = MsOS_GetSystemTime();
2638 printf("[tmm8]t16-t15 = %ld (%ld - %ld)\n",u32tmm_16-u32tmm_15,u32tmm_16,u32tmm_15);
2639 DBG_DEMOD_LOAD_I2C(printf("[msb124x][end]MSB124X_MEM_switch, , mem_type=0x%x, bRet=0x%x\n",mem_type,bRet));
2640 #endif
2641
2642 return bRet;
2643 }
2644
_LoadSdram2Sram(MS_U8 CodeNum)2645 static MS_BOOL _LoadSdram2Sram(MS_U8 CodeNum)
2646 {
2647 MS_BOOL bRet = true;
2648 MS_U8 u8_data = 0;
2649 MS_U8 u8_timeout = 0xFF;
2650 tMSB124XData *pDemod = DEMOD_GET_ACTIVE_NODE();
2651
2652
2653 #ifdef MS_DEBUG
2654 MS_U32 u32tmm_17 = 0, u32tmm_18 = 0;
2655 #endif
2656
2657 #ifdef MS_DEBUG
2658 DBG_DEMOD_FLOW(printf("%s(),%d\n",__func__,__LINE__));
2659 DBG_DEMOD_LOAD_I2C(printf("[msb124x][beg]LoadSdram2Sram, g_sram_code=0x%x, codeNum=0x%x\n",u8DMD_MSB124X_Sram_Code,CodeNum));
2660 u32tmm_17 = MsOS_GetSystemTime();
2661 #endif
2662
2663 if(CodeNum == pDemod->u8DMD_MSB124X_Sram_Code)
2664 {
2665 #ifdef MS_DEBUG
2666 printf("[msb124x]LoadSdram2Sram, code is available.\n");
2667 #endif
2668 return bRet;
2669 }
2670 /*
2671 MS_U8 u8_tmp = 0;
2672 MS_U32 u32Timeout = 0;
2673 MS_U8 u8DoneFlag = 0;
2674
2675 bRet &= _MSB124X_MEM_switch(0);
2676
2677 if(CodeNum == MSB124X_DVBT2)
2678 u8_tmp = 1|0x10;
2679 else if(CodeNum == MSB124X_DVBT)
2680 u8_tmp = 2|0x10;
2681 else if(CodeNum == MSB124X_DVBC)
2682 u8_tmp = 3|0x10;
2683 else
2684 u8_tmp = 0|0x10;
2685
2686 // Assign f/w code type to load => 0x11: dvbt2, 0x12: dvbt, 0x13: dvbc
2687 bRet &= _MDrv_DMD_MSB124X_SetReg(0x0900+(0x4f)*2, u8_tmp);
2688
2689 // enable miu mask, miu, mcu, gdma
2690 bRet &= _MDrv_DMD_MSB124X_SetReg(0x1200+(0x23)*2 + 1,0x0f);
2691 bRet &= _MDrv_DMD_MSB124X_SetReg(0x1200+(0x23)*2,0xf0);
2692
2693 MsOS_DelayTaskUs(10);
2694 // enable mcu
2695 bRet &= _MDrv_DMD_MSB124X_SetReg(0x0b00+(0x19)*2, 0x00);
2696
2697 do
2698 {
2699 bRet &= _MDrv_DMD_MSB124X_GetReg(0x0900+(0x4f)*2, &u8DoneFlag);
2700
2701 if (u32Timeout++ > 500)
2702 {
2703 printf("@msb124x, LoadSdram2Sram boot move code fail.!!!\n");
2704 return FALSE;
2705 }
2706 MsOS_DelayTaskUs(1*1000);
2707
2708 }
2709 while(u8DoneFlag != 0xaa);
2710
2711 // mask miu access of mcu
2712 bRet &= _MDrv_DMD_MSB124X_SetReg(0x1200+(0x23)*2,0xf2);
2713
2714 // 10us delay
2715 MsOS_DelayTaskUs(10);
2716
2717 // Disable MCU
2718 bRet &= _MDrv_DMD_MSB124X_SetReg(0x0b00+(0x19)*2, 0x03);
2719
2720 // enable miu mask, miu, mcu, gdma
2721 bRet &= _MDrv_DMD_MSB124X_SetReg(0x1200+(0x23)*2 + 1,0x0f);
2722 bRet &= _MDrv_DMD_MSB124X_SetReg(0x1200+(0x23)*2,0xf0);
2723 */
2724 // mask miu access of fdp, tdi, djb
2725 bRet &= _MDrv_DMD_MSB124X_SetReg(0x1200 + (0x23) * 2 + 1, 0x0f);
2726 bRet &= _MDrv_DMD_MSB124X_SetReg(0x1200 + (0x23) * 2, 0xf0);
2727
2728 // 10us delay
2729 MsOS_DelayTaskUs(10);
2730
2731 // Disable MCU
2732 bRet &= _MDrv_DMD_MSB124X_SetReg(0x0b00+(0x19)*2, 0x03);
2733
2734 // Use GDMA move code from SDRAM to SRAM
2735 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x0300+(0x00)*2, 0x4254); // rst
2736 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x0300+(0x00)*2, 0x4257); // cfg & trig
2737
2738 switch(CodeNum)
2739 {
2740 case 0x02: //DVB-T2 @001000h ~ 008FFFh
2741 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x0300+(0x01)*2, 0x0000); // Set src_addr
2742 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x0300+(0x02)*2, 0x0011); // start from 1M+64k
2743 break;
2744
2745 case 0x04: //DVB-T @010000h ~ 017FFFh
2746 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x0300+(0x01)*2, 0x8000); // Set src_addr
2747 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x0300+(0x02)*2, 0x0011); // start from 1M+96k
2748 break;
2749
2750 case 0x08: //DVB-C @018000h ~ 01FFFFh
2751 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x0300+(0x01)*2, 0x0000); // Set src_addr
2752 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x0300+(0x02)*2, 0x0012); // start from 1M+128k
2753 break;
2754 case 0x10: //DVB-S2 @020000h ~ 027FDFh
2755 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x0300+(0x01)*2, 0x0000); // Set src_addr
2756 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x0300+(0x02)*2, 0x0013); // start from 1M+160k
2757 break;
2758 default:
2759 bRet &= false;
2760 break;
2761 }
2762
2763 // Set dst_addr
2764 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x0300+(0x03)*2, 0x0000);
2765 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x0300+(0x04)*2, 0x0000);
2766
2767 // Set data_size
2768 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x0300+(0x05)*2, 0x8000);
2769 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x0300+(0x06)*2, 0x0000);
2770
2771 bRet &= _MDrv_DMD_MSB124X_SetReg(0x0300+(0x07)*2, 0x01); //start GDMA
2772
2773 // Wait for GDMA
2774 do
2775 {
2776 MsOS_DelayTaskUs(10);
2777 bRet &= _MDrv_DMD_MSB124X_GetReg(0x0300+(0x08)*2, &u8_data);
2778 u8_timeout--;
2779 }while(((u8_data&0x01) != 0x01) && (u8_timeout != 0x00));
2780
2781 if(u8_data != 0x01)
2782 {
2783 printf("[msb124x][err]LoadSdram2Sram, GDMA move code fail!!\n");
2784 return false;
2785 }
2786
2787 #ifdef MS_DEBUG
2788 DBG_DEMOD_LOAD_I2C(printf("[msb124x]LoadSdram2Sram, GDMA move code done!!\n"));
2789 #endif
2790
2791 //if(CodeNum == 0x02)
2792 // bRet &= _MSB124X_MEM_switch(2); // setting for rom code
2793 //else
2794 bRet &= _MSB124X_MEM_switch(1);
2795
2796 if(bRet == FALSE)
2797 {
2798 pDemod->u8DMD_MSB124X_Sram_Code = 0x00;
2799 }
2800 else
2801 {
2802 pDemod->u8DMD_MSB124X_Sram_Code = CodeNum;
2803 }
2804
2805 #ifdef MS_DEBUG
2806 u32tmm_18 = MsOS_GetSystemTime();
2807 printf("[tmm9]t18-t17 = %ld (%ld - %ld)\n",u32tmm_18-u32tmm_17,u32tmm_18,u32tmm_17);
2808 DBG_DEMOD_LOAD_I2C(printf("[msb124x][end]LoadSdram2Sram, codeNum=0x%x, g_sram_code=0x%x, bRet=0x%x\n",CodeNum,u8DMD_MSB124X_Sram_Code,bRet));
2809 #endif
2810
2811 return bRet;
2812 }
2813
_DTV_DVBC_DSPReg_Init(void)2814 static MS_BOOL _DTV_DVBC_DSPReg_Init(void)
2815 {
2816 MS_U8 idx = 0;
2817 tMSB124XData *pDemod = DEMOD_GET_ACTIVE_NODE();
2818
2819 #ifdef MS_DEBUG
2820 DBG_DEMOD_FLOW(printf("%s(),%d\n",__func__,__LINE__));
2821 #endif
2822 for (idx = 0; idx<sizeof(MSB124X_DVBC_DSPREG_TABLE); idx++)
2823 {
2824 if( _MDrv_DMD_MSB124X_SetDSPReg(idx + 0x20, pDemod->DVBC_DSP_REG[idx])!=TRUE)
2825 {
2826 printf("dvbc dsp reg init NG\n");
2827 return FALSE;
2828 }
2829 }
2830
2831
2832
2833 if( _MDrv_DMD_MSB124X_SetDSPReg(C_config_spread_span, C_TS_SPREAD_SPAN)!=TRUE)
2834 {
2835 printf("dvbc dsp reg init NG\n");
2836 return FALSE;
2837 }
2838 if( _MDrv_DMD_MSB124X_SetDSPReg(C_config_spread_step, C_TS_SPREAD_STEP_SIZE)!=TRUE)
2839 {
2840 printf("dvbc dsp reg init NG\n");
2841 return FALSE;
2842 }
2843
2844 if( _MDrv_DMD_MSB124X_SetDSPReg(C_phase_tuning_en, C_TS_PHASE_TUNING_EN)!=TRUE)
2845 {
2846 printf("dvbc dsp reg init NG\n");
2847 return FALSE;
2848 }
2849 if( _MDrv_DMD_MSB124X_SetDSPReg(C_phase_tuning_num, C_TS_PHASE_TUNING_NUM)!=TRUE)
2850 {
2851 printf("dvbc dsp reg init NG\n");
2852 return FALSE;
2853 }
2854
2855 printf("DVBC dsp reg init ok\n");
2856
2857 return TRUE;
2858 }
2859
2860
_DTV_DVBT_DSPReg_CRC(void)2861 static MS_U8 _DTV_DVBT_DSPReg_CRC(void)
2862 {
2863 MS_U8 crc = 0;
2864 MS_U8 idx = 0;
2865 tMSB124XData *pDemod = DEMOD_GET_ACTIVE_NODE();
2866
2867 #ifdef MS_DEBUG
2868 DBG_DEMOD_FLOW(printf("%s(),%d\n",__func__,__LINE__));
2869 #endif
2870 for (idx = 0; idx<(sizeof(pDemod->DVBT_DSP_REG)); idx++)
2871 {
2872 crc ^= pDemod->DVBT_DSP_REG[idx];
2873 }
2874
2875 crc = ~crc;
2876
2877 return crc;
2878 }
2879
_DTV_DVBT_DSPReg_Init(void)2880 static MS_BOOL _DTV_DVBT_DSPReg_Init(void)
2881 {
2882 #ifdef MS_DEBUG
2883 MS_U32 u32tmm_7 = 0, u32tmm_8 = 0;
2884 #endif
2885 tMSB124XData *pDemod = DEMOD_GET_ACTIVE_NODE();
2886
2887 #ifdef MS_DEBUG
2888 DBG_DEMOD_FLOW(printf("%s(),%d\n",__func__,__LINE__));
2889 u32tmm_7 = MsOS_GetSystemTime();
2890 #endif
2891
2892 if( _MDrv_DMD_MSB124X_SetDSPReg((MS_U8)T_CONFIG_BW, pDemod->DVBT_DSP_REG[0]) != TRUE)
2893 {
2894 printf("dvbt dsp reg init NG\n"); return FALSE;
2895 }
2896 if( _MDrv_DMD_MSB124X_SetDSPReg((MS_U8)T_CONFIG_FC_L, pDemod->DVBT_DSP_REG[1]) != TRUE)
2897 {
2898 printf("dvbt dsp reg init NG\n"); return FALSE;
2899 }
2900 if( _MDrv_DMD_MSB124X_SetDSPReg((MS_U8)T_CONFIG_FC_H, pDemod->DVBT_DSP_REG[2]) != TRUE)
2901 {
2902 printf("dvbt dsp reg init NG\n"); return FALSE;
2903 }
2904 if( _MDrv_DMD_MSB124X_SetDSPReg((MS_U8)T_CONFIG_TS_SERIAL, pDemod->DVBT_DSP_REG[3]) != TRUE)
2905 {
2906 printf("dvbt dsp reg init NG\n"); return FALSE;
2907 }
2908 if( _MDrv_DMD_MSB124X_SetDSPReg((MS_U8)T_CONFIG_TS_CLK_RATE, pDemod->DVBT_DSP_REG[4]) != TRUE)
2909 {
2910 printf("dvbt dsp reg init NG\n"); return FALSE;
2911 }
2912 if( _MDrv_DMD_MSB124X_SetDSPReg((MS_U8)T_CONFIG_TS_OUT_INV, pDemod->DVBT_DSP_REG[5]) != TRUE)
2913 {
2914 printf("dvbt dsp reg init NG\n"); return FALSE;
2915 }
2916 if( _MDrv_DMD_MSB124X_SetDSPReg((MS_U8)T_CONFIG_TS_DATA_SWAP, pDemod->DVBT_DSP_REG[6]) != TRUE)
2917 {
2918 printf("dvbt dsp reg init NG\n"); return FALSE;
2919 }
2920 if( _MDrv_DMD_MSB124X_SetDSPReg((MS_U8)T_CONFIG_IQ_SWAP, pDemod->DVBT_DSP_REG[7]) != TRUE)
2921 {
2922 printf("dvbt dsp reg init NG\n"); return FALSE;
2923 }
2924 if( _MDrv_DMD_MSB124X_SetDSPReg((MS_U8)T_CONFIG_IF_INV_PWM_OUT_EN, pDemod->DVBT_DSP_REG[8]) != TRUE)
2925 {
2926 printf("dvbt dsp reg init NG\n"); return FALSE;
2927 }
2928
2929 // APLL
2930 if( _MDrv_DMD_MSB124X_SetDSPReg((MS_U8)T_CONFIG_SPREAD_SPAN, T_TS_SPREAD_SPAN) != TRUE)
2931 {
2932 printf("dvbt dsp reg init NG\n"); return FALSE;
2933 }
2934 if( _MDrv_DMD_MSB124X_SetDSPReg((MS_U8)T_CONFIG_SPREAD_STEP, T_TS_SPREAD_STEP_SIZE) != TRUE)
2935 {
2936 printf("dvbt dsp reg init NG\n"); return FALSE;
2937 }
2938 //APLL
2939
2940 if( _MDrv_DMD_MSB124X_SetDSPReg((MS_U8)T_PHASE_TUNING_EN, T_TS_PHASE_TUNING_EN) != TRUE)
2941 {
2942 printf("dvbt dsp reg init NG\n"); return FALSE;
2943 }
2944 if( _MDrv_DMD_MSB124X_SetDSPReg((MS_U8)T_PHASE_TUNING_NUM, T_TS_PHASE_TUNING_NUM) != TRUE)
2945 {
2946 printf("dvbt dsp reg init NG\n"); return FALSE;
2947 }
2948
2949
2950 #ifdef MS_DEBUG
2951 u32tmm_8 = MsOS_GetSystemTime();
2952 printf("[3333]t8 - t7 = %ld (%ld - %ld) \n",u32tmm_8-u32tmm_7,u32tmm_8,u32tmm_7);
2953 #endif
2954
2955 printf("dvbt dsp reg init ok\n");
2956
2957 return TRUE;
2958 }
2959
_DTV_DVBT2_DSPReg_Init(void)2960 static MS_BOOL _DTV_DVBT2_DSPReg_Init(void)
2961 {
2962 #ifdef MS_DEBUG
2963 DBG_DEMOD_FLOW(printf("%s(),%d\n",__func__,__LINE__));
2964 #endif
2965 tMSB124XData *pDemod = DEMOD_GET_ACTIVE_NODE();
2966
2967 if( _MDrv_DMD_MSB124X_SetDSPReg((MS_U8)E_T2_BW, pDemod->DVBT2_DSP_REG[0]) != TRUE)
2968 {
2969 printf("T2 dsp reg init NG\n"); return FALSE;
2970 }
2971 if( _MDrv_DMD_MSB124X_SetDSPReg((MS_U8)E_T2_FC_L, pDemod->DVBT2_DSP_REG[1]) != TRUE)
2972 {
2973 printf("T2 dsp reg init NG\n"); return FALSE;
2974 }
2975 if( _MDrv_DMD_MSB124X_SetDSPReg((MS_U8)E_T2_FC_H, pDemod->DVBT2_DSP_REG[2]) != TRUE)
2976 {
2977 printf("T2 dsp reg init NG\n"); return FALSE;
2978 }
2979 if( _MDrv_DMD_MSB124X_SetDSPReg((MS_U8)E_T2_TS_SERIAL, pDemod->DVBT2_DSP_REG[3]) != TRUE)
2980 {
2981 printf("T2 dsp reg init NG\n"); return FALSE;
2982 }
2983 if( _MDrv_DMD_MSB124X_SetDSPReg((MS_U8)E_T2_TS_CLK_RATE, pDemod->DVBT2_DSP_REG[4]) != TRUE)
2984 {
2985 printf("T2 dsp reg init NG\n"); return FALSE;
2986 }
2987 if( _MDrv_DMD_MSB124X_SetDSPReg((MS_U8)E_T2_TS_OUT_INV, pDemod->DVBT2_DSP_REG[5]) != TRUE)
2988 {
2989 printf("T2 dsp reg init NG\n"); return FALSE;
2990 }
2991 if( _MDrv_DMD_MSB124X_SetDSPReg((MS_U8)E_T2_TS_DATA_SWAP, pDemod->DVBT2_DSP_REG[6]) != TRUE)
2992 {
2993 printf("T2 dsp reg init NG\n"); return FALSE;
2994 }
2995 if( _MDrv_DMD_MSB124X_SetDSPReg((MS_U8)E_T2_TS_ERR_POL, pDemod->DVBT2_DSP_REG[7]) != TRUE)
2996 {
2997 printf("T2 dsp reg init NG\n"); return FALSE;
2998 }
2999
3000 // APLL span
3001 if( _MDrv_DMD_MSB124X_SetDSPReg((MS_U8)E_T2_SPREAD_SPAN, T2_TS_SPREAD_SPAN) != TRUE)
3002 {
3003 printf("T2 dsp reg init NG\n"); return FALSE;
3004 }
3005 if( _MDrv_DMD_MSB124X_SetDSPReg((MS_U8)E_T2_SPREAD_STEP, T2_TS_SPREAD_STEP_SIZE) != TRUE)
3006 {
3007 printf("T2 dsp reg init NG\n"); return FALSE;
3008 }
3009 // APLL span
3010
3011 if( _MDrv_DMD_MSB124X_SetDSPReg((MS_U8)E_T2_PHASE_TUNING_EN, T2_TS_PHASE_TUNING_EN) != TRUE)
3012 {
3013 printf("T2 dsp reg init NG\n"); return FALSE;
3014 }
3015 if( _MDrv_DMD_MSB124X_SetDSPReg((MS_U8)E_T2_PHASE_TUNING_NUM, T2_TS_PHASE_TUNING_NUM) != TRUE)
3016 {
3017 printf("T2 dsp reg init NG\n"); return FALSE;
3018 }
3019
3020 printf("T2 dsp reg init ok\n");
3021
3022 return TRUE;
3023 }
3024
_LoadDSPCode(void)3025 static MS_BOOL _LoadDSPCode(void)
3026 {
3027 ////MAPI_U32 u32Now = MsOS_GetSystemTime();
3028 //printf("\t\t\tLoadDSPCode TIME %ld (=%ld-%ld)\n", u32Now-u32StartTime, u32Now, u32StartTime);
3029 ////DBG_DEMOD_MSB(printf("\t\t\tLoadDSPCode TIME %ld (=%ld-%ld)\n", u32Now-u32StartTime, u32Now, u32StartTime));//to measure time
3030 //u32StartTime = u32Now;
3031
3032 MS_U32 u32Timeout = 0;
3033 MS_U8 u8DoneFlag = 0;
3034 MS_U8 u8Data = 0;
3035 MS_BOOL bRet = true;
3036 MS_U8 u8FirmwareType = MSB124X_DVBT;
3037 //kirin bonding option
3038 MS_U32 Bonding_Control = 0;
3039 MS_U16 Chip_ID = 0;
3040 #ifdef MS_DEBUG
3041 MS_U32 u32tmm_9 = 0, u32tmm_10 = 0, u32tmm_11 = 0, u32tmm_12 = 0, u32tmm_13 = 0;
3042 #endif
3043 tMSB124XData *pDemod = DEMOD_GET_ACTIVE_NODE();
3044
3045 #ifdef MS_DEBUG
3046 DBG_DEMOD_FLOW(printf("%s(),%d\n",__func__,__LINE__));
3047 DBG_DEMOD_LOAD_I2C(printf("[msb124x][beg]LoadDspCode\n"));
3048 DBG_DEMOD_MSB(printf(">>>MSB124X: Load DSP...\n"));
3049 #endif
3050
3051
3052
3053 /*
3054 add this for Kirin(Windermere MCP) bonding option
3055 */
3056 #if 1
3057 //kirin bonding option
3058
3059
3060 Chip_ID = MDrv_SYS_GetChipID();
3061 DBG_KIRIN_BOND(printf(">>> Kirin Debug:Chip ID = %x \n",Chip_ID));
3062
3063 if(((Chip_ID & 0xFF) ==0x98)&&((pDemod->eDMD_MSB124X_CurrentDemodulatorType)==E_DMD_MSB124X_DEMOD_DVBS2))//bit[8:7]
3064 {
3065
3066 MS_VIRT u32MMIOBaseAdr;
3067 MS_PHY u32BankSize;
3068 if (MDrv_MMIO_GetBASE(&u32MMIOBaseAdr, &u32BankSize, MS_MODULE_HW))
3069 {
3070 Bonding_Control = DRV_RIU_ReadByte(((0xBF342BEC-0xBF200000)+u32MMIOBaseAdr));
3071 DBG_KIRIN_BOND(printf(">>> Kirin Debug: Bouning_Control = %x \n",Bonding_Control)); //OTP_DVB_SEL; [8:7]=2b'10 means no DVBS/S2
3072 }
3073 if (((Bonding_Control&0x0180)==0x100))
3074 {
3075 DBG_KIRIN_BOND(printf(">>> Kirin Debug: disable DVBS load code of bonding option \n"));
3076 return false;
3077 }
3078 }
3079 #endif
3080
3081
3082 switch(pDemod->eDMD_MSB124X_CurrentDemodulatorType)
3083 {
3084 case E_DMD_MSB124X_DEMOD_DVBT2:
3085 u8Data=1;
3086 break;
3087 case E_DMD_MSB124X_DEMOD_DVBT:
3088 u8Data=2;
3089 break;
3090 case E_DMD_MSB124X_DEMOD_DVBC:
3091 u8Data=3;
3092 break;
3093 case E_DMD_MSB124X_DEMOD_DVBS2:
3094 u8Data=4;
3095 break;
3096 default:
3097 u8Data=2;
3098 return FALSE;
3099 }
3100
3101 if(pDemod->_sDMD_MSB124X_InitData.u8WO_Sdram==1) // 1 means no SDRAM on board
3102 {
3103 //no sdram case
3104 #ifdef MS_DEBUG
3105 u32tmm_11 = MsOS_GetSystemTime();
3106 #endif
3107 switch (u8Data)
3108 {
3109 //since no sdram IC not support DVBT2
3110 case 2:
3111 default:
3112 u8FirmwareType = MSB124X_DVBT;
3113 break;
3114 case 3:
3115 u8FirmwareType = MSB124X_DVBC;
3116 break;
3117 case 4:
3118 u8FirmwareType = MSB124X_DVBS2;
3119 break;
3120 }
3121 bRet &= _LoadDspCodeToSRAM(u8FirmwareType);
3122
3123 bRet &= _MSB124X_MEM_switch(1);
3124
3125 // Enable MCU
3126 bRet &= _MDrv_DMD_MSB124X_SetReg(0x0b00+(0x19)*2, 0x00);
3127
3128
3129 }
3130 else if((pDemod->_sDMD_MSB124X_InitData.u8WO_SPI_Flash == 1)&&(pDemod->_sDMD_MSB124X_InitData.u8WO_Sdram==0))
3131 {
3132 //MS_U8 u8FirmwareType = MSB124X_DVBT;
3133
3134 #ifdef MS_DEBUG
3135 u32tmm_11 = MsOS_GetSystemTime();
3136 #endif
3137
3138 switch (u8Data)
3139 {
3140 case 1:
3141 u8FirmwareType = MSB124X_DVBT2;
3142 break;
3143 case 2:
3144 default:
3145 u8FirmwareType = MSB124X_DVBT;
3146 break;
3147 case 3:
3148 u8FirmwareType = MSB124X_DVBC;
3149 break;
3150 case 4:
3151 u8FirmwareType = MSB124X_DVBS2;
3152 break;
3153 }
3154
3155 bRet &= _LoadDspCodeToSDRAM(u8FirmwareType);
3156
3157 bRet &= _LoadSdram2Sram(u8FirmwareType);
3158
3159 // Enable MCU
3160 bRet &= _MDrv_DMD_MSB124X_SetReg(0x0b00+(0x19)*2, 0x00);
3161 }
3162 else
3163 {
3164 #ifdef MS_DEBUG
3165 u32tmm_9 = MsOS_GetSystemTime();
3166 #endif
3167 // mask miu access for all and mcu
3168 bRet &= _MDrv_DMD_MSB124X_SetReg(0x1200+(0x23)*2 + 1,0x7f);
3169 bRet &= _MDrv_DMD_MSB124X_SetReg(0x1200+(0x23)*2,0xfe);
3170 // 10us delay
3171 MsOS_DelayTaskUs(10);
3172
3173 // Disable MCU
3174 _MDrv_DMD_MSB124X_SetReg(0x0b00+(0x19)*2, 0x03);
3175
3176 // Run code on bootloader
3177 _MDrv_DMD_MSB124X_SetReg(0x1000+(0x0c)*2, 0x02);
3178
3179 // Assign f/w code type to load => 0: boot-loader 1: dvbt2, 2: dvbt, 3: dvbc
3180 _MDrv_DMD_MSB124X_SetReg(0x0900 + (0x4f) * 2, u8Data);
3181
3182
3183 // enable miu access of mcu gdma
3184 bRet &= _MDrv_DMD_MSB124X_SetReg(0x1200+(0x23)*2,0xf0);
3185 // 10us delay
3186 MsOS_DelayTaskUs(10);
3187
3188 // Enable MCU
3189 _MDrv_DMD_MSB124X_SetReg(0x0b00+(0x19)*2, 0x00);
3190
3191 #ifdef MS_DEBUG
3192 u32tmm_10 = MsOS_GetSystemTime();
3193 printf("[tmm8]t10 - t9 = %ld (%ld - %ld)\n",u32tmm_10-u32tmm_9,u32tmm_10,u32tmm_9);
3194 #endif
3195
3196
3197 do
3198 {
3199 _MDrv_DMD_MSB124X_GetReg(0x0900+(0x4f)*2, &u8DoneFlag);
3200
3201 if (u32Timeout++ > 500)
3202 return FALSE;
3203
3204 MsOS_DelayTaskUs(1*1000);
3205
3206 }
3207 while(u8DoneFlag != 0xaa);
3208
3209 #ifdef MS_DEBUG
3210 u32tmm_11 = MsOS_GetSystemTime();
3211 printf("[tmm8]t11 - t10 = %ld (%ld - %ld)\n",u32tmm_11-u32tmm_10,u32tmm_11,u32tmm_10);
3212 #endif
3213
3214 // mask miu access for all and mcu
3215 bRet &= _MDrv_DMD_MSB124X_SetReg(0x1200+(0x23)*2 + 1,0x7f);
3216 bRet &= _MDrv_DMD_MSB124X_SetReg(0x1200+(0x23)*2,0xfe);
3217 // 10us delay
3218 MsOS_DelayTaskUs(10);
3219
3220 // Disable MCU
3221 _MDrv_DMD_MSB124X_SetReg(0x0b00+(0x19)*2, 0x03);
3222
3223 // Run code on loaded firmware
3224 _MDrv_DMD_MSB124X_SetReg(0x1000+(0x0c)*2, 0x05);
3225
3226 do
3227 {
3228 _MDrv_DMD_MSB124X_GetReg(0x1000+(0x0c)*2, &u8DoneFlag);
3229
3230 if (u32Timeout++ > 500)
3231 return FALSE;
3232
3233 MsOS_DelayTaskUs(1*1000);
3234
3235 }
3236 while(u8DoneFlag != 0x05);
3237
3238 // enable miu access of mcu gdma
3239 bRet &= _MDrv_DMD_MSB124X_SetReg(0x1200+(0x23)*2,0xf0);
3240 // 10us delay
3241 MsOS_DelayTaskUs(10);
3242
3243 // Enable MCU
3244 _MDrv_DMD_MSB124X_SetReg(0x0b00+(0x19)*2, 0x00);
3245 }
3246
3247 #ifdef MS_DEBUG
3248 u32tmm_12 = MsOS_GetSystemTime();
3249 printf("[tmm8]t12 - t11 = %ld (%ld - %ld), TYPE is %d \n",u32tmm_12-u32tmm_11,u32tmm_12,u32tmm_11, eDMD_MSB124X_CurrentDemodulatorType);
3250 #endif
3251
3252 switch(pDemod->eDMD_MSB124X_CurrentDemodulatorType)
3253 {
3254 case E_DMD_MSB124X_DEMOD_DVBT2:
3255 _DTV_DVBT2_DSPReg_Init();
3256 break;
3257 case E_DMD_MSB124X_DEMOD_DVBT:
3258 _DTV_DVBT_DSPReg_Init();
3259 break;
3260 case E_DMD_MSB124X_DEMOD_DVBC://mick
3261 _DTV_DVBC_DSPReg_Init();
3262 break;
3263 case E_DMD_MSB124X_DEMOD_DVBS2:
3264 printf("_DTV_DVBS_DSPReg_Init NULL\n");
3265 break;
3266 default:
3267 return FALSE;
3268 }
3269
3270 #ifdef MS_DEBUG
3271 u32tmm_13 = MsOS_GetSystemTime();
3272 printf("[tmm8]t13 - t12 = %ld (%ld - %ld)\n",u32tmm_13-u32tmm_12,u32tmm_13,u32tmm_12);
3273 DBG_DEMOD_LOAD_I2C(printf("[msb124x][end]LoadDspCode\n"));
3274 #endif
3275
3276 return bRet;
3277 }
3278
_msb124x_flash_mode_en(void)3279 static MS_BOOL _msb124x_flash_mode_en(void)
3280 {
3281 MS_BOOL bRet = TRUE;
3282 MS_U8 data[5] = {0x53, 0x45, 0x52, 0x44, 0x42};
3283 MS_U8 u8MsbData[6] = {0};
3284 MS_U8 ch_num = 3;
3285 MS_U8 u8Data = 0;
3286 MS_U16 u16Addr = 0;
3287 MS_U8 retry_num = MSB124X_MAX_FLASH_ON_RETRY_NUM;
3288 tMSB124XData *pDemod = DEMOD_GET_ACTIVE_NODE();
3289
3290 #ifdef MS_DEBUG
3291 DBG_DEMOD_LOAD_I2C(printf("[msb124x][beg]msb124x_flash_mode_en\n"));
3292 #endif
3293
3294 do{
3295
3296 if (retry_num != MSB124X_MAX_FLASH_ON_RETRY_NUM)
3297 {
3298 ERR_DEMOD_MSB(printf("[msb124x][error]flash mode en fail.....retry=%d\n",retry_num);)
3299 }
3300 // bRet = TRUE;
3301 // password
3302 // 8'hb2(SRID)->8,h53(PWD1)->8,h45(PWD2)->8,h52(PWD3)->8,h44(PWD4)->8,h42(PWD5)
3303 data[0] = 0x53;
3304 bRet &= (pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB124X_DEMOD_I2C_WRITE_BYTES, 0, NULL, 5, data);
3305
3306 // 8'hb2(SRID)->8,h71(CMD) //TV.n_iic_
3307 data[0] = 0x71;
3308 bRet &= (pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB124X_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, data);
3309
3310 // 8'hb2(SRID)->8,h81(CMD) //TV.n_iic_sel_b0
3311 data[0] = ((ch_num & 0x01) != 0)? 0x81 : 0x80;
3312 bRet &= (pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB124X_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, data);
3313
3314 // 8'hb2(SRID)->8,h83(CMD) //TV.n_iic_sel_b1
3315 data[0] = ((ch_num & 0x02) != 0)? 0x83 : 0x82;
3316 bRet &= (pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB124X_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, data);
3317
3318 // 8'hb2(SRID)->8,h84(CMD) //TV.n_iic_sel_b2
3319 data[0] = ((ch_num & 0x04) != 0)? 0x85 : 0x84;
3320 bRet &= (pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB124X_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, data);
3321
3322 // 8'hb2(SRID)->8,h53(CMD) //TV.n_iic_ad_byte_en2, 32bit read/write
3323 data[0] = 0x53;
3324 bRet &= (pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB124X_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, data);
3325
3326 // 8'hb2(SRID)->8,h7f(CMD) //TV.n_iic_sel_use_cfg
3327 data[0] = 0x7f;
3328 bRet &= (pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB124X_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, data);
3329
3330 /*
3331 // 8'hb2(SRID)->8,h35(CMD) //TV.n_iic_use
3332 data[0] = 0x35;
3333 bRet &= iptr->WriteBytes(0, NULL, 1, data);
3334
3335 // 8'hb2(SRID)->8,h71(CMD) //TV.n_iic_Re-shape
3336 data[0] = 0x71;
3337 bRet &= iptr->WriteBytes(0, NULL, 1, data);
3338 */
3339 bRet = TRUE;
3340
3341 // confirm first, 0x99 and 0xaa.
3342 // beg read register
3343 u16Addr = 0x0900+(0x4f<<1);
3344 u8Data = 0x0;
3345
3346 u8MsbData[0] = 0x10;
3347 u8MsbData[1] = 0x00;
3348 u8MsbData[2] = 0x00;
3349 u8MsbData[3] = (u16Addr >> 8) &0xff;
3350 u8MsbData[4] = u16Addr &0xff;
3351
3352 u8MsbData[0] = 0x35;
3353 bRet &= (pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB124X_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, u8MsbData);
3354
3355 u8MsbData[0] = 0x10;
3356 bRet &= (pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB124X_DEMOD_I2C_WRITE_BYTES, 0, NULL, 5, u8MsbData);
3357 bRet &= (pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB124X_DEMOD_I2C_READ_BYTES, 0, NULL, 1, &u8Data);
3358
3359 u8MsbData[0] = 0x34;
3360 bRet &= (pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB124X_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, u8MsbData);
3361 // end read register
3362
3363 if ((u8Data == 0x99) || (u8Data == 0xaa))
3364 {
3365 ERR_DEMOD_MSB(printf("[msb124x][warning]flash is already on....\n");)
3366 break;
3367 }
3368 // flash mode enable.
3369 // beg read register
3370 u16Addr = 0x0900+(0x28<<1)+1;
3371 u8Data = 0x0;
3372
3373 u8MsbData[0] = 0x10;
3374 u8MsbData[1] = 0x00;
3375 u8MsbData[2] = 0x00;
3376 u8MsbData[3] = (u16Addr >> 8) &0xff;
3377 u8MsbData[4] = u16Addr &0xff;
3378
3379 u8MsbData[0] = 0x35;
3380
3381 bRet &= (pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB124X_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, u8MsbData);
3382
3383
3384
3385 u8MsbData[0] = 0x10;
3386 bRet &= (pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB124X_DEMOD_I2C_WRITE_BYTES, 0, NULL, 5, u8MsbData);
3387 bRet &= (pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB124X_DEMOD_I2C_READ_BYTES, 0, NULL, 1, &u8Data);
3388
3389 u8MsbData[0] = 0x34;
3390 bRet &= (pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB124X_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, u8MsbData);
3391 // end read register
3392
3393 // beg write register
3394 u16Addr = 0x0900+(0x28<<1) + 1;
3395 u8Data &= (0xff-0x01);
3396
3397 u8MsbData[0] = 0x10;
3398 u8MsbData[1] = 0x00;
3399 u8MsbData[2] = 0x00;
3400 u8MsbData[3] = (u16Addr >> 8) &0xff;
3401 u8MsbData[4] = u16Addr &0xff;
3402 u8MsbData[5] = u8Data;
3403
3404 u8MsbData[0] = 0x35;
3405 bRet &= (pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB124X_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, u8MsbData);
3406
3407 u8MsbData[0] = 0x10;
3408 bRet &= (pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB124X_DEMOD_I2C_WRITE_BYTES, 0, NULL, 6, u8MsbData);
3409
3410 u8MsbData[0] = 0x34;
3411 bRet &= (pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB124X_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, u8MsbData);
3412 // end write register
3413
3414 // beg write register
3415 u16Addr = 0x0900+(0x06<<1);
3416 u8Data = 0x10;
3417
3418 u8MsbData[0] = 0x10;
3419 u8MsbData[1] = 0x00;
3420 u8MsbData[2] = 0x00;
3421 u8MsbData[3] = (u16Addr >> 8) &0xff;
3422 u8MsbData[4] = u16Addr &0xff;
3423 u8MsbData[5] = u8Data;
3424
3425 u8MsbData[0] = 0x35;
3426 bRet &= (pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB124X_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, u8MsbData);
3427
3428 u8MsbData[0] = 0x10;
3429 bRet &= (pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB124X_DEMOD_I2C_WRITE_BYTES, 0, NULL, 6, u8MsbData);
3430
3431 u8MsbData[0] = 0x34;
3432 bRet &= (pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB124X_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, u8MsbData);
3433 // end write register
3434
3435 // beg write register
3436
3437 u16Addr = 0x0900+(0x07<<1);
3438 u8Data = 0x10;
3439
3440 u8MsbData[0] = 0x10;
3441 u8MsbData[1] = 0x00;
3442 u8MsbData[2] = 0x00;
3443 u8MsbData[3] = (u16Addr >> 8) &0xff;
3444 u8MsbData[4] = u16Addr &0xff;
3445 u8MsbData[5] = u8Data;
3446
3447 u8MsbData[0] = 0x35;
3448 bRet &= (pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB124X_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, u8MsbData);
3449
3450 u8MsbData[0] = 0x10;
3451 bRet &= (pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB124X_DEMOD_I2C_WRITE_BYTES, 0, NULL, 6, u8MsbData);
3452
3453 u8MsbData[0] = 0x34;
3454 bRet &= (pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB124X_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, u8MsbData);
3455 }while( (bRet == FALSE) && (retry_num-- != 0));
3456 // end write register
3457
3458 #ifdef MS_DEBUG
3459 DBG_DEMOD_LOAD_I2C(printf("[msb124x][end]msb124x_flash_mode_en,bRet=%d\n",bRet));
3460 #endif
3461
3462 return bRet;
3463 }
3464
_msb124x_flash_boot_ready_waiting(MS_U8 * ptimeout)3465 static MS_BOOL _msb124x_flash_boot_ready_waiting(MS_U8 *ptimeout)
3466 {
3467
3468 MS_BOOL bRet = TRUE;
3469 // MAPI_U8 data[5] = {0x53, 0x45, 0x52, 0x44, 0x42};
3470 MS_U8 u8MsbData[6] = {0};
3471 MS_U8 u8Data = 0;
3472 MS_U16 u16Addr = 0;
3473 MS_U8 u8_timeout = 0;
3474 tMSB124XData *pDemod = DEMOD_GET_ACTIVE_NODE();
3475
3476 #ifdef MS_DEBUG
3477 DBG_DEMOD_LOAD_I2C(printf("[msb124x][beg]msb124x_flash_boot_ready_waiting\n"));
3478 #endif
3479
3480 // wait for flash->dram ready.
3481 // read register
3482
3483 u16Addr = 0x0900+(0x4f<<1);
3484 u8Data = 0x0;
3485
3486 u8MsbData[0] = 0x10;
3487 u8MsbData[1] = 0x00;
3488 u8MsbData[2] = 0x00;
3489 u8MsbData[3] = (u16Addr >> 8) &0xff;
3490 u8MsbData[4] = u16Addr &0xff;
3491
3492 u8_timeout = 0xff;
3493
3494 while( (u8Data != 0x99) && (u8Data != 0xaa) && (u8_timeout-->0))
3495 {
3496 u8MsbData[0] = 0x35;
3497 bRet &= (pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB124X_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, u8MsbData);
3498
3499 u8MsbData[0] = 0x10;
3500 bRet &= (pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB124X_DEMOD_I2C_WRITE_BYTES, 0, NULL, 5, u8MsbData);
3501 bRet &= (pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB124X_DEMOD_I2C_READ_BYTES, 0, NULL, 1, &u8Data);
3502
3503 u8MsbData[0] = 0x34;
3504 bRet &= (pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB124X_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, u8MsbData);
3505 // 10ms
3506 MsOS_DelayTaskUs(1000*10);
3507 }
3508 // end read register
3509 *ptimeout = 0;
3510 if (u8_timeout == 0x00)
3511 {
3512 *ptimeout = 1;
3513 ERR_DEMOD_MSB(printf("[msb124x][error]msb124x_flash_boot_ready_waiting, timeout....\n");)
3514 }
3515
3516 #ifdef MS_DEBUG
3517 DBG_DEMOD_LOAD_I2C(printf("[msb124x][end]msb124x_flash_boot_ready_waiting, t=%d\n",u8_timeout));
3518 #endif
3519 return bRet;
3520 }
3521
_msb124x_flash_WP_reg_read(MS_U16 u16Addr,MS_U8 * pu8Data)3522 static MS_BOOL _msb124x_flash_WP_reg_read(MS_U16 u16Addr, MS_U8 *pu8Data)
3523 {
3524 MS_BOOL bRet;
3525 MS_U8 u8MsbData[5];
3526 tMSB124XData *pDemod = DEMOD_GET_ACTIVE_NODE();
3527
3528 u8MsbData[0] = 0x10;
3529 u8MsbData[1] = 0x00;
3530 u8MsbData[2] = 0x00;
3531 u8MsbData[3] = (u16Addr >> 8) &0xff;
3532 u8MsbData[4] = u16Addr &0xff;
3533
3534 u8MsbData[0] = 0x35;
3535 (pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB124X_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, u8MsbData);
3536
3537 u8MsbData[0] = 0x10;
3538 (pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB124X_DEMOD_I2C_WRITE_BYTES, 0, NULL, 5, u8MsbData);
3539 (pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB124X_DEMOD_I2C_READ_BYTES, 0, NULL, 1, pu8Data);
3540
3541 u8MsbData[0] = 0x34;
3542 bRet=(pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB124X_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, u8MsbData);
3543 return bRet;
3544 }
3545
_msb124x_flash_WP_reg_write(MS_U16 u16Addr,MS_U8 u8Data)3546 static MS_BOOL _msb124x_flash_WP_reg_write(MS_U16 u16Addr, MS_U8 u8Data)
3547 {
3548 MS_BOOL bRet;
3549 MS_U8 u8MsbData[6];
3550 tMSB124XData *pDemod = DEMOD_GET_ACTIVE_NODE();
3551
3552 //bRet &= iptr->SetSpeed(0);
3553
3554
3555 u8MsbData[0] = 0x10;
3556 u8MsbData[1] = 0x00;
3557 u8MsbData[2] = 0x00;
3558 u8MsbData[3] = (u16Addr >> 8) &0xff;
3559 u8MsbData[4] = u16Addr &0xff;
3560 u8MsbData[5] = u8Data;
3561
3562 u8MsbData[0] = 0x35;
3563 (pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB124X_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, u8MsbData);
3564
3565 u8MsbData[0] = 0x10;
3566 (pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB124X_DEMOD_I2C_WRITE_BYTES, 0, NULL, 6, u8MsbData);
3567
3568 u8MsbData[0] = 0x34;
3569 bRet=(pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB124X_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, u8MsbData);
3570 return bRet;
3571 }
3572
_msbMSB124X_flash_WRSR(MS_U8 reg)3573 static MS_BOOL _msbMSB124X_flash_WRSR(MS_U8 reg)
3574 {
3575 MS_U8 bWriteData[5]={0x4D, 0x53, 0x54, 0x41, 0x52};
3576 MS_U8 bAddr[1];
3577 MS_BOOL bRet = TRUE;
3578 tMSB124XData *pDemod = DEMOD_GET_ACTIVE_NODE();
3579
3580 (pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_2, E_DMD_MSB124X_DEMOD_I2C_WRITE_BYTES, 0, NULL, 5, bWriteData);
3581
3582 // WREN
3583 bAddr[0] = 0x10;
3584 bWriteData[0] = 0x06;
3585 (pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_2, E_DMD_MSB124X_DEMOD_I2C_WRITE_BYTES, 1, bAddr, 1, bWriteData);
3586
3587 bWriteData[0] = 0x12;
3588 (pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_2, E_DMD_MSB124X_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, bWriteData);
3589
3590 // WRSR
3591 bAddr[0] = 0x10;
3592 bWriteData[0] = 0x01;
3593 bWriteData[1] = reg;
3594 (pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_2, E_DMD_MSB124X_DEMOD_I2C_WRITE_BYTES, 1, bAddr, 2, bWriteData);
3595
3596 bWriteData[0] = 0x12;
3597 (pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_2, E_DMD_MSB124X_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, bWriteData);
3598
3599 // WRDI
3600 bAddr[0] = 0x10;
3601 bWriteData[0] = 0x04;
3602 (pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_2, E_DMD_MSB124X_DEMOD_I2C_WRITE_BYTES, 1, bAddr, 1, bWriteData);
3603
3604 bWriteData[0] = 0x12;
3605 (pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_2, E_DMD_MSB124X_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, bWriteData);
3606
3607 // end
3608 bWriteData[0] = 0x24;
3609 (pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_2, E_DMD_MSB124X_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, bWriteData);
3610
3611 #ifdef MS_DEBUG
3612 DBG_FLASH_WP(printf("[wb]msbMSB124X_flash_WRSR, reg=0x%x\n",reg);)
3613 #endif
3614
3615 return bRet;
3616 }
3617
_msbMSB124X_flash_SRSR(MS_U8 * p_reg)3618 static MS_BOOL _msbMSB124X_flash_SRSR(MS_U8 *p_reg)
3619 {
3620 MS_U8 bWriteData[5]={0x4D, 0x53, 0x54, 0x41, 0x52};
3621 MS_U8 bAddr[1];
3622 MS_BOOL bRet = TRUE;
3623 tMSB124XData *pDemod = DEMOD_GET_ACTIVE_NODE();
3624
3625 (pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_2, E_DMD_MSB124X_DEMOD_I2C_WRITE_BYTES, 0, NULL, 5, bWriteData);
3626
3627 bAddr[0] = 0x10;
3628 bWriteData[0] = 0x05;
3629 (pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_2, E_DMD_MSB124X_DEMOD_I2C_WRITE_BYTES, 1, bAddr, 1, bWriteData);
3630
3631 bAddr[0] = 0x11;
3632 (pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_2, E_DMD_MSB124X_DEMOD_I2C_READ_BYTES, 1, bAddr, 1, p_reg);
3633
3634 bWriteData[0] = 0x12;
3635 (pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_2, E_DMD_MSB124X_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, bWriteData);
3636
3637 // end
3638 bWriteData[0] = 0x24 ;
3639 (pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_2, E_DMD_MSB124X_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, bWriteData);
3640
3641 #ifdef MS_DEBUG
3642 DBG_FLASH_WP(printf("[wb]msbMSB124X_flash_SRSR, reg=0x%x\n",*p_reg);)
3643 #endif
3644
3645 return bRet;
3646 }
3647
_msb124x_flash_WP(MS_U8 enable)3648 static MS_BOOL _msb124x_flash_WP(MS_U8 enable)
3649 #if 0
3650 {
3651 MAPI_U8 reg = 0;
3652 MAPI_BOOL bRet = true;
3653 MAPI_U8 u8_count = 0;
3654
3655 DBG_FLASH_WP(printf("[wb]msb1233c_flash_WP_Enable=%d\n",enable);)
3656
3657 if (enable == 1)
3658 {
3659 u8_count = 20;
3660 do
3661 {
3662 msb1233c_flash_SRSR(®);
3663 usleep(1*1000);
3664 }while(reg&0x01 && u8_count--);
3665
3666 if (u8_count == 0)
3667 {
3668 bRet = false;
3669 DBG_FLASH_WP(printf("[wb]Err, flash_SRSR timeout!!!\n");)
3670 return bRet;
3671 }
3672
3673 msb1233c_flash_WRSR(reg|0x9c);
3674
3675
3676 u8_count = 20;
3677 do
3678 {
3679 msb1233c_flash_SRSR(®);
3680 usleep(1*1000);
3681 }while(reg&0x01 && u8_count--);
3682
3683 if (u8_count == 0)
3684 {
3685 bRet = false;
3686 DBG_FLASH_WP(printf("[wb]Err, flash_SRSR timeout!!!\n");)
3687 return bRet;
3688 }
3689
3690 // active low
3691 // pull low
3692 bRet &= msb1233c_flash_WP_reg_read(0x0900+0x63*2+1, ®);
3693 bRet &= msb1233c_flash_WP_reg_write(0x0900+0x63*2+1, reg&(~0x08));
3694
3695 // gpio11 output enable
3696 bRet &= msb1233c_flash_WP_reg_read(0x0900+0x64*2+1, ®);
3697 bRet &= msb1233c_flash_WP_reg_write(0x0900+0x64*2+1, reg&(~0x08));
3698 }
3699 else
3700 {
3701 // unactive high
3702 // pull high
3703 bRet &= msb1233c_flash_WP_reg_read(0x0900+0x63*2+1, ®);
3704 bRet &= msb1233c_flash_WP_reg_write(0x0900+0x63*2+1, reg|0x08);
3705
3706 // gpio11 output enable
3707 bRet &= msb1233c_flash_WP_reg_read(0x0900+0x64*2+1, ®);
3708 bRet &= msb1233c_flash_WP_reg_write(0x0900+0x64*2+1, reg&(~0x08));
3709
3710 u8_count = 20;
3711 do
3712 {
3713 msb1233c_flash_SRSR(®);
3714 usleep(1*1000);
3715 }while(reg&0x01 && u8_count--);
3716
3717 if (u8_count == 0)
3718 {
3719 bRet = false;
3720 DBG_FLASH_WP(printf("[wb]Err, flash_SRSR timeout!!!\n");)
3721 return bRet;
3722 }
3723
3724 msb1233c_flash_WRSR(reg&(~0x9c));
3725
3726 u8_count = 20;
3727 do
3728 {
3729 msb1233c_flash_SRSR(®);
3730 usleep(1*1000);
3731 }while(reg&0x01 && u8_count--);
3732
3733 if (u8_count == 0)
3734 {
3735 bRet = false;
3736 DBG_FLASH_WP(printf("[wb]Err, flash_SRSR timeout!!!\n");)
3737 return bRet;
3738 }
3739 }
3740
3741 return bRet;
3742 }
3743 #else
3744 {
3745 MS_U8 reg = 0;
3746 MS_BOOL bRet = TRUE;
3747 MS_U8 u8_count = 0;
3748
3749 #ifdef MS_DEBUG
3750 DBG_FLASH_WP(printf("[wb]msb124x_flash_WP_Enable=%d\n",enable);)
3751 #endif
3752
3753 if (enable == 1)
3754 {
3755 u8_count = 20;
3756 do
3757 {
3758 _msbMSB124X_flash_SRSR(®);
3759 MsOS_DelayTaskUs(1*1000);
3760 }while(reg&0x01 && u8_count--);
3761
3762 if (u8_count == 0)
3763 {
3764 bRet = FALSE;
3765 #ifdef MS_DEBUG
3766 DBG_FLASH_WP(printf("[wb]Err, flash_SRSR timeout!!!\n");)
3767 #endif
3768 return bRet;
3769 }
3770
3771 _msbMSB124X_flash_WRSR(reg|0x9c);
3772 u8_count = 20;
3773
3774 do
3775 {
3776 _msbMSB124X_flash_SRSR(®);
3777 MsOS_DelayTaskUs(1*1000);
3778 }while(reg&0x01 && u8_count--);
3779
3780 if (u8_count == 0)
3781 {
3782 bRet = FALSE;
3783 #ifdef MS_DEBUG
3784 DBG_FLASH_WP(printf("[wb]Err, flash_SRSR timeout!!!\n");)
3785 #endif
3786 return bRet;
3787 }
3788
3789 // active low
3790 // pull low
3791 bRet &= _msb124x_flash_WP_reg_read(0x0A00+0x22*2, ®);
3792 bRet &= _msb124x_flash_WP_reg_write(0x0A00+0x22*2, reg&(~0x01));
3793 // gpio11 output enable
3794 bRet &= _msb124x_flash_WP_reg_read(0x0A00+0x22*2, ®);
3795 bRet &= _msb124x_flash_WP_reg_write(0x0A00+0x22*2, reg&(~0x02));
3796 }
3797 else
3798 {
3799 // unactive high
3800 // pull high
3801 bRet &= _msb124x_flash_WP_reg_read(0x0A00+0x22*2, ®);
3802 bRet &= _msb124x_flash_WP_reg_write(0x0A00+0x22*2, reg|0x01);
3803 // gpio11 output enable
3804 bRet &= _msb124x_flash_WP_reg_read(0x0A00+0x22*2, ®);
3805 bRet &= _msb124x_flash_WP_reg_write(0x0A00+0x22*2, reg&(~0x02));
3806 u8_count = 20;
3807
3808 do
3809 {
3810 _msbMSB124X_flash_SRSR(®);
3811 MsOS_DelayTaskUs(1*1000);
3812 }while(reg&0x01 && u8_count--);
3813
3814 if (u8_count == 0)
3815 {
3816 bRet = FALSE;
3817 #ifdef MS_DEBUG
3818 DBG_FLASH_WP(printf("[wb]Err, flash_SRSR timeout!!!\n");)
3819 #endif
3820 return bRet;
3821 }
3822 _msbMSB124X_flash_WRSR(reg&(~0x9c));
3823 u8_count = 20;
3824
3825 do
3826 {
3827 _msbMSB124X_flash_SRSR(®);
3828 MsOS_DelayTaskUs(1*1000);
3829 }while(reg&0x01 && u8_count--);
3830
3831 if (u8_count == 0)
3832 {
3833 bRet = FALSE;
3834 #ifdef MS_DEBUG
3835 DBG_FLASH_WP(printf("[wb]Err, flash_SRSR timeout!!!\n");)
3836 #endif
3837 return bRet;
3838 }
3839 }
3840 return bRet;
3841 }
3842 #endif
3843
3844 MS_U16 _MSB124X_CHIP_MATCH_TABLE[] =
3845 {
3846 //Kaiser, Kaiserin, Keltic, Kronus, Kappa
3847 0x56, 0x41, 0x72, 0x2F, 0x75,
3848 };
3849 /*
3850 static MS_BOOL _msbMSB124X_set_bonding_option(MS_U16 u16ChipID)
3851 {
3852 MS_BOOL bRet = TRUE;
3853 MS_U8 u8Idx;
3854 MS_U8 u8MatchFlag = 0;
3855 MS_U8 u8Data = 0;
3856 MS_U32 u32_timeout = 0;
3857 #ifdef MS_DEBUG
3858 DBG_DEMOD_FLOW(printf("%s(),%d\n",__func__,__LINE__));
3859 #endif
3860
3861 printf("_msbMSB124X_set_bonding_option u16ChipID %x\n", u16ChipID);
3862
3863 for (u8Idx = 0 ; u8Idx < sizeof( _MSB124X_CHIP_MATCH_TABLE) ; u8Idx++)
3864 {
3865 if(u16ChipID == _MSB124X_CHIP_MATCH_TABLE[u8Idx])
3866 {
3867 u8MatchFlag = 0x01;
3868 break;
3869 }
3870 else
3871 {
3872 u8MatchFlag = 0x00;
3873 }
3874 }
3875
3876 if (_MSB124X_I2C_CH_Reset(3) == FALSE)
3877 {
3878 printf(">>>MSB124X CH3 Reset:Fail\n");
3879 return FALSE;
3880 }
3881
3882 // MSB124X : 0x0902[8]=0 , 0x0902[0]=0;
3883 // MSB1235 : 0x0902[8]=1 , 0x0902[0]=1; (before overwrite, SDRAM not enable)
3884 // 0x0902[8]=1 , 0x0902[0]=0; (after overwrite, SDRAM enable)
3885 // check bonding value, 0x0902[8]
3886 bRet &= _MDrv_DMD_MSB124X_GetReg(0x0900+(0x02)*2+1, &u8Data);
3887 if((u8Data & 0x01) == 0x01) //for MSB1236C
3888 {
3889 if(u8MatchFlag == 0x01)
3890 {
3891 //check overwrite or not
3892 //0x0902[0] : reg_bonding[0]
3893 bRet &= _MDrv_DMD_MSB124X_GetReg(0x0900+(0x02)*2, &u8Data);
3894 if((u8Data & 0x01) != 0x00)
3895 {
3896 //0x0905[0] : reg_bond_ov_en[0] = 1
3897 //0x0905[8] : reg_bond_ov[0] = 0
3898 // set overwrite enable
3899 bRet &= _MDrv_DMD_MSB124X_SetReg(0x0900+(0x05)*2, 0x01);
3900 // set overwrite value
3901 bRet &= _MDrv_DMD_MSB124X_SetReg(0x0900+(0x05)*2+1, 0x00);
3902 }
3903
3904 do
3905 {
3906 bRet &= _MDrv_DMD_MSB124X_GetReg(0x0900+(0x02)*2, &u8Data);
3907 if(u32_timeout++ > 500)
3908 {
3909 ERR_DEMOD_MSB(printf("@msb124x, Set bonding option failure.!!!\n"));
3910 return FALSE;
3911 }
3912 }while((u8Data & 0x01) == 0x01);
3913
3914 #ifdef MS_DEBUG
3915 printf("@ Set bonding option for MSB1236 \n");
3916 #endif
3917 }
3918 else
3919 {
3920 return FALSE;
3921 }
3922 }
3923 else // for MSB124X
3924 {
3925 //check overwrite or not
3926 //0x0902[0] : reg_bonding[0]
3927 bRet &= _MDrv_DMD_MSB124X_GetReg(0x0900+(0x02)*2, &u8Data);
3928 if((u8Data & 0x01) != 0x00)
3929 {
3930 //0x0905[0] : reg_bond_ov_en[0] = 1
3931 //0x0905[8] : reg_bond_ov[0] = 0
3932 // set overwrite enable
3933 bRet &= _MDrv_DMD_MSB124X_SetReg(0x0900+(0x05)*2, 0x01);
3934 // set overwrite value
3935 bRet &= _MDrv_DMD_MSB124X_SetReg(0x0900+(0x05)*2+1, 0x00);
3936 }
3937
3938 do
3939 {
3940 bRet &= _MDrv_DMD_MSB124X_GetReg(0x0900+(0x02)*2, &u8Data);
3941 if(u32_timeout++ > 500)
3942 {
3943 ERR_DEMOD_MSB(printf("@msbMSB124X, Set bonding option failure.!!!\n"));
3944 return FALSE;
3945 }
3946 }while((u8Data & 0x01) == 0x01);
3947
3948 #ifdef MS_DEBUG
3949 printf("@ Set bonding option for MSB124X \n");
3950 #endif
3951 }
3952
3953 #ifdef MS_DEBUG
3954 if (!bRet) printf("%s %d Error\n", __func__, __LINE__);
3955 #endif
3956 return bRet;
3957 }
3958 */
_IspCheckVer(MS_U8 * pLibData,MS_BOOL * pMatch)3959 static MS_BOOL _IspCheckVer(MS_U8* pLibData, MS_BOOL* pMatch)
3960 {
3961 MS_U8 bReadData[VERSION_CODE_SIZE];
3962 MS_U32 indx = 0;
3963 *pMatch = true;
3964 tMSB124XData *pDemod = DEMOD_GET_ACTIVE_NODE();
3965
3966 MS_U8 bWriteData[5] = {0x4D, 0x53, 0x54, 0x41, 0x52};
3967 (pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB124X_DEMOD_I2C_WRITE_BYTES, 0, NULL, 5, bWriteData);
3968
3969 MS_U8 bAddr[1], bError = true;
3970 //MAPI_U16 Count;
3971
3972 memset(bReadData, 0 , sizeof(bReadData));
3973
3974 bAddr[0] = 0x10;
3975 //dwStartAddr=0;
3976
3977 bWriteData[0] = 0x03;
3978 bWriteData[1] = VERSION_CODE_ADDR >> 16;
3979 bWriteData[2] = VERSION_CODE_ADDR >> 8;
3980 bWriteData[3] = VERSION_CODE_ADDR & 0xFF;
3981
3982 bError &= (pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_2, E_DMD_MSB124X_DEMOD_I2C_WRITE_BYTES, 1, bAddr, 4, bWriteData);
3983
3984 bAddr[0] = 0x11;
3985 bError &= (pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_2, E_DMD_MSB124X_DEMOD_I2C_READ_BYTES, 1, bAddr, VERSION_CODE_SIZE, bReadData);
3986
3987 bWriteData[0] = 0x12;
3988 bError &= (pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_2, E_DMD_MSB124X_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, bWriteData);
3989
3990 if(FALSE == bError)
3991 {
3992 bWriteData[0] = 0x24 ;
3993 (pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_2, E_DMD_MSB124X_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, bWriteData);
3994 return FALSE;
3995 }
3996
3997 bWriteData[0] = 0x24 ;
3998 (pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_2, E_DMD_MSB124X_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, bWriteData);
3999
4000 printf("sttest version data = ");
4001 for(indx = 0; indx < (VERSION_CODE_SIZE); indx++)
4002 {
4003 printf(" %x ,", bReadData[indx]);
4004 if(pLibData[indx+VERSION_CODE_ADDR] != bReadData[indx])
4005 {
4006 *pMatch = FALSE;
4007 //break;
4008 }
4009 }
4010 printf(" \n");
4011
4012 return TRUE;
4013 }
4014
_dram_crc_check(MS_U16 chksum_lib,MS_BOOL * pMatch)4015 static MS_BOOL _dram_crc_check(MS_U16 chksum_lib, MS_BOOL* pMatch)
4016 {
4017 MS_U16 chksum = 0;
4018 // MAPI_U16 chksum_lib = 0;
4019 MS_U16 u16Addr = 0;
4020 MS_U8 u8MsbData[5];
4021 MS_U8 reg = 0;
4022 MS_BOOL bRet;
4023 MS_U8 mcu_status = 0;
4024 tMSB124XData *pDemod = DEMOD_GET_ACTIVE_NODE();
4025
4026 *pMatch = false;
4027
4028 // MAPI_U8 bWriteData[5]={0x4D, 0x53, 0x54, 0x41, 0x52};
4029 // iptr->WriteBytes(0, NULL, 5, bWriteData);
4030
4031 /// crc H byte
4032 u16Addr = 0x0c00+0x0d*2+1;
4033
4034 u8MsbData[0] = 0x10;
4035 u8MsbData[1] = 0x00;
4036 u8MsbData[2] = 0x00;
4037 u8MsbData[3] = (u16Addr >> 8) &0xff;
4038 u8MsbData[4] = u16Addr &0xff;
4039
4040 u8MsbData[0] = 0x35;
4041 (pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB124X_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, u8MsbData);
4042
4043 u8MsbData[0] = 0x10;
4044 (pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB124X_DEMOD_I2C_WRITE_BYTES, 0, NULL, 5, u8MsbData);
4045 (pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB124X_DEMOD_I2C_READ_BYTES, 0, NULL, 1, ®);
4046
4047 u8MsbData[0] = 0x34;
4048 bRet=(pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB124X_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, u8MsbData);
4049
4050
4051 chksum = reg;
4052
4053 /// crc L byte
4054 u16Addr = 0x0c00+0x0d*2;
4055
4056 u8MsbData[0] = 0x10;
4057 u8MsbData[1] = 0x00;
4058 u8MsbData[2] = 0x00;
4059 u8MsbData[3] = (u16Addr >> 8) &0xff;
4060 u8MsbData[4] = u16Addr &0xff;
4061
4062 u8MsbData[0] = 0x35;
4063 (pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB124X_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, u8MsbData);
4064
4065 u8MsbData[0] = 0x10;
4066 (pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB124X_DEMOD_I2C_WRITE_BYTES, 0, NULL, 5, u8MsbData);
4067 (pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB124X_DEMOD_I2C_READ_BYTES, 0, NULL, 1, ®);
4068
4069 u8MsbData[0] = 0x34;
4070 bRet=(pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB124X_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, u8MsbData);
4071
4072
4073 chksum = (chksum<<8)|reg;
4074
4075 // get mcu status
4076
4077 u16Addr = 0x0900+0x4f*2;
4078
4079 u8MsbData[0] = 0x10;
4080 u8MsbData[1] = 0x00;
4081 u8MsbData[2] = 0x00;
4082 u8MsbData[3] = (u16Addr >> 8) &0xff;
4083 u8MsbData[4] = u16Addr &0xff;
4084
4085 u8MsbData[0] = 0x35;
4086 (pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB124X_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, u8MsbData);
4087
4088 u8MsbData[0] = 0x10;
4089 (pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB124X_DEMOD_I2C_WRITE_BYTES, 0, NULL, 5, u8MsbData);
4090 (pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB124X_DEMOD_I2C_READ_BYTES, 0, NULL, 1, ®);
4091
4092 u8MsbData[0] = 0x34;
4093 bRet=(pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_1, E_DMD_MSB124X_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, u8MsbData);
4094
4095
4096 mcu_status = reg;
4097
4098
4099 /// check the crc in dsp lib array
4100
4101 if (mcu_status == 0xaa && ((chksum_lib&0xff00) == (chksum&0xff00)) )
4102 *pMatch = true;
4103 else if(chksum_lib == chksum)
4104 *pMatch = true;
4105
4106 #ifdef MS_DEBUG
4107 printf("[crc]chksum_lib=0x%x, chksum=0x%x, bRet=%d, Match=%d, mcu_status=0x%x\n",chksum_lib,chksum,bRet,*pMatch,mcu_status);
4108 #endif
4109
4110 return bRet;
4111 }
4112
_IspProcFlash(MS_U8 * pLibArry,MS_U32 dwLibSize)4113 static MS_BOOL _IspProcFlash(MS_U8* pLibArry, MS_U32 dwLibSize)
4114 {
4115 MS_U32 dwLoop, dwTimeOut;
4116 MS_U32 dwStartAddr, dwEndAddr;
4117 //MAPI_U16 wLoop;
4118 MS_U8 bError = false;//, bWriteData[PAGE_WRITE_SIZE];
4119 tMSB124XData *pDemod = DEMOD_GET_ACTIVE_NODE();
4120
4121 MS_U8 bWriteData[5]={0x4D, 0x53, 0x54, 0x41, 0x52};
4122 (pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_2, E_DMD_MSB124X_DEMOD_I2C_WRITE_BYTES, 0, NULL, 5, bWriteData);
4123
4124 dwStartAddr = (MS_U32) 0;
4125 dwEndAddr = dwLibSize;
4126
4127
4128 MS_U8 bAddr[1];
4129 MS_U8 bReadData=0;
4130 for(dwLoop=dwStartAddr; (dwLoop < dwEndAddr); dwLoop+=PAGE_WRITE_SIZE)
4131 {
4132
4133 dwTimeOut = 10000;
4134
4135 while(dwTimeOut--)
4136 {
4137 bAddr[0] = 0x10;
4138 bWriteData[0] = 0x05;
4139 (pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_2, E_DMD_MSB124X_DEMOD_I2C_WRITE_BYTES, 1, bAddr, 1, bWriteData);
4140
4141 bAddr[0] = 0x11;
4142 (pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_2, E_DMD_MSB124X_DEMOD_I2C_READ_BYTES, 1, bAddr, 1, &bReadData);
4143
4144 bWriteData[0] = 0x12;
4145 (pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_2, E_DMD_MSB124X_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, bWriteData);
4146
4147 if (!(bReadData & 0x01))
4148 break;
4149
4150 if(dwTimeOut==1)
4151 {
4152 bError = 1;
4153 break;
4154 }
4155 MsOS_DelayTaskUs(0);
4156 }
4157
4158 if(!bError)
4159 {
4160
4161 MS_U8 bAddr[5], bWriteData[1];
4162 MS_BOOL bError = TRUE;
4163
4164 bAddr[0] = 0x10;
4165 bWriteData[0] = 0x06;
4166 bError &= (pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_2, E_DMD_MSB124X_DEMOD_I2C_WRITE_BYTES, 1, bAddr, 1, bWriteData);
4167
4168 bWriteData[0] = 0x12;
4169 bError &= (pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_2, E_DMD_MSB124X_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, bWriteData);
4170
4171 // Page Program
4172 bAddr[0] = 0x10;
4173 bAddr[1] = 0x02;
4174 bAddr[2] = dwLoop >> 16;
4175 bAddr[3] = dwLoop >> 8;
4176 bAddr[4] = dwLoop;
4177
4178 bError &= (pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_2, E_DMD_MSB124X_DEMOD_I2C_WRITE_BYTES, 5, bAddr, PAGE_WRITE_SIZE, (pLibArry+dwLoop));
4179
4180 bWriteData[0] = 0x12;
4181 bError &= (pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_2, E_DMD_MSB124X_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, bWriteData);
4182
4183 bAddr[0] = 0x10;
4184 bWriteData[0] = 0x04;
4185 bError &= (pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_2, E_DMD_MSB124X_DEMOD_I2C_WRITE_BYTES, 1, bAddr, 1, bWriteData);
4186
4187 bWriteData[0] = 0x12;
4188 bError &= (pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_2, E_DMD_MSB124X_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, bWriteData);
4189
4190 if(bError == FALSE)
4191 {
4192 break;
4193 }
4194 }
4195 }
4196
4197 bWriteData[0]=0x24 ;
4198 (pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_2, E_DMD_MSB124X_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, bWriteData);
4199
4200 if(bError==FALSE)
4201 return TRUE;
4202 else
4203 return FALSE;
4204
4205 }
4206
MDrv_DMD_MSB124X_SetCurrentDemodulatorType(eDMD_MSB124X_DemodulatorType eCurrentDemodulatorType)4207 void MDrv_DMD_MSB124X_SetCurrentDemodulatorType(eDMD_MSB124X_DemodulatorType eCurrentDemodulatorType)
4208 {
4209 tMSB124XData *pDemod = DEMOD_GET_ACTIVE_NODE();
4210 #ifdef MS_DEBUG
4211 printf("MDrv_DMD_MSB124X_SetCurrentDemodulatorType %d\n", eCurrentDemodulatorType);
4212 #endif
4213 pDemod->eDMD_MSB124X_CurrentDemodulatorType = eCurrentDemodulatorType;
4214 }
4215
MDrv_DMD_MSB124X_LoadDSPCode(void)4216 MS_BOOL MDrv_DMD_MSB124X_LoadDSPCode(void)
4217 {
4218 MS_BOOL bRet = TRUE;
4219 DMD_LOCK();
4220 bRet = _LoadDSPCode();
4221 DMD_UNLOCK();
4222 return bRet;
4223 }
4224
MDrv_DMD_MSB124X_DTV_DVBT_DSPReg_CRC(void)4225 MS_BOOL MDrv_DMD_MSB124X_DTV_DVBT_DSPReg_CRC(void)
4226 {
4227 MS_BOOL bRet = TRUE;
4228 DMD_LOCK();
4229 bRet = _DTV_DVBT_DSPReg_CRC();
4230 DMD_UNLOCK();
4231 return bRet;
4232 }
4233
MDrv_DMD_MSB1245_LoadDSPCodeToSram(void)4234 MS_BOOL MDrv_DMD_MSB1245_LoadDSPCodeToSram(void)
4235 {
4236 MS_BOOL bRet=true;
4237 MS_U16 u16dat_size;
4238 MS_U16 u16Address;
4239 MS_U8 u8Data;
4240 tMSB124XData *pDemod = DEMOD_GET_ACTIVE_NODE();
4241
4242 DMD_LOCK();
4243
4244 if (pDemod->_sDMD_MSB124X_InitData.bPreloadDSPCodeFromMainCHIPI2C)
4245 {
4246 DMD_UNLOCK();
4247 return TRUE;
4248 }
4249
4250 //change I2C channel
4251 bRet &=_MSB124X_I2C_CH_Reset(3);
4252 if (bRet==FALSE)
4253 {
4254 PRINTE(("utopia MSB1245 i2c change fail!!!\n"));
4255 }
4256 else
4257 {
4258 PRINTE(("utopia MSB1245 i2c change success!!!\n"));
4259 }
4260
4261
4262 //HW version Check
4263 u16Address=0x0900;
4264 bRet &=_MDrv_DMD_MSB124X_GetReg(u16Address, &u8Data);
4265 if (bRet==FALSE)
4266 {
4267 PRINTE(("utopia MSB1245 i2c read reg fail!!!\n"));
4268 }
4269 else
4270 {
4271 PRINTE(("utopia MSB1245 HW version: 0x%x=0x%x\n", u16Address, u8Data));
4272 }
4273
4274 u16dat_size=sizeof(MSB1245_LIB);
4275 if (pDemod->_sDMD_MSB124X_InitData.bEnableSPILoadCode)
4276 {
4277 //SPI load code
4278 (pDemod->_sDMD_MSB124X_InitData.fpMSB124x_SPIPAD_En)(TRUE);
4279 // ------enable to use TS_PAD as SSPI_PAD
4280 // [0:0] reg_en_sspi_pad
4281 // [1:1] reg_ts_sspi_en, 1: use TS_PAD as SSPI_PAD
4282 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x0900 + (0x3b) * 2, 0x0002);
4283 //Turn off all pad in
4284 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x0900 + (0x28) * 2, 0x0000);
4285 //Transport Stream pad on
4286 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x0900 + (0x2d) * 2, 0x00ff);
4287 // ------- MSPI protocol setting
4288 // [8] cpha
4289 // [9] cpol
4290 _MDrv_DMD_MSB124X_GetReg(0x0900+(0x3a)*2+1,&u8Data);
4291 u8Data &= 0xFC;
4292 _MDrv_DMD_MSB124X_SetReg(0x0900+(0x3a)*2+1, u8Data);
4293
4294 // -------------------------------------------------------------------
4295 // Initialize DMD_ANA_MISC
4296 // -------------------------------------------------------------------
4297 // [0] reg_tst_ldo25i
4298 // [1] reg_tst_ldo25q
4299 // [5:4] reg_tst_ldo25i_selfb
4300 // [7:6] reg_tst_ldo25q_selfb
4301 // [8] reg_pd_dm2p5ldoi = 1'b0
4302 // [9] reg_pd_dm2p5ldoq = 1'b0
4303 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x0A00+(0x4f)*2, 0x0000);
4304
4305 // [0] reg_tst_ldo11_clk
4306 // [1] reg_tst_ldo26
4307 // [2] reg_tst_ldo11_cmp
4308 // [3] reg_pd_dm1p1ldo_clk = 1'b0
4309 // [4] reg_pd_dm1p1ldo_cmp = 1'b0
4310 // [6] reg_tst_ldo26_selfb
4311 // [7] reg_pd_dm2p6ldo = 1'b0
4312 // [9:8] reg_tst_ldo11_cmp_selfb
4313 // [11:10] reg_tst_ldo11_clk_selfb
4314 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x0A00+(0x4e)*2, 0x0000);
4315
4316 // [1:0] reg_mpll_loop_div_first feedback divider 00:div by 1 01:div by 2 10:div by 4 11:div by 8
4317 // [15:8] reg_mpll_loop_div_second feedback divider, div by binary data number
4318 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x0A00+(0x33)*2, 0x1201);
4319
4320 // [2:0] reg_mpll_ictrl charge pump current control
4321 // [3] reg_mpll_in_sel 1.8V or 3.3V reference clock domain select (1'b0=0==>3.3 V reference clock domain)
4322 // [4] reg_mpll_xtal2adc_sel select the XTAL clock bypass to MPLL_ADC_CLK
4323 // [5] reg_mpll_xtal2next_pll_sel crystal clock bypass to next PLL select
4324 // [6] reg_mpll_vco_offset set VCO initial offset frequency
4325 // [7] reg_mpll_pd gated reference clock and power down PLL analog_3v: 1=power down
4326 // [8] reg_xtal_en XTAL enable register; 1: enable
4327 // [10:9] reg_xtal_sel XTAL driven strength select.
4328 // [11] reg_mpll_porst MPLL input power on reset, connect to reg as MPLL_RESET
4329 // [12] reg_mpll_reset PLL software reset; 1:reset
4330 // [13] reg_pd_dmpll_clk XTAL to MPLL clock reference power down
4331 // [14] reg_pd_3p3_1 XTAL to CLK_24M_3P3_1 power down
4332 // [15] reg_pd_3p3_2 XTAL to CLK_24M_3P3_2 power down
4333 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x0A00+(0x35)*2, 0x1803);
4334 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x0A00+(0x35)*2, 0x0003);
4335
4336 // [0] reg_mpll_clk_dp_pd dummy
4337 // [1] reg_adc_clk_pd ADC output clock power down
4338 // [2] reg_mpll_div2_pd MPLL_DIV2 power down
4339 // [3] reg_mpll_div3_pd MPLL_DIV3 power down
4340 // [4] reg_mpll_div4_pd MPLL_DIV4 power down
4341 // [5] reg_mpll_div8_pd MPLL_DIV8 power down
4342 // [6] reg_mpll_div10_pd MPLL_DIV10 power down
4343 // `RIU_W((`RIUBASE_ADCPLL>>1)+7'h30, 2'b11, 16'h2400); // divide ADC clock to 24Mhz = 24*36/36
4344 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x0A00+(0x30)*2, 0x0800);
4345
4346 //set MCU CLK to 108MHz
4347 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x0900+(0x0b)*2, 0x0020);
4348 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x0900+(0x0b)*2, 0x0000);
4349
4350 bRet &=_Load2Sram(MSB1245_LIB, u16dat_size,0);
4351
4352
4353 // ------disable to use TS_PAD as SSPI_PAD after load code
4354 // [0:0] reg_en_sspi_pad
4355 // [1:1] reg_ts_sspi_en, 1: use TS_PAD as SSPI_PAD
4356 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x0900 + (0x3b) * 2, 0x0001);
4357 //Transport Stream pad off
4358 bRet &= _MDrv_DMD_MSB124X_SetReg2Bytes(0x0900 + (0x2d) * 2, 0x0000);
4359 (pDemod->_sDMD_MSB124X_InitData.fpMSB124x_SPIPAD_En)(FALSE);
4360
4361 // Set Inst map for Program SRAM
4362 //set lower bound "SRAM_A_START_ADDR"
4363 bRet &= _MDrv_DMD_MSB124X_SetReg(0x1004, 0x00);
4364 bRet &= _MDrv_DMD_MSB124X_SetReg(0x1005, 0x00);
4365 bRet &= _MDrv_DMD_MSB124X_SetReg(0x1000, 0x00);
4366 //set upper bound "SRAM_A_END_ADDR"
4367 bRet &= _MDrv_DMD_MSB124X_SetReg(0x1006, 0x7F);
4368 bRet &= _MDrv_DMD_MSB124X_SetReg(0x1007, 0xFF);
4369 bRet &= _MDrv_DMD_MSB124X_SetReg(0x1002, 0x00);
4370 // Enable Program SRAM
4371 bRet &= _MDrv_DMD_MSB124X_SetReg(0x1018, 0x01);
4372
4373 // End MCU reset
4374 bRet &= _MDrv_DMD_MSB124X_SetReg(0x0b32, 0x00);
4375
4376 if (bRet==FALSE)
4377 {
4378 PRINTE(("utopia MSB1245 SPI Load FW fail!!!\n"));
4379 }
4380 else
4381 {
4382 PRINTE(("utopia MSB1245 SPI Load FW success!!!\n"));
4383 }
4384
4385 DMD_UNLOCK();
4386 return TRUE;
4387 }
4388 else
4389 {
4390 //I2C load code
4391 bRet &=_Load2Sram(MSB1245_LIB, u16dat_size,0);
4392 if (bRet==FALSE)
4393 {
4394 PRINTE(("utopia MSB1245 I2C Load FW fail!!!\n"));
4395 }
4396 else
4397 {
4398 PRINTE(("utopia MSB1245 I2C Load FW success!!!\n"));
4399 }
4400 DMD_UNLOCK();
4401 return TRUE;
4402 }
4403
4404 }
4405
MDrv_DMD_MSB124X_Power_On(void)4406 MS_BOOL MDrv_DMD_MSB124X_Power_On(void)
4407 {
4408 MS_U8 status = TRUE;
4409 tMSB124XData *pDemod = DEMOD_GET_ACTIVE_NODE();
4410
4411 #ifdef MS_DEBUG
4412 DBG_DEMOD_FLOW(printf("%s(),%d\n",__func__,__LINE__));
4413 #endif
4414 /*
4415 printf("ppp used \n");
4416 if ( _msbMSB124X_set_bonding_option( MDrv_SYS_GetChipID() ) == FALSE )
4417 {
4418 printf("hhhhh-\n");
4419 // return TRUE;
4420 }
4421 printf("hihi \n");
4422 */
4423 status &= _MSB124X_I2C_CH_Reset(3);
4424 status &= _MSB124X_HW_init();
4425
4426 if(pDemod->_sDMD_MSB124X_InitData.u8WO_Sdram==0)//with sdram on board
4427 {
4428 status &= _LoadDspCodeToSDRAM(MSB124X_ALL);//need boot code into sdram
4429 }
4430
4431 if (_LoadDSPCode() == FALSE)
4432 {
4433 printf(">>>>MSB124X:Fail\n");
4434 status= FALSE;
4435 }
4436 return TRUE;
4437 }
4438
MDrv_DMD_MSB124X_Power_On_Initialization(void)4439 MS_BOOL MDrv_DMD_MSB124X_Power_On_Initialization(void)
4440 {
4441 MS_U8 status = TRUE;
4442 MS_BOOL bMatch = false;
4443 MS_U8 u8RetryCnt = 6;
4444 tMSB124XData *pDemod = DEMOD_GET_ACTIVE_NODE();
4445 #ifdef MS_DEBUG
4446 MS_U32 u32tmm_1, u32tmm_2, u32tmm_3, u32tmm_4, u32tmm_5, u32tmm_6 = 0x00;
4447 DBG_DEMOD_FLOW(printf("%s(),%d\n",__func__,__LINE__));
4448 #endif
4449
4450 DMD_LOCK();
4451 #ifdef MS_DEBUG
4452 u32tmm_1 = MsOS_GetSystemTime();
4453 #endif
4454
4455 if (pDemod->_sDMD_MSB124X_InitData.bPreloadDSPCodeFromMainCHIPI2C)
4456 {
4457 DMD_UNLOCK();
4458 return TRUE;
4459 }
4460
4461 #ifdef MS_DEBUG
4462 if (eDMD_MSB124X_DbgLevel >= E_DMD_MSB124X_DBGLV_DEBUG)
4463 {
4464 printf(">>>MSB124X: Enter Power_On_Initialization()\n");
4465 }
4466 #endif
4467
4468 //if ( _msbMSB124X_set_bonding_option( MDrv_SYS_GetChipID() ) == FALSE )
4469 //{
4470 // DMD_UNLOCK();
4471 // return TRUE;
4472 //}
4473
4474 if (pDemod->bDMD_MSB124X_Power_init_en == TRUE)
4475 {
4476 DMD_UNLOCK();
4477 return TRUE;
4478 }
4479 else
4480 {
4481 pDemod->bDMD_MSB124X_Power_init_en = (pDemod->u8DMD_MSB124X_PowerOnInitialization_Flow == 2) ? (TRUE) : (FALSE);
4482 }
4483
4484 if(pDemod->_sDMD_MSB124X_InitData.u8WO_SPI_Flash== 1)
4485 {
4486 if (pDemod->_sDMD_MSB124X_InitData.bPreloadDSPCodeFromMainCHIPI2C)
4487 {
4488
4489 }
4490 else
4491 {
4492 status &= _MSB124X_I2C_CH_Reset(3);
4493 status &= _MSB124X_HW_init();
4494 if(pDemod->_sDMD_MSB124X_InitData.u8WO_Sdram==0)//with sdram on board
4495 {
4496 status &= _LoadDspCodeToSDRAM(MSB124X_ALL);
4497 }
4498
4499 if (_LoadDSPCode() == FALSE)
4500 {
4501 printf(">>>>MSB124X:Fail\n");
4502 status= FALSE;
4503 }
4504 }
4505 }
4506 else
4507 {
4508 #ifdef MS_DEBUG
4509 if (eDMD_MSB124X_DbgLevel >= E_DMD_MSB124X_DBGLV_DEBUG)
4510 {
4511 printf("u8DMD_MSB124X_PowerOnInitialization_Flow = %d\n", u8DMD_MSB124X_PowerOnInitialization_Flow);
4512 }
4513 #endif
4514 if(pDemod->u8DMD_MSB124X_PowerOnInitialization_Flow ==0)
4515 {
4516 status = _msb124x_flash_mode_en();
4517 if (status == FALSE)
4518 {
4519 printf("[msb124x][error]msb124x_flash_mode_en fail....\n");
4520 }
4521 pDemod->u8DMD_MSB124X_PowerOnInitialization_Flow++;
4522 }
4523 else
4524 {
4525 if(pDemod->u8DMD_MSB124X_PowerOnInitialization_Flow<2)
4526 {
4527 pDemod->u8DMD_MSB124X_PowerOnInitialization_Flow++;
4528 }
4529
4530 MS_U8 u8DoneFlag = 0;
4531 MS_U16 u16_counter = 0;
4532
4533 MS_U16 crc16 = 0;
4534
4535 crc16 = MSB124X_LIB[sizeof(MSB124X_LIB)-2];
4536 crc16 = (crc16<<8)|MSB124X_LIB[sizeof(MSB124X_LIB)-1];
4537
4538 do
4539 {
4540 printf(">>>MSB124X: u8RetryCnt = %d\n",u8RetryCnt);
4541
4542 MS_U8 flash_waiting_ready_timeout = 0;
4543 u8RetryCnt--;
4544
4545 #ifdef MS_DEBUG
4546 u32tmm_3 = MsOS_GetSystemTime();
4547 #endif
4548
4549 status = _msb124x_flash_boot_ready_waiting(&flash_waiting_ready_timeout);
4550 if ( (flash_waiting_ready_timeout == 1) || (status == FALSE) )
4551 {
4552 printf("[msb124x][error]msb124x_flash_boot_ready_waiting fail....\n");
4553 }
4554
4555 #ifdef MS_DEBUG
4556 u32tmm_4 = MsOS_GetSystemTime();
4557 printf("[tmm1]t4-t3 = %ld (%ld - %ld)\n",u32tmm_4-u32tmm_3,u32tmm_4,u32tmm_3);
4558 #endif
4559
4560 if(status == FALSE)
4561 {
4562 if (pDemod->_sDMD_MSB124X_InitData.fpGPIOReset != NULL)
4563 {
4564 #ifdef MS_DEBUG
4565 printf(">>>MSB124X: Reset Demodulator\n");
4566 #endif
4567 (pDemod->_sDMD_MSB124X_InitData.fpGPIOReset)(FALSE); // gptr->SetOff();
4568 MsOS_DelayTaskUs(resetDemodTime*1000);
4569 (pDemod->_sDMD_MSB124X_InitData.fpGPIOReset)(TRUE); // gptr->SetOn();
4570 MsOS_DelayTaskUs(waitFlashTime * 1000);
4571 }
4572
4573 if (_MSB124X_I2C_CH_Reset(3) == FALSE)
4574 {
4575 printf(">>>MSB124X CH Reset:Fail\n");
4576 status= FALSE;
4577 continue;
4578 }
4579
4580 u16_counter = 1000;
4581 do
4582 {
4583 // 10 ms
4584 MsOS_DelayTaskUs(10*1000);
4585 u16_counter--;
4586 _MDrv_DMD_MSB124X_GetReg(0x0900+(0x4f)*2, &u8DoneFlag);
4587 } while(u8DoneFlag != 0x99 && u16_counter != 0);
4588
4589 if(u16_counter == 0 && u8DoneFlag != 0x99)
4590 {
4591 printf("[wb]Err, MSB124X didn't ready yet\n");
4592 status = false;
4593 }
4594 else
4595 {
4596 status = TRUE;
4597 }
4598
4599 }
4600 // No need to switch to CH0 before SPI Flash access.
4601
4602 {
4603 #ifdef MS_DEBUG
4604 if (eDMD_MSB124X_DbgLevel >= E_DMD_MSB124X_DBGLV_DEBUG)
4605 {
4606 printf(">>>MSB124X: Check Version...");
4607 }
4608 #endif
4609
4610 if (_IspCheckVer(MSB124X_LIB, &bMatch) == FALSE)
4611 {
4612 printf(">>> ISP read FAIL!\n");
4613 status= FALSE;
4614 continue;
4615 }
4616
4617
4618 if(bMatch == FALSE)
4619 {
4620 printf(">>> IspCheckVer FAIL!\n");
4621 }
4622 else
4623 {
4624 if (_MSB124X_I2C_CH_Reset(3) == FALSE)
4625 {
4626 printf(">>>MSB124X CH Reset:Fail\n");
4627 status= FALSE;
4628 continue;
4629 }
4630 else
4631 {
4632 #ifdef MS_DEBUG
4633 if (eDMD_MSB124X_DbgLevel >= E_DMD_MSB124X_DBGLV_DEBUG)
4634 {
4635 printf(">>>MSB124X CH Reset:OK\n");
4636 }
4637 #endif
4638 }
4639
4640 if (_dram_crc_check(crc16, &bMatch) == FALSE)
4641 {
4642 printf(">>> reg read fail!\n");
4643 status= FALSE;
4644 continue;
4645 }
4646
4647 if(bMatch == FALSE)
4648 printf(">>> dram crc check FAIL!\n");
4649 else
4650 printf(">>> dram crc check OK!\n");
4651
4652
4653 }
4654
4655 if (pDemod->_sDMD_MSB124X_InitData.bFlashWPEnable)
4656 {
4657 if (bMatch == FALSE)
4658 {
4659 // disable flash WP, pull high.
4660 if(_msb124x_flash_WP(0) == FALSE)
4661 {
4662 printf("[wb]Err, FLASH WP Disable Fail!!!\n");
4663 }
4664 MsOS_DelayTaskUs(100*1000);
4665 }
4666 }
4667
4668 ////bMatch = true; //FIXME : Remove this to enable auto FW reload.
4669 if (bMatch == FALSE)// Version not match
4670 {
4671 MS_U8 bAddr[1];
4672 MS_U8 bWriteData[5]={0x4D, 0x53, 0x54, 0x41, 0x52};
4673
4674 printf(">>> Not match! Reload Flash...");
4675 if ( (sizeof(MSB124X_LIB)%256) != 0)
4676 {
4677 printf(" MSB124X_LIB 256byte alignment error!%u \n",sizeof(MSB124X_LIB));
4678 }
4679
4680 (pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_2, E_DMD_MSB124X_DEMOD_I2C_WRITE_BYTES, 0, NULL, 5, bWriteData);
4681
4682 bAddr[0] = 0x10;
4683 bWriteData[0] = 0x06;
4684 (pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_2, E_DMD_MSB124X_DEMOD_I2C_WRITE_BYTES, 1, bAddr, 1, bWriteData);
4685
4686 bWriteData[0] = 0x12;
4687 (pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_2, E_DMD_MSB124X_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, bWriteData);
4688
4689 bAddr[0] = 0x10;
4690
4691 bWriteData[0] = 0xC7;
4692 (pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_2, E_DMD_MSB124X_DEMOD_I2C_WRITE_BYTES, 1, bAddr, 1, bWriteData);
4693
4694 bWriteData[0] = 0x12;
4695 (pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_2, E_DMD_MSB124X_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, bWriteData);
4696
4697 bWriteData[0]=0x24 ;
4698 (pDemod->_sDMD_MSB124X_InitData.fpMSB124X_I2C_Access)(E_DMD_MSB124X_DEMOD_I2C_DYNAMIC_SLAVE_ID_2, E_DMD_MSB124X_DEMOD_I2C_WRITE_BYTES, 0, NULL, 1, bWriteData);
4699
4700 #ifdef MS_DEBUG
4701 printf("\t\t\tStart %ld\n", MsOS_GetSystemTime());
4702 #endif
4703 if ( (sizeof(MSB124X_LIB) - 2) > MAX_MSB124X_LIB_LEN)
4704 {
4705 printf("Err, msb124xc_lib size(%d) is larger than flash size(%d)\n", sizeof(MSB124X_LIB), MAX_MSB124X_LIB_LEN);
4706 }
4707
4708 // if (IspProcFlash(MSB124X_LIB, sizeof(MSB124X_LIB)) == MAPI_FALSE)
4709 if (_IspProcFlash(MSB124X_LIB, sizeof(MSB124X_LIB)-2) == FALSE)
4710 {
4711 printf("ISP write FAIL\n");
4712 status= FALSE;
4713 continue;
4714 }
4715 else
4716 {
4717 #ifdef MS_DEBUG
4718 printf("\t\t\tEnd %ld\n", MsOS_GetSystemTime());
4719 #endif
4720 //check again
4721 if ((_IspCheckVer(MSB124X_LIB, &bMatch) == FALSE)||(bMatch==false))
4722 {
4723 printf(">>> ISP read FAIL! bMatch %d \n",bMatch);
4724 status= FALSE;
4725 continue;
4726 }
4727 else // reset again
4728 {
4729 if (pDemod->_sDMD_MSB124X_InitData.fpGPIOReset != NULL)
4730 {
4731 #ifdef MS_DEBUG
4732 printf(">>>MSB124X[2]: Reset Demodulator\n");
4733 #endif
4734 (pDemod->_sDMD_MSB124X_InitData.fpGPIOReset)(FALSE); // gptr->SetOff();
4735 MsOS_DelayTaskUs(resetDemodTime*1000);
4736 (pDemod->_sDMD_MSB124X_InitData.fpGPIOReset)(TRUE); // gptr->SetOn();
4737 MsOS_DelayTaskUs(waitFlashTime * 1000);
4738 }
4739
4740 if (_MSB124X_I2C_CH_Reset(3) == FALSE)
4741 {
4742 printf(">>>MSB124X CH Reset:Fail\n");
4743 status= FALSE;
4744 continue;
4745 }
4746
4747 u16_counter = 1000;
4748 do
4749 {
4750 // 10 ms
4751 MsOS_DelayTaskUs(10*1000);
4752 u16_counter--;
4753 _MDrv_DMD_MSB124X_GetReg(0x0900+(0x4f)*2, &u8DoneFlag);
4754 } while(u8DoneFlag != 0x99 && u16_counter != 0);
4755
4756 if(u16_counter == 0 && u8DoneFlag != 0x99)
4757 {
4758 printf("[wb]Err, MSB124X didn't ready yet\n");
4759 status = FALSE;
4760 }
4761 else
4762 status = TRUE;
4763
4764 if (_MSB124X_I2C_CH_Reset(3) == FALSE)
4765 {
4766 printf(">>>MSB124X CH Reset:Fail\n");
4767 status= FALSE;
4768 continue;
4769 }
4770 else
4771 {
4772 printf(">>>MSB124X CH Reset:OK\n");
4773 }
4774
4775 if (_dram_crc_check(crc16, &bMatch) == FALSE)
4776 {
4777 printf(">>> reg read fail!\n");
4778 status= FALSE;
4779 continue;
4780 }
4781
4782 if(bMatch == false)
4783 printf(">>> dram crc check FAIL!\n");
4784 else
4785 printf(">>> dram crc check OK!\n");
4786 }
4787 #ifdef MS_DEBUG
4788 printf(" OK\n");
4789 #endif
4790 }
4791 }
4792 else
4793 { // Version match, do nothing
4794 #ifdef MS_DEBUG
4795 printf(">>> Match\n");
4796 #endif
4797 } // if (bMatch == false)
4798
4799 if (pDemod->_sDMD_MSB124X_InitData.bFlashWPEnable)
4800 {
4801 if (bMatch == TRUE)
4802 {
4803 // Enable flash WP, pull high.
4804 if(_msb124x_flash_WP(1) == FALSE)
4805 {
4806 printf("[wb]Err, FLASH WP Enable Fail!!!\n");
4807 }
4808 MsOS_DelayTaskUs(100*1000);
4809 }
4810 } // bFlashWPEnable
4811 }
4812
4813
4814 if (_MSB124X_I2C_CH_Reset(3) == FALSE)
4815 {
4816 printf(">>>MSB124X CH Reset:Fail\n");
4817 status= FALSE;
4818 continue;
4819 }
4820 else
4821 {
4822 #ifdef MS_DEBUG
4823 printf(">>>MSB124X CH Reset:OK\n");
4824 #endif
4825 }
4826
4827 #ifdef MS_DEBUG
4828 u32tmm_5 = MsOS_GetSystemTime();
4829 #endif
4830
4831 if (_LoadDSPCode() == FALSE)
4832 {
4833 printf(">>>>MSB124X:Fail\n");
4834 status= FALSE;
4835 continue;
4836 }
4837 else
4838 {
4839 #ifdef MS_DEBUG
4840 printf(">>>MSB124X:OK\n");
4841 #endif
4842 }
4843
4844 #ifdef MS_DEBUG
4845 u32tmm_6 = MsOS_GetSystemTime();
4846 printf("[tmm1]t6-t5 = %ld (%ld - %ld)\n",u32tmm_6-u32tmm_5,u32tmm_6,u32tmm_5);
4847 #endif
4848
4849 #ifdef MS_DEBUG
4850 {
4851 MS_U8 u8ChipRevId = 0;
4852 _MDrv_DMD_MSB124X_GetReg(0x0900+(0x01)*2, &u8ChipRevId);
4853 printf(">>>MSB124X:Edinburgh RevID:%x\n", u8ChipRevId);
4854
4855
4856 _MDrv_DMD_MSB124X_GetReg(0x0900+(0x49)*2, &u8ChipRevId);
4857 printf(">>>MSB124X:Edinburgh 0x49_L:%x\n", u8ChipRevId);
4858
4859 _MDrv_DMD_MSB124X_GetReg(0x0900+(0x49)*2+1, &u8ChipRevId);
4860 printf(">>>MSB124X:Edinburgh 0x49_H:%x\n", u8ChipRevId);
4861
4862 _MDrv_DMD_MSB124X_GetReg(0x0900+(0x4A)*2, &u8ChipRevId);
4863 printf(">>>MSB124X:Edinburgh 0x4A_L:%x\n", u8ChipRevId);
4864 }
4865 #endif
4866
4867 }while((u8RetryCnt>0)&&(status==FALSE));
4868 }
4869 }
4870
4871 if(status==FALSE)
4872 {
4873 printf("msb124x power_on_init FAIL !!!!!! \n\n");
4874 }
4875 else
4876 {
4877 #ifdef MS_DEBUG
4878 printf("msb124x power_on_init OK !!!!!! \n\n");
4879 u32tmm_2 = MsOS_GetSystemTime();
4880 printf("[tmm]t2-t1 = %ld (%ld - %ld)\n",u32tmm_2-u32tmm_1,u32tmm_2,u32tmm_1);
4881 #endif
4882 }
4883
4884 DMD_UNLOCK();
4885 return status;
4886 }
4887
4888
4889 ////////////////EXT API//////////////////////////////
MDrv_DMD_MSB124X_Init_EX(MS_S32 s32Handle,sDMD_MSB124X_InitData * pDMD_MSB124X_InitData,MS_U32 u32InitDataLen)4890 MS_BOOL MDrv_DMD_MSB124X_Init_EX(MS_S32 s32Handle, sDMD_MSB124X_InitData *pDMD_MSB124X_InitData, MS_U32 u32InitDataLen)
4891 {
4892 MS_BOOL bRet;
4893 DMD_LOCK();
4894
4895 if(MDrv_DMD_MSB124X_SwitchHandle(s32Handle) == FALSE)
4896 {
4897 DMD_UNLOCK();
4898 return FALSE;
4899 }
4900 bRet = MDrv_DMD_MSB124X_Init(pDMD_MSB124X_InitData, u32InitDataLen);
4901 DMD_UNLOCK();
4902 return bRet;
4903 }
MDrv_DMD_MSB124X_Exit_EX(MS_S32 s32Handle)4904 MS_BOOL MDrv_DMD_MSB124X_Exit_EX(MS_S32 s32Handle)
4905 {
4906 MS_BOOL bRet;
4907 DMD_LOCK();
4908 if(MDrv_DMD_MSB124X_SwitchHandle(s32Handle) == FALSE)
4909 {
4910 DMD_UNLOCK();
4911 return FALSE;
4912 }
4913 bRet = MDrv_DMD_MSB124X_Exit();
4914 DMD_UNLOCK();
4915 return bRet;
4916 }
4917 //////////////////////////////////////////////////////
MDrv_DMD_MSB124X_GetReg_EX(MS_S32 s32Handle,MS_U16 u16Addr,MS_U8 * pu8Data)4918 MS_BOOL MDrv_DMD_MSB124X_GetReg_EX(MS_S32 s32Handle, MS_U16 u16Addr, MS_U8 *pu8Data)
4919 {
4920 MS_BOOL bRet;
4921
4922 DMD_LOCK();
4923
4924 if(MDrv_DMD_MSB124X_SwitchHandle(s32Handle) == FALSE)
4925 {
4926 DMD_UNLOCK();
4927 return FALSE;
4928 }
4929 bRet = MDrv_DMD_MSB124X_GetReg(u16Addr, pu8Data);
4930 DMD_UNLOCK();
4931 return bRet;
4932 }
4933
MDrv_DMD_MSB124X_SetReg_EX(MS_S32 s32Handle,MS_U16 u16Addr,MS_U8 u8Data)4934 MS_BOOL MDrv_DMD_MSB124X_SetReg_EX(MS_S32 s32Handle, MS_U16 u16Addr, MS_U8 u8Data)
4935 {
4936 MS_BOOL bRet;
4937
4938 DMD_LOCK();
4939
4940 if(MDrv_DMD_MSB124X_SwitchHandle(s32Handle) == FALSE)
4941 {
4942 DMD_UNLOCK();
4943 return FALSE;
4944 }
4945 bRet = MDrv_DMD_MSB124X_SetReg(u16Addr, u8Data);
4946 DMD_UNLOCK();
4947 return bRet;
4948
4949 }
MDrv_DMD_MSB124X_SetRegs_EX(MS_S32 s32Handle,MS_U16 u16Addr,MS_U8 * u8pData,MS_U16 data_size)4950 MS_BOOL MDrv_DMD_MSB124X_SetRegs_EX(MS_S32 s32Handle,MS_U16 u16Addr, MS_U8* u8pData, MS_U16 data_size)
4951 {
4952 MS_BOOL bRet;
4953
4954 DMD_LOCK();
4955 if(MDrv_DMD_MSB124X_SwitchHandle(s32Handle) == FALSE)
4956 {
4957 DMD_UNLOCK();
4958 return FALSE;
4959 }
4960 bRet = MDrv_DMD_MSB124X_SetRegs(u16Addr, u8pData, data_size);
4961 DMD_UNLOCK();
4962 return bRet;
4963
4964 }
MDrv_DMD_MSB124X_SetReg2Bytes_EX(MS_S32 s32Handle,MS_U16 u16Addr,MS_U16 u16Data)4965 MS_BOOL MDrv_DMD_MSB124X_SetReg2Bytes_EX(MS_S32 s32Handle, MS_U16 u16Addr, MS_U16 u16Data)
4966 {
4967 MS_BOOL bRet;
4968
4969 DMD_LOCK();
4970 if(MDrv_DMD_MSB124X_SwitchHandle(s32Handle) == FALSE)
4971 {
4972 DMD_UNLOCK();
4973 return FALSE;
4974 }
4975 bRet = MDrv_DMD_MSB124X_SetReg2Bytes(u16Addr, u16Data);
4976 DMD_UNLOCK();
4977 return bRet;
4978
4979 }
4980
MDrv_DMD_MSB124X_GetDSPReg_EX(MS_S32 s32Handle,MS_U16 u16Addr,MS_U8 * pu8Data)4981 MS_BOOL MDrv_DMD_MSB124X_GetDSPReg_EX(MS_S32 s32Handle, MS_U16 u16Addr, MS_U8 *pu8Data)
4982 {
4983 MS_BOOL bRet;
4984
4985 DMD_LOCK();
4986 if(MDrv_DMD_MSB124X_SwitchHandle(s32Handle) == FALSE)
4987 {
4988 DMD_UNLOCK();
4989 return FALSE;
4990 }
4991 bRet = MDrv_DMD_MSB124X_GetDSPReg(u16Addr, pu8Data);
4992 DMD_UNLOCK();
4993 return bRet;
4994
4995 }
4996
MDrv_DMD_MSB124X_SetDSPReg_EX(MS_S32 s32Handle,MS_U16 u16Addr,MS_U8 u8Data)4997 MS_BOOL MDrv_DMD_MSB124X_SetDSPReg_EX(MS_S32 s32Handle, MS_U16 u16Addr, MS_U8 u8Data)
4998 {
4999 MS_BOOL bRet;
5000
5001 DMD_LOCK();
5002 if(MDrv_DMD_MSB124X_SwitchHandle(s32Handle) == FALSE)
5003 {
5004 DMD_UNLOCK();
5005 return FALSE;
5006 }
5007 bRet = MDrv_DMD_MSB124X_SetDSPReg(u16Addr, u8Data);
5008 DMD_UNLOCK();
5009 return bRet;
5010
5011 }
MDrv_DMD_MSB124X_SetCurrentDemodulatorType_EX(MS_S32 s32Handle,eDMD_MSB124X_DemodulatorType eCurrentDemodulatorType)5012 void MDrv_DMD_MSB124X_SetCurrentDemodulatorType_EX(MS_S32 s32Handle, eDMD_MSB124X_DemodulatorType eCurrentDemodulatorType)
5013 {
5014
5015 DMD_LOCK();
5016 if(MDrv_DMD_MSB124X_SwitchHandle(s32Handle) == FALSE)
5017 {
5018 DMD_UNLOCK();
5019 return ;
5020 }
5021 MDrv_DMD_MSB124X_SetCurrentDemodulatorType(eCurrentDemodulatorType);
5022 DMD_UNLOCK();
5023 return ;
5024 }
MDrv_DMD_MSB124X_LoadDSPCode_EX(MS_S32 s32Handle)5025 MS_BOOL MDrv_DMD_MSB124X_LoadDSPCode_EX(MS_S32 s32Handle)
5026 {
5027 MS_BOOL bRet;
5028
5029 DMD_LOCK();
5030 if(MDrv_DMD_MSB124X_SwitchHandle(s32Handle) == FALSE)
5031 {
5032 DMD_UNLOCK();
5033 return FALSE;
5034 }
5035 bRet = MDrv_DMD_MSB124X_LoadDSPCode();
5036 DMD_UNLOCK();
5037 return bRet;
5038
5039 }
MDrv_DMD_MSB124X_DTV_DVBT_DSPReg_CRC_EX(MS_S32 s32Handle)5040 MS_BOOL MDrv_DMD_MSB124X_DTV_DVBT_DSPReg_CRC_EX(MS_S32 s32Handle)
5041 {
5042 MS_BOOL bRet;
5043
5044 DMD_LOCK();
5045 if(MDrv_DMD_MSB124X_SwitchHandle(s32Handle) == FALSE)
5046 {
5047 DMD_UNLOCK();
5048 return FALSE;
5049 }
5050 bRet = MDrv_DMD_MSB124X_DTV_DVBT_DSPReg_CRC();
5051 DMD_UNLOCK();
5052 return bRet;
5053
5054 }
MDrv_DMD_MSB124X_Power_On_Initialization_EX(MS_S32 s32Handle)5055 extern MS_BOOL MDrv_DMD_MSB124X_Power_On_Initialization_EX(MS_S32 s32Handle)
5056 {
5057 MS_BOOL bRet;
5058
5059 DMD_LOCK();
5060 if(MDrv_DMD_MSB124X_SwitchHandle(s32Handle) == FALSE)
5061 {
5062 DMD_UNLOCK();
5063 return FALSE;
5064 }
5065 bRet = MDrv_DMD_MSB124X_Power_On_Initialization();
5066 DMD_UNLOCK();
5067 return bRet;
5068
5069 }
5070 ////////////////////////////////////////////////////////////////////////////////
5071 /// load dsp code
5072 ////////////////////////////////////////////////////////////////////////////////
MDrv_DMD_MSB1245_LoadDSPCodeToSram_EX(MS_S32 s32Handle)5073 extern MS_BOOL MDrv_DMD_MSB1245_LoadDSPCodeToSram_EX(MS_S32 s32Handle)
5074 {
5075 MS_BOOL bRet;
5076
5077 DMD_LOCK();
5078 if(MDrv_DMD_MSB124X_SwitchHandle(s32Handle) == FALSE)
5079 {
5080 DMD_UNLOCK();
5081 return FALSE;
5082 }
5083 bRet = MDrv_DMD_MSB1245_LoadDSPCodeToSram();
5084 DMD_UNLOCK();
5085 return bRet;
5086
5087 }
5088
5089
5090
5091
5092