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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 /////////////////////////////////////////////////////////////////////////////////////////////////// 96 /// 97 /// @file halDAC.h 98 /// @brief DAC Driver Interface 99 /// @author MStar Semiconductor Inc. 100 /////////////////////////////////////////////////////////////////////////////////////////////////// 101 102 #ifndef _HAL_DAC_H_ 103 #define _HAL_DAC_H_ 104 #include "UFO.h" 105 #ifdef __cplusplus 106 extern "C" { 107 #endif 108 109 //------------------------------------------------------------------------------------------------- 110 // Driver Capability 111 //------------------------------------------------------------------------------------------------- 112 113 //------------------------------------------------------------------------------------------------- 114 // Macro and Define 115 //------------------------------------------------------------------------------------------------- 116 #define NONPM_BASE (0x100000) 117 #define XC_DAC_BASE (0x101A00) 118 #define XC_LPLL_BASE (0x103100) 119 #define CHIP_REG_BASE (0x100B00) 120 #define CHIPTOP_REG_BASE (0x101E00) 121 #define HDMITX_MISC_REG_BASE (0x172A00) 122 #define CLKGEN1_BASE (0x103300) 123 #define ANA_MISC_HDMI_BASE (0x110B00) 124 #define DAC_PLL_BASE (0x121100) 125 126 // DAC PLL address offset 127 #define DAC_PLL_ADDR_OFFSET 0x120000 128 // HDMI Tx divider address offset 129 #define HDMITX_DIV_ADDR_OFFSET 0x110000 130 131 // SCALER_BASE 132 #define XC_SC_BASE (0x102F00) 133 #define XC_SC_BK_SELECT XC_SC_BASE 134 135 // HDGEN BASE 136 #define HDGEN_BASE (0x103000) 137 #define HDGEN_BK_SELECT HDGEN_BASE 138 139 // MOD_BASE 140 #define XC_MOD_BASE (0x103200) 141 #define XC_MOD_BK_SELECT XC_MOD_BASE 142 143 #define BK_SC(u32Addr) (XC_SC_BASE + (u32Addr)) 144 #define BK_HDGEN(u32Addr) (HDGEN_BASE + (u32Addr)) 145 #define BK_MOD(u32Addr) (XC_MOD_BASE + ((u32Addr) << 1)) ///< convert 16 bit address to 8 bit address 146 147 #define BK_CHIPTOP(u32Addr) (XC_LPLL_BASE + ((u32Addr) << 1)) ///< convert 16 bit address to 8 bit address) 148 #define BK_LPLL(u32Addr) (XC_LPLL_BASE + ((u32Addr) << 1)) ///< convert 16 bit address to 8 bit address 149 #define BK_DAC(u32Addr) (XC_DAC_BASE + ((u32Addr) << 1)) ///< convert 16 bit address to 8 bit address 150 #define BK_HDGEN_MAP(u16Addr) ((u16Addr>>8)&0xFF), (u16Addr&0xFF) 151 152 #define BK_REG_L( x, y ) ((x) | (((y) << 1))) 153 #define BK_REG_H( x, y ) (((x) | (((y) << 1))) + 1) 154 155 #define L_BK_DAC(x) BK_REG_L(XC_DAC_BASE, x) 156 #define H_BK_DAC(x) BK_REG_H(XC_DAC_BASE, x) 157 #define L_BK_CHIPTOP(x) BK_REG_L(CHIP_REG_BASE, x) 158 #define H_BK_CHIPTOP(x) BK_REG_H(CHIP_REG_BASE, x) 159 #define L_BK_LPLL(x) BK_REG_L(XC_LPLL_BASE, x) 160 #define H_BK_LPLL(x) BK_REG_H(XC_LPLL_BASE, x) 161 #define L_BK_HDMITX(x) BK_REG_L(HDMITX_MISC_REG_BASE, x) 162 #define H_BK_HDMITX(x) BK_REG_H(HDMITX_MISC_REG_BASE, x) 163 #define L_BK_CLKGEN1(x) BK_REG_L(CLKGEN1_BASE, x) 164 #define H_BK_CLKGEN1(x) BK_REG_H(CLKGEN1_BASE, x) 165 #define L_BK_ANA_MISC_HDMI(x) BK_REG_L(ANA_MISC_HDMI_BASE, x) 166 #define H_BK_ANA_MISC_HDMI(x) BK_REG_H(ANA_MISC_HDMI_BASE, x) 167 #define L_BK_CHIPTOP_TOP(x) BK_REG_L(CHIPTOP_REG_BASE, x) 168 #define H_BK_CHIPTOP_TOP(x) BK_REG_H(CHIPTOP_REG_BASE, x) 169 170 171 #define REG_DAC_SD_CTRL (0x00) 172 #define REG_DAC_SD_CLK (0x01) 173 #define REG_DAC_SD_SEL (0x02) 174 #define REG_DAC_HD_CTRL (0x03) 175 #define REG_DAC_HD_CLK (0x04) 176 #define REG_DAC_HD_SEL (0x05) 177 #define REG_DAC_LEVEL_CTRL (0x08) 178 #define REG_DAC_PLUG_INOUT_PERIOD (0x09) 179 #define REG_DAC_SD_DETECT_CTRL (0x0a) 180 #define REG_DAC_HD_DETECT_CTRL (0x0b) 181 #define REG_DAC_SD_CMP_RESULT (0x0c) 182 #define REG_DAC_HD_CMP_RESULT (0x0d) 183 #define REG_DAC_Delay_Sel (0x0e) 184 #define REG_DAC_GCR_LEVEL_CTRL (0x11) 185 #define REG_DAC_VSYNC_DETECT_CTRL (0x14) 186 #define REG_DAC_HD_PLUG_IN_THD (0x21) 187 #define REG_DAC_HD_PLUG_OUT_THD (0x22) 188 #define REG_DAC_HD_IRQ_CTRL (0x23) 189 #define REG_DAC_BIAS_CUR_CTRL (0x27) 190 #define REG_DAC_CHN_BUF_EN (0x28) 191 #define REG_DAC_SD_PLUG_IN_THD (0x31) 192 #define REG_DAC_SD_PLUG_OUT_THD (0x32) 193 #define REG_DAC_SD_IRQ_CTRL (0x33) 194 195 //for check VDAC IC for IDAC IC , bank CHIPTOP_REG_BASE 0x101E00 196 #define REG_CHIPTOP_DACMODE (0x60) 197 198 #define DAC_MODE_IDAC (0x3F) 199 #define DAC_MODE_VDAC (0x3E) 200 #ifdef UFO_XC_GETOUTPUTINTELACETIMING 201 #define DAC_SC_OUTPUT_INTERLACE (0x136B02) 202 #endif 203 204 #define R1BYTE(u32Addr, u8mask) \ 205 (READ_BYTE (gu32DacRiuBaseAddr + (u32Addr << 1) - (u32Addr & 1)) & BMASK(u8mask)) 206 207 // to write 0x2F02[4:3] with 2'b10, please use W1BYTE(0x2F02, 0x02, 4:3) 208 #define W1BYTE(u32Addr, u8Val, u8mask) \ 209 (WRITE_BYTE(gu32DacRiuBaseAddr + (u32Addr << 1) - (u32Addr & 1), (R1BYTE(u32Addr, 7:0) & ~BMASK(u8mask)) | (BITS(u8mask, u8Val) & BMASK(u8mask)))) 210 211 // u32Addr must be 16bit aligned 212 #define R2BYTE(u32Addr, u16mask) \ 213 (READ_WORD (gu32DacRiuBaseAddr + (u32Addr << 1)) & BMASK(u16mask)) 214 215 // u32Addr must be 16bit aligned 216 #define W2BYTE(u32Addr, u16Val, u16mask) \ 217 (WRITE_WORD(gu32DacRiuBaseAddr + (u32Addr << 1), (R2BYTE(u32Addr, 15:0) & ~BMASK(u16mask)) | (BITS(u16mask, u16Val) & BMASK(u16mask)))) 218 219 // u32Addr must be 16bit aligned 220 #define R2BYTE_TAB(u32Addr, u16mask) \ 221 (READ_WORD (gu32DacRiuBaseAddr + ( (u32Addr) << 1)) & u16mask) 222 223 // u32Addr must be 16bit aligned 224 #define W2BYTE_TAB(u32Addr, u16Val, u16mask) \ 225 (WRITE_WORD(gu32DacRiuBaseAddr + ( (u32Addr) << 1), (R2BYTE( (u32Addr) , 15:0) & ~u16mask) | ( (u16Val) & u16mask))) 226 227 // u32Addr must be 16bit aligned 228 #define W1BYTE_TAB(u32Addr, u8Val, u8mask) \ 229 (WRITE_BYTE(gu32DacRiuBaseAddr + ( (u32Addr) << 1) - (u32Addr & 1), (R1BYTE( (u32Addr) , 7:0) & ~u8mask) | ( (u8Val) & u8mask))) 230 231 //------------------------------------------------------------------------------------------------- 232 // Type and Structure 233 //------------------------------------------------------------------------------------------------- 234 235 //------------------------------------------------------------------------------------------------- 236 // Function and Variable 237 //------------------------------------------------------------------------------------------------- 238 #if defined(HAL_DAC_C) || defined(HAL_CLKSEL_C) 239 #define INTERFACE 240 #else 241 #define INTERFACE extern 242 #endif 243 244 extern MS_VIRT gu32DacRiuBaseAddr; 245 246 INTERFACE void Hal_DAC_SetIOMapBase(MS_VIRT u32NPMBase, MS_VIRT u32PMBase); 247 INTERFACE void Hal_HDMITx_InitSeq(void); 248 INTERFACE void Hal_DAC_Enable(MS_BOOL bEnable, MS_BOOL bIsYPbPr); 249 INTERFACE void Hal_DAC_SetClkInv(MS_BOOL bEnable, MS_BOOL bIsYPbPr); 250 INTERFACE void Hal_DAC_SetOutputSource(EN_DAC_OUTPUT_TYPE enOutputType, MS_BOOL bIsYPbPr); 251 INTERFACE void Hal_DAC_SetOutputLevel(EN_DAC_MAX_OUTPUT_LEVEL enLevel, MS_BOOL bIsYPbPr); 252 INTERFACE void Hal_DAC_SetOutputSwapSel(EN_DAC_SWAP_SEL enSwap,MS_BOOL bIsYPbPr); 253 INTERFACE void Hal_HDGEN_SetTiming(EN_OUTPUT_VIDEO_TIMING_TYPE enTiming); 254 //INTERFACE void Hal_ClkSel_Set(EN_OUTPUT_VIDEO_TIMING_TYPE enTiming, EN_OUTPUT_BIT_TYPE enBits); 255 INTERFACE void Hal_DAC_Power_Saving(MS_BOOL POWER_SAVING); 256 INTERFACE void Hal_DAC_OnOffSD(EN_DAC_SD_ENABLE_CTRL enBit); 257 INTERFACE EN_DAC_SD_ENABLE_CTRL Hal_DAC_GetSDStatus(void); 258 INTERFACE void Hal_DAC_OnOffHD(EN_DAC_HD_ENABLE_CTRL enBit); 259 INTERFACE EN_DAC_HD_ENABLE_CTRL Hal_DAC_GetHDStatus(void); 260 261 INTERFACE void Hal_HDGEN_SetWSSOnOff(MS_BOOL bEnable); 262 INTERFACE MS_BOOL Hal_HDGEN_GetWSSStatus(void); 263 INTERFACE void Hal_HDGEN_ResetWSSData(void); 264 INTERFACE MS_BOOL Hal_HDGEN_Set_WSS_data(MS_BOOL ben, EN_OUTPUT_VIDEO_TIMING_TYPE eVideo_Timing, MS_U16 u16wssdata); 265 INTERFACE MS_U16 Hal_HDGEN_Get_WSS_data(void); 266 INTERFACE MS_BOOL Hal_HDGEN_Set_WSS525_A_data(MS_BOOL ben, EN_OUTPUT_VIDEO_TIMING_TYPE eVideo_Timing, MS_U32 u32wssdata); 267 INTERFACE MS_U32 Hal_HDGEN_Get_WSS525_A_data(void); 268 269 //---------------------------------------------------------------- 270 // DAC - set half output current 271 // @return none 272 //---------------------------------------------------------------- 273 INTERFACE void Hal_DAC_SetIHalfOutput(MS_BOOL bEnable, MS_BOOL bIsYPbPr); 274 //---------------------------------------------------------------- 275 // DAC - set quart output current 276 // @return none 277 //---------------------------------------------------------------- 278 INTERFACE void Hal_DAC_SetQuartOutput(MS_BOOL bEnable, MS_BOOL bIsYPbPr); 279 //---------------------------------------------------------------- 280 // Hal_DAC_SetDACState - Set DAC init state 281 // @param: bEnable: TRUE for DAC is initialized, FALSE for not initialized 282 // @param: bIsYPbPr: TRUE for YPbPr, FALSE for CVBS 283 // @return none 284 //---------------------------------------------------------------- 285 INTERFACE void Hal_DAC_SetDACState(MS_BOOL bEnable, MS_BOOL bIsYPbPr); 286 //---------------------------------------------------------------- 287 // Hal_DAC_GetDACState - Get DAC init state 288 // @param: bIsYPbPr: TRUE for YPbPr, FALSE for CVBS 289 // @return: TRUE is DAC is initialized 290 //---------------------------------------------------------------- 291 INTERFACE MS_BOOL Hal_DAC_GetDACState(MS_BOOL bIsYPbPr); 292 293 //---------------------------------------------------------------- 294 // Hal_DAC_HotPlugDetect - Get DAC HotPlug state 295 // @param: SelDAC: DAC_DETECT_HD, DAC_DETECT_SD 296 // @param: DetectType: DAC_DETECT_PLUGIN, DAC_DETECT_PLUGOUT 297 // @param: bIsSignIn: Report signal is in/out 298 // @return: TRUE is working successful 299 //---------------------------------------------------------------- 300 INTERFACE MS_BOOL Hal_DAC_HotPlugDetect(EN_DAC_DETECT SelDAC, EN_DAC_DETECT_TYPE DetectType, MS_BOOL *State); 301 302 //---------------------------------------------------------------- 303 // Hal_DAC_DumpTable - Dump DAC tables 304 // @param: pDACTable: pointer to DAC table 305 // @param: u8DACtype: DAC table type 306 //---------------------------------------------------------------- 307 INTERFACE void Hal_DAC_DumpTable(MS_U8 *pDACTable, MS_U8 u8DACtype); 308 309 INTERFACE void Hal_DAC_SetDataReverse(MS_BOOL bTrue); 310 311 INTERFACE void Hal_DAC_EnableChannelBuf(MS_BOOL bTrue); 312 313 INTERFACE MS_BOOL Hal_DAC_EnableHotPlugDetectISR(MS_BOOL bEnabled); 314 315 #ifdef UFO_XC_GETOUTPUTINTELACETIMING 316 INTERFACE MS_BOOL Hal_DAC_GetOutputInterlaceTiming(void); 317 #endif 318 319 INTERFACE MS_BOOL Hal_HDGEN_EnableICT(MS_BOOL bEnable); 320 321 322 //---------------------------------------------------------------- 323 // DAC - set VGA Hsync Vsync 324 // @return none 325 //---------------------------------------------------------------- 326 INTERFACE void Hal_DAC_SetVGAHsyncVsync(MS_BOOL bEnable); 327 328 329 #ifdef __cplusplus 330 } 331 #endif 332 333 #endif 334 335 336