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MStar hereby reserves the 91 // rights to any and all damages, losses, costs and expenses resulting therefrom. 92 // 93 //////////////////////////////////////////////////////////////////////////////// 94 95 //////////////////////////////////////////////////////////////////////////////////////////////////// 96 // file halCMDQ.h 97 // @brief CMDQ HAL 98 // @author MStar Semiconductor,Inc. 99 //////////////////////////////////////////////////////////////////////////////////////////////////// 100 #ifndef __HAL_CMDQ_H__ 101 #define __HAL_CMDQ_H__ 102 103 #include "regCMDQ.h" 104 105 // Trigger Bus Defination 106 #define HAL_GE_GE2CMDQ_TRI 0xFFFF 107 #define HAL_BDMA_INT_BDMA_0 0xFFFF 108 #define HAL_BDMA_INT_BDMA_1 0xFFFF 109 #define HAL_GPU_GPU2CMDQ_TRIG 0xFFFF 110 #define HAL_GOPG0_GOP_CMDQ_INT_0 0xFFFF 111 #define HAL_GOPG1_GOP_CMDQ_INT_1 0xFFFF 112 #define HAL_GOPG2_GOP_CMDQ_INT_2 0xFFFF 113 #define HAL_GOPG3_GOP_CMDQ_INT_3 0xFFFF 114 #define HAL_SCALAR_SC2CMDQ_TRIG_0 0xFFFF 115 #define HAL_SCALAR_SC2CMDQ_TRIG_1 0xFFFF 116 #define HAL_SCALAR_SC2CMDQ_TRIG_2 0xFFFF 117 #define HAL_SCALAR_SC2CMDQ_TRIG_3 0xFFFF 118 #define HAL_AESDMA_CMDQDMA_FINISHED 0xFFFF 119 #define HAL_AESDMA_CMDQDMA_FINISHED_2 0xFFFF 120 #define HAL_VOP_DCM2GOP_VDE 0xFFFF 121 #define HAL_VOP_DCS2GOP_VDE 0xFFFF 122 #define HAL_XC_DIP_CMDQ_INT 0xFFFF 123 124 125 #define BUS_SHIFT 4 126 127 //-------------------------------------------------------------------------------------------------- 128 //-------------------------------------------------------------------------------------------------- 129 // Macro of bit operations 130 //-------------------------------------------------------------------------------------------------- 131 #define HAS_FLAG(flag, bit) ((flag) & (bit)) 132 #define SET_FLAG(flag, bit) ((flag)|= (bit)) 133 #define RESET_FLAG(flag, bit) ((flag)&= (~(bit))) 134 #define SET_FLAG1(flag, bit) ((flag)| (bit)) 135 #define RESET_FLAG1(flag, bit) ((flag)& (~(bit))) 136 //////////////////////////////////////////////// 137 // HAL API 138 //////////////////////////////////////////////// 139 void HAL_CMDQ_SetBank(MS_U32 u32BankAddr); 140 void HAL_CMDQ_Enable(void); 141 void HAL_CMDQ_Stop(void); 142 void HAL_CMDQ_Reset(void); 143 void HAL_CMDQ_Set_Miu_Length(MS_U32 value); 144 void HAL_CMDQ_Set_Miu_Request(MS_U32 value); 145 MS_BOOL HAL_CMDQ_Set_Mode(int ModeSel); 146 void HAL_CMDQ_Set_Start_Pointer(MS_U32 StartAddr); 147 void HAL_CMDQ_Set_End_Pointer(MS_U32 EndAddr); 148 void HAL_CMDQ_Set_Offset_Pointer(MS_U32 OffsetAddr); 149 void HAL_CMDQ_Set_Timer(MS_U32 time); 150 void HAL_CMDQ_Set_Ratio(MS_U32 ratio); 151 void HAL_CMDQ_Reset_Soft_Interrupt(void); 152 void HAL_CMDQ_Reset_Start_Pointer_bit(void); 153 void HAL_CMDQ_Read_Soft_Interrupt(void); 154 void HAL_CMDQ_Read_Dec_Done(void); 155 void HAL_CMDQ_Start(void); 156 MS_U32 HAL_CMDQ_Read_Dummy_Register(void); 157 void HAL_CMDQ_Write_Dummy_Register(MS_U32 DummyValue); 158 void HAL_CMDQ_Set_MIU_SELECT(MS_U32 miu_select); 159 MS_U32 HAL_CMDQ_Read_Start_Pointer(void); 160 MS_U32 HAL_CMDQ_Read_End_Pointer(void); 161 void HAL_CMDQ_Write_Dummy_Register_release_polling(int Write_bit); 162 MS_U32 HAL_CMDQ_Error_Command(MS_U32 select_bit); 163 void HAL_CMDQ_Write_Pointer(MS_U32 Write_value); 164 MS_U32 HAL_CMDQ_Read_Pointer(void); 165 MS_U32 HAL_CMDQ_Get_Write_Pointer(void); 166 167 168 169 #endif // #ifndef _CMDQ_REG_MCU_H_ 170