1 /* 2 * Copyright 2020 Rockchip Electronics Co. LTD 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 #ifndef __HAL_H265E_VEPU54X_REG_L2_H__ 18 #define __HAL_H265E_VEPU54X_REG_L2_H__ 19 20 #include "rk_type.h" 21 22 typedef struct { 23 /* 0x48 - ATF_THD0 */ 24 struct { 25 RK_U32 atf_thd0_i32 : 6; 26 RK_U32 reserved0 : 10; 27 RK_U32 atf_thd1_i32 : 6; 28 RK_U32 reserved1 : 10; 29 } atf_thd0; 30 31 /* 0x4c - ATF_THD1 */ 32 struct { 33 RK_U32 atf_thd0_i16 : 6; 34 RK_U32 reserved0 : 10; 35 RK_U32 atf_thd1_i16 : 6; 36 RK_U32 reserved1 : 10; 37 } atf_thd1; 38 39 /* 0x50 - ATF_SAD_THD0 */ 40 struct { 41 RK_U32 atf_thd0_p64 : 6; 42 RK_U32 reserved0 : 10; 43 RK_U32 atf_thd1_p64 : 6; 44 RK_U32 reserved1 : 10; 45 } atf_sad_thd0; 46 47 /* 0x54 - ATF_SAD_THD1 */ 48 struct { 49 RK_U32 atf_thd0_p32 : 6; 50 RK_U32 reserved0 : 10; 51 RK_U32 atf_thd1_p32 : 6; 52 RK_U32 reserved1 : 10; 53 } atf_sad_thd1; 54 55 /* 0x58 - ATF_SAD_WGT0 */ 56 struct { 57 RK_U32 atf_thd0_p16 : 6; 58 RK_U32 reserved0 : 10; 59 RK_U32 atf_thd1_p16 : 6; 60 RK_U32 reserved1 : 10; 61 } atf_sad_wgt0; 62 } vepu541_intra_thd; 63 64 typedef struct { 65 /* 0x48 - ATF_THD0 */ 66 struct { 67 RK_U32 atf_thd0_i32 : 10; 68 RK_U32 reserved0 : 6; 69 RK_U32 atf_thd1_i32 : 10; 70 RK_U32 reserved1 : 6; 71 } atf_thd0; 72 73 /* 0x4c - ATF_THD1 */ 74 struct { 75 RK_U32 atf_thd0_i16 : 10; 76 RK_U32 reserved0 : 6; 77 RK_U32 atf_thd1_i16 : 10; 78 RK_U32 reserved1 : 6; 79 } atf_thd1; 80 81 /* 0x50 - ATF_SAD_THD0 */ 82 struct { 83 RK_U32 atf_thd0_p64 : 10; 84 RK_U32 reserved0 : 6; 85 RK_U32 atf_thd1_p64 : 10; 86 RK_U32 reserved1 : 6; 87 } atf_sad_thd0; 88 89 /* 0x54 - ATF_SAD_THD1 */ 90 struct { 91 RK_U32 atf_thd0_p32 : 10; 92 RK_U32 reserved0 : 6; 93 RK_U32 atf_thd1_p32 : 10; 94 RK_U32 reserved1 : 6; 95 } atf_sad_thd1; 96 97 /* 0x58 - ATF_SAD_WGT0 */ 98 struct { 99 RK_U32 atf_thd0_p16 : 10; 100 RK_U32 reserved0 : 6; 101 RK_U32 atf_thd1_p16 : 10; 102 RK_U32 reserved1 : 6; 103 } atf_sad_wgt0; 104 } vepu540_intra_thd; 105 106 107 typedef struct H265eV54xL2RegSet_t { 108 /* L2 Register: 0x4 */ 109 struct { 110 RK_U32 lvl32_intra_cst_thd0 : 12; 111 RK_U32 reserved0 : 4; 112 RK_U32 lvl32_intra_cst_thd1 : 12; 113 RK_U32 reserved1 : 4; 114 } lvl32_intra_CST_THD0; 115 116 struct { 117 RK_U32 lvl32_intra_cst_thd2 : 12; 118 RK_U32 reserved0 : 4; 119 RK_U32 lvl32_intra_cst_thd3 : 12; 120 RK_U32 reserved1 : 4; 121 } lvl32_intra_CST_THD1; 122 123 struct { 124 RK_U32 lvl16_intra_cst_thd0 : 12; 125 RK_U32 reserved0 : 4; 126 RK_U32 lvl16_intra_cst_thd1 : 12; 127 RK_U32 reserved1 : 4; 128 } lvl16_intra_CST_THD0; 129 130 struct { 131 RK_U32 lvl16_intra_cst_thd2 : 12; 132 RK_U32 reserved0 : 4; 133 RK_U32 lvl16_intra_cst_thd3 : 12; 134 RK_U32 reserved1 : 4; 135 } lvl16_intra_CST_THD1; 136 137 /* 0x14-0x1c - reserved */ 138 RK_U32 lvl8_intra_CST_THD0; 139 RK_U32 lvl8_intra_CST_THD1; 140 RK_U32 lvl16_intra_UL_CST_THD; 141 142 struct { 143 RK_U32 lvl32_intra_cst_wgt0 : 8; 144 RK_U32 lvl32_intra_cst_wgt1 : 8; 145 RK_U32 lvl32_intra_cst_wgt2 : 8; 146 RK_U32 lvl32_intra_cst_wgt3 : 8; 147 } lvl32_intra_CST_WGT0; 148 149 struct { 150 RK_U32 lvl32_intra_cst_wgt4 : 8; 151 RK_U32 lvl32_intra_cst_wgt5 : 8; 152 RK_U32 lvl32_intra_cst_wgt6 : 8; 153 RK_U32 reserved2 : 8; 154 } lvl32_intra_CST_WGT1; 155 156 struct { 157 RK_U32 lvl16_intra_cst_wgt0 : 8; 158 RK_U32 lvl16_intra_cst_wgt1 : 8; 159 RK_U32 lvl16_intra_cst_wgt2 : 8; 160 RK_U32 lvl16_intra_cst_wgt3 : 8; 161 } lvl16_intra_CST_WGT0; 162 163 struct { 164 RK_U32 lvl16_intra_cst_wgt4 : 8; 165 RK_U32 lvl16_intra_cst_wgt5 : 8; 166 RK_U32 lvl16_intra_cst_wgt6 : 8; 167 RK_U32 reserved2 : 8; 168 } lvl16_intra_CST_WGT1; 169 170 /* 0x30 - RDO_QUANT */ 171 struct { 172 RK_U32 quant_f_bias_I : 10; 173 RK_U32 quant_f_bias_P : 10; 174 RK_U32 reserved : 12; 175 } rdo_quant; 176 177 /* 0x34 - ATR_THD0, reserved */ 178 struct { 179 RK_U32 atr_thd0 : 12; 180 RK_U32 reserved0 : 4; 181 RK_U32 atr_thd1 : 12; 182 RK_U32 reserved1 : 4; 183 } atr_thd0; 184 185 /* 0x38 - ATR_THD1, reserved */ 186 struct { 187 RK_U32 atr_thd2 : 12; 188 RK_U32 reserved0 : 4; 189 RK_U32 atr_thdqp : 6; 190 RK_U32 reserved1 : 10; 191 } atr_thd1; 192 193 /* 0x3c - Lvl16_ATR_WGT, reserved */ 194 struct { 195 RK_U32 lvl16_atr_wgt0 : 8; 196 RK_U32 lvl16_atr_wgt1 : 8; 197 RK_U32 lvl16_atr_wgt2 : 8; 198 RK_U32 reserved : 8; 199 } lvl16_atr_wgt; 200 201 /* 0x40 - Lvl8_ATR_WGT, reserved */ 202 struct { 203 RK_U32 lvl8_atr_wgt0 : 8; 204 RK_U32 lvl8_atr_wgt1 : 8; 205 RK_U32 lvl8_atr_wgt2 : 8; 206 RK_U32 reserved : 8; 207 } lvl8_atr_wgt; 208 209 /* 0x44 - Lvl4_ATR_WGT, reserved */ 210 struct { 211 RK_U32 lvl4_atr_wgt0 : 8; 212 RK_U32 lvl4_atr_wgt1 : 8; 213 RK_U32 lvl4_atr_wgt2 : 8; 214 RK_U32 reserved : 8; 215 } lvl4_atr_wgt; 216 217 union { 218 vepu541_intra_thd thd_541; 219 vepu540_intra_thd thd_540; 220 }; 221 222 /* 0x5c - ATF_SAD_WGT1 */ 223 struct { 224 RK_U32 atf_wgt_i16 : 6; 225 RK_U32 reserved0 : 10; 226 RK_U32 atf_wgt_i32 : 6; 227 RK_U32 reserved1 : 10; 228 } atf_sad_wgt1; 229 230 /* 0x60 - ATF_SAD_WGT2 */ 231 struct { 232 RK_U32 atf_wgt_p32 : 6; 233 RK_U32 reserved0 : 10; 234 RK_U32 atf_wgt_p64 : 6; 235 RK_U32 reserved1 : 10; 236 } atf_sad_wgt2; 237 238 /* 0x64 - ATF_SAD_OFST0 */ 239 struct { 240 RK_U32 atf_wgt_p16 : 6; 241 RK_U32 reserved : 26; 242 } atf_sad_ofst0; 243 244 /* 0x68 - ATF_SAD_OFST1, reserved */ 245 struct { 246 RK_U32 atf_sad_ofst12 : 14; 247 RK_U32 reserved0 : 2; 248 RK_U32 atf_sad_ofst20 : 14; 249 RK_U32 reserved1 : 2; 250 } atf_sad_ofst1; 251 252 /* 0x6c - ATF_SAD_OFST2, reserved */ 253 struct { 254 RK_U32 atf_sad_ofst21 : 14; 255 RK_U32 reserved0 : 2; 256 RK_U32 atf_sad_ofst30 : 14; 257 RK_U32 reserved1 : 2; 258 } atf_sad_ofst2; 259 260 /* 0x70-0x13c - LAMD_SATD_qp */ 261 RK_U32 lamd_satd_qp[52]; 262 263 /* 0x140-0x20c - LAMD_MOD_qp, combo for I and P */ 264 RK_U32 lamd_moda_qp[52]; 265 /* 0x210-0x2dc */ 266 RK_U32 lamd_modb_qp[52]; 267 268 /* 0x2e0 - MADI_CFG */ 269 struct { 270 RK_U32 reserved : 16; 271 RK_U32 madi_thd : 8; 272 RK_U32 reserved1 : 8; 273 } madi_cfg; 274 275 /* 0x2e4 - AQ_THD0 - 0x2f0 - AQ_THD3 */ 276 RK_U8 aq_tthd[16]; 277 278 /* 279 * 0x2f4 - AQ_QP_DLT0 - 0x300 - AQ_QP_DLT3 280 * only low 6 bits is valid for per step. 281 */ 282 RK_U8 aq_step[16]; 283 284 /*0x304-0x30c*/ 285 RK_U32 reserve[3]; 286 /*pre_intra class mode */ 287 // 0x0310~0x394 288 // 0x0310 289 struct { 290 RK_U32 pre_intra_cla0_m0 : 6; 291 RK_U32 pre_intra_cla0_m1 : 6; 292 RK_U32 pre_intra_cla0_m2 : 6; 293 RK_U32 pre_intra_cla0_m3 : 6; 294 RK_U32 pre_intra_cla0_m4 : 6; 295 RK_U32 reserved : 2; 296 } pre_intra_cla0_B0; 297 298 // 0x0314 299 struct { 300 RK_U32 pre_intra_cla0_m5 : 6; 301 RK_U32 pre_intra_cla0_m6 : 6; 302 RK_U32 pre_intra_cla0_m7 : 6; 303 RK_U32 pre_intra_cla0_m8 : 6; 304 RK_U32 pre_intra_cla0_m9 : 6; 305 RK_U32 reserved : 2; 306 } pre_intra_cla0_B1; 307 308 // 0x0318 309 struct { 310 RK_U32 pre_intra_cla1_m0 : 6; 311 RK_U32 pre_intra_cla1_m1 : 6; 312 RK_U32 pre_intra_cla1_m2 : 6; 313 RK_U32 pre_intra_cla1_m3 : 6; 314 RK_U32 pre_intra_cla1_m4 : 6; 315 RK_U32 reserved : 2; 316 } pre_intra_cla1_B0; 317 318 // 0x031c 319 struct { 320 RK_U32 pre_intra_cla1_m5 : 6; 321 RK_U32 pre_intra_cla1_m6 : 6; 322 RK_U32 pre_intra_cla1_m7 : 6; 323 RK_U32 pre_intra_cla1_m8 : 6; 324 RK_U32 pre_intra_cla1_m9 : 6; 325 RK_U32 reserved : 2; 326 } pre_intra_cla1_B1; 327 328 // 0x0320 329 struct { 330 RK_U32 pre_intra_cla2_m0 : 6; 331 RK_U32 pre_intra_cla2_m1 : 6; 332 RK_U32 pre_intra_cla2_m2 : 6; 333 RK_U32 pre_intra_cla2_m3 : 6; 334 RK_U32 pre_intra_cla2_m4 : 6; 335 RK_U32 reserved : 2; 336 } pre_intra_cla2_B0; 337 338 // 0x0324 339 struct { 340 RK_U32 pre_intra_cla2_m5 : 6; 341 RK_U32 pre_intra_cla2_m6 : 6; 342 RK_U32 pre_intra_cla2_m7 : 6; 343 RK_U32 pre_intra_cla2_m8 : 6; 344 RK_U32 pre_intra_cla2_m9 : 6; 345 RK_U32 reserved : 2; 346 } pre_intra_cla2_B1; 347 348 // 0x0328 349 struct { 350 RK_U32 pre_intra_cla3_m0 : 6; 351 RK_U32 pre_intra_cla3_m1 : 6; 352 RK_U32 pre_intra_cla3_m2 : 6; 353 RK_U32 pre_intra_cla3_m3 : 6; 354 RK_U32 pre_intra_cla3_m4 : 6; 355 RK_U32 reserved : 2; 356 } pre_intra_cla3_B0; 357 358 // 0x032c 359 struct { 360 RK_U32 pre_intra_cla3_m5 : 6; 361 RK_U32 pre_intra_cla3_m6 : 6; 362 RK_U32 pre_intra_cla3_m7 : 6; 363 RK_U32 pre_intra_cla3_m8 : 6; 364 RK_U32 pre_intra_cla3_m9 : 6; 365 RK_U32 reserved : 2; 366 } pre_intra_cla3_B1; 367 368 // 0x0330 369 struct { 370 RK_U32 pre_intra_cla4_m0 : 6; 371 RK_U32 pre_intra_cla4_m1 : 6; 372 RK_U32 pre_intra_cla4_m2 : 6; 373 RK_U32 pre_intra_cla4_m3 : 6; 374 RK_U32 pre_intra_cla4_m4 : 6; 375 RK_U32 reserved : 2; 376 } pre_intra_cla4_B0; 377 378 // 0x0334 379 struct { 380 RK_U32 pre_intra_cla4_m5 : 6; 381 RK_U32 pre_intra_cla4_m6 : 6; 382 RK_U32 pre_intra_cla4_m7 : 6; 383 RK_U32 pre_intra_cla4_m8 : 6; 384 RK_U32 pre_intra_cla4_m9 : 6; 385 RK_U32 reserved : 2; 386 } pre_intra_cla4_B1; 387 388 // 0x0338 389 struct { 390 RK_U32 pre_intra_cla5_m0 : 6; 391 RK_U32 pre_intra_cla5_m1 : 6; 392 RK_U32 pre_intra_cla5_m2 : 6; 393 RK_U32 pre_intra_cla5_m3 : 6; 394 RK_U32 pre_intra_cla5_m4 : 6; 395 RK_U32 reserved : 2; 396 } pre_intra_cla5_B0; 397 398 // 0x033c 399 struct { 400 RK_U32 pre_intra_cla5_m5 : 6; 401 RK_U32 pre_intra_cla5_m6 : 6; 402 RK_U32 pre_intra_cla5_m7 : 6; 403 RK_U32 pre_intra_cla5_m8 : 6; 404 RK_U32 pre_intra_cla5_m9 : 6; 405 RK_U32 reserved : 2; 406 } pre_intra_cla5_B1; 407 408 // 0x0340 409 struct { 410 RK_U32 pre_intra_cla6_m0 : 6; 411 RK_U32 pre_intra_cla6_m1 : 6; 412 RK_U32 pre_intra_cla6_m2 : 6; 413 RK_U32 pre_intra_cla6_m3 : 6; 414 RK_U32 pre_intra_cla6_m4 : 6; 415 RK_U32 reserved : 2; 416 } pre_intra_cla6_B0; 417 418 // 0x0344 419 struct { 420 RK_U32 pre_intra_cla6_m5 : 6; 421 RK_U32 pre_intra_cla6_m6 : 6; 422 RK_U32 pre_intra_cla6_m7 : 6; 423 RK_U32 pre_intra_cla6_m8 : 6; 424 RK_U32 pre_intra_cla6_m9 : 6; 425 RK_U32 reserved : 2; 426 } pre_intra_cla6_B1; 427 428 // 0x0348 429 struct { 430 RK_U32 pre_intra_cla7_m0 : 6; 431 RK_U32 pre_intra_cla7_m1 : 6; 432 RK_U32 pre_intra_cla7_m2 : 6; 433 RK_U32 pre_intra_cla7_m3 : 6; 434 RK_U32 pre_intra_cla7_m4 : 6; 435 RK_U32 reserved : 2; 436 } pre_intra_cla7_B0; 437 438 // 0x034c 439 struct { 440 RK_U32 pre_intra_cla7_m5 : 6; 441 RK_U32 pre_intra_cla7_m6 : 6; 442 RK_U32 pre_intra_cla7_m7 : 6; 443 RK_U32 pre_intra_cla7_m8 : 6; 444 RK_U32 pre_intra_cla7_m9 : 6; 445 RK_U32 reserved : 2; 446 } pre_intra_cla7_B1; 447 448 // 0x0350 449 struct { 450 RK_U32 pre_intra_cla8_m0 : 6; 451 RK_U32 pre_intra_cla8_m1 : 6; 452 RK_U32 pre_intra_cla8_m2 : 6; 453 RK_U32 pre_intra_cla8_m3 : 6; 454 RK_U32 pre_intra_cla8_m4 : 6; 455 RK_U32 reserved : 2; 456 } pre_intra_cla8_B0; 457 458 // 0x0354 459 struct { 460 RK_U32 pre_intra_cla8_m5 : 6; 461 RK_U32 pre_intra_cla8_m6 : 6; 462 RK_U32 pre_intra_cla8_m7 : 6; 463 RK_U32 pre_intra_cla8_m8 : 6; 464 RK_U32 pre_intra_cla8_m9 : 6; 465 RK_U32 reserved : 2; 466 } pre_intra_cla8_B1; 467 468 // 0x0358 469 struct { 470 RK_U32 pre_intra_cla9_m0 : 6; 471 RK_U32 pre_intra_cla9_m1 : 6; 472 RK_U32 pre_intra_cla9_m2 : 6; 473 RK_U32 pre_intra_cla9_m3 : 6; 474 RK_U32 pre_intra_cla9_m4 : 6; 475 RK_U32 reserved : 2; 476 } pre_intra_cla9_B0; 477 478 // 0x035c 479 struct { 480 RK_U32 pre_intra_cla9_m5 : 6; 481 RK_U32 pre_intra_cla9_m6 : 6; 482 RK_U32 pre_intra_cla9_m7 : 6; 483 RK_U32 pre_intra_cla9_m8 : 6; 484 RK_U32 pre_intra_cla9_m9 : 6; 485 RK_U32 reserved : 2; 486 } pre_intra_cla9_B1; 487 488 // 0x0360 489 struct { 490 RK_U32 pre_intra_cla10_m0 : 6; 491 RK_U32 pre_intra_cla10_m1 : 6; 492 RK_U32 pre_intra_cla10_m2 : 6; 493 RK_U32 pre_intra_cla10_m3 : 6; 494 RK_U32 pre_intra_cla10_m4 : 6; 495 RK_U32 reserved : 2; 496 } pre_intra_cla10_B0; 497 498 // 0x0364 499 struct { 500 RK_U32 pre_intra_cla10_m5 : 6; 501 RK_U32 pre_intra_cla10_m6 : 6; 502 RK_U32 pre_intra_cla10_m7 : 6; 503 RK_U32 pre_intra_cla10_m8 : 6; 504 RK_U32 pre_intra_cla10_m9 : 6; 505 RK_U32 reserved : 2; 506 } pre_intra_cla10_B1; 507 508 // 0x0368 509 struct { 510 RK_U32 pre_intra_cla11_m0 : 6; 511 RK_U32 pre_intra_cla11_m1 : 6; 512 RK_U32 pre_intra_cla11_m2 : 6; 513 RK_U32 pre_intra_cla11_m3 : 6; 514 RK_U32 pre_intra_cla11_m4 : 6; 515 RK_U32 reserved : 2; 516 } pre_intra_cla11_B0; 517 518 // 0x036c 519 struct { 520 RK_U32 pre_intra_cla11_m5 : 6; 521 RK_U32 pre_intra_cla11_m6 : 6; 522 RK_U32 pre_intra_cla11_m7 : 6; 523 RK_U32 pre_intra_cla11_m8 : 6; 524 RK_U32 pre_intra_cla11_m9 : 6; 525 RK_U32 reserved : 2; 526 } pre_intra_cla11_B1; 527 528 // 0x0370 529 struct { 530 RK_U32 pre_intra_cla12_m0 : 6; 531 RK_U32 pre_intra_cla12_m1 : 6; 532 RK_U32 pre_intra_cla12_m2 : 6; 533 RK_U32 pre_intra_cla12_m3 : 6; 534 RK_U32 pre_intra_cla12_m4 : 6; 535 RK_U32 reserved : 2; 536 } pre_intra_cla12_B0; 537 538 // 0x0374 539 struct { 540 RK_U32 pre_intra_cla12_m5 : 6; 541 RK_U32 pre_intra_cla12_m6 : 6; 542 RK_U32 pre_intra_cla12_m7 : 6; 543 RK_U32 pre_intra_cla12_m8 : 6; 544 RK_U32 pre_intra_cla12_m9 : 6; 545 RK_U32 reserved : 2; 546 } pre_intra_cla12_B1; 547 548 // 0x0378 549 struct { 550 RK_U32 pre_intra_cla13_m0 : 6; 551 RK_U32 pre_intra_cla13_m1 : 6; 552 RK_U32 pre_intra_cla13_m2 : 6; 553 RK_U32 pre_intra_cla13_m3 : 6; 554 RK_U32 pre_intra_cla13_m4 : 6; 555 RK_U32 reserved : 2; 556 } pre_intra_cla13_B0; 557 558 // 0x037c 559 struct { 560 RK_U32 pre_intra_cla13_m5 : 6; 561 RK_U32 pre_intra_cla13_m6 : 6; 562 RK_U32 pre_intra_cla13_m7 : 6; 563 RK_U32 pre_intra_cla13_m8 : 6; 564 RK_U32 pre_intra_cla13_m9 : 6; 565 RK_U32 reserved : 2; 566 } pre_intra_cla13_B1; 567 568 // 0x0380 569 struct { 570 RK_U32 pre_intra_cla14_m0 : 6; 571 RK_U32 pre_intra_cla14_m1 : 6; 572 RK_U32 pre_intra_cla14_m2 : 6; 573 RK_U32 pre_intra_cla14_m3 : 6; 574 RK_U32 pre_intra_cla14_m4 : 6; 575 RK_U32 reserved : 2; 576 } pre_intra_cla14_B0; 577 578 // 0x0384 579 struct { 580 RK_U32 pre_intra_cla14_m5 : 6; 581 RK_U32 pre_intra_cla14_m6 : 6; 582 RK_U32 pre_intra_cla14_m7 : 6; 583 RK_U32 pre_intra_cla14_m8 : 6; 584 RK_U32 pre_intra_cla14_m9 : 6; 585 RK_U32 reserved : 2; 586 } pre_intra_cla14_B1; 587 588 // 0x0388 589 struct { 590 RK_U32 pre_intra_cla15_m0 : 6; 591 RK_U32 pre_intra_cla15_m1 : 6; 592 RK_U32 pre_intra_cla15_m2 : 6; 593 RK_U32 pre_intra_cla15_m3 : 6; 594 RK_U32 pre_intra_cla15_m4 : 6; 595 RK_U32 reserved : 2; 596 } pre_intra_cla15_B0; 597 598 // 0x038c 599 struct { 600 RK_U32 pre_intra_cla15_m5 : 6; 601 RK_U32 pre_intra_cla15_m6 : 6; 602 RK_U32 pre_intra_cla15_m7 : 6; 603 RK_U32 pre_intra_cla15_m8 : 6; 604 RK_U32 pre_intra_cla15_m9 : 6; 605 RK_U32 reserved : 2; 606 } pre_intra_cla15_B1; 607 608 // 0x0390 609 struct { 610 RK_U32 pre_intra_cla16_m0 : 6; 611 RK_U32 pre_intra_cla16_m1 : 6; 612 RK_U32 pre_intra_cla16_m2 : 6; 613 RK_U32 pre_intra_cla16_m3 : 6; 614 RK_U32 pre_intra_cla16_m4 : 6; 615 RK_U32 reserved : 2; 616 } pre_intra_cla16_B0; 617 618 // 0x0394 619 struct { 620 RK_U32 pre_intra_cla16_m5 : 6; 621 RK_U32 pre_intra_cla16_m6 : 6; 622 RK_U32 pre_intra_cla16_m7 : 6; 623 RK_U32 pre_intra_cla16_m8 : 6; 624 RK_U32 pre_intra_cla16_m9 : 6; 625 RK_U32 reserved : 2; 626 } pre_intra_cla16_B1; 627 628 // 0x0398 0x03fC 629 RK_U32 reg_L2reserved1[26]; 630 631 // 0x400 632 RK_U32 reg_rdo_ckg_hevc; 633 634 // 0x404~0x40c 635 RK_U32 reg_L2reserved2[3]; 636 637 // 0x410 638 struct { 639 RK_U32 intra_l16_sobel_t0 : 12; 640 RK_U32 reserved0 : 4; 641 RK_U32 intra_l16_sobel_t1 : 12; 642 RK_U32 reserved1 : 4; 643 } i16_sobel_t_hevc; 644 645 struct { 646 RK_U32 intra_l16_sobel_a0_qp0 : 6; 647 RK_U32 intra_l16_sobel_a0_qp1 : 6; 648 RK_U32 intra_l16_sobel_a0_qp2 : 6; 649 RK_U32 intra_l16_sobel_a0_qp3 : 6; 650 RK_U32 intra_l16_sobel_a0_qp4 : 6; 651 RK_U32 reserved0 : 2; 652 } i16_sobel_a_00_hevc; 653 654 struct { 655 RK_U32 intra_l16_sobel_a0_qp5 : 6; 656 RK_U32 intra_l16_sobel_a0_qp6 : 6; 657 RK_U32 intra_l16_sobel_a0_qp7 : 6; 658 RK_U32 intra_l16_sobel_a0_qp8 : 6; 659 RK_U32 reserved0 : 8; 660 } i16_sobel_a_01_hevc; 661 662 struct { 663 RK_U32 intra_l16_sobel_b0_qp0 : 15; 664 RK_U32 reserved0 : 1; 665 RK_U32 intra_l16_sobel_b0_qp1 : 15; 666 RK_U32 reserved1 : 1; 667 } i16_sobel_b_00_hevc; 668 669 struct { 670 RK_U32 intra_l16_sobel_b0_qp2 : 15; 671 RK_U32 reserved0 : 1; 672 RK_U32 intra_l16_sobel_b0_qp3 : 15; 673 RK_U32 reserved1 : 1; 674 } i16_sobel_b_01_hevc; 675 676 struct { 677 RK_U32 intra_l16_sobel_b0_qp4 : 15; 678 RK_U32 reserved0 : 1; 679 RK_U32 intra_l16_sobel_b0_qp5 : 15; 680 RK_U32 reserved1 : 1; 681 } i16_sobel_b_02_hevc; 682 683 struct { 684 RK_U32 intra_l16_sobel_b0_qp6 : 15; 685 RK_U32 reserved0 : 1; 686 RK_U32 intra_l16_sobel_b0_qp7 : 15; 687 RK_U32 reserved1 : 1; 688 } i16_sobel_b_03_hevc; 689 690 struct { 691 RK_U32 intra_l16_sobel_b0_qp8 : 15; 692 RK_U32 reserved0 : 17; 693 } i16_sobel_b_04_hevc; 694 695 struct { 696 RK_U32 intra_l16_sobel_c0_qp0 : 6; 697 RK_U32 intra_l16_sobel_c0_qp1 : 6; 698 RK_U32 intra_l16_sobel_c0_qp2 : 6; 699 RK_U32 intra_l16_sobel_c0_qp3 : 6; 700 RK_U32 intra_l16_sobel_c0_qp4 : 6; 701 RK_U32 reserved0 : 2; 702 } i16_sobel_c_00_hevc; 703 704 struct { 705 RK_U32 intra_l16_sobel_c0_qp5 : 6; 706 RK_U32 intra_l16_sobel_c0_qp6 : 6; 707 RK_U32 intra_l16_sobel_c0_qp7 : 6; 708 RK_U32 intra_l16_sobel_c0_qp8 : 6; 709 RK_U32 reserved0 : 8; 710 } i16_sobel_c_01_hevc; 711 712 struct { 713 RK_U32 intra_l16_sobel_d0_qp0 : 15; 714 RK_U32 reserved0 : 1; 715 RK_U32 intra_l16_sobel_d0_qp1 : 15; 716 RK_U32 reserved1 : 1; 717 } i16_sobel_d_00_hevc; 718 719 struct { 720 RK_U32 intra_l16_sobel_d0_qp2 : 15; 721 RK_U32 reserved0 : 1; 722 RK_U32 intra_l16_sobel_d0_qp3 : 15; 723 RK_U32 reserved1 : 1; 724 } i16_sobel_d_01_hevc; 725 726 struct { 727 RK_U32 intra_l16_sobel_d0_qp4 : 15; 728 RK_U32 reserved0 : 1; 729 RK_U32 intra_l16_sobel_d0_qp5 : 15; 730 RK_U32 reserved1 : 1; 731 } i16_sobel_d_02_hevc; 732 733 struct { 734 RK_U32 intra_l16_sobel_d0_qp6 : 15; 735 RK_U32 reserved0 : 1; 736 RK_U32 intra_l16_sobel_d0_qp7 : 15; 737 RK_U32 reserved1 : 1; 738 } i16_sobel_d_03_hevc; 739 740 struct { 741 RK_U32 intra_l16_sobel_d0_qp8 : 15; 742 RK_U32 reserved0 : 17; 743 } i16_sobel_d_04_hevc; 744 745 RK_U32 i16_sobel_e_00_17_hevc[18];// 0 2 4 ... low 32bit ; 1 3 5 ... high 2bit 746 747 // 0x494 748 struct { 749 RK_U32 intra_l32_sobel_t2 : 12; 750 RK_U32 reserved0 : 4; 751 RK_U32 intra_l32_sobel_t3 : 12; 752 RK_U32 reserved1 : 4; 753 } i32_sobel_t_00_hevc; 754 755 struct { 756 RK_U32 intra_l32_sobel_t4 : 6; 757 RK_U32 reserved0 : 24; 758 759 } i32_sobel_t_01_hevc; 760 761 struct { 762 RK_U32 intra_l32_sobel_t5 : 12; 763 RK_U32 reserved0 : 4; 764 RK_U32 intra_l32_sobel_t6 : 12; 765 RK_U32 reserved1 : 4; 766 } i32_sobel_t_02_hevc; 767 768 struct { 769 RK_U32 intra_l32_sobel_a1_qp0 : 6; 770 RK_U32 intra_l32_sobel_a1_qp1 : 6; 771 RK_U32 intra_l32_sobel_a1_qp2 : 6; 772 RK_U32 intra_l32_sobel_a1_qp3 : 6; 773 RK_U32 intra_l32_sobel_a1_qp4 : 6; 774 RK_U32 reserved0 : 2; 775 } i32_sobel_a_hevc; 776 777 struct { 778 RK_U32 intra_l32_sobel_b1_qp0 : 15; 779 RK_U32 reserved0 : 1; 780 RK_U32 intra_l32_sobel_b1_qp1 : 15; 781 RK_U32 reserved1 : 1; 782 } i32_sobel_b_00_hevc; 783 784 struct { 785 RK_U32 intra_l32_sobel_b1_qp2 : 15; 786 RK_U32 reserved0 : 1; 787 RK_U32 intra_l32_sobel_b1_qp3 : 15; 788 RK_U32 reserved1 : 1; 789 } i32_sobel_b_01_hevc; 790 791 struct { 792 RK_U32 intra_l32_sobel_b1_qp4 : 15; 793 RK_U32 reserved0 : 17; 794 } i32_sobel_b_02_hevc; 795 796 struct { 797 RK_U32 intra_l32_sobel_c1_qp0 : 6; 798 RK_U32 intra_l32_sobel_c1_qp1 : 6; 799 RK_U32 intra_l32_sobel_c1_qp2 : 6; 800 RK_U32 intra_l32_sobel_c1_qp3 : 6; 801 RK_U32 intra_l32_sobel_c1_qp4 : 6; 802 RK_U32 reserved0 : 2; 803 } i32_sobel_c_hevc; 804 805 struct { 806 RK_U32 intra_l32_sobel_d1_qp0 : 15; 807 RK_U32 reserved0 : 1; 808 RK_U32 intra_l32_sobel_d1_qp1 : 15; 809 RK_U32 reserved1 : 1; 810 } i32_sobel_d_00_hevc; 811 812 struct { 813 RK_U32 intra_l32_sobel_d1_qp2 : 15; 814 RK_U32 reserved0 : 1; 815 RK_U32 intra_l32_sobel_d1_qp3 : 15; 816 RK_U32 reserved1 : 1; 817 } i32_sobel_d_01_hevc; 818 819 struct { 820 RK_U32 intra_l32_sobel_d1_qp4 : 15; 821 RK_U32 reserved0 : 17; 822 } i32_sobel_d_02_hevc; 823 // 0x4c0~0x4e4 824 RK_U32 i32_sobel_e_00_09_hevc[10];// 0 2 4 ... low 32bit ; 1 3 5 ... high 9bit 825 } H265eV54xL2RegSet; 826 827 #endif /* __HAL_H265E_VEPU54X_REG_L2_H__ */ 828