xref: /rockchip-linux_mpp/mpp/base/test/mpp_enc_cfg_test.c (revision 437bfbeb9567cca9cd9080e3f6954aa9d6a94f18)
1*437bfbebSnyanmisaka /* SPDX-License-Identifier: Apache-2.0 OR MIT */
2*437bfbebSnyanmisaka /*
3*437bfbebSnyanmisaka  * Copyright (c) 2015 Rockchip Electronics Co., Ltd.
4*437bfbebSnyanmisaka  */
5*437bfbebSnyanmisaka 
6*437bfbebSnyanmisaka #define MODULE_TAG "mpp_enc_cfg_test"
7*437bfbebSnyanmisaka 
8*437bfbebSnyanmisaka #include "mpp_log.h"
9*437bfbebSnyanmisaka #include "mpp_mem.h"
10*437bfbebSnyanmisaka #include "mpp_time.h"
11*437bfbebSnyanmisaka #include "mpp_common.h"
12*437bfbebSnyanmisaka 
13*437bfbebSnyanmisaka #include "rk_venc_cfg.h"
14*437bfbebSnyanmisaka #include "mpp_enc_cfg.h"
15*437bfbebSnyanmisaka 
main()16*437bfbebSnyanmisaka int main()
17*437bfbebSnyanmisaka {
18*437bfbebSnyanmisaka     MPP_RET ret = MPP_OK;
19*437bfbebSnyanmisaka     MppEncCfg cfg;
20*437bfbebSnyanmisaka     RK_S64 end = 0;
21*437bfbebSnyanmisaka     RK_S64 start = 0;
22*437bfbebSnyanmisaka 
23*437bfbebSnyanmisaka     mpp_enc_cfg_show();
24*437bfbebSnyanmisaka 
25*437bfbebSnyanmisaka     mpp_log("mpp_enc_cfg_test start\n");
26*437bfbebSnyanmisaka 
27*437bfbebSnyanmisaka     ret = mpp_enc_cfg_init(&cfg);
28*437bfbebSnyanmisaka     if (ret) {
29*437bfbebSnyanmisaka         mpp_err("mpp_enc_cfg_init failed\n");
30*437bfbebSnyanmisaka         goto DONE;
31*437bfbebSnyanmisaka     }
32*437bfbebSnyanmisaka 
33*437bfbebSnyanmisaka     RK_S32 rc_mode = 1;
34*437bfbebSnyanmisaka     RK_S32 bps_target = 400000;
35*437bfbebSnyanmisaka     RK_S32 aq_thrd_i[16] = {
36*437bfbebSnyanmisaka         0,  0,  0,  0,
37*437bfbebSnyanmisaka         3,  3,  5,  5,
38*437bfbebSnyanmisaka         8,  8,  8,  15,
39*437bfbebSnyanmisaka         15, 20, 25, 35
40*437bfbebSnyanmisaka     };
41*437bfbebSnyanmisaka 
42*437bfbebSnyanmisaka     RK_S32 aq_thrd_i_ret[16] = {
43*437bfbebSnyanmisaka         -1, -1, -1, -1,
44*437bfbebSnyanmisaka         -1, -1, -1, -1,
45*437bfbebSnyanmisaka         -1, -1, -1, -1,
46*437bfbebSnyanmisaka         -1, -1, -1, -1,
47*437bfbebSnyanmisaka     };
48*437bfbebSnyanmisaka 
49*437bfbebSnyanmisaka     MppEncCfgSet *impl = (MppEncCfgSet *)kmpp_obj_to_entry(cfg);
50*437bfbebSnyanmisaka 
51*437bfbebSnyanmisaka     mpp_log("before set: rc mode %d bps_target %d\n",
52*437bfbebSnyanmisaka             impl->rc.rc_mode, impl->rc.bps_target);
53*437bfbebSnyanmisaka 
54*437bfbebSnyanmisaka     start = mpp_time();
55*437bfbebSnyanmisaka     ret = mpp_enc_cfg_set_u32(cfg, "rc:mode", rc_mode);
56*437bfbebSnyanmisaka     ret = mpp_enc_cfg_set_s32(cfg, "rc:mode", rc_mode);
57*437bfbebSnyanmisaka     ret = mpp_enc_cfg_set_s32(cfg, "rc:bps", 400000);
58*437bfbebSnyanmisaka     ret = mpp_enc_cfg_set_s32(cfg, "rc:bps_target", bps_target);
59*437bfbebSnyanmisaka     end = mpp_time();
60*437bfbebSnyanmisaka     mpp_log("set s32 time %lld us\n", end - start);
61*437bfbebSnyanmisaka 
62*437bfbebSnyanmisaka     mpp_log("after  set: rc mode %d bps_target %d\n",
63*437bfbebSnyanmisaka             impl->rc.rc_mode, impl->rc.bps_target);
64*437bfbebSnyanmisaka 
65*437bfbebSnyanmisaka     rc_mode = 0;
66*437bfbebSnyanmisaka     bps_target = 0;
67*437bfbebSnyanmisaka 
68*437bfbebSnyanmisaka     mpp_log("before get: rc mode %d bps_target %d\n", rc_mode, bps_target);
69*437bfbebSnyanmisaka 
70*437bfbebSnyanmisaka     ret = mpp_enc_cfg_get_s32(cfg, "rc:mode", &rc_mode);
71*437bfbebSnyanmisaka     ret = mpp_enc_cfg_get_s32(cfg, "rc:bps_target", &bps_target);
72*437bfbebSnyanmisaka     mpp_log("after  get: rc mode %d bps_target %d\n", rc_mode, bps_target);
73*437bfbebSnyanmisaka 
74*437bfbebSnyanmisaka     mpp_log("before set: rc aq_thrd_i: %2d %2d %2d %2d %2d %2d %2d %2d %2d %2d %2d %2d %2d %2d %2d %2d\n",
75*437bfbebSnyanmisaka             aq_thrd_i_ret[0], aq_thrd_i_ret[1], aq_thrd_i_ret[2], aq_thrd_i_ret[3],
76*437bfbebSnyanmisaka             aq_thrd_i_ret[4], aq_thrd_i_ret[5], aq_thrd_i_ret[6], aq_thrd_i_ret[7],
77*437bfbebSnyanmisaka             aq_thrd_i_ret[8], aq_thrd_i_ret[9], aq_thrd_i_ret[10], aq_thrd_i_ret[11],
78*437bfbebSnyanmisaka             aq_thrd_i_ret[12], aq_thrd_i_ret[13], aq_thrd_i_ret[14], aq_thrd_i_ret[15]);
79*437bfbebSnyanmisaka 
80*437bfbebSnyanmisaka     ret = mpp_enc_cfg_set_st(cfg, "hw:aq_step_i", aq_thrd_i);
81*437bfbebSnyanmisaka     ret = mpp_enc_cfg_get_st(cfg, "hw:aq_step_i", aq_thrd_i_ret);
82*437bfbebSnyanmisaka 
83*437bfbebSnyanmisaka     mpp_log("after  get: rc aq_thrd_i: %2d %2d %2d %2d %2d %2d %2d %2d %2d %2d %2d %2d %2d %2d %2d %2d\n",
84*437bfbebSnyanmisaka             aq_thrd_i_ret[0], aq_thrd_i_ret[1], aq_thrd_i_ret[2], aq_thrd_i_ret[3],
85*437bfbebSnyanmisaka             aq_thrd_i_ret[4], aq_thrd_i_ret[5], aq_thrd_i_ret[6], aq_thrd_i_ret[7],
86*437bfbebSnyanmisaka             aq_thrd_i_ret[8], aq_thrd_i_ret[9], aq_thrd_i_ret[10], aq_thrd_i_ret[11],
87*437bfbebSnyanmisaka             aq_thrd_i_ret[12], aq_thrd_i_ret[13], aq_thrd_i_ret[14], aq_thrd_i_ret[15]);
88*437bfbebSnyanmisaka 
89*437bfbebSnyanmisaka     ret = mpp_enc_cfg_deinit(cfg);
90*437bfbebSnyanmisaka     if (ret) {
91*437bfbebSnyanmisaka         mpp_err("mpp_enc_cfg_deinit failed\n");
92*437bfbebSnyanmisaka         goto DONE;
93*437bfbebSnyanmisaka     }
94*437bfbebSnyanmisaka 
95*437bfbebSnyanmisaka DONE:
96*437bfbebSnyanmisaka     mpp_log("mpp_enc_cfg_test done %s\n", ret ? "failed" : "success");
97*437bfbebSnyanmisaka     return ret;
98*437bfbebSnyanmisaka }
99