xref: /rockchip-linux_mpp/mpp/base/test/mpp_enc_cfg_test.c (revision 437bfbeb9567cca9cd9080e3f6954aa9d6a94f18)
1 /* SPDX-License-Identifier: Apache-2.0 OR MIT */
2 /*
3  * Copyright (c) 2015 Rockchip Electronics Co., Ltd.
4  */
5 
6 #define MODULE_TAG "mpp_enc_cfg_test"
7 
8 #include "mpp_log.h"
9 #include "mpp_mem.h"
10 #include "mpp_time.h"
11 #include "mpp_common.h"
12 
13 #include "rk_venc_cfg.h"
14 #include "mpp_enc_cfg.h"
15 
main()16 int main()
17 {
18     MPP_RET ret = MPP_OK;
19     MppEncCfg cfg;
20     RK_S64 end = 0;
21     RK_S64 start = 0;
22 
23     mpp_enc_cfg_show();
24 
25     mpp_log("mpp_enc_cfg_test start\n");
26 
27     ret = mpp_enc_cfg_init(&cfg);
28     if (ret) {
29         mpp_err("mpp_enc_cfg_init failed\n");
30         goto DONE;
31     }
32 
33     RK_S32 rc_mode = 1;
34     RK_S32 bps_target = 400000;
35     RK_S32 aq_thrd_i[16] = {
36         0,  0,  0,  0,
37         3,  3,  5,  5,
38         8,  8,  8,  15,
39         15, 20, 25, 35
40     };
41 
42     RK_S32 aq_thrd_i_ret[16] = {
43         -1, -1, -1, -1,
44         -1, -1, -1, -1,
45         -1, -1, -1, -1,
46         -1, -1, -1, -1,
47     };
48 
49     MppEncCfgSet *impl = (MppEncCfgSet *)kmpp_obj_to_entry(cfg);
50 
51     mpp_log("before set: rc mode %d bps_target %d\n",
52             impl->rc.rc_mode, impl->rc.bps_target);
53 
54     start = mpp_time();
55     ret = mpp_enc_cfg_set_u32(cfg, "rc:mode", rc_mode);
56     ret = mpp_enc_cfg_set_s32(cfg, "rc:mode", rc_mode);
57     ret = mpp_enc_cfg_set_s32(cfg, "rc:bps", 400000);
58     ret = mpp_enc_cfg_set_s32(cfg, "rc:bps_target", bps_target);
59     end = mpp_time();
60     mpp_log("set s32 time %lld us\n", end - start);
61 
62     mpp_log("after  set: rc mode %d bps_target %d\n",
63             impl->rc.rc_mode, impl->rc.bps_target);
64 
65     rc_mode = 0;
66     bps_target = 0;
67 
68     mpp_log("before get: rc mode %d bps_target %d\n", rc_mode, bps_target);
69 
70     ret = mpp_enc_cfg_get_s32(cfg, "rc:mode", &rc_mode);
71     ret = mpp_enc_cfg_get_s32(cfg, "rc:bps_target", &bps_target);
72     mpp_log("after  get: rc mode %d bps_target %d\n", rc_mode, bps_target);
73 
74     mpp_log("before set: rc aq_thrd_i: %2d %2d %2d %2d %2d %2d %2d %2d %2d %2d %2d %2d %2d %2d %2d %2d\n",
75             aq_thrd_i_ret[0], aq_thrd_i_ret[1], aq_thrd_i_ret[2], aq_thrd_i_ret[3],
76             aq_thrd_i_ret[4], aq_thrd_i_ret[5], aq_thrd_i_ret[6], aq_thrd_i_ret[7],
77             aq_thrd_i_ret[8], aq_thrd_i_ret[9], aq_thrd_i_ret[10], aq_thrd_i_ret[11],
78             aq_thrd_i_ret[12], aq_thrd_i_ret[13], aq_thrd_i_ret[14], aq_thrd_i_ret[15]);
79 
80     ret = mpp_enc_cfg_set_st(cfg, "hw:aq_step_i", aq_thrd_i);
81     ret = mpp_enc_cfg_get_st(cfg, "hw:aq_step_i", aq_thrd_i_ret);
82 
83     mpp_log("after  get: rc aq_thrd_i: %2d %2d %2d %2d %2d %2d %2d %2d %2d %2d %2d %2d %2d %2d %2d %2d\n",
84             aq_thrd_i_ret[0], aq_thrd_i_ret[1], aq_thrd_i_ret[2], aq_thrd_i_ret[3],
85             aq_thrd_i_ret[4], aq_thrd_i_ret[5], aq_thrd_i_ret[6], aq_thrd_i_ret[7],
86             aq_thrd_i_ret[8], aq_thrd_i_ret[9], aq_thrd_i_ret[10], aq_thrd_i_ret[11],
87             aq_thrd_i_ret[12], aq_thrd_i_ret[13], aq_thrd_i_ret[14], aq_thrd_i_ret[15]);
88 
89     ret = mpp_enc_cfg_deinit(cfg);
90     if (ret) {
91         mpp_err("mpp_enc_cfg_deinit failed\n");
92         goto DONE;
93     }
94 
95 DONE:
96     mpp_log("mpp_enc_cfg_test done %s\n", ret ? "failed" : "success");
97     return ret;
98 }
99