1function 1: modify ddr.bin file from ddrbin_param.txt. 2 1) modify 'ddrbin_param.txt', set ddr frequency, uart info etc what you want. 3 If want to keep items default, please keep these items blank. 4 2) run 'ddrbin_tool' with argument 1: chip_name, argument 2: ddrbin_param.txt, argument 3: ddr bin file. 5 like: ./ddrbin_tool px30 ddrbin_param.txt px30_ddr_333MHz_v1.13.bin 6 7function 2: get ddr.bin file config to gen_param.txt file 8 If want to get ddrbin file config, please run like that: 9 ./ddrbin_tool px30 -g gen_param.txt px30_ddr_333MHz_v1.15.bin 10 The config will show in gen_param.txt. 11 12The detail information as following: 13 14* support ddrbin version 15 The 'X' means not support change those parameters by tool. 16 +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+ 17 | platform | uart info | ddr freq | ssmod | DDR 2T | sr pd | drv, odt, Vref etc| dis print training info | dis CBT | ddr2/3/4, lp2/3 Vref | 18 +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+ 19 | RV1108 | V1.08 | V1.08 | V1.10 | V1.08 | V1.08 | X | X | X | X | 20 +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+ 21 | PX30/RK3326 | V1.11 | X | V1.16 | V1.12 | V1.15 | X | X | X | X | 22 +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+ 23 | RK1808 | V1.03 | V1.03 | V1.05 | V1.03 | V1.04 | X | X | X | X | 24 +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+ 25 | RK322x | V1.08 | V1.08 | X | V1.09 | X | X | X | X | X | 26 +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+ 27 | RK322xh | V1.14 | X | V1.17 | V1.16 | V1.17 | X | X | X | X | 28 +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+ 29 | RK3288 | V1.11 | X | X | V1.11 | X | X | X | X | X | 30 +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+ 31 | RK3308 | V1.28 | V1.28 | V1.31 | V1.29 | V1.30 | X | X | X | X | 32 +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+ 33 | RK3308S | V2.05 | V2.05 | V2.05 | V2.05 | V2.05 | X | X | X | X | 34 +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+ 35 | RK3368 | V2.04 | V2.04 | X | V2.05 | X | X | X | X | X | 36 +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+ 37 | RK3328 | V1.14 | X | V1.17 | V1.16 | V1.17 | X | X | X | X | 38 +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+ 39 | RK3399 | V1.25 | X | V1.25 | X | X | X | X | X | X | 40 +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+ 41 | RK3399PRO NPU | V1.03 | V1.03 | V1.05 | V1.03 | V1.04 | X | X | X | X | 42 +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+ 43 | RV1126/RV1109 | V1.00 | V1.00 | V1.05 | V1.00 | V1.05 | V1.05 | X | X | X | 44 +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+ 45 | RK3566/RK3568 | V1.00 | V1.00 | V1.06 | V1.00 | V1.00 | V1.06 | V1.07 | X | V1.19 | 46 +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+ 47 | RK3588 | V1.00 | V1.00 | X | V1.00 | V1.00 | V1.00 | X | X | X | 48 +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+ 49 | RK3528 | V1.00 | V1.00 | V1.00 | V1.00 | V1.00 | V1.00 | V1.00 | X | V1.08 | 50 +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+ 51 | RK3562 | X | V1.00 | V1.00 | V1.00 | V1.00 | V1.00 | V1.00 | X | V1.05 | 52 +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+ 53 54| function | platform and ddrbin version | 55| ------------------------------------- | ------------------------------------------ | 56| first scan channel/channel mask | RK3588 V1.00/RK3399 V1.25/RK3288 V1.11 | 57| stride type | RK3588 V1.00/RK3399 V1.25/RK3288 V1.11 | 58| ext_temp_ref | RK356x V1.16 | 59| link_ecc_en | Null | 60| per_bank_ref_en | RK3588 V1.09 | 61| derate_en | RK3588 V1.09 | 62| auto_precharge_en | Null | 63| res_space_remap_portion | RK3588 V1.09 | 64| res_space_remap_all | RK3588 V1.09 | 65| rd_vref_scan_en | RK3588 V1.08 | 66| wr_vref_scan_en | RK3588 V1.08 | 67| eye_2d_scan_en | RK3588 V1.08 | 68| ch/bank/rank_mask | RK3588 V1.00 | 69| pstore base_addr/buf_size | RK3588 V1.09 | 70| uboot/atf/optee/spl/tpl log en | RK3588 V1.09 | 71| boot_fsp | RK3588 V1.09 | 72| pageclose | RK3588 V1.10 | 73| first_init_dram_type/dfs_disable | RK3588 V1.11 | 74 75* UART info 76 77uart id: uart number. 0 for uart0, 1 for uart1, 2 for uart2..., 0xf will disable uart. 78uart iomux: uart iomux info, 0 for uartn_m0, 1 for uartn_m1, 2 for uartn_m2...(like uart2_m0, uart2_m1,uart2_m2), 79or 1 for uartn_a, 2 for uartn_b, 3 for uartn_c.(like uar2a, uart2b, uart2c). 80uart baudrate: uart baudrate should be 115200 or 1500000. 81 82* disable print training information 83 84dis_train_print: 1: will disabled print training information; 0: will enable print training information. 85 86* recycle registers space(remap register space to DDR) 87 88res_space_remap_portion 891: will remap the part of registers to DDR memory space(will not larger than 4GB). 90It is PCIE and some reserved space in RK3588, and the PCIE can not be used when set to 1. 91 92res_space_remap_all 931: will wrap all registers space(include res_space_remap_portion enable space) to DDR memory space. This space would be place in larger than 4GB. 94The PCIE can be used when set to 1 in RK3588. 95 96* DDR eye scanning 971) eye_2d_scan_en: 1: will enable 2D eye scanning for debug purpose, vref and skew eye scanning. 982) wr_vref_scan_en: 1: enable vref scan and use scanning result for write. 993) rd_vref_scan_en: 1: enable vref scan and use scanning result for read. 100 101* DDR auto precharge 102 103auto_precharge_en: 1: will enable the DDR auto precharge. 104 105* DDR refresh derate 106 107derate_en: 1: will enable derate function of the LP2/LP3/LP4/LP4X/LP5. 108The high temperature will issue more refresh command and the low temperature will less. 109 110* DDR per bank refresh 111 112per_bank_ref_en: 1: will enable per bank refresh 113 114* link ECC enable 115 116link_ecc_en: 1: read/write link ecc enable. 117 118* Extended temperature refresh 119 120ext_temp_ref: 121 0: ref1x for normal chip, 2x for 3568M/3568J 122 1: fix 2x ref for all chip 123 2: fix 4x ref for all chip 124 3: fix 1x ref for all chip 125Note: If derate-enabled DDR are configured with derate_en=1, the ext_temp_ref configuration does not take effect. 126 127* pstore_base_addr pstore_buf_size 128The pstore buffer base address: pstore_base_addr << 16, 64kB align. 129The pstore buffer size: pstore_buf_size * 4KB. 130It is define the addr and size to save ddrbin log for last log. 131 132* uboot_log_en 1331: enable uboot log. 1340: disable uboot log. 135 136* atf_log_en 1371: enable atf log. 1380: disable atf log. 139 140* optee_log_en 1411: enable optee log. 1420: disable optee log. 143 144* spl_log_en 1451: enable spl log. 1460: disable spl log. 147 148* tpl_log_en 1491: enable tpl log. 1500: disable tpl log. 151 152* pageclose 1531: enable pageclose. 1540: disable pageclose. 155 156* boot_fsp 157To choose the which DDR freq to boot system. 0 means fsp0_freq, 1 means fsp1_freq, 2 means fsp2_freq, 3 means fsp3_freq, the default is 0. 158 159* first_init_dram_type 160The define first init dram type to saving initial time. 161|----------------------------|-----------------| 162| first_init_dram_type value | DDR type | 163| 0 | DDR4 | 164| 2 | DDR2 | 165| 3 | DDR3 | 166| 5 | LPDDR2 | 167| 6 | LPDDR3 | 168| 7 | LPDDR4 | 169| 8 | LPDDR4X | 170| 9 | LPDDR5 | 171| 10 | DDR5 | 172|----------------------------|-----------------| 173 174* dfs_disable 1751: disbale ddr freq switch function 1760: enable ddr freq switch function 177 178Note: 179The starting frequency is fixed to f0 frequency after turning off the frequency scaling. 180If the DDR frequency needs to be modified, ddrx_f0_freq/fsp0_freq should be modified. 181 182* DDR (final) freq(also called ddrx_f0_freq_mhz/fsp0_freq) 183 184For RK3588, the boot_fsp used to choose which ddrx_fx_freq_mhz/fspx_freq to boot system, default is ddrx_f0_freq_mhz/fsp0_freq. 185For the others platform, it is the final freq to boot system. 186 187ddr2_freq(ddr2_f0_freq_mhz): ddr2 frequency, unit:MHz. 188lp2_freq (lp2_f0_freq_mhz): lpddr2 frequency, unit:MHz. 189ddr3_freq(ddr3_f0_freq_mhz): ddr3 frequency, unit:MHz. 190lp3_freq (lp3_f0_freq_mhz): lpddr3 frequency, unit:MHz. 191ddr4_freq(ddr4_f0_freq_mhz): ddr4 frequency, unit:MHz. 192lp4_freq (lp4_f0_freq_mhz): lpddr4 frequency, unit:MHz. 193lp4x_freq(lp4x_f0_freq_mhz): lpddr4x frequency, unit:MHz. 194lp5_freq (lp5_f0_freq_mhz): lpddr5 frequency, unit:MHz. 195 196* support ddr frequency: 197The 'X' as follows means not support change frequencies by tool. 198+---------------+-----------------------------------------------------------------+ 199| platform | support frequencies(MHZ) | 200+---------------+-----------------------------------------------------------------+ 201| RK1108 | DDR2: 400; LP2: <= 533; DDR3: <= 800 | 202+---------------+-----------------------------------------------------------------+ 203| PX30/RK3326 | X | 204+---------------+-----------------------------------------------------------------+ 205| RK1808 | 333,400,533,666,786,933 | 206+---------------+-----------------------------------------------------------------+ 207| RK322x | DDR2/LP2: <= 533; others: <= 800 | 208+---------------+-----------------------------------------------------------------+ 209| RK322xh | X | 210+---------------+-----------------------------------------------------------------+ 211| RK3288 | X | 212+---------------+-----------------------------------------------------------------+ 213| RK3308/RK3308S| DDR2/LP2: 393,451; DDR3: 393,451,589 | 214+---------------+-----------------------------------------------------------------+ 215| RK3368 | DDR3: <= 800; LP3: <= 666 | 216+---------------+-----------------------------------------------------------------+ 217| RK3328 | X | 218+---------------+-----------------------------------------------------------------+ 219| RK3399 | X | 220+---------------+-----------------------------------------------------------------+ 221| RK3399PRO NPU | 333,400,533,666,786,933 | 222+---------------+-----------------------------------------------------------------+ 223| RV1126/RV1109 | 328,396,528,664,784,924,1056 | 224+---------------+-----------------------------------------------------------------+ 225| RK3566 | 324,396,528,630,780,920,1056 | 226+---------------+-----------------------------------------------------------------+ 227| RK3568 | DDR3/LP3: 324,396,528,630,780,920,1056 | 228| | DDR4/LP4/LP4X: 324,396,528,630,780,920,1056,1184,1332,1560 | 229+---------------+-----------------------------------------------------------------+ 230| RK3588 | LP4/LP4x [306.5MHz - 2133MHz]; LP5: [400MHz - 2750MHz] | 231+---------------+-----------------------------------------------------------------+ 232| RK3528 | DDR3/LP3/LP4/LP4X: 324,396,528,630,780,920,1056 | 233| | DDR4: 324,396,528,630,780,920,1056,1184 | 234+---------------+-----------------------------------------------------------------+ 235| RK3562 | DDR3/LP3: [324MHz - 1056MHz]; LP4/LP4X/DDR4: [324MHz - 1392MHz] | 236+---------------+-----------------------------------------------------------------+ 237 238* DDR frequencies(add more) 239 240ddr2_f1_freq_mhz: ddr2 frequency fsp 1, unit:MHz. 241ddr2_f2_freq_mhz: ddr2 frequency fsp 2, unit:MHz. 242ddr2_f3_freq_mhz: ddr2 frequency fsp 3, unit:MHz. 243ddr2_f4_freq_mhz: ddr2 frequency fsp 4, unit:MHz. 244ddr2_f5_freq_mhz: ddr2 frequency fsp 5, unit:MHz. 245... 246The ddrx_f0_freq_mhz(the fsp0 frequency) is named ddrx_freq. 247 248ddr*_f*_freq_mhz/lp*_f*_freq_mhz: Only RV1126/RV1109, RK3566/RK3568, RK3588 used. 249The program will initialize dram by following order. 250for example: ddr4_f1_freq_mhz --> ddr4_f2_freq_mhz --> ddr4_f3_freq_mhz --> ddr4_freq. 251And the final frequency is ddr4_freq to boot system. 252The ddr frequency table in kernel dts/dtsi file need correspond to these frequencies. 253So it is better to arrange the frequency values in order as above. That means the max freq is in final freq(lp*/ddr*_freq) and the min freq is in 'ddr*/lp*_f1_freq_mhz'. 254Such as: ddr*/lp*_f1_freq_mhz < ddr*/lp*_f2_freq_mhz < ddr*/lp*_f3_freq_mhz < lp*/ddr*_freq(the final freq) 255For example: 256 ... 257 ddr4_freq=1560 258 ... 259 ddr4_f1_freq_mhz=324 260 ddr4_f2_freq_mhz=528 261 ddr4_f3_freq_mhz=780 262 ... 263 264Note: The ddr frequency table in kernel dts/dtsi file need correspond to these frequencies. 265 266* SR PD idle 267 268sr_idle: auto self-refresh mode delay time. 269pd_idle: auto power-down mode delay time. 270 271* DDR 2T 272 273ddr_2t: ddr 2T timing mode. 1: enable ddr 2T, 0: disable ddr 2T. 274 275* PLL ssmod 276 277These parameters are about Spread Spectrum Modulator(ssmod) for PLL. 278ssmod_downspread: ssmod work mode. 2792'b00: center spread. (Suggest to use center spread for better clock jitter) 2802'b01: down spread. 2812'b10: up spread.(Please refer to the datasheet for support information) 2822'b11: reserved 283 284ssmod_div: Divider required to set the modulation frequency. 285 RK3308 suggests to ssmod_div=2, others platforms suggest to ssmod_div=5. 286ssmod_spread: spread amplitude % = 0.1 * ssmod_spread; 0: disable ssmod, others will enable ssmod, max to 0x1f. 287 The larger the ssmod_spread value, the smaller of EMI, the worse of clk jitter. 288 Suggest to use ssmod_spread = 5, which means the center spread is +/-0.5%. 289Please refer to "Rockchip_Developer_Guide_Pll_Ssmod_Clock_CN" for more information. 290 291* driver strength 292 293phy_ddr*_dq_drv_when_odten_ohm: The PHY DQ/DQS driver strength(write direction) when DRAM odt on. unit: ohm. 294phy_ddr*_ca_drv_when_odten_ohm: The PHY CMD/ADDR driver strength when DRAM odt on. unit: ohm. 295phy_ddr*_clk_drv_when_odten_ohm: The PHY clock driver strength when DRAM odt on. unit: ohm. 296ddr*_dq_drv_when_odten_ohm: The DRAM DQ/DQS driver strength(read direction) when PHY odt on. unit: ohm. 297phy_ddr*_dq_drv_when_odtoff_ohm: The PHY DQ/DQS driver strength(write direction) when DRAM odt off. unit: ohm. 298phy_ddr*_ca_drv_when_odtoff_ohm: The PHY CMD/ADDR driver strength when DRAM odt off. unit: ohm. 299phy_ddr*_clk_drv_when_odtoff_ohm: The PHY clock driver strength when DRAM odt off. unit: ohm. 300ddr*_dq_drv_when_odtoff_ohm: The DRAM DQ/DQS driver strength(read direction) when PHY odt off. unit: ohm. 301 302The phy side driver strength support value as follows: 303+---------------+-------------------+-------------------+--------------+-----------------+----------------+----------------+-------------+ 304| platform | DDR3 | DDR4 | LP3 | LP4 | LP4X pull up | LP4X pull down | LP5 | 305+---------------+-------------------+-------------------+--------------+-----------------+----------------+----------------+-------------+ 306| | 455,230,153,115, | 482,244,162,122, | | 501,253,168,126,| | | | 307| | 91,76,65,57,51,46,| 97,81,69,61,54,48,| | 101,84,72,63,56,| | | | 308| RV1126/RV1109 | 41,38,35,32,30,28,| 44,40,37,34,32,30,| follow DDR4 | 50,46,42,38,36, | follow LP4 | follow LP4 | X | 309| | 27,25,24,23,22,21,| 28,27,25,24,23,22,| | 33,31,29,28,26, | | | | 310| | 20 | 21 | | 25,24,23,22 | | | | 311+---------------+-------------------+-------------------+--------------+-----------------+----------------+----------------+-------------+ 312| | 500,250,167,125, | 556,279,185,139, | | 576,289,192,144,| 646,323,215, | 513,259,172, | | 313| | 100,83,71,63,56, | 111,93,79,69,62, | | 115,96,82,72,64,| 162,129,108,92,| 130,104,86,74, | | 314| RK3566/RK3568 | 50,45,41,38,36,33,| 55,50,46,42,39,37,| follow DDR4 | 57,52,48,44,41, | 81,72,65,59,54,| 65,58,52,47,43,| X | 315| | 31,29,28,26,25,24,| 34,32,31,29,27,26,| | 38,36,34,32,30, | 50,46,43,40,38,| 40,37,35,32,30,| | 316| | 23,22 | 25,24 | | 28,27,26,25 | 36,34,32,31,29,| 29,27,26,25,24,| | 317| | | | | | 28 | 23 | | 318+---------------+-------------------+-------------------+--------------+-----------------+----------------+----------------+-------------+ 319| RK3588 | X | X | X | 240,120,80,60, | follow LP4 | follow LP4 | follow LP4 | 320| | | | | 48,40,34,30 | | | | 321+---------------+-------------------+-------------------+--------------+-----------------+----------------+----------------+-------------+ 322| | 572,289,195,145, | 595,300,202,151, | | 654,328,221,165,| 585,297,202, | 585,297,202, | | 323| | 117,99,85,73,66, | 122,102,89,76,68, | |133,112,97,83,74,| 150,122,103,90,| 150,122,103,90,| | 324| RK3528 | 60,55,50,47,44,41,| 62,57,52,49,45,43,| follow DDR4 | 67,62,57,53,49, | 77,69,63,58,53,| 77,69,63,58,53,| X | 325| | 38,36,34,33,31,30,| 39,37,35,34,32,31,| | 46,43,40,38,37, | 50,47,44,40,38,| 50,47,44,40,38,| | 326| | 29,28 | 30,29 | | 35,33,32,31 | 37,35,33,32,31,| 37,35,33,32,31,| | 327| | | | | | 30 | 30 | | 328+---------------+-------------------+-------------------+--------------+-----------------+----------------+----------------+-------------+ 329 330The DRAM side driver strength support value as follows: 331+---------------+-------------------+-------------------+----------------+----------------------+----------------+-------------+ 332| platform | DDR3 | DDR4 | LP3 | LP4 | LP4X | LP5 | 333+---------------+-------------------+-------------------+----------------+----------------------+----------------+-------------+ 334| all | 40,34 | 34,48 | 34,40,48,60,80 | 40,48,60,80,120,240 | follow LP4 | follow LP4 | 335+---------------+-------------------+-------------------+----------------+----------------------+----------------+-------------+ 336 337* ODT 338phy_ddr*_odt_ohm: The PHY ODT strength(read direction). unit: ohm. 339ddr*_odt_ohm: The DRAM ODT strength(write direction). unit: ohm. 340phy_ddr*_odt_pull_up_en: 1: enable PHY pull up odt. 0: disable 341phy_ddr*_odt_pull_dn_en: 1: enable PHY pull down odt. 0: disable 342phy_ddr*_odten_freq_mhz: The PHY odt enable when larger than this frequency. unit: MHz. 343ddr*_odten_freq_mhz: The DRAM odt(DQ/DQS) enable when larger than this frequency. unit: MHz. 344 345The phy side ODT support value as follows: 346The ODT "0" means disabled ODT. 347+---------------+-------------------+--------------------+--------------+-------------------+----------------+----------------+-------------+ 348| platform | DDR3 | DDR4 | LP3 | LP4 | LP4X pull up | LP4X pull down | LP5 | 349+---------------+-------------------+--------------------+--------------+-------------------+----------------+----------------+-------------+ 350| | 0,561,282,188,141,| 0,586,294,196,148, | | 0,604,303,202,152,| | | | 351| | 113,94,81,72,64, | 118,99,58,76,67,60,| | 122,101,87,78,69, | | | | 352| RV1126/RV1109 | 58,52,48,44,41, | 55,50,46,43,40,38, | follow DDR4 | 62,56,52,48,44,41,| follow LP4 | follow LP4 | X | 353| | 38,37,34,32,31,29,| 36,34,32,31,29,28, | | 39,37,35,33,32,30,| | | | 354| | 28,27,25 | 27 | | 29,27 | | | | 355+---------------+-------------------+--------------------+--------------+-------------------+----------------+----------------+-------------+ 356| | 0,500,250,167,125,| 0,556,279,185,139, | | 0,576,289,192,144,| 0,646,323,215, | 0,513,259,172, | | 357| | 100,83,71,63,56, | 111,93,79,69,62, | | 115,96,82,72,64, | 162,129,108,92,| 130,104,86,74, | | 358| RK3566/RK3568 | 50,45,41,38,36,33,| 55,50,46,42,39,37, | follow DDR4 | 57,52,48,44,41, | 81,72,65,59,54,| 65,58,52,47,43,| X | 359| | 31,29,28,26,25,24,| 34,32,31,29,27,26, | | 38,36,34,32,30, | 50,46,43,40,38,| 40,37,35,32,30,| | 360| | 23,22 | 25,24 | | 28,27,26,25 | 36,34,32,31,29,| 29,27,26,25,24,| | 361| | | | | | 28 | 23 | | 362+---------------+-------------------+--------------------+--------------+-------------------+----------------+----------------+-------------+ 363| RK3588 | X | X | X | 0,240,120,80, | follow LP4 | follow LP4 | follow LP4 | 364| | | | | 60,48,40,34,30 | | | | 365+---------------+-------------------+--------------------+--------------+-------------------+----------------+----------------+-------------+ 366| | 572,289,195,145, | 595,300,202,151, | | 654,328,221,165, | 585,297,202, | 585,297,202, | | 367| | 117,99,85,73,66, | 122,102,89,76,68, | |133,112,97,83,74, | 150,122,103,90,| 150,122,103,90,| | 368| RK3528 | 60,55,50,47,44,41,| 62,57,52,49,45,43, | follow DDR4 | 67,62,57,53,49, | 77,69,63,58,53,| 77,69,63,58,53,| X | 369| | 38,36,34,33,31,30,| 39,37,35,34,32,31, | | 46,43,40,38,37, | 50,47,44,40,38,| 50,47,44,40,38,| | 370| | 29,28 | 30,29 | | 35,33,32,31 | 37,35,33,32,31,| 37,35,33,32,31,| | 371| | | | | | 30 | 30 | | 372+---------------+-------------------+--------------------+--------------+-------------------+----------------+----------------+-------------+ 373The DRAM side ODT support value as follows: 374+---------------+-------------------+-------------------+--------------+-----------------------+----------------+---------------+ 375| platform | DDR3 | DDR4 | LP3 | LP4(include DQ and CA)| LP4X | LP5 | 376+---------------+-------------------+-------------------+--------------+-----------------------+----------------+---------------+ 377| all | 0,40,60,120 | 0,34,40,48,60,120 | 0,60,120,240 | 0,40,48,60,80,120,240 | follow LP4 | follow LP4 | 378+---------------+-------------------+-------------------+--------------+-----------------------+----------------+---------------+ 379 380* slew rate 381 382phy_ddr*_dq_sr_when_odten: The PHY DQ/DQS slew rate when odt on. 383phy_ddr*_ca_sr_when_odten: The PHY CMD/ADDR slew rate when odt on. 384phy_ddr*_clk_sr_when_odten: The PHY clock slew rate when odt on. 385phy_ddr*_dq_sr_when_odtoff: The PHY DQ/DQS slew rate when odt off. 386phy_ddr*_ca_sr_when_odtoff: The PHY CMD/ADDR slew rate when odt off. 387phy_ddr*_clk_sr_when_odtoff: The PHY clock slew rate when odt off. 388 389The max value is 0x1f, the min is 0x0. 390 391* byte map 392 393ddr*_bytes_map: The bytes remap in PHY. 394 395* dq remap 396 397lp*_dq*_*_map: The dq remap in PHY. 398ddr*_cs*_dq*_dq*_map: The dq remap in PHY. 399 400* lp4/lp4x more information 401 402lp4*_ca_odten_freq_mhz: The DRAM CMD/ADDR odt enable when larger than this frequency. unit: MHz. 403 404* vref 405 406phy_ddr*_dq_vref_when_odten: The PHY VrefDQ when PHY odt on. uint: parts per thousand. 407ddr*_dq_vref_when_odten: The DRAM VrefDQ when DRAM DQ/DQS odt on. uint: parts per thousand. 408ddr*_ca_vref_when_odten: The DRAM VrefCA when DRAM CA odt on. uint: parts per thousand. 409phy_ddr*_dq_vref_when_odtoff: The PHY VrefDQ when PHY odt off. uint: parts per thousand. 410ddr*_dq_vref_when_odtoff: The DRAM VrefDQ when DRAM DQ/DQS odt off. uint: parts per thousand. 411ddr*_ca_vref_when_odtoff: The DRAM VrefCA when DRAM CA odt off. uint: parts per thousand. 412 413For DDR2/3/4 and LPDDR2/3, if the configuration value is "0", Vref is automatically calculated by the code. 414 415* hash info 416ch/bank/rank_mask*: is used to DDR address hash mask. 417 418* modify skew info 419 420ddr*_skew_freq_mhz: Used to specify the frequency of skew. 421 422ddr*_skew: The skew value of dram type are need to modify. If need to modify skew, you must check with the hardware engineer. 423 424The support platform: 425|---------------------------|--------------------|--------------------------------------------| 426| platform | ddrbin version | calculate one step delay(ps) | 427| RK3528 | V1.06 | 1000000 / ddr*_skew_freq_mhz / 128 | 428|---------------------------|--------------------|--------------------------------------------| 429 430For RK3528, the skew one step is 7.398ps when ddr*_skew_freq_mhz is 1056. 431 432Before modify skew, it is recommended to read every CA skew from the bin file and then adjust the CA skew which want to change. 433