1function 1: modify ddr.bin file from ddrbin_param.txt. 2 1) modify 'ddrbin_param.txt', set ddr frequency, uart info etc what you want. 3 If want to keep items default, please keep these items blank. 4 2) run 'ddrbin_tool.py' with argument 1: chip_name, argument 2: ddrbin_param.txt, argument 3: ddr bin file. 5 like: ./ddrbin_tool.py px30 ddrbin_param.txt px30_ddr_333MHz_v1.13.bin 6 7function 2: get ddr.bin file config to gen_param.txt file 8 If want to get ddrbin file config, please run like that: 9 ./ddrbin_tool.py px30 -g gen_param.txt px30_ddr_333MHz_v1.15.bin 10 The config will show in gen_param.txt. 11 12The detail information as following: 13 14* support ddrbin version 15 The 'X' means not support change those parameters by tool. 16 +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+ 17 | platform | uart info | ddr freq | ssmod | DDR 2T | sr pd | drv, odt, Vref etc| dis print training info | dis CBT | ddr2/3/4, lp2/3 Vref | 18 +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+ 19 | RV1108 | V1.08 | V1.08 | V1.10 | V1.08 | V1.08 | X | X | X | X | 20 +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+ 21 | PX30/RK3326 | V1.11 | X | X | V1.12 | X | X | X | X | X | 22 +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+ 23 | RK1808 | V1.03 | V1.03 | V1.05 | V1.03 | V1.04 | X | X | X | X | 24 +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+ 25 | RK322x | V1.08 | V1.08 | X | V1.09 | X | X | X | X | X | 26 +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+ 27 | RK322xh | V1.14 | X | V1.17 | V1.16 | V1.17 | X | X | X | X | 28 +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+ 29 | RK3288 | V1.11 | X | X | V1.11 | X | X | X | X | X | 30 +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+ 31 | RK3308 | V1.28 | V1.28 | V1.31 | V1.29 | V1.30 | X | X | X | X | 32 +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+ 33 | RK3308S | V2.05 | V2.05 | V2.05 | V2.05 | V2.05 | X | X | X | X | 34 +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+ 35 | RK3368 | V2.04 | V2.04 | X | V2.05 | X | X | X | X | X | 36 +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+ 37 | RK3328 | V1.14 | X | V1.17 | V1.16 | V1.17 | X | X | X | X | 38 +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+ 39 | RK3399 | V1.25 | X | V1.25 | X | X | X | X | X | X | 40 +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+ 41 | RK3399PRO NPU | V1.03 | V1.03 | V1.05 | V1.03 | V1.04 | X | X | X | X | 42 +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+ 43 | RV1126/RV1109 | V1.00 | V1.00 | V1.05 | V1.00 | V1.05 | V1.05 | X | X | X | 44 +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+ 45 | RK3566/RK3568 | V1.00 | V1.00 | V1.06 | V1.00 | V1.00 | V1.06 | V1.07 | X | V1.19 | 46 +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+ 47 | RK3588 | V1.00 | V1.00 | X | V1.00 | V1.00 | V1.00 | X | X | X | 48 +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+ 49 | RK3528 | V1.00 | V1.00 | V1.00 | V1.00 | V1.00 | V1.00 | V1.00 | X | V1.08 | 50 +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+ 51 | RK3562 | X | V1.00 | V1.00 | V1.00 | V1.00 | V1.00 | V1.00 | X | V1.05 | 52 +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+ 53 | RV1106/RV1103 | V1.10 | V1.10 | V1.10 | V1.10 | V1.10 | X | X | X | X | 54 +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+ 55 | RV1126B/BP | V1.00 | V1.00 | V1.00 | V1.00 | V1.00 | V1.00 | V1.00 | X | V1.00 | 56 +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+ 57 58| function | platform and ddrbin version | 59| ------------------------------------- | ------------------------------------------ | 60| first scan channel/channel mask | RK3588 V1.00/RK3399 V1.25/RK3288 V1.11 | 61| stride type | RK3588 V1.00/RK3399 V1.25/RK3288 V1.11 | 62| ext_temp_ref | RK356x V1.16/RK3528 V1.07/RK1808 V1.06/RV1126B V1.00 | 63| link_ecc_en | Null | 64| per_bank_ref_en | RK3588 V1.09/RV1126B V1.00 | 65| derate_en | RK3588 V1.09/RK356x V1.19/RK3528 V1.07/RV1126B V1.00 | 66| auto_precharge_en | Null | 67| res_space_remap_portion | RK3588 V1.09 | 68| res_space_remap_all | RK3588 V1.09 | 69| rd_vref_scan_en | RK3588 V1.08/RV1126B V1.00 | 70| wr_vref_scan_en | RK3588 V1.08/RV1126B V1.00 | 71| eye_2d_scan_en | RK3588 V1.08 | 72| ch/bank/rank_mask | RK3588 V1.00 | 73| pstore base_addr/buf_size | RK3588 V1.09 | 74| uboot/atf/optee/spl/tpl log en | RK3588 V1.09 | 75| boot_fsp | RK3588 V1.09 | 76| pageclose | RK3588 V1.10/RV1126B V1.00 | 77| first_init_dram_type/dfs_disable | RK3588 V1.11/RV1126B V1.00 | 78 79* UART info 80 81uart id: uart number. 0 for uart0, 1 for uart1, 2 for uart2..., 0xf will disable uart. 82uart iomux: uart iomux info, 0 for uartn_m0, 1 for uartn_m1, 2 for uartn_m2...(like uart2_m0, uart2_m1,uart2_m2), 83or 1 for uartn_a, 2 for uartn_b, 3 for uartn_c.(like uar2a, uart2b, uart2c). 84uart baudrate: uart baudrate should be 115200 or 1500000. 85 86* disable print training information 87 88dis_train_print: 1: will disabled print training information; 0: will enable print training information. 89 90* recycle registers space(remap register space to DDR) 91 92res_space_remap_portion 931: will remap the part of registers to DDR memory space(will not larger than 4GB). 94It is PCIE and some reserved space in RK3588, and the PCIE can not be used when set to 1. 95 96res_space_remap_all 971: will wrap all registers space(include res_space_remap_portion enable space) to DDR memory space. This space would be place in larger than 4GB. 98The PCIE can be used when set to 1 in RK3588. 99 100* DDR eye scanning 1011) eye_2d_scan_en: 1: will enable 2D eye scanning for debug purpose, vref and skew eye scanning. 1022) wr_vref_scan_en: 1: enable vref scan and use scanning result for write. 1033) rd_vref_scan_en: 1: enable vref scan and use scanning result for read. 104 105* DDR auto precharge 106 107auto_precharge_en: 1: will enable the DDR auto precharge. 108 109* DDR refresh derate 110 111derate_en: 1: will enable derate function of the LP2/LP3/LP4/LP4X/LP5. 112The high temperature will issue more refresh command and the low temperature will less. 113 114* DDR per bank refresh 115 116per_bank_ref_en: 1: will enable per bank refresh 117 118* link ECC enable 119 120link_ecc_en: 1: read/write link ecc enable. 121 122* Extended temperature refresh 123 124ext_temp_ref: 125 0: ref1x for normal chip, 2x for 3568M/3568J 126 1: fix 2x ref for all chip 127 2: fix 4x ref for all chip 128 3: fix 1x ref for all chip 129Note: If derate-enabled DDR are configured with derate_en=1, the ext_temp_ref configuration does not take effect. 130 131* pstore_base_addr pstore_buf_size 132The pstore buffer base address: pstore_base_addr << 16, 64kB align. 133The pstore buffer size: pstore_buf_size * 4KB. 134It is define the addr and size to save ddrbin log for last log. 135 136* uboot_log_en 1371: enable uboot log. 1380: disable uboot log. 139 140* atf_log_en 1411: enable atf log. 1420: disable atf log. 143 144* optee_log_en 1451: enable optee log. 1460: disable optee log. 147 148* spl_log_en 1491: enable spl log. 1500: disable spl log. 151 152* tpl_log_en 1531: enable tpl log. 1540: disable tpl log. 155 156* pageclose 1571: enable pageclose. 1580: disable pageclose. 159 160* boot_fsp 161To choose the which DDR freq to boot system. 0 means fsp0_freq, 1 means fsp1_freq, 2 means fsp2_freq, 3 means fsp3_freq, the default is 0. 162 163* periodic interval 164The 0 means disable periodic training, others means enable. Unit: 100ms. 165 166* trfc_mode 1670: use default trfc 1681: use next density trfc 1692: use max trfc 1703: use min trfc 171 172* first_init_dram_type 173The define first init dram type to saving initial time. 174|----------------------------|-----------------| 175| first_init_dram_type value | DDR type | 176| 0 | DDR4 | 177| 2 | DDR2 | 178| 3 | DDR3 | 179| 5 | LPDDR2 | 180| 6 | LPDDR3 | 181| 7 | LPDDR4 | 182| 8 | LPDDR4X | 183| 9 | LPDDR5 | 184| 10 | DDR5 | 185|----------------------------|-----------------| 186 187* dfs_disable 1881: disbale ddr freq switch function 1890: enable ddr freq switch function 190 191Note: 192The starting frequency is fixed to f0 frequency after turning off the frequency scaling. 193If the DDR frequency needs to be modified, ddrx_f0_freq/fsp0_freq should be modified. 194 195* DDR (final) freq(also called ddrx_f0_freq_mhz/fsp0_freq) 196 197For RK3588, the boot_fsp used to choose which ddrx_fx_freq_mhz/fspx_freq to boot system, default is ddrx_f0_freq_mhz/fsp0_freq. 198For the others platform, it is the final freq to boot system. 199 200ddr2_freq(ddr2_f0_freq_mhz): ddr2 frequency, unit:MHz. 201lp2_freq (lp2_f0_freq_mhz): lpddr2 frequency, unit:MHz. 202ddr3_freq(ddr3_f0_freq_mhz): ddr3 frequency, unit:MHz. 203lp3_freq (lp3_f0_freq_mhz): lpddr3 frequency, unit:MHz. 204ddr4_freq(ddr4_f0_freq_mhz): ddr4 frequency, unit:MHz. 205lp4_freq (lp4_f0_freq_mhz): lpddr4 frequency, unit:MHz. 206lp4x_freq(lp4x_f0_freq_mhz): lpddr4x frequency, unit:MHz. 207lp5_freq (lp5_f0_freq_mhz): lpddr5 frequency, unit:MHz. 208 209* support ddr frequency: 210The 'X' as follows means not support change frequencies by tool. 211+---------------+-----------------------------------------------------------------+ 212| platform | support frequencies(MHZ) | 213+---------------+-----------------------------------------------------------------+ 214| RK1108 | DDR2: 400; LP2: <= 533; DDR3: <= 800 | 215+---------------+-----------------------------------------------------------------+ 216| PX30/RK3326 | X | 217+---------------+-----------------------------------------------------------------+ 218| RK1808 | 333,400,533,666,786,933 | 219+---------------+-----------------------------------------------------------------+ 220| RK322x | DDR2/LP2: <= 533; others: <= 800 | 221+---------------+-----------------------------------------------------------------+ 222| RK322xh | X | 223+---------------+-----------------------------------------------------------------+ 224| RK3288 | X | 225+---------------+-----------------------------------------------------------------+ 226| RK3308/RK3308S| DDR2/LP2: 393,451; DDR3: 393,451,589 | 227+---------------+-----------------------------------------------------------------+ 228| RK3368 | DDR3: <= 800; LP3: <= 666 | 229+---------------+-----------------------------------------------------------------+ 230| RK3328 | X | 231+---------------+-----------------------------------------------------------------+ 232| RK3399 | X | 233+---------------+-----------------------------------------------------------------+ 234| RK3399PRO NPU | 333,400,533,666,786,933 | 235+---------------+-----------------------------------------------------------------+ 236| RV1126/RV1109 | 328,396,528,664,784,924,1056 | 237+---------------+-----------------------------------------------------------------+ 238| RK3566 | 324,396,528,630,780,920,1056 | 239+---------------+-----------------------------------------------------------------+ 240| RK3568 | DDR3/LP3: 324,396,528,630,780,920,1056 | 241| | DDR4/LP4/LP4X: 324,396,528,630,780,920,1056,1184,1332,1560 | 242+---------------+-----------------------------------------------------------------+ 243| RK3588 | LP4/LP4x [306.5MHz - 2133MHz]; LP5: [400MHz - 2750MHz] | 244+---------------+-----------------------------------------------------------------+ 245| RK3528 | DDR3/LP3/LP4/LP4X: 324,396,528,630,780,920,1056 | 246| | DDR4: 324,396,528,630,780,920,1056,1184 | 247+---------------+-----------------------------------------------------------------+ 248| RK3562 | DDR3/LP3: [324MHz - 1056MHz]; LP4/LP4X/DDR4: [324MHz - 1392MHz] | 249+---------------+-----------------------------------------------------------------+ 250| RV1106/RV1103 | DDR2: 528MHz; DDR3: 324,660,792,924; | 251+---------------+-----------------------------------------------------------------+ 252| RV1126B | DDR3/LP3: [324MHz - 1056MHz]; LP4/LP4X/DDR4: [324MHz - 1392MHz] | 253| | LP4/LP4X f1: [324MHz - 400MHz] | 254+---------------+-----------------------------------------------------------------+ 255| RV1126BP | [324MHz - 1056MHz] | 256| | LP4/LP4X f1: [324MHz - 400MHz] | 257+---------------+-----------------------------------------------------------------+ 258 259* DDR frequencies(add more) 260 261ddr2_f1_freq_mhz: ddr2 frequency fsp 1, unit:MHz. 262ddr2_f2_freq_mhz: ddr2 frequency fsp 2, unit:MHz. 263ddr2_f3_freq_mhz: ddr2 frequency fsp 3, unit:MHz. 264ddr2_f4_freq_mhz: ddr2 frequency fsp 4, unit:MHz. 265ddr2_f5_freq_mhz: ddr2 frequency fsp 5, unit:MHz. 266... 267The ddrx_f0_freq_mhz(the fsp0 frequency) is named ddrx_freq. 268 269ddr*_f*_freq_mhz/lp*_f*_freq_mhz: Only RV1126/RV1109, RK3566/RK3568, RK3588 used. 270The program will initialize dram by following order. 271for example: ddr4_f1_freq_mhz --> ddr4_f2_freq_mhz --> ddr4_f3_freq_mhz --> ddr4_freq. 272And the final frequency is ddr4_freq to boot system. 273The ddr frequency table in kernel dts/dtsi file need correspond to these frequencies. 274So it is better to arrange the frequency values in order as above. That means the max freq is in final freq(lp*/ddr*_freq) and the min freq is in 'ddr*/lp*_f1_freq_mhz'. 275Such as: ddr*/lp*_f1_freq_mhz < ddr*/lp*_f2_freq_mhz < ddr*/lp*_f3_freq_mhz < lp*/ddr*_freq(the final freq) 276For example: 277 ... 278 ddr4_freq=1560 279 ... 280 ddr4_f1_freq_mhz=324 281 ddr4_f2_freq_mhz=528 282 ddr4_f3_freq_mhz=780 283 ... 284 285Note: The ddr frequency table in kernel dts/dtsi file need correspond to these frequencies. 286 287* SR PD idle 288 289sr_idle: auto self-refresh mode delay time. 290pd_idle: auto power-down mode delay time. 291 292* DDR 2T 293 294ddr_2t: ddr 2T timing mode. 1: enable ddr 2T, 0: disable ddr 2T. 295 296* PLL ssmod 297 298These parameters are about Spread Spectrum Modulator(ssmod) for PLL. 299ssmod_downspread: ssmod work mode. 3002'b00: center spread. (Suggest to use center spread for better clock jitter) 3012'b01: down spread. 3022'b10: up spread.(Please refer to the datasheet for support information) 3032'b11: reserved 304 305ssmod_div: Divider required to set the modulation frequency. 306 RK3308 suggests to ssmod_div=2, others platforms suggest to ssmod_div=5. 307ssmod_spread: spread amplitude % = 0.1 * ssmod_spread; 0: disable ssmod, others will enable ssmod, max to 0x1f. 308 The larger the ssmod_spread value, the smaller of EMI, the worse of clk jitter. 309 Suggest to use ssmod_spread = 5, which means the center spread is +/-0.5%. 310Please refer to "Rockchip_Developer_Guide_Pll_Ssmod_Clock_CN" for more information. 311 312* driver strength 313 314phy_ddr*_dq_drv_when_odten_ohm: The PHY DQ/DQS driver strength(write direction) when DRAM odt on. unit: ohm. 315phy_ddr*_ca_drv_when_odten_ohm: The PHY CMD/ADDR driver strength when DRAM odt on. unit: ohm. 316phy_ddr*_clk_drv_when_odten_ohm: The PHY clock driver strength when DRAM odt on. unit: ohm. 317ddr*_dq_drv_when_odten_ohm: The DRAM DQ/DQS driver strength(read direction) when PHY odt on. unit: ohm. 318phy_ddr*_dq_drv_when_odtoff_ohm: The PHY DQ/DQS driver strength(write direction) when DRAM odt off. unit: ohm. 319phy_ddr*_ca_drv_when_odtoff_ohm: The PHY CMD/ADDR driver strength when DRAM odt off. unit: ohm. 320phy_ddr*_clk_drv_when_odtoff_ohm: The PHY clock driver strength when DRAM odt off. unit: ohm. 321ddr*_dq_drv_when_odtoff_ohm: The DRAM DQ/DQS driver strength(read direction) when PHY odt off. unit: ohm. 322 323The phy side driver strength support value as follows: 324+---------------+-------------------+-------------------+--------------+-----------------+----------------+----------------+-------------+ 325| platform | DDR3 | DDR4 | LP3 | LP4 | LP4X pull up | LP4X pull down | LP5 | 326+---------------+-------------------+-------------------+--------------+-----------------+----------------+----------------+-------------+ 327| | 455,230,153,115, | 482,244,162,122, | | 501,253,168,126,| | | | 328| | 91,76,65,57,51,46,| 97,81,69,61,54,48,| | 101,84,72,63,56,| | | | 329| RV1126/RV1109 | 41,38,35,32,30,28,| 44,40,37,34,32,30,| follow DDR4 | 50,46,42,38,36, | follow LP4 | follow LP4 | X | 330| | 27,25,24,23,22,21,| 28,27,25,24,23,22,| | 33,31,29,28,26, | | | | 331| | 20 | 21 | | 25,24,23,22 | | | | 332+---------------+-------------------+-------------------+--------------+-----------------+----------------+----------------+-------------+ 333| | 500,250,167,125, | 556,279,185,139, | | 576,289,192,144,| 646,323,215, | 513,259,172, | | 334| | 100,83,71,63,56, | 111,93,79,69,62, | | 115,96,82,72,64,| 162,129,108,92,| 130,104,86,74, | | 335| RK3566/RK3568 | 50,45,41,38,36,33,| 55,50,46,42,39,37,| follow DDR4 | 57,52,48,44,41, | 81,72,65,59,54,| 65,58,52,47,43,| X | 336| | 31,29,28,26,25,24,| 34,32,31,29,27,26,| | 38,36,34,32,30, | 50,46,43,40,38,| 40,37,35,32,30,| | 337| | 23,22 | 25,24 | | 28,27,26,25 | 36,34,32,31,29,| 29,27,26,25,24,| | 338| | | | | | 28 | 23 | | 339+---------------+-------------------+-------------------+--------------+-----------------+----------------+----------------+-------------+ 340| RK3588 | X | X | X | 240,120,80,60, | follow LP4 | follow LP4 | follow LP4 | 341| | | | | 48,40,34,30 | | | | 342+---------------+-------------------+-------------------+--------------+-----------------+----------------+----------------+-------------+ 343| | 572,289,195,145, | 595,300,202,151, | | 654,328,221,165,| 585,297,202, | 585,297,202, | | 344| | 117,99,85,73,66, | 122,102,89,76,68, | |133,112,97,83,74,| 150,122,103,90,| 150,122,103,90,| | 345| RK3528 | 60,55,50,47,44,41,| 62,57,52,49,45,43,| follow DDR4 | 67,62,57,53,49, | 77,69,63,58,53,| 77,69,63,58,53,| X | 346| | 38,36,34,33,31,30,| 39,37,35,34,32,31,| | 46,43,40,38,37, | 50,47,44,40,38,| 50,47,44,40,38,| | 347| | 29,28 | 30,29 | | 35,33,32,31 | 37,35,33,32,31,| 37,35,33,32,31,| | 348| | | | | | 30 | 30 | | 349+---------------+-------------------+-------------------+--------------+-----------------+----------------+----------------+-------------+ 350| | 573,289,195,145, | 595,300,202,151, | | 654,328,221,165,| 586,297,202, | 558,282,190, | | 351| | 117,99,85,73,66, | 122,102,89,76,68, | |133,112,97,83,74,| 150,122,103,90,| 142,115,96,84, | | 352| RV1126B/BP | 60,55,50,47,44,41,| 62,57,52,49,46,43,| follow DDR4 | 67,62,57,53,49, | 76,69,63,58,53,| 72,64,58,54,49,| X | 353| | 38,36,35,33,32,30,| 40,38,36,34,33,31,| | 46,43,41,39,37, | 49,47,44,41,39,| 46,43,40,38,36,| | 354| | 29,28 | 30,29 | | 35,34,33,31 | 37,35,34,33,31,| 34,32,31,30,29,| | 355| | | | | | 30 | 28 | | 356+---------------+-------------------+-------------------+--------------+-----------------+----------------+----------------+-------------+ 357 358The DRAM side driver strength support value as follows: 359+---------------+-------------------+-------------------+----------------+----------------------+----------------+-------------+ 360| platform | DDR3 | DDR4 | LP3 | LP4 | LP4X | LP5 | 361+---------------+-------------------+-------------------+----------------+----------------------+----------------+-------------+ 362| all | 40,34 | 34,48 | 34,40,48,60,80 | 40,48,60,80,120,240 | follow LP4 | follow LP4 | 363+---------------+-------------------+-------------------+----------------+----------------------+----------------+-------------+ 364 365* ODT 366phy_ddr*_odt_ohm: The PHY ODT strength(read direction). unit: ohm. 367ddr*_odt_ohm: The DRAM ODT strength(write direction). unit: ohm. 368phy_ddr*_odt_pull_up_en: 1: enable PHY pull up odt. 0: disable 369phy_ddr*_odt_pull_dn_en: 1: enable PHY pull down odt. 0: disable 370phy_ddr*_odten_freq_mhz: The PHY odt enable when larger than this frequency. unit: MHz. 371ddr*_odten_freq_mhz: The DRAM odt(DQ/DQS) enable when larger than this frequency. unit: MHz. 372 373Note: 374ddr4_odten_freq_mhz: The DDR4 DRAM ODT is not supported below 625MHz according to JEDEC standard. It means ddr4_odten_freq_mhz should not less than 625. 375lp4_dq_odten_freq_mhz/lp4x_dq_odten_freq_mhz: The lp4/lp4x DRAM DQ ODT is not supported below 800MHz according to JEDEC standard. 376 It means lp4_dq_odten_freq_mhz/lp4x_dq_odten_freq_mhz should not less than 800. 377 378The phy side ODT support value as follows: 379The ODT "0" means disabled ODT. 380+---------------+-------------------+--------------------+--------------+-------------------+----------------+----------------+-------------+ 381| platform | DDR3 | DDR4 | LP3 | LP4 | LP4X pull up | LP4X pull down | LP5 | 382+---------------+-------------------+--------------------+--------------+-------------------+----------------+----------------+-------------+ 383| | 0,561,282,188,141,| 0,586,294,196,148, | | 0,604,303,202,152,| | | | 384| | 113,94,81,72,64, | 118,99,58,76,67,60,| | 122,101,87,78,69, | | | | 385| RV1126/RV1109 | 58,52,48,44,41, | 55,50,46,43,40,38, | follow DDR4 | 62,56,52,48,44,41,| follow LP4 | follow LP4 | X | 386| | 38,37,34,32,31,29,| 36,34,32,31,29,28, | | 39,37,35,33,32,30,| | | | 387| | 28,27,25 | 27 | | 29,27 | | | | 388+---------------+-------------------+--------------------+--------------+-------------------+----------------+----------------+-------------+ 389| | 0,500,250,167,125,| 0,556,279,185,139, | | 0,576,289,192,144,| 0,646,323,215, | 0,513,259,172, | | 390| | 100,83,71,63,56, | 111,93,79,69,62, | | 115,96,82,72,64, | 162,129,108,92,| 130,104,86,74, | | 391| RK3566/RK3568 | 50,45,41,38,36,33,| 55,50,46,42,39,37, | follow DDR4 | 57,52,48,44,41, | 81,72,65,59,54,| 65,58,52,47,43,| X | 392| | 31,29,28,26,25,24,| 34,32,31,29,27,26, | | 38,36,34,32,30, | 50,46,43,40,38,| 40,37,35,32,30,| | 393| | 23,22 | 25,24 | | 28,27,26,25 | 36,34,32,31,29,| 29,27,26,25,24,| | 394| | | | | | 28 | 23 | | 395+---------------+-------------------+--------------------+--------------+-------------------+----------------+----------------+-------------+ 396| RK3588 | X | X | X | 0,240,120,80, | follow LP4 | follow LP4 | follow LP4 | 397| | | | | 60,48,40,34,30 | | | | 398+---------------+-------------------+--------------------+--------------+-------------------+----------------+----------------+-------------+ 399| | 572,289,195,145, | 595,300,202,151, | | 654,328,221,165, | 585,297,202, | 585,297,202, | | 400| | 117,99,85,73,66, | 122,102,89,76,68, | |133,112,97,83,74, | 150,122,103,90,| 150,122,103,90,| | 401| RK3528 | 60,55,50,47,44,41,| 62,57,52,49,45,43, | follow DDR4 | 67,62,57,53,49, | 77,69,63,58,53,| 77,69,63,58,53,| X | 402| | 38,36,34,33,31,30,| 39,37,35,34,32,31, | | 46,43,40,38,37, | 50,47,44,40,38,| 50,47,44,40,38,| | 403| | 29,28 | 30,29 | | 35,33,32,31 | 37,35,33,32,31,| 37,35,33,32,31,| | 404| | | | | | 30 | 30 | | 405+---------------+-------------------+--------------------+--------------+-------------------+----------------+----------------+-------------+ 406| | 573,289,195,145, | 595,300,202,151, | | 654,328,221,165, | 586,297,202, | 558,282,190, | | 407| | 117,99,85,73,66, | 122,102,89,76,68, | |133,112,97,83,74, | 150,122,103,90,| 142,115,96,84, | | 408| RV1126B/BP | 60,55,50,47,44,41,| 62,57,52,49,46,43, | follow DDR4 | 67,62,57,53,49, | 76,69,63,58,53,| 72,64,58,54,49,| X | 409| | 38,36,35,33,32,30,| 40,38,36,34,33,31, | | 46,43,41,39,37, | 49,47,44,41,39,| 46,43,40,38,36,| | 410| | 29,28 | 30,29 | | 35,34,33,31 | 37,35,34,33,31,| 34,32,31,30,29,| | 411| | | | | | 30 | 28 | | 412+---------------+-------------------+--------------------+--------------+-------------------+----------------+----------------+-------------+ 413 414The DRAM side ODT support value as follows: 415+---------------+-------------------+-------------------+--------------+-----------------------+----------------+---------------+ 416| platform | DDR3 | DDR4 | LP3 | LP4(include DQ and CA)| LP4X | LP5 | 417+---------------+-------------------+-------------------+--------------+-----------------------+----------------+---------------+ 418| all | 0,40,60,120 | 0,34,40,48,60,120 | 0,60,120,240 | 0,40,48,60,80,120,240 | follow LP4 | follow LP4 | 419+---------------+-------------------+-------------------+--------------+-----------------------+----------------+---------------+ 420 421* slew rate 422 423phy_ddr*_dq_sr_when_odten: The PHY DQ/DQS slew rate when odt on. 424phy_ddr*_ca_sr_when_odten: The PHY CMD/ADDR slew rate when odt on. 425phy_ddr*_clk_sr_when_odten: The PHY clock slew rate when odt on. 426phy_ddr*_dq_sr_when_odtoff: The PHY DQ/DQS slew rate when odt off. 427phy_ddr*_ca_sr_when_odtoff: The PHY CMD/ADDR slew rate when odt off. 428phy_ddr*_clk_sr_when_odtoff: The PHY clock slew rate when odt off. 429 430The max value is 0x1f, the min is 0x0. 431 432* byte map 433 434ddr*_bytes_map: The bytes remap in PHY. 435 436* dq remap 437 438lp*_dq*_*_map: The dq remap in PHY. 439ddr*_cs*_dq*_dq*_map: The dq remap in PHY. 440 441* lp4/lp4x more information 442 443lp4*_ca_odten_freq_mhz: The DRAM CMD/ADDR odt enable when larger than this frequency. unit: MHz. 444 445* vref 446 447phy_ddr*_dq_vref_when_odten: The PHY VrefDQ when PHY odt on. uint: parts per thousand. 448ddr*_dq_vref_when_odten: The DRAM VrefDQ when DRAM DQ/DQS odt on. uint: parts per thousand. 449ddr*_ca_vref_when_odten: The DRAM VrefCA when DRAM CA odt on. uint: parts per thousand. 450phy_ddr*_dq_vref_when_odtoff: The PHY VrefDQ when PHY odt off. uint: parts per thousand. 451ddr*_dq_vref_when_odtoff: The DRAM VrefDQ when DRAM DQ/DQS odt off. uint: parts per thousand. 452ddr*_ca_vref_when_odtoff: The DRAM VrefCA when DRAM CA odt off. uint: parts per thousand. 453 454For DDR2/3/4 and LPDDR2/3, if the configuration value is "0", Vref is automatically calculated by the code. 455 456* hash info 457ch/bank/rank_mask*: is used to DDR address hash mask. 458 459* modify skew info 460 461ddr*_skew_freq_mhz: Used to specify the frequency of skew. 462 463ddr*_skew: The skew value of dram type are need to modify. If need to modify skew, you must check with the hardware engineer. 464 465The support platform: 466|---------------------------|--------------------|--------------------------------------------| 467| platform | ddrbin version | calculate one step delay(ps) | 468| RK3528 | V1.06 | 1000000 / ddr*_skew_freq_mhz / 128 | 469|---------------------------|--------------------|--------------------------------------------| 470 471For RK3528, the skew one step is 7.398ps when ddr*_skew_freq_mhz is 1056. 472 473Before modify skew, it is recommended to read every CA skew from the bin file and then adjust the CA skew which want to change. 474