1function 1: modify ddr.bin file from ddrbin_param.txt. 2 1) modify 'ddrbin_param.txt', set ddr frequency, uart info etc what you want. 3 If want to keep items default, please keep these items blank. 4 2) run 'ddrbin_tool.py' with argument 1: chip_name, argument 2: ddrbin_param.txt, argument 3: ddr bin file. 5 like: ./ddrbin_tool.py px30 ddrbin_param.txt px30_ddr_333MHz_v1.13.bin 6 7function 2: get ddr.bin file config to gen_param.txt file 8 If want to get ddrbin file config, please run like that: 9 ./ddrbin_tool.py px30 -g gen_param.txt px30_ddr_333MHz_v1.15.bin 10 The config will show in gen_param.txt. 11 12The detail information as following: 13 14* support ddrbin version 15 The 'X' means not support change those parameters by tool. 16 +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+ 17 | platform | uart info | ddr freq | ssmod | DDR 2T | sr pd | drv, odt, Vref etc| dis print training info | dis CBT | ddr2/3/4, lp2/3 Vref | 18 +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+ 19 | RV1108 | V1.08 | V1.08 | V1.10 | V1.08 | V1.08 | X | X | X | X | 20 +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+ 21 | PX30/RK3326 | V1.11 | X | X | V1.12 | X | X | X | X | X | 22 +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+ 23 | RK1808 | V1.03 | V1.03 | V1.05 | V1.03 | V1.04 | X | X | X | X | 24 +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+ 25 | RK322x | V1.08 | V1.08 | X | V1.09 | X | X | X | X | X | 26 +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+ 27 | RK322xh | V1.14 | X | V1.17 | V1.16 | V1.17 | X | X | X | X | 28 +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+ 29 | RK3288 | V1.11 | X | X | V1.11 | X | X | X | X | X | 30 +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+ 31 | RK3308 | V1.28 | V1.28 | V1.31 | V1.29 | V1.30 | X | X | X | X | 32 +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+ 33 | RK3308S | V2.05 | V2.05 | V2.05 | V2.05 | V2.05 | X | X | X | X | 34 +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+ 35 | RK3368 | V2.04 | V2.04 | X | V2.05 | X | X | X | X | X | 36 +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+ 37 | RK3328 | V1.14 | X | V1.17 | V1.16 | V1.17 | X | X | X | X | 38 +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+ 39 | RK3399 | V1.25 | X | V1.25 | X | X | X | X | X | X | 40 +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+ 41 | RK3399PRO NPU | V1.03 | V1.03 | V1.05 | V1.03 | V1.04 | X | X | X | X | 42 +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+ 43 | RV1126/RV1109 | V1.00 | V1.00 | V1.05 | V1.00 | V1.05 | V1.05 | X | X | X | 44 +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+ 45 | RK3566/RK3568 | V1.00 | V1.00 | V1.06 | V1.00 | V1.00 | V1.06 | V1.07 | X | V1.19 | 46 +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+ 47 | RK3588 | V1.00 | V1.00 | X | V1.00 | V1.00 | V1.00 | X | X | X | 48 +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+ 49 | RK3528 | V1.00 | V1.00 | V1.00 | V1.00 | V1.00 | V1.00 | V1.00 | X | V1.08 | 50 +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+ 51 | RK3562 | X | V1.00 | V1.00 | V1.00 | V1.00 | V1.00 | V1.00 | X | V1.05 | 52 +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+ 53 | RV1106/RV1103 | V1.10 | V1.10 | V1.10 | V1.10 | V1.10 | X | X | X | X | 54 +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+----------------------+ 55 56| function | platform and ddrbin version | 57| ------------------------------------- | ------------------------------------------ | 58| first scan channel/channel mask | RK3588 V1.00/RK3399 V1.25/RK3288 V1.11 | 59| stride type | RK3588 V1.00/RK3399 V1.25/RK3288 V1.11 | 60| ext_temp_ref | RK356x V1.16/RK3528 V1.07/RK1808 V1.06 | 61| link_ecc_en | Null | 62| per_bank_ref_en | RK3588 V1.09 | 63| derate_en | RK3588 V1.09/RK356x V1.19/RK3528 V1.07 | 64| auto_precharge_en | Null | 65| res_space_remap_portion | RK3588 V1.09 | 66| res_space_remap_all | RK3588 V1.09 | 67| rd_vref_scan_en | RK3588 V1.08 | 68| wr_vref_scan_en | RK3588 V1.08 | 69| eye_2d_scan_en | RK3588 V1.08 | 70| ch/bank/rank_mask | RK3588 V1.00 | 71| pstore base_addr/buf_size | RK3588 V1.09 | 72| uboot/atf/optee/spl/tpl log en | RK3588 V1.09 | 73| boot_fsp | RK3588 V1.09 | 74| pageclose | RK3588 V1.10 | 75| first_init_dram_type/dfs_disable | RK3588 V1.11 | 76 77* UART info 78 79uart id: uart number. 0 for uart0, 1 for uart1, 2 for uart2..., 0xf will disable uart. 80uart iomux: uart iomux info, 0 for uartn_m0, 1 for uartn_m1, 2 for uartn_m2...(like uart2_m0, uart2_m1,uart2_m2), 81or 1 for uartn_a, 2 for uartn_b, 3 for uartn_c.(like uar2a, uart2b, uart2c). 82uart baudrate: uart baudrate should be 115200 or 1500000. 83 84* disable print training information 85 86dis_train_print: 1: will disabled print training information; 0: will enable print training information. 87 88* recycle registers space(remap register space to DDR) 89 90res_space_remap_portion 911: will remap the part of registers to DDR memory space(will not larger than 4GB). 92It is PCIE and some reserved space in RK3588, and the PCIE can not be used when set to 1. 93 94res_space_remap_all 951: will wrap all registers space(include res_space_remap_portion enable space) to DDR memory space. This space would be place in larger than 4GB. 96The PCIE can be used when set to 1 in RK3588. 97 98* DDR eye scanning 991) eye_2d_scan_en: 1: will enable 2D eye scanning for debug purpose, vref and skew eye scanning. 1002) wr_vref_scan_en: 1: enable vref scan and use scanning result for write. 1013) rd_vref_scan_en: 1: enable vref scan and use scanning result for read. 102 103* DDR auto precharge 104 105auto_precharge_en: 1: will enable the DDR auto precharge. 106 107* DDR refresh derate 108 109derate_en: 1: will enable derate function of the LP2/LP3/LP4/LP4X/LP5. 110The high temperature will issue more refresh command and the low temperature will less. 111 112* DDR per bank refresh 113 114per_bank_ref_en: 1: will enable per bank refresh 115 116* link ECC enable 117 118link_ecc_en: 1: read/write link ecc enable. 119 120* Extended temperature refresh 121 122ext_temp_ref: 123 0: ref1x for normal chip, 2x for 3568M/3568J 124 1: fix 2x ref for all chip 125 2: fix 4x ref for all chip 126 3: fix 1x ref for all chip 127Note: If derate-enabled DDR are configured with derate_en=1, the ext_temp_ref configuration does not take effect. 128 129* pstore_base_addr pstore_buf_size 130The pstore buffer base address: pstore_base_addr << 16, 64kB align. 131The pstore buffer size: pstore_buf_size * 4KB. 132It is define the addr and size to save ddrbin log for last log. 133 134* uboot_log_en 1351: enable uboot log. 1360: disable uboot log. 137 138* atf_log_en 1391: enable atf log. 1400: disable atf log. 141 142* optee_log_en 1431: enable optee log. 1440: disable optee log. 145 146* spl_log_en 1471: enable spl log. 1480: disable spl log. 149 150* tpl_log_en 1511: enable tpl log. 1520: disable tpl log. 153 154* pageclose 1551: enable pageclose. 1560: disable pageclose. 157 158* boot_fsp 159To choose the which DDR freq to boot system. 0 means fsp0_freq, 1 means fsp1_freq, 2 means fsp2_freq, 3 means fsp3_freq, the default is 0. 160 161* periodic interval 162The 0 means disable periodic training, others means enable. Unit: 100ms. 163 164* trfc_mode 1650: use default trfc 1661: use next density trfc 1672: use max trfc 1683: use min trfc 169 170* first_init_dram_type 171The define first init dram type to saving initial time. 172|----------------------------|-----------------| 173| first_init_dram_type value | DDR type | 174| 0 | DDR4 | 175| 2 | DDR2 | 176| 3 | DDR3 | 177| 5 | LPDDR2 | 178| 6 | LPDDR3 | 179| 7 | LPDDR4 | 180| 8 | LPDDR4X | 181| 9 | LPDDR5 | 182| 10 | DDR5 | 183|----------------------------|-----------------| 184 185* dfs_disable 1861: disbale ddr freq switch function 1870: enable ddr freq switch function 188 189Note: 190The starting frequency is fixed to f0 frequency after turning off the frequency scaling. 191If the DDR frequency needs to be modified, ddrx_f0_freq/fsp0_freq should be modified. 192 193* DDR (final) freq(also called ddrx_f0_freq_mhz/fsp0_freq) 194 195For RK3588, the boot_fsp used to choose which ddrx_fx_freq_mhz/fspx_freq to boot system, default is ddrx_f0_freq_mhz/fsp0_freq. 196For the others platform, it is the final freq to boot system. 197 198ddr2_freq(ddr2_f0_freq_mhz): ddr2 frequency, unit:MHz. 199lp2_freq (lp2_f0_freq_mhz): lpddr2 frequency, unit:MHz. 200ddr3_freq(ddr3_f0_freq_mhz): ddr3 frequency, unit:MHz. 201lp3_freq (lp3_f0_freq_mhz): lpddr3 frequency, unit:MHz. 202ddr4_freq(ddr4_f0_freq_mhz): ddr4 frequency, unit:MHz. 203lp4_freq (lp4_f0_freq_mhz): lpddr4 frequency, unit:MHz. 204lp4x_freq(lp4x_f0_freq_mhz): lpddr4x frequency, unit:MHz. 205lp5_freq (lp5_f0_freq_mhz): lpddr5 frequency, unit:MHz. 206 207* support ddr frequency: 208The 'X' as follows means not support change frequencies by tool. 209+---------------+-----------------------------------------------------------------+ 210| platform | support frequencies(MHZ) | 211+---------------+-----------------------------------------------------------------+ 212| RK1108 | DDR2: 400; LP2: <= 533; DDR3: <= 800 | 213+---------------+-----------------------------------------------------------------+ 214| PX30/RK3326 | X | 215+---------------+-----------------------------------------------------------------+ 216| RK1808 | 333,400,533,666,786,933 | 217+---------------+-----------------------------------------------------------------+ 218| RK322x | DDR2/LP2: <= 533; others: <= 800 | 219+---------------+-----------------------------------------------------------------+ 220| RK322xh | X | 221+---------------+-----------------------------------------------------------------+ 222| RK3288 | X | 223+---------------+-----------------------------------------------------------------+ 224| RK3308/RK3308S| DDR2/LP2: 393,451; DDR3: 393,451,589 | 225+---------------+-----------------------------------------------------------------+ 226| RK3368 | DDR3: <= 800; LP3: <= 666 | 227+---------------+-----------------------------------------------------------------+ 228| RK3328 | X | 229+---------------+-----------------------------------------------------------------+ 230| RK3399 | X | 231+---------------+-----------------------------------------------------------------+ 232| RK3399PRO NPU | 333,400,533,666,786,933 | 233+---------------+-----------------------------------------------------------------+ 234| RV1126/RV1109 | 328,396,528,664,784,924,1056 | 235+---------------+-----------------------------------------------------------------+ 236| RK3566 | 324,396,528,630,780,920,1056 | 237+---------------+-----------------------------------------------------------------+ 238| RK3568 | DDR3/LP3: 324,396,528,630,780,920,1056 | 239| | DDR4/LP4/LP4X: 324,396,528,630,780,920,1056,1184,1332,1560 | 240+---------------+-----------------------------------------------------------------+ 241| RK3588 | LP4/LP4x [306.5MHz - 2133MHz]; LP5: [400MHz - 2750MHz] | 242+---------------+-----------------------------------------------------------------+ 243| RK3528 | DDR3/LP3/LP4/LP4X: 324,396,528,630,780,920,1056 | 244| | DDR4: 324,396,528,630,780,920,1056,1184 | 245+---------------+-----------------------------------------------------------------+ 246| RK3562 | DDR3/LP3: [324MHz - 1056MHz]; LP4/LP4X/DDR4: [324MHz - 1392MHz] | 247+---------------+-----------------------------------------------------------------+ 248| RV1106/RV1103 | DDR2: 528MHz; DDR3: 324,660,792,924; | 249+---------------+-----------------------------------------------------------------+ 250 251* DDR frequencies(add more) 252 253ddr2_f1_freq_mhz: ddr2 frequency fsp 1, unit:MHz. 254ddr2_f2_freq_mhz: ddr2 frequency fsp 2, unit:MHz. 255ddr2_f3_freq_mhz: ddr2 frequency fsp 3, unit:MHz. 256ddr2_f4_freq_mhz: ddr2 frequency fsp 4, unit:MHz. 257ddr2_f5_freq_mhz: ddr2 frequency fsp 5, unit:MHz. 258... 259The ddrx_f0_freq_mhz(the fsp0 frequency) is named ddrx_freq. 260 261ddr*_f*_freq_mhz/lp*_f*_freq_mhz: Only RV1126/RV1109, RK3566/RK3568, RK3588 used. 262The program will initialize dram by following order. 263for example: ddr4_f1_freq_mhz --> ddr4_f2_freq_mhz --> ddr4_f3_freq_mhz --> ddr4_freq. 264And the final frequency is ddr4_freq to boot system. 265The ddr frequency table in kernel dts/dtsi file need correspond to these frequencies. 266So it is better to arrange the frequency values in order as above. That means the max freq is in final freq(lp*/ddr*_freq) and the min freq is in 'ddr*/lp*_f1_freq_mhz'. 267Such as: ddr*/lp*_f1_freq_mhz < ddr*/lp*_f2_freq_mhz < ddr*/lp*_f3_freq_mhz < lp*/ddr*_freq(the final freq) 268For example: 269 ... 270 ddr4_freq=1560 271 ... 272 ddr4_f1_freq_mhz=324 273 ddr4_f2_freq_mhz=528 274 ddr4_f3_freq_mhz=780 275 ... 276 277Note: The ddr frequency table in kernel dts/dtsi file need correspond to these frequencies. 278 279* SR PD idle 280 281sr_idle: auto self-refresh mode delay time. 282pd_idle: auto power-down mode delay time. 283 284* DDR 2T 285 286ddr_2t: ddr 2T timing mode. 1: enable ddr 2T, 0: disable ddr 2T. 287 288* PLL ssmod 289 290These parameters are about Spread Spectrum Modulator(ssmod) for PLL. 291ssmod_downspread: ssmod work mode. 2922'b00: center spread. (Suggest to use center spread for better clock jitter) 2932'b01: down spread. 2942'b10: up spread.(Please refer to the datasheet for support information) 2952'b11: reserved 296 297ssmod_div: Divider required to set the modulation frequency. 298 RK3308 suggests to ssmod_div=2, others platforms suggest to ssmod_div=5. 299ssmod_spread: spread amplitude % = 0.1 * ssmod_spread; 0: disable ssmod, others will enable ssmod, max to 0x1f. 300 The larger the ssmod_spread value, the smaller of EMI, the worse of clk jitter. 301 Suggest to use ssmod_spread = 5, which means the center spread is +/-0.5%. 302Please refer to "Rockchip_Developer_Guide_Pll_Ssmod_Clock_CN" for more information. 303 304* driver strength 305 306phy_ddr*_dq_drv_when_odten_ohm: The PHY DQ/DQS driver strength(write direction) when DRAM odt on. unit: ohm. 307phy_ddr*_ca_drv_when_odten_ohm: The PHY CMD/ADDR driver strength when DRAM odt on. unit: ohm. 308phy_ddr*_clk_drv_when_odten_ohm: The PHY clock driver strength when DRAM odt on. unit: ohm. 309ddr*_dq_drv_when_odten_ohm: The DRAM DQ/DQS driver strength(read direction) when PHY odt on. unit: ohm. 310phy_ddr*_dq_drv_when_odtoff_ohm: The PHY DQ/DQS driver strength(write direction) when DRAM odt off. unit: ohm. 311phy_ddr*_ca_drv_when_odtoff_ohm: The PHY CMD/ADDR driver strength when DRAM odt off. unit: ohm. 312phy_ddr*_clk_drv_when_odtoff_ohm: The PHY clock driver strength when DRAM odt off. unit: ohm. 313ddr*_dq_drv_when_odtoff_ohm: The DRAM DQ/DQS driver strength(read direction) when PHY odt off. unit: ohm. 314 315The phy side driver strength support value as follows: 316+---------------+-------------------+-------------------+--------------+-----------------+----------------+----------------+-------------+ 317| platform | DDR3 | DDR4 | LP3 | LP4 | LP4X pull up | LP4X pull down | LP5 | 318+---------------+-------------------+-------------------+--------------+-----------------+----------------+----------------+-------------+ 319| | 455,230,153,115, | 482,244,162,122, | | 501,253,168,126,| | | | 320| | 91,76,65,57,51,46,| 97,81,69,61,54,48,| | 101,84,72,63,56,| | | | 321| RV1126/RV1109 | 41,38,35,32,30,28,| 44,40,37,34,32,30,| follow DDR4 | 50,46,42,38,36, | follow LP4 | follow LP4 | X | 322| | 27,25,24,23,22,21,| 28,27,25,24,23,22,| | 33,31,29,28,26, | | | | 323| | 20 | 21 | | 25,24,23,22 | | | | 324+---------------+-------------------+-------------------+--------------+-----------------+----------------+----------------+-------------+ 325| | 500,250,167,125, | 556,279,185,139, | | 576,289,192,144,| 646,323,215, | 513,259,172, | | 326| | 100,83,71,63,56, | 111,93,79,69,62, | | 115,96,82,72,64,| 162,129,108,92,| 130,104,86,74, | | 327| RK3566/RK3568 | 50,45,41,38,36,33,| 55,50,46,42,39,37,| follow DDR4 | 57,52,48,44,41, | 81,72,65,59,54,| 65,58,52,47,43,| X | 328| | 31,29,28,26,25,24,| 34,32,31,29,27,26,| | 38,36,34,32,30, | 50,46,43,40,38,| 40,37,35,32,30,| | 329| | 23,22 | 25,24 | | 28,27,26,25 | 36,34,32,31,29,| 29,27,26,25,24,| | 330| | | | | | 28 | 23 | | 331+---------------+-------------------+-------------------+--------------+-----------------+----------------+----------------+-------------+ 332| RK3588 | X | X | X | 240,120,80,60, | follow LP4 | follow LP4 | follow LP4 | 333| | | | | 48,40,34,30 | | | | 334+---------------+-------------------+-------------------+--------------+-----------------+----------------+----------------+-------------+ 335| | 572,289,195,145, | 595,300,202,151, | | 654,328,221,165,| 585,297,202, | 585,297,202, | | 336| | 117,99,85,73,66, | 122,102,89,76,68, | |133,112,97,83,74,| 150,122,103,90,| 150,122,103,90,| | 337| RK3528 | 60,55,50,47,44,41,| 62,57,52,49,45,43,| follow DDR4 | 67,62,57,53,49, | 77,69,63,58,53,| 77,69,63,58,53,| X | 338| | 38,36,34,33,31,30,| 39,37,35,34,32,31,| | 46,43,40,38,37, | 50,47,44,40,38,| 50,47,44,40,38,| | 339| | 29,28 | 30,29 | | 35,33,32,31 | 37,35,33,32,31,| 37,35,33,32,31,| | 340| | | | | | 30 | 30 | | 341+---------------+-------------------+-------------------+--------------+-----------------+----------------+----------------+-------------+ 342 343The DRAM side driver strength support value as follows: 344+---------------+-------------------+-------------------+----------------+----------------------+----------------+-------------+ 345| platform | DDR3 | DDR4 | LP3 | LP4 | LP4X | LP5 | 346+---------------+-------------------+-------------------+----------------+----------------------+----------------+-------------+ 347| all | 40,34 | 34,48 | 34,40,48,60,80 | 40,48,60,80,120,240 | follow LP4 | follow LP4 | 348+---------------+-------------------+-------------------+----------------+----------------------+----------------+-------------+ 349 350* ODT 351phy_ddr*_odt_ohm: The PHY ODT strength(read direction). unit: ohm. 352ddr*_odt_ohm: The DRAM ODT strength(write direction). unit: ohm. 353phy_ddr*_odt_pull_up_en: 1: enable PHY pull up odt. 0: disable 354phy_ddr*_odt_pull_dn_en: 1: enable PHY pull down odt. 0: disable 355phy_ddr*_odten_freq_mhz: The PHY odt enable when larger than this frequency. unit: MHz. 356ddr*_odten_freq_mhz: The DRAM odt(DQ/DQS) enable when larger than this frequency. unit: MHz. 357 358Note: 359ddr4_odten_freq_mhz: The DDR4 DRAM ODT is not supported below 625MHz according to JEDEC standard. It means ddr4_odten_freq_mhz should not less than 625. 360lp4_dq_odten_freq_mhz/lp4x_dq_odten_freq_mhz: The lp4/lp4x DRAM DQ ODT is not supported below 800MHz according to JEDEC standard. 361 It means lp4_dq_odten_freq_mhz/lp4x_dq_odten_freq_mhz should not less than 800. 362 363The phy side ODT support value as follows: 364The ODT "0" means disabled ODT. 365+---------------+-------------------+--------------------+--------------+-------------------+----------------+----------------+-------------+ 366| platform | DDR3 | DDR4 | LP3 | LP4 | LP4X pull up | LP4X pull down | LP5 | 367+---------------+-------------------+--------------------+--------------+-------------------+----------------+----------------+-------------+ 368| | 0,561,282,188,141,| 0,586,294,196,148, | | 0,604,303,202,152,| | | | 369| | 113,94,81,72,64, | 118,99,58,76,67,60,| | 122,101,87,78,69, | | | | 370| RV1126/RV1109 | 58,52,48,44,41, | 55,50,46,43,40,38, | follow DDR4 | 62,56,52,48,44,41,| follow LP4 | follow LP4 | X | 371| | 38,37,34,32,31,29,| 36,34,32,31,29,28, | | 39,37,35,33,32,30,| | | | 372| | 28,27,25 | 27 | | 29,27 | | | | 373+---------------+-------------------+--------------------+--------------+-------------------+----------------+----------------+-------------+ 374| | 0,500,250,167,125,| 0,556,279,185,139, | | 0,576,289,192,144,| 0,646,323,215, | 0,513,259,172, | | 375| | 100,83,71,63,56, | 111,93,79,69,62, | | 115,96,82,72,64, | 162,129,108,92,| 130,104,86,74, | | 376| RK3566/RK3568 | 50,45,41,38,36,33,| 55,50,46,42,39,37, | follow DDR4 | 57,52,48,44,41, | 81,72,65,59,54,| 65,58,52,47,43,| X | 377| | 31,29,28,26,25,24,| 34,32,31,29,27,26, | | 38,36,34,32,30, | 50,46,43,40,38,| 40,37,35,32,30,| | 378| | 23,22 | 25,24 | | 28,27,26,25 | 36,34,32,31,29,| 29,27,26,25,24,| | 379| | | | | | 28 | 23 | | 380+---------------+-------------------+--------------------+--------------+-------------------+----------------+----------------+-------------+ 381| RK3588 | X | X | X | 0,240,120,80, | follow LP4 | follow LP4 | follow LP4 | 382| | | | | 60,48,40,34,30 | | | | 383+---------------+-------------------+--------------------+--------------+-------------------+----------------+----------------+-------------+ 384| | 572,289,195,145, | 595,300,202,151, | | 654,328,221,165, | 585,297,202, | 585,297,202, | | 385| | 117,99,85,73,66, | 122,102,89,76,68, | |133,112,97,83,74, | 150,122,103,90,| 150,122,103,90,| | 386| RK3528 | 60,55,50,47,44,41,| 62,57,52,49,45,43, | follow DDR4 | 67,62,57,53,49, | 77,69,63,58,53,| 77,69,63,58,53,| X | 387| | 38,36,34,33,31,30,| 39,37,35,34,32,31, | | 46,43,40,38,37, | 50,47,44,40,38,| 50,47,44,40,38,| | 388| | 29,28 | 30,29 | | 35,33,32,31 | 37,35,33,32,31,| 37,35,33,32,31,| | 389| | | | | | 30 | 30 | | 390+---------------+-------------------+--------------------+--------------+-------------------+----------------+----------------+-------------+ 391The DRAM side ODT support value as follows: 392+---------------+-------------------+-------------------+--------------+-----------------------+----------------+---------------+ 393| platform | DDR3 | DDR4 | LP3 | LP4(include DQ and CA)| LP4X | LP5 | 394+---------------+-------------------+-------------------+--------------+-----------------------+----------------+---------------+ 395| all | 0,40,60,120 | 0,34,40,48,60,120 | 0,60,120,240 | 0,40,48,60,80,120,240 | follow LP4 | follow LP4 | 396+---------------+-------------------+-------------------+--------------+-----------------------+----------------+---------------+ 397 398* slew rate 399 400phy_ddr*_dq_sr_when_odten: The PHY DQ/DQS slew rate when odt on. 401phy_ddr*_ca_sr_when_odten: The PHY CMD/ADDR slew rate when odt on. 402phy_ddr*_clk_sr_when_odten: The PHY clock slew rate when odt on. 403phy_ddr*_dq_sr_when_odtoff: The PHY DQ/DQS slew rate when odt off. 404phy_ddr*_ca_sr_when_odtoff: The PHY CMD/ADDR slew rate when odt off. 405phy_ddr*_clk_sr_when_odtoff: The PHY clock slew rate when odt off. 406 407The max value is 0x1f, the min is 0x0. 408 409* byte map 410 411ddr*_bytes_map: The bytes remap in PHY. 412 413* dq remap 414 415lp*_dq*_*_map: The dq remap in PHY. 416ddr*_cs*_dq*_dq*_map: The dq remap in PHY. 417 418* lp4/lp4x more information 419 420lp4*_ca_odten_freq_mhz: The DRAM CMD/ADDR odt enable when larger than this frequency. unit: MHz. 421 422* vref 423 424phy_ddr*_dq_vref_when_odten: The PHY VrefDQ when PHY odt on. uint: parts per thousand. 425ddr*_dq_vref_when_odten: The DRAM VrefDQ when DRAM DQ/DQS odt on. uint: parts per thousand. 426ddr*_ca_vref_when_odten: The DRAM VrefCA when DRAM CA odt on. uint: parts per thousand. 427phy_ddr*_dq_vref_when_odtoff: The PHY VrefDQ when PHY odt off. uint: parts per thousand. 428ddr*_dq_vref_when_odtoff: The DRAM VrefDQ when DRAM DQ/DQS odt off. uint: parts per thousand. 429ddr*_ca_vref_when_odtoff: The DRAM VrefCA when DRAM CA odt off. uint: parts per thousand. 430 431For DDR2/3/4 and LPDDR2/3, if the configuration value is "0", Vref is automatically calculated by the code. 432 433* hash info 434ch/bank/rank_mask*: is used to DDR address hash mask. 435 436* modify skew info 437 438ddr*_skew_freq_mhz: Used to specify the frequency of skew. 439 440ddr*_skew: The skew value of dram type are need to modify. If need to modify skew, you must check with the hardware engineer. 441 442The support platform: 443|---------------------------|--------------------|--------------------------------------------| 444| platform | ddrbin version | calculate one step delay(ps) | 445| RK3528 | V1.06 | 1000000 / ddr*_skew_freq_mhz / 128 | 446|---------------------------|--------------------|--------------------------------------------| 447 448For RK3528, the skew one step is 7.398ps when ddr*_skew_freq_mhz is 1056. 449 450Before modify skew, it is recommended to read every CA skew from the bin file and then adjust the CA skew which want to change. 451