1function 1: modify ddr.bin file from ddrbin_param.txt. 2 1) modify 'ddrbin_param.txt', set ddr frequency, uart info etc what you want. 3 If want to keep items default, please keep these items blank. 4 2) run 'ddrbin_tool' with argument 1: ddrbin_param.txt, argument 2: ddr bin file. 5 like: ./ddrbin_tool ddrbin_param.txt px30_ddr_333MHz_v1.13.bin 6 7function 2: get ddr.bin file config to gen_param.txt file 8 If want to get ddrbin file config, please run like that: 9 ./ddrbin_tool -g gen_param.txt px30_ddr_333MHz_v1.15.bin 10 The config will show in gen_param.txt. 11 12The detail information as following: 13 14* support ddrbin version 15 The 'X' means not support change those parameters by tool. 16 +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+ 17 | platform | uart info | ddr freq | ssmod | DDR 2T | sr pd | drv, odt, Vref etc| dis print training info | dis CBT | 18 +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+ 19 | RV1108 | V1.08 | V1.08 | V1.10 | V1.08 | V1.08 | X | X | X | 20 +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+ 21 | PX30/RK3326 | V1.11 | X | V1.16 | V1.12 | V1.15 | X | X | X | 22 +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+ 23 | RK1808 | V1.03 | V1.03 | V1.05 | V1.03 | V1.04 | X | X | X | 24 +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+ 25 | RK322x | V1.08 | V1.08 | X | V1.09 | X | X | X | X | 26 +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+ 27 | RK322xh | V1.14 | X | V1.17 | V1.16 | V1.17 | X | X | X | 28 +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+ 29 | RK3288 | V1.11 | X | X | V1.11 | X | X | X | X | 30 +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+ 31 | RK3308 | V1.28 | V1.28 | V1.31 | V1.29 | V1.30 | X | X | X | 32 +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+ 33 | RK3308S | V2.05 | V2.05 | V2.05 | V2.05 | V2.05 | X | X | X | 34 +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+ 35 | RK3368 | V2.04 | V2.04 | X | V2.05 | X | X | X | X | 36 +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+ 37 | RK3328 | V1.14 | X | V1.17 | V1.16 | V1.17 | X | X | X | 38 +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+ 39 | RK3399 | V1.25 | X | V1.25 | X | X | X | X | X | 40 +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+ 41 | RK3399PRO NPU | V1.03 | V1.03 | X | V1.03 | X | X | X | X | 42 +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+ 43 | RV1126/RV1109 | V1.00 | V1.00 | V1.05 | V1.00 | V1.05 | V1.05 | X | X | 44 +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+ 45 | RK3566/RK3568 | V1.00 | V1.00 | V1.06 | V1.00 | V1.00 | V1.06 | V1.07 | X | 46 +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+ 47 | RK3588 | V1.00 | V1.00 | X | V1.00 | V1.00 | V1.00 | X | X | 48 +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+ 49 50| function | platform and ddrbin version | 51| ------------------------------- | -------------------------------------- | 52| first scan channel/channel mask | RK3588 V1.00/RK3399 V1.25/RK3288 V1.11 | 53| stride type | RK3588 V1.00/RK3399 V1.25/RK3288 V1.11 | 54| ext_temp_ref | Null | 55| link_ecc_en | Null | 56| per_bank_ref_en | RK3588 V1.09 | 57| derate_en | RK3588 V1.09 | 58| auto_precharge_en | Null | 59| res_space_remap_portion | RK3588 V1.09 | 60| res_space_remap_all | RK3588 V1.09 | 61| rd_vref_scan_en | RK3588 V1.08 | 62| wr_vref_scan_en | RK3588 V1.08 | 63| eye_2d_scan_en | RK3588 V1.08 | 64| ch/bank/rank_mask | RK3588 V1.00 | 65| pstore base_addr/buf_size | RK3588 V1.09 | 66| uboot/atf/optee/spl/tpl log en | RK3588 V1.09 | 67| boot_fsp | RK3588 V1.09 | 68| pageclose | RK3588 V1.10 | 69 70* UART info 71 72uart id: uart number. 0 for uart0, 1 for uart1, 2 for uart2..., 0xf will disable uart. 73uart iomux: uart iomux info, 0 for uartn_m0, 1 for uartn_m1, 2 for uartn_m2...(like uart2_m0, uart2_m1,uart2_m2), 74or 1 for uartn_a, 2 for uartn_b, 3 for uartn_c.(like uar2a, uart2b, uart2c). 75uart baudrate: uart baudrate should be 115200 or 1500000. 76 77* disable print training information 78 79dis_train_print: 1: will disabled print training information; 0: will enable print training information. 80 81* recycle registers space(remap register space to DDR) 82 83res_space_remap_portion 841: will remap the part of registers to DDR memory space(will not larger than 4GB). 85It is PCIE and some reserved space in RK3588, and the PCIE can not be used when set to 1. 86 87res_space_remap_all 881: will wrap all registers space(include res_space_remap_portion enable space) to DDR memory space. This space would be place in larger than 4GB. 89The PCIE can be used when set to 1 in RK3588. 90 91* DDR eye scanning 921) eye_2d_scan_en: 1: will enable 2D eye scanning for debug purpose, vref and skew eye scanning. 932) wr_vref_scan_en: 1: enable vref scan and use scanning result for write. 943) rd_vref_scan_en: 1: enable vref scan and use scanning result for read. 95 96* DDR auto precharge 97 98auto_precharge_en: 1: will enable the DDR auto precharge. 99 100* DDR refresh derate 101 102derate_en: 1: will enable derate function of the LP2/LP3/LP4/LP4X/LP5. 103The high temperature will issue more refresh command and the low temperature will less. 104 105* DDR per bank refresh 106 107per_bank_ref_en: 1: will enable per bank refresh 108 109* link ECC enable 110 111link_ecc_en: 1: read/write link ecc enable. 112 113* Extended temperature refresh 114 115ext_temp_ref: 116 0: ref1x for normal chip, 2x for 3568M/3568J 117 1: fix 2x ref for all chip 118 2: fix 4x ref for all chip 119 3: fix 1x ref for all chip 120Note: If derate-enabled DDR are configured with derate_en=1, the ext_temp_ref configuration does not take effect. 121 122* pstore_base_addr pstore_buf_size 123The pstore buffer base address: pstore_base_addr << 16, 64kB align. 124The pstore buffer size: pstore_buf_size * 4KB. 125It is define the addr and size to save ddrbin log for last log. 126 127* uboot_log_en 1281: enable uboot log. 1290: disable uboot log. 130 131* atf_log_en 1321: enable atf log. 1330: disable atf log. 134 135* optee_log_en 1361: enable optee log. 1370: disable optee log. 138 139* spl_log_en 1401: enable spl log. 1410: disable spl log. 142 143* tpl_log_en 1441: enable tpl log. 1450: disable tpl log. 146 147* pageclose 1481: enable pageclose. 1490: disable pageclose. 150 151* boot_fsp 152To choose the which DDR freq to boot system. 0 means fsp0_freq, 1 means fsp1_freq, 2 means fsp2_freq, 3 means fsp3_freq, the default is 0. 153 154* DDR (final) freq(also called ddrx_f0_freq_mhz/fsp0_freq) 155 156For RK3588, the boot_fsp used to choose which ddrx_fx_freq_mhz/fspx_freq to boot system, default is ddrx_f0_freq_mhz/fsp0_freq. 157For the others platform, it is the final freq to boot system. 158 159ddr2_freq(ddr2_f0_freq_mhz): ddr2 frequency, unit:MHz. 160lp2_freq (lp2_f0_freq_mhz): lpddr2 frequency, unit:MHz. 161ddr3_freq(ddr3_f0_freq_mhz): ddr3 frequency, unit:MHz. 162lp3_freq (lp3_f0_freq_mhz): lpddr3 frequency, unit:MHz. 163ddr4_freq(ddr4_f0_freq_mhz): ddr4 frequency, unit:MHz. 164lp4_freq (lp4_f0_freq_mhz): lpddr4 frequency, unit:MHz. 165lp4x_freq(lp4x_f0_freq_mhz): lpddr4x frequency, unit:MHz. 166lp5_freq (lp5_f0_freq_mhz): lpddr5 frequency, unit:MHz. 167 168* support ddr frequency: 169The 'X' as follows means not support change frequencies by tool. 170+---------------+-----------------------------------------------------------------+ 171| platform | support frequencies(MHZ) | 172+---------------+-----------------------------------------------------------------+ 173| RK1108 | DDR2: 400; LP2: <= 533; DDR3: <= 800 | 174+---------------+-----------------------------------------------------------------+ 175| PX30/RK3326 | X | 176+---------------+-----------------------------------------------------------------+ 177| RK1808 | 333,400,533,666,786,933 | 178+---------------+-----------------------------------------------------------------+ 179| RK322x | DDR2/LP2: <= 533; others: <= 800 | 180+---------------+-----------------------------------------------------------------+ 181| RK322xh | X | 182+---------------+-----------------------------------------------------------------+ 183| RK3288 | X | 184+---------------+-----------------------------------------------------------------+ 185| RK3308/RK3308S| DDR2/LP2: 393,451; DDR3: 393,451,589 | 186+---------------+-----------------------------------------------------------------+ 187| RK3368 | DDR3: <= 800; LP3: <= 666 | 188+---------------+-----------------------------------------------------------------+ 189| RK3328 | X | 190+---------------+-----------------------------------------------------------------+ 191| RK3399 | X | 192+---------------+-----------------------------------------------------------------+ 193| RK3399PRO NPU | 333,400,533,666,786,933 | 194+---------------+-----------------------------------------------------------------+ 195| RV1126/RV1109 | 328,396,528,664,784,924,1056 | 196+---------------+-----------------------------------------------------------------+ 197| RK3566 | 324,396,528,630,780,920,1056 | 198+---------------+-----------------------------------------------------------------+ 199| RK3568 | DDR3/LP3: 324,396,528,630,780,920,1056 | 200| | DDR4/LP4/LP4X: 324,396,528,630,780,920,1056,1184,1332,1560 | 201+---------------+-----------------------------------------------------------------+ 202| RK3588 | LP4/LP4x [306.5MHz - 2133MHz]; LP5: [400MHz - 2750MHz] | 203+---------------+-----------------------------------------------------------------+ 204| RK3528 | DDR3/LP3: 324,396,528,630,780,920,1056 | 205| | DDR4/LP4/LP4X: 324,396,528,630,780,920,1056,1184 | 206+---------------+-----------------------------------------------------------------+ 207 208* DDR frequencies(add more) 209 210ddr2_f1_freq_mhz: ddr2 frequency fsp 1, unit:MHz. 211ddr2_f2_freq_mhz: ddr2 frequency fsp 2, unit:MHz. 212ddr2_f3_freq_mhz: ddr2 frequency fsp 3, unit:MHz. 213ddr2_f4_freq_mhz: ddr2 frequency fsp 4, unit:MHz. 214ddr2_f5_freq_mhz: ddr2 frequency fsp 5, unit:MHz. 215... 216The ddrx_f0_freq_mhz(the fsp0 frequency) is named ddrx_freq. 217 218ddr*_f*_freq_mhz/lp*_f*_freq_mhz: Only RV1126/RV1109, RK3566/RK3568, RK3588 used. 219The program will initialize dram by following order. 220for example: ddr4_f1_freq_mhz --> ddr4_f2_freq_mhz --> ddr4_f3_freq_mhz --> ddr4_freq. 221And the final frequency is ddr4_freq to boot system. 222The ddr frequency table in kernel dts/dtsi file need correspond to these frequencies. 223So it is better to arrange the frequency values in order as above. That means the max freq is in final freq(lp*/ddr*_freq) and the min freq is in 'ddr*/lp*_f1_freq_mhz'. 224Such as: ddr*/lp*_f1_freq_mhz < ddr*/lp*_f2_freq_mhz < ddr*/lp*_f3_freq_mhz < lp*/ddr*_freq(the final freq) 225For example: 226 ... 227 ddr4_freq=1560 228 ... 229 ddr4_f1_freq_mhz=324 230 ddr4_f2_freq_mhz=528 231 ddr4_f3_freq_mhz=780 232 ... 233 234Note: The ddr frequency table in kernel dts/dtsi file need correspond to these frequencies. 235 236* SR PD idle 237 238sr_idle: auto self-refresh mode delay time. 239pd_idle: auto power-down mode delay time. 240 241* DDR 2T 242 243ddr_2t: ddr 2T timing mode. 1: enable ddr 2T, 0: disable ddr 2T. 244 245* PLL ssmod 246 247These parameters are about Spread Spectrum Modulator(ssmod) for PLL. 248ssmod_downspread: ssmod work mode. 1: down spread, 0: center spread. 249ssmod_div: Divider required to set the modulation frequency. RK3308 suggests to ssmod_div=2, others platforms suggest to ssmod_div=5. 250ssmod_spread: spread amplitude % = 0.1 * ssmod_spread; 0: disable ssmod, others will enable ssmod, max to 0x1f. 251 252* driver strength 253 254phy_ddr*_dq_drv_when_odten_ohm: The PHY DQ/DQS driver strength(write direction) when DRAM odt on. unit: ohm. 255phy_ddr*_ca_drv_when_odten_ohm: The PHY CMD/ADDR driver strength when DRAM odt on. unit: ohm. 256phy_ddr*_clk_drv_when_odten_ohm: The PHY clock driver strength when DRAM odt on. unit: ohm. 257ddr*_dq_drv_when_odten_ohm: The DRAM DQ/DQS driver strength(read direction) when PHY odt on. unit: ohm. 258phy_ddr*_dq_drv_when_odtoff_ohm: The PHY DQ/DQS driver strength(write direction) when DRAM odt off. unit: ohm. 259phy_ddr*_ca_drv_when_odtoff_ohm: The PHY CMD/ADDR driver strength when DRAM odt off. unit: ohm. 260phy_ddr*_clk_drv_when_odtoff_ohm: The PHY clock driver strength when DRAM odt off. unit: ohm. 261ddr*_dq_drv_when_odtoff_ohm: The DRAM DQ/DQS driver strength(read direction) when PHY odt off. unit: ohm. 262 263The phy side driver strength support value as follows: 264+---------------+-------------------+-------------------+--------------+-----------------+----------------+----------------+-------------+ 265| platform | DDR3 | DDR4 | LP3 | LP4 | LP4X pull up | LP4X pull down | LP5 | 266+---------------+-------------------+-------------------+--------------+-----------------+----------------+----------------+-------------+ 267| | 455,230,153,115, | 482,244,162,122, | | 501,253,168,126,| | | | 268| | 91,76,65,57,51,46,| 97,81,69,61,54,48,| | 101,84,72,63,56,| | | | 269| RV1126/RV1109 | 41,38,35,32,30,28,| 44,40,37,34,32,30,| follow DDR4 | 50,46,42,38,36, | follow LP4 | follow LP4 | X | 270| | 27,25,24,23,22,21,| 28,27,25,24,23,22,| | 33,31,29,28,26, | | | | 271| | 20 | 21 | | 25,24,23,22 | | | | 272+---------------+-------------------+-------------------+--------------+-----------------+----------------+----------------+-------------+ 273| | 500,250,167,125, | 556,279,185,139, | | 576,289,192,144,| 646,323,215, | 513,259,172, | | 274| | 100,83,71,63,56, | 111,93,79,69,62, | | 115,96,82,72,64,| 162,129,108,92,| 130,104,86,74, | | 275| RK3566/RK3568 | 50,45,41,38,36,33,| 55,50,46,42,39,37,| follow DDR4 | 57,52,48,44,41, | 81,72,65,59,54,| 65,58,52,47,43,| X | 276| | 31,29,28,26,25,24,| 34,32,31,29,27,26,| | 38,36,34,32,30, | 50,46,43,40,38,| 40,37,35,32,30,| | 277| | 23,22 | 25,24 | | 28,27,26,25 | 36,34,32,31,29,| 29,27,26,25,24,| | 278| | | | | | 28 | 23 | | 279+---------------+-------------------+-------------------+--------------+-----------------+----------------+----------------+-------------+ 280| RK3588 | X | X | X | 240,120,80,60, | follow LP4 | follow LP4 | follow LP4 | 281| | | | | 48,40,34,30 | | | | 282+---------------+-------------------+-------------------+--------------+-----------------+----------------+----------------+-------------+ 283| | 572,289,195,145, | 595,300,202,151, | | 654,328,221,165,| 585,297,202, | 585,297,202, | | 284| | 117,99,85,73,66, | 122,102,89,76,68, | |133,112,97,83,74,| 150,122,103,90,| 150,122,103,90,| | 285| RK3528 | 60,55,50,47,44,41,| 62,57,52,49,45,43,| follow DDR4 | 67,62,57,53,49, | 77,69,63,58,53,| 77,69,63,58,53,| X | 286| | 38,36,34,33,31,30,| 39,37,35,34,32,31,| | 46,43,40,38,37, | 50,47,44,40,38,| 50,47,44,40,38,| | 287| | 29,28 | 30,29 | | 35,33,32,31 | 37,35,33,32,31,| 37,35,33,32,31,| | 288| | | | | | 30 | 30 | | 289+---------------+-------------------+-------------------+--------------+-----------------+----------------+----------------+-------------+ 290 291The DRAM side driver strength support value as follows: 292+---------------+-------------------+-------------------+----------------+----------------------+----------------+-------------+ 293| platform | DDR3 | DDR4 | LP3 | LP4 | LP4X | LP5 | 294+---------------+-------------------+-------------------+----------------+----------------------+----------------+-------------+ 295| all | 40,34 | 34,48 | 34,40,48,60,80 | 40,48,60,80,120,240 | follow LP4 | follow LP4 | 296+---------------+-------------------+-------------------+----------------+----------------------+----------------+-------------+ 297 298* ODT 299phy_ddr*_odt_ohm: The PHY ODT strength(read direction). unit: ohm. 300ddr*_odt_ohm: The DRAM ODT strength(write direction). unit: ohm. 301phy_ddr*_odt_pull_up_en: 1: enable PHY pull up odt. 0: disable 302phy_ddr*_odt_pull_dn_en: 1: enable PHY pull down odt. 0: disable 303phy_ddr*_odten_freq_mhz: The PHY odt enable when larger than this frequency. unit: MHz. 304ddr*_odten_freq_mhz: The DRAM odt(DQ/DQS) enable when larger than this frequency. unit: MHz. 305 306The phy side ODT support value as follows: 307The ODT "0" means disabled ODT. 308+---------------+-------------------+--------------------+--------------+-------------------+----------------+----------------+-------------+ 309| platform | DDR3 | DDR4 | LP3 | LP4 | LP4X pull up | LP4X pull down | LP5 | 310+---------------+-------------------+--------------------+--------------+-------------------+----------------+----------------+-------------+ 311| | 0,561,282,188,141,| 0,586,294,196,148, | | 0,604,303,202,152,| | | | 312| | 113,94,81,72,64, | 118,99,58,76,67,60,| | 122,101,87,78,69, | | | | 313| RV1126/RV1109 | 58,52,48,44,41, | 55,50,46,43,40,38, | follow DDR4 | 62,56,52,48,44,41,| follow LP4 | follow LP4 | X | 314| | 38,37,34,32,31,29,| 36,34,32,31,29,28, | | 39,37,35,33,32,30,| | | | 315| | 28,27,25 | 27 | | 29,27 | | | | 316+---------------+-------------------+--------------------+--------------+-------------------+----------------+----------------+-------------+ 317| | 0,500,250,167,125,| 0,556,279,185,139, | | 0,576,289,192,144,| 0,646,323,215, | 0,513,259,172, | | 318| | 100,83,71,63,56, | 111,93,79,69,62, | | 115,96,82,72,64, | 162,129,108,92,| 130,104,86,74, | | 319| RK3566/RK3568 | 50,45,41,38,36,33,| 55,50,46,42,39,37, | follow DDR4 | 57,52,48,44,41, | 81,72,65,59,54,| 65,58,52,47,43,| X | 320| | 31,29,28,26,25,24,| 34,32,31,29,27,26, | | 38,36,34,32,30, | 50,46,43,40,38,| 40,37,35,32,30,| | 321| | 23,22 | 25,24 | | 28,27,26,25 | 36,34,32,31,29,| 29,27,26,25,24,| | 322| | | | | | 28 | 23 | | 323+---------------+-------------------+--------------------+--------------+-------------------+----------------+----------------+-------------+ 324| RK3588 | X | X | X | 0,240,120,80, | follow LP4 | follow LP4 | follow LP4 | 325| | | | | 60,48,40,34,30 | | | | 326+---------------+-------------------+--------------------+--------------+-------------------+----------------+----------------+-------------+ 327| | 572,289,195,145, | 595,300,202,151, | | 654,328,221,165, | 585,297,202, | 585,297,202, | | 328| | 117,99,85,73,66, | 122,102,89,76,68, | |133,112,97,83,74, | 150,122,103,90,| 150,122,103,90,| | 329| RK3528 | 60,55,50,47,44,41,| 62,57,52,49,45,43, | follow DDR4 | 67,62,57,53,49, | 77,69,63,58,53,| 77,69,63,58,53,| X | 330| | 38,36,34,33,31,30,| 39,37,35,34,32,31, | | 46,43,40,38,37, | 50,47,44,40,38,| 50,47,44,40,38,| | 331| | 29,28 | 30,29 | | 35,33,32,31 | 37,35,33,32,31,| 37,35,33,32,31,| | 332| | | | | | 30 | 30 | | 333+---------------+-------------------+--------------------+--------------+-------------------+----------------+----------------+-------------+ 334The DRAM side ODT support value as follows: 335+---------------+-------------------+-------------------+--------------+-----------------------+----------------+---------------+ 336| platform | DDR3 | DDR4 | LP3 | LP4(include DQ and CA)| LP4X | LP5 | 337+---------------+-------------------+-------------------+--------------+-----------------------+----------------+---------------+ 338| all | 0,40,60,120 | 0,34,40,48,60,120 | 0,60,120,240 | 0,40,48,60,80,120,240 | follow LP4 | follow LP4 | 339+---------------+-------------------+-------------------+--------------+-----------------------+----------------+---------------+ 340 341* slew rate 342 343phy_ddr*_dq_sr_when_odten: The PHY DQ/DQS slew rate when odt on. 344phy_ddr*_ca_sr_when_odten: The PHY CMD/ADDR slew rate when odt on. 345phy_ddr*_clk_sr_when_odten: The PHY clock slew rate when odt on. 346phy_ddr*_dq_sr_when_odtoff: The PHY DQ/DQS slew rate when odt off. 347phy_ddr*_ca_sr_when_odtoff: The PHY CMD/ADDR slew rate when odt off. 348phy_ddr*_clk_sr_when_odtoff: The PHY clock slew rate when odt off. 349 350The max value is 0x1f, the min is 0x0. 351 352* byte map 353 354ddr*_bytes_map: The bytes remap in PHY. 355 356* dq remap 357 358lp*_dq*_*_map: The dq remap in PHY. 359ddr*_cs*_dq*_dq*_map: The dq remap in PHY. 360 361* lp4/lp4x more information 362 363lp4*_ca_odten_freq_mhz: The DRAM CMD/ADDR odt enable when larger than this frequency. unit: MHz. 364phy_lp4*_dq_vref_when_odten: The PHY VrefDQ when PHY odt on. uint: parts per thousand. 365lp4*_dq_vref_when_odten: The DRAM VrefDQ when DRAM DQ/DQS odt on. uint: parts per thousand. 366lp4*_ca_vref_when_odten: The DRAM VrefCA when DRAM CA odt on. uint: parts per thousand. 367phy_lp4_dq_vref_when_odtoff: The PHY VrefDQ when PHY odt off. uint: parts per thousand. 368lp4_dq_vref_when_odtoff: The DRAM VrefDQ when DRAM DQ/DQS odt off. uint: parts per thousand. 369lp4_ca_vref_when_odtoff: The DRAM VrefCA when DRAM CA odt off. uint: parts per thousand. 370 371* hash info 372ch/bank/rank_mask*: is used to DDR address hash mask. 373