186251429SZhihuan Hefunction 1: modify ddr.bin file from ddrbin_param.txt. 2612e733eSZhihuan He 1) modify 'ddrbin_param.txt', set ddr frequency, uart info etc what you want. 386251429SZhihuan He If want to keep items default, please keep these items blank. 4612e733eSZhihuan He 2) run 'ddrbin_tool' with argument 1: ddrbin_param.txt, argument 2: ddr bin file. 554a17cb1STang Yun ping like: ./ddrbin_tool ddrbin_param.txt px30_ddr_333MHz_v1.13.bin 6612e733eSZhihuan He 786251429SZhihuan Hefunction 2: get ddr.bin file config to gen_param.txt file 886251429SZhihuan He If want to get ddrbin file config, please run like that: 986251429SZhihuan He ./ddrbin_tool -g gen_param.txt px30_ddr_333MHz_v1.15.bin 1086251429SZhihuan He The config will show in gen_param.txt. 1154a17cb1STang Yun ping 12612e733eSZhihuan HeNote: The function 1 and function 2 are two separate functions 13612e733eSZhihuan He The gen_param.txt file which is generated by function 2 no need use in function 1. 14612e733eSZhihuan He 1586251429SZhihuan HeThe detail information as following: 1654a17cb1STang Yun ping 1786251429SZhihuan He* support ddrbin version 18612e733eSZhihuan He +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------+----------+----------------+ 19612e733eSZhihuan He | platform | uart info | ddr freq | ssmod | DDR 2T | sr pd | drv, odt, Vref etc| dis training info | eye sacn | res space remap| 20612e733eSZhihuan He +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------+----------+----------------+ 21612e733eSZhihuan He | PX30/RK3326 | V1.11 | X | X | V1.12 | V1.15 | X | X | X | X | 22612e733eSZhihuan He +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------+----------+----------------+ 23612e733eSZhihuan He | RK1808 | V1.03 | V1.03 | X | V1.03 | V1.04 | X | X | X | X | 24612e733eSZhihuan He +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------+----------+----------------+ 25612e733eSZhihuan He | RK322x | V1.08 | V1.08 | X | V1.09 | X | X | X | X | X | 26612e733eSZhihuan He +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------+----------+----------------+ 27612e733eSZhihuan He | RK322xh | V1.14 | X | X | V1.16 | V1.17 | X | X | X | X | 28612e733eSZhihuan He +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------+----------+----------------+ 29612e733eSZhihuan He | RK3288 | V1.07 | X | X | V1.08 | X | X | X | X | X | 30612e733eSZhihuan He +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------+----------+----------------+ 31612e733eSZhihuan He | RK3308 | V1.28 | V1.28 | X | V1.29 | V1.30 | X | X | X | X | 32612e733eSZhihuan He +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------+----------+----------------+ 33612e733eSZhihuan He | RK3368 | V2.04 | V2.04 | X | V2.05 | X | X | X | X | X | 34612e733eSZhihuan He +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------+----------+----------------+ 35612e733eSZhihuan He | RK3328 | V1.14 | X | X | V1.16 | V1.17 | X | X | X | X | 36612e733eSZhihuan He +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------+----------+----------------+ 37612e733eSZhihuan He | RK3399 | V1.25 | X | V1.25 | X | X | X | X | X | X | 38612e733eSZhihuan He +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------+----------+----------------+ 39612e733eSZhihuan He | RK3399PRO NPU | V1.03 | V1.03 | X | V1.03 | X | X | X | X | X | 40612e733eSZhihuan He +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------+----------+----------------+ 41612e733eSZhihuan He | RV1126/RV1109 | V1.00 | V1.00 | V1.05 | V1.00 | V1.05 | V1.05 | X | X | X | 42612e733eSZhihuan He +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------+----------+----------------+ 43612e733eSZhihuan He | RK3566/RK3568 | V1.00 | V1.00 | V1.06 | V1.00 | V1.00 | V1.06 | V1.07 | X | X | 44612e733eSZhihuan He +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------+----------+----------------+ 45612e733eSZhihuan He | RK3588 | V1.00 | V1.00 | X | V1.00 | V1.00 | V1.00 | V1.03 | V1.06 | V1.06 | 46612e733eSZhihuan He +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------+----------+----------------+ 4786251429SZhihuan He 4886251429SZhihuan He* UART info 4986251429SZhihuan He 5086251429SZhihuan Heuart id: uart number. 0 for uart0, 1 for uart1, 2 for uart2..., 0xf will disable uart. 5186251429SZhihuan Heuart iomux: uart iomux info, 0 for uartn_m0, 1 for uartn_m1, 2 for uartn_m2...(like uart2_m0, uart2_m1,uart2_m2), 5286251429SZhihuan Heor 1 for uartn_a, 2 for uartn_b, 3 for uartn_c.(like uar2a, uart2b, uart2c). 5386251429SZhihuan Heuart baudrate: uart baudrate should be 115200 or 1500000. 5486251429SZhihuan He 5586251429SZhihuan He* disable print training information 5686251429SZhihuan He 5786251429SZhihuan Hedis_printf_training: 1: will disabled print training information; 0: will enable print training information. 5886251429SZhihuan He 59612e733eSZhihuan He* remap pcie 100M reg to DDR 6086251429SZhihuan He 61612e733eSZhihuan Heres_space_remap: 1: will remap pcie 100M reg to DDR memory space. 62612e733eSZhihuan He 63612e733eSZhihuan He* DDR eye scanning 64612e733eSZhihuan He1) eye_2d_scan_en: 1: will enable 2D eye scanning for debug purpose, vref and skew eye scanning. 65612e733eSZhihuan He2) wr_vref_scan_en: 1: enable vref scan and use scanning result for write. 66612e733eSZhihuan He3) rd_vref_scan_en: 1: enable vref scan and use scanning result for read. 6786251429SZhihuan He 68*d42b646fSZhihuan He* DDR (final) freq(ddrx_f0_freq_mhz) 6986251429SZhihuan He 70*d42b646fSZhihuan Heddr2_freq(ddr2_f0_freq_mhz): ddr2 frequency, unit:MHz. 71*d42b646fSZhihuan Help2_freq (lp2_f0_freq_mhz): lpddr2 frequency, unit:MHz. 72*d42b646fSZhihuan Heddr3_freq(ddr3_f0_freq_mhz): ddr3 frequency, unit:MHz. 73*d42b646fSZhihuan Help3_freq (lp3_f0_freq_mhz): lpddr3 frequency, unit:MHz. 74*d42b646fSZhihuan Heddr4_freq(ddr4_f0_freq_mhz): ddr4 frequency, unit:MHz. 75*d42b646fSZhihuan Help4_freq (lp4_f0_freq_mhz): lpddr4 frequency, unit:MHz. 76*d42b646fSZhihuan Help4x_freq(lp4x_f0_freq_mhz): lpddr4x frequency, unit:MHz. 77*d42b646fSZhihuan Help5_freq (lp5_f0_freq_mhz): lpddr5 frequency, unit:MHz. 7854a17cb1STang Yun ping 79612e733eSZhihuan HeFor RV1126/RV1109, RK3566/RK3568, RK3588 those frequencies are the final freq in loader. 80612e733eSZhihuan He 81612e733eSZhihuan He+---------------+--------------------------------------------------------+ 8286251429SZhihuan He| platform | support frequencies | 83612e733eSZhihuan He+---------------+--------------------------------------------------------+ 8486251429SZhihuan He| PX30/RK3326 | X | 85612e733eSZhihuan He+---------------+--------------------------------------------------------+ 8686251429SZhihuan He| RK1808 | 333,400,533,666,786,933 | 87612e733eSZhihuan He+---------------+--------------------------------------------------------+ 88612e733eSZhihuan He| RK322x | not larger than 800 | 89612e733eSZhihuan He+---------------+--------------------------------------------------------+ 9086251429SZhihuan He| RK322xh | X | 91612e733eSZhihuan He+---------------+--------------------------------------------------------+ 9286251429SZhihuan He| RK3288 | X | 93612e733eSZhihuan He+---------------+--------------------------------------------------------+ 94612e733eSZhihuan He| RK3308 | 393,451,589 | 95612e733eSZhihuan He+---------------+--------------------------------------------------------+ 9686251429SZhihuan He| RK3368 | DDR3 not larger than 800, LP3 not larger than 666 | 97612e733eSZhihuan He+---------------+--------------------------------------------------------+ 9886251429SZhihuan He| RK3328 | X | 99612e733eSZhihuan He+---------------+--------------------------------------------------------+ 10086251429SZhihuan He| RK3399 | X | 101612e733eSZhihuan He+---------------+--------------------------------------------------------+ 10286251429SZhihuan He| RK3399PRO NPU | 333,400,533,666,786,933 | 103612e733eSZhihuan He+---------------+--------------------------------------------------------+ 10486251429SZhihuan He| RV1126/RV1109 | 328,396,528,664,784,924,1056 | 105612e733eSZhihuan He+---------------+--------------------------------------------------------+ 106612e733eSZhihuan He| RK3566/RK3568 | 324,396,528,630,780,920,1056,1184,1332,1560 | 107612e733eSZhihuan He+---------------+--------------------------------------------------------+ 1088edfcbeaSZhihuan He| RK3588 | LP4/LP4x [306.5MHz - 2133MHz]; LP5: [400MHz - 2750MHz] | 109612e733eSZhihuan He+---------------+--------------------------------------------------------+ 110558a25b2STang Yun ping 11186251429SZhihuan He* DDR frequencies(add more) 112eea48410SZhihuan He 11372640b4bSZhihuan Heddr2_f1_freq_mhz: ddr2 frequency number 1, unit:MHz. 11472640b4bSZhihuan Heddr2_f2_freq_mhz: ddr2 frequency number 2, unit:MHz. 11572640b4bSZhihuan Heddr2_f3_freq_mhz: ddr2 frequency number 3, unit:MHz. 11672640b4bSZhihuan Heddr2_f4_freq_mhz: ddr2 frequency number 4, unit:MHz. 11772640b4bSZhihuan Heddr2_f5_freq_mhz: ddr2 frequency number 5, unit:MHz. 11872640b4bSZhihuan He... 119*d42b646fSZhihuan HeThe ddrx_f0_freq_mhz is named ddrx_freq. 12086251429SZhihuan He 121612e733eSZhihuan Heddr*_f*_freq_mhz/lp*_f*_freq_mhz: Only RV1126/RV1109, RK3566/RK3568, RK3588 used. 1228edfcbeaSZhihuan HeThe program will initialize dram by following order. 12386251429SZhihuan Hefor example: ddr4_f1_freq_mhz --> ddr4_f2_freq_mhz --> ddr4_f3_freq_mhz --> ddr4_freq. 124612e733eSZhihuan HeAnd the final frequency is ddr4_freq to boot system. 125612e733eSZhihuan HeThe ddr frequency table in kernel dts/dtsi file need correspond to these frequencies. 12686251429SZhihuan HeSo it is better to arrange the frequency values in order as above. That means the max freq is in final freq(lp*/ddr*_freq) and the min freq is in 'ddr*/lp*_f1_freq_mhz'. 127612e733eSZhihuan HeSuch as: ddr*/lp*_f1_freq_mhz < ddr*/lp*_f2_freq_mhz < ddr*/lp*_f3_freq_mhz < lp*/ddr*_freq(the final freq) 12886251429SZhihuan HeFor example: 12986251429SZhihuan He ... 13086251429SZhihuan He ddr4_freq=1560 13186251429SZhihuan He ... 13286251429SZhihuan He ddr4_f1_freq_mhz=324 13386251429SZhihuan He ddr4_f2_freq_mhz=528 13486251429SZhihuan He ddr4_f3_freq_mhz=780 13586251429SZhihuan He ... 13686251429SZhihuan He 13786251429SZhihuan He* SR PD idle 13886251429SZhihuan He 13986251429SZhihuan Hesr_idle: auto self-refresh mode delay time. 14086251429SZhihuan Hepd_idle: auto power-down mode delay time. 14186251429SZhihuan He 14286251429SZhihuan He* DDR 2T 14386251429SZhihuan He 14486251429SZhihuan Heddr_2t: ddr 2T timing mode. 1: enable ddr 2T, 0: disable ddr 2T. 14586251429SZhihuan He 14686251429SZhihuan He* PLL ssmod 14786251429SZhihuan He 1483e8d76b8SZhihuan HeThese parameters are about Spread Spectrum Modulator(ssmod) for PLL. 1493e8d76b8SZhihuan Hessmod_downspread: ssmod work mode. 0: down spread, 1: center spread. 150612e733eSZhihuan Hessmod_div: Divider required to set the modulation frequency. RK3308 suggests to ssmod_div=2, others platforms suggest to ssmod_div=5. 1513e8d76b8SZhihuan Hessmod_spread: spread amplitude % = 0.1 * ssmod_spread; 0: disable ssmod, others will enable ssmod, max to 0x1f. 15286251429SZhihuan He 15386251429SZhihuan He* driver strength 15486251429SZhihuan He 15586251429SZhihuan Hephy_ddr*_dq_drv_when_odten_ohm: The PHY DQ/DQS driver strength(write direction) when DRAM odt on. unit: ohm. 15686251429SZhihuan Hephy_ddr*_ca_drv_when_odten_ohm: The PHY CMD/ADDR driver strength when DRAM odt on. unit: ohm. 15786251429SZhihuan Hephy_ddr*_clk_drv_when_odten_ohm: The PHY clock driver strength when DRAM odt on. unit: ohm. 15886251429SZhihuan Heddr*_dq_drv_when_odten_ohm: The DRAM DQ/DQS driver strength(read direction) when PHY odt on. unit: ohm. 15986251429SZhihuan Hephy_ddr*_dq_drv_when_odtoff_ohm: The PHY DQ/DQS driver strength(write direction) when DRAM odt off. unit: ohm. 16086251429SZhihuan Hephy_ddr*_ca_drv_when_odtoff_ohm: The PHY CMD/ADDR driver strength when DRAM odt off. unit: ohm. 16186251429SZhihuan Hephy_ddr*_clk_drv_when_odtoff_ohm: The PHY clock driver strength when DRAM odt off. unit: ohm. 16286251429SZhihuan Heddr*_dq_drv_when_odtoff_ohm: The DRAM DQ/DQS driver strength(read direction) when PHY odt off. unit: ohm. 16386251429SZhihuan He 16486251429SZhihuan HeThe phy side driver strength support value as follows: 165612e733eSZhihuan He+---------------+-------------------+-------------------+--------------+-----------------+----------------+----------------+-------------+ 166612e733eSZhihuan He| platform | DDR3 | DDR4 | LP3 | LP4 | LP4X pull up | LP4X pull down | LP5 | 167612e733eSZhihuan He+---------------+-------------------+-------------------+--------------+-----------------+----------------+----------------+-------------+ 168612e733eSZhihuan He| | 455,230,153,115, | 482,244,162,122, | | 501,253,168,126,| | | | 169612e733eSZhihuan He| | 91,76,65,57,51,46,| 97,81,69,61,54,48,| | 101,84,72,63,56,| | | | 170612e733eSZhihuan He| RV1126/RV1109 | 41,38,35,32,30,28,| 44,40,37,34,32,30,| follow DDR4 | 50,46,42,38,36, | follow LP4 | follow LP4 | X | 171612e733eSZhihuan He| | 27,25,24,23,22,21,| 28,27,25,24,23,22,| | 33,31,29,28,26, | | | | 172612e733eSZhihuan He| | 20 | 21 | | 25,24,23,22 | | | | 173612e733eSZhihuan He+---------------+-------------------+-------------------+--------------+-----------------+----------------+----------------+-------------+ 174612e733eSZhihuan He| | 500,250,167,125, | 556,279,185,139, | | 576,289,192,144,| 646,323,215, | 513,259,172, | | 175612e733eSZhihuan He| | 100,83,71,63,56, | 111,93,79,69,62, | | 115,96,82,72,64,| 162,129,108,92,| 130,104,86,74, | | 176612e733eSZhihuan He| RK3566/RK3568 | 50,45,41,38,36,33,| 55,50,46,42,39,37,| follow DDR4 | 57,52,48,44,41, | 81,72,65,59,54,| 65,58,52,47,43,| X | 177612e733eSZhihuan He| | 31,29,28,26,25,24,| 34,32,31,29,27,26,| | 38,36,34,32,30, | 50,46,43,40,38,| 40,37,35,32,30,| | 178612e733eSZhihuan He| | 23,22 | 25,24 | | 28,27,26,25 | 36,34,32,31,29,| 29,27,26,25,24,| | 179612e733eSZhihuan He| | | | | | 28 | 23 | | 180612e733eSZhihuan He+---------------+-------------------+-------------------+--------------+-----------------+----------------+----------------+-------------+ 181612e733eSZhihuan He| RK3588 | X | X | X | 240,120,80,60, | follow LP4 | follow LP4 | follow LP4 | 182612e733eSZhihuan He| | | | | 48,40,34,30 | | | | 183612e733eSZhihuan He+---------------+-------------------+-------------------+--------------+-----------------+----------------+----------------+-------------+ 18486251429SZhihuan He 18586251429SZhihuan HeThe DRAM side driver strength support value as follows: 186612e733eSZhihuan He+---------------+-------------------+-------------------+----------------+----------------------+----------------+-------------+ 187612e733eSZhihuan He| platform | DDR3 | DDR4 | LP3 | LP4 | LP4X | LP5 | 188612e733eSZhihuan He+---------------+-------------------+-------------------+----------------+----------------------+----------------+-------------+ 189612e733eSZhihuan He| all | 40,34 | 34,48 | 34,40,48,60,80 | 40,48,60,80,120,240 | follow LP4 | follow LP4 | 190612e733eSZhihuan He+---------------+-------------------+-------------------+----------------+----------------------+----------------+-------------+ 19186251429SZhihuan He 19286251429SZhihuan He* ODT 19386251429SZhihuan Hephy_ddr*_odt_ohm: The PHY ODT strength(read direction). unit: ohm. 19486251429SZhihuan Heddr*_odt_ohm: The DRAM ODT strength(write direction). unit: ohm. 19586251429SZhihuan Hephy_ddr*_odt_pull_up_en: 1: enable PHY pull up odt. 0: disable 19686251429SZhihuan Hephy_ddr*_odt_pull_dn_en: 1: enable PHY pull down odt. 0: disable 19786251429SZhihuan Hephy_ddr*_odten_freq_mhz: The PHY odt enable when larger than this frequency. unit: MHz. 19886251429SZhihuan Heddr*_odten_freq_mhz: The DRAM odt(DQ/DQS) enable when larger than this frequency. unit: MHz. 19986251429SZhihuan He 20086251429SZhihuan HeThe phy side ODT support value as follows: 20186251429SZhihuan HeThe ODT "0" means disabled ODT. 202612e733eSZhihuan He+---------------+-------------------+--------------------+--------------+-------------------+----------------+----------------+-------------+ 203612e733eSZhihuan He| platform | DDR3 | DDR4 | LP3 | LP4 | LP4X pull up | LP4X pull down | LP5 | 204612e733eSZhihuan He+---------------+-------------------+--------------------+--------------+-------------------+----------------+----------------+-------------+ 205612e733eSZhihuan He| | 0,561,282,188,141,| 0,586,294,196,148, | | 0,604,303,202,152,| | | | 206612e733eSZhihuan He| | 113,94,81,72,64, | 118,99,58,76,67,60,| | 122,101,87,78,69, | | | | 207612e733eSZhihuan He| RV1126/RV1109 | 58,52,48,44,41, | 55,50,46,43,40,38, | follow DDR4 | 62,56,52,48,44,41,| follow LP4 | follow LP4 | X | 208612e733eSZhihuan He| | 38,37,34,32,31,29,| 36,34,32,31,29,28, | | 39,37,35,33,32,30,| | | | 209612e733eSZhihuan He| | 28,27,25 | 27 | | 29,27 | | | | 210612e733eSZhihuan He+---------------+-------------------+--------------------+--------------+-------------------+----------------+----------------+-------------+ 211612e733eSZhihuan He| | 0,500,250,167,125,| 0,556,279,185,139, | | 0,576,289,192,144,| 0,646,323,215, | 0,513,259,172, | | 212612e733eSZhihuan He| | 100,83,71,63,56, | 111,93,79,69,62, | | 115,96,82,72,64, | 162,129,108,92,| 130,104,86,74, | | 213612e733eSZhihuan He| RK3566/RK3568 | 50,45,41,38,36,33,| 55,50,46,42,39,37, | follow DDR4 | 57,52,48,44,41, | 81,72,65,59,54,| 65,58,52,47,43,| X | 214612e733eSZhihuan He| | 31,29,28,26,25,24,| 34,32,31,29,27,26, | | 38,36,34,32,30, | 50,46,43,40,38,| 40,37,35,32,30,| | 215612e733eSZhihuan He| | 23,22 | 25,24 | | 28,27,26,25 | 36,34,32,31,29,| 29,27,26,25,24,| | 216612e733eSZhihuan He| | | | | | 28 | 23 | | 217612e733eSZhihuan He+---------------+-------------------+--------------------+--------------+-------------------+----------------+----------------+-------------+ 218612e733eSZhihuan He| RK3588 | X | X | X | 0,240,120,80, | follow LP4 | follow LP4 | follow LP4 | 219612e733eSZhihuan He| | | | | 60,48,40,34,30 | | | | 220612e733eSZhihuan He+---------------+-------------------+--------------------+--------------+-------------------+----------------+----------------+-------------+ 22186251429SZhihuan He 22286251429SZhihuan HeThe DRAM side ODT support value as follows: 223612e733eSZhihuan He+---------------+-------------------+-------------------+--------------+-----------------------+----------------+---------------+ 224612e733eSZhihuan He| platform | DDR3 | DDR4 | LP3 | LP4(include DQ and CA)| LP4X | LP5 | 225612e733eSZhihuan He+---------------+-------------------+-------------------+--------------+-----------------------+----------------+---------------+ 226612e733eSZhihuan He| all | 0,40,60,120 | 0,34,40,48,60,120 | 0,60,120,240 | 0,40,48,60,80,120,240 | follow LP4 | follow LP4 | 227612e733eSZhihuan He+---------------+-------------------+-------------------+--------------+-----------------------+----------------+---------------+ 22886251429SZhihuan He 22986251429SZhihuan He* slew rate 23086251429SZhihuan He 23186251429SZhihuan Hephy_ddr*_dq_sr_when_odten: The PHY DQ/DQS slew rate when odt on. 23286251429SZhihuan Hephy_ddr*_ca_sr_when_odten: The PHY CMD/ADDR slew rate when odt on. 23386251429SZhihuan Hephy_ddr*_clk_sr_when_odten: The PHY clock slew rate when odt on. 23486251429SZhihuan Hephy_ddr*_dq_sr_when_odtoff: The PHY DQ/DQS slew rate when odt off. 23586251429SZhihuan Hephy_ddr*_ca_sr_when_odtoff: The PHY CMD/ADDR slew rate when odt off. 23686251429SZhihuan Hephy_ddr*_clk_sr_when_odtoff: The PHY clock slew rate when odt off. 23786251429SZhihuan He 238612e733eSZhihuan HeThe max value is 0x1f, the min is 0x0. 239612e733eSZhihuan He 24086251429SZhihuan He* byte map 24186251429SZhihuan He 242612e733eSZhihuan Heddr*_bytes_map: The bytes remap in PHY. 24386251429SZhihuan He 24486251429SZhihuan He* dq remap 24586251429SZhihuan He 246612e733eSZhihuan Help*_dq*_*_map: The dq remap in PHY. 247612e733eSZhihuan Heddr*_cs*_dq*_dq*_map: The dq remap in PHY. 24886251429SZhihuan He 24986251429SZhihuan He* lp4/lp4x more information 25086251429SZhihuan He 25186251429SZhihuan Help4*_ca_odten_freq_mhz: The DRAM CMD/ADDR odt enable when larger than this frequency. unit: MHz. 25286251429SZhihuan Hephy_lp4*_dq_vref_when_odten: The PHY VrefDQ when PHY odt on. uint: parts per thousand. 25386251429SZhihuan Help4*_dq_vref_when_odten: The DRAM VrefDQ when DRAM DQ/DQS odt on. uint: parts per thousand. 25486251429SZhihuan Help4*_ca_vref_when_odten: The DRAM VrefCA when DRAM CA odt on. uint: parts per thousand. 25586251429SZhihuan Hephy_lp4_dq_vref_when_odtoff: The PHY VrefDQ when PHY odt off. uint: parts per thousand. 25686251429SZhihuan Help4_dq_vref_when_odtoff: The DRAM VrefDQ when DRAM DQ/DQS odt off. uint: parts per thousand. 25786251429SZhihuan Help4_ca_vref_when_odtoff: The DRAM VrefCA when DRAM CA odt off. uint: parts per thousand. 2588edfcbeaSZhihuan He 2598edfcbeaSZhihuan He* hash info 2608edfcbeaSZhihuan Hech/bank/rank_mask*: is used to DDR address hash mask. 261