1*86251429SZhihuan Hefunction 1: modify ddr.bin file from ddrbin_param.txt. 2*86251429SZhihuan He 1) modify "ddrbin_param.txt", set ddr frequency, uart info etc what you want. 3*86251429SZhihuan He If want to keep items default, please keep these items blank. 4*86251429SZhihuan He 2) run "ddrbin_tool" with argument 1: ddrbin_param.txt, argument 2: ddr bin file. 554a17cb1STang Yun ping like: ./ddrbin_tool ddrbin_param.txt px30_ddr_333MHz_v1.13.bin 6*86251429SZhihuan Hefunction 2: get ddr.bin file config to gen_param.txt file 7*86251429SZhihuan He If want to get ddrbin file config, please run like that: 8*86251429SZhihuan He ./ddrbin_tool -g gen_param.txt px30_ddr_333MHz_v1.15.bin 9*86251429SZhihuan He The config will show in gen_param.txt. 1054a17cb1STang Yun ping 11*86251429SZhihuan HeThe detail information as following: 1254a17cb1STang Yun ping 13*86251429SZhihuan He* support ddrbin version 14*86251429SZhihuan He The 'X' means not support change those parameters by tool. 15*86251429SZhihuan He +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+ 16*86251429SZhihuan He | platform | uart info | ddr freq | ssmod | DDR 2T | sr pd | drv, odt, Vref etc| dis print training info | dis CBT | 17*86251429SZhihuan He +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+ 18*86251429SZhihuan He | RV1108 | V1.08 | V1.08 | V1.10 | V1.08 | V1.08 | X | X | X | 19*86251429SZhihuan He +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+ 20*86251429SZhihuan He | PX30/RK3326 | V1.11 | X | V1.16 | V1.12 | V1.15 | X | X | X | 21*86251429SZhihuan He +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+ 22*86251429SZhihuan He | RK1808 | V1.03 | V1.03 | V1.05 | V1.03 | V1.04 | X | X | X | 23*86251429SZhihuan He +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+ 24*86251429SZhihuan He | RK322x | V1.08 | V1.08 | X | V1.09 | X | X | X | X | 25*86251429SZhihuan He +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+ 26*86251429SZhihuan He | RK322xh | V1.14 | X | V1.17 | V1.16 | V1.17 | X | X | X | 27*86251429SZhihuan He +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+ 28*86251429SZhihuan He | RK3288 | V1.07 | X | X | V1.08 | X | X | X | X | 29*86251429SZhihuan He +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+ 30*86251429SZhihuan He | RK3308 | V1.28 | V1.28 | V1.31 | V1.29 | V1.30 | X | X | X | 31*86251429SZhihuan He +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+ 32*86251429SZhihuan He | RK3368 | V2.04 | V2.04 | X | V2.05 | X | X | X | X | 33*86251429SZhihuan He +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+ 34*86251429SZhihuan He | RK3328 | V1.14 | X | V1.17 | V1.16 | V1.17 | X | X | X | 35*86251429SZhihuan He +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+ 36*86251429SZhihuan He | RK3399 | V1.25 | X | V1.25 | X | X | X | X | X | 37*86251429SZhihuan He +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+ 38*86251429SZhihuan He | RK3399PRO NPU | V1.03 | V1.03 | X | V1.03 | X | X | X | X | 39*86251429SZhihuan He +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+ 40*86251429SZhihuan He | RV1126/RV1109 | V1.00 | V1.00 | V1.05 | V1.00 | V1.05 | V1.05 | X | X | 41*86251429SZhihuan He +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+ 42*86251429SZhihuan He | RK3566/RK3568 | V1.00 | V1.00 | V1.06 | V1.00 | V1.00 | V1.06 | V1.07 | X | 43*86251429SZhihuan He +---------------+-----------+----------+-------+--------+-------+-------------------+-------------------------+---------+ 44*86251429SZhihuan He 45*86251429SZhihuan He* UART info 46*86251429SZhihuan He 47*86251429SZhihuan Heuart id: uart number. 0 for uart0, 1 for uart1, 2 for uart2..., 0xf will disable uart. 48*86251429SZhihuan Heuart iomux: uart iomux info, 0 for uartn_m0, 1 for uartn_m1, 2 for uartn_m2...(like uart2_m0, uart2_m1,uart2_m2), 49*86251429SZhihuan Heor 1 for uartn_a, 2 for uartn_b, 3 for uartn_c.(like uar2a, uart2b, uart2c). 50*86251429SZhihuan Heuart baudrate: uart baudrate should be 115200 or 1500000. 51*86251429SZhihuan He 52*86251429SZhihuan He* disable print training information 53*86251429SZhihuan He 54*86251429SZhihuan Hedis_printf_training: 1: will disabled print training information; 0: will enable print training information. 55*86251429SZhihuan He 56*86251429SZhihuan He* disable Command Bus Training(CBT) for lp4/lp4x 57*86251429SZhihuan He 58*86251429SZhihuan Hedis_cbt_for_lp4_lp4x: 1: will disbaled CBT for lp4/lp4x; 0: will enable CBT for lp4/lp4x. Reserve function, all platforms are not support. 59*86251429SZhihuan He 60*86251429SZhihuan He* DDR (final) freq 61*86251429SZhihuan He 62*86251429SZhihuan HeFor RV1126/RV1109, RK3566/RK3568, the frequencies as follows can choose to final freq in loader. 63*86251429SZhihuan He 642820321cSZhihuan Heddr2_freq: ddr2 frequency, unit:MHz. 652820321cSZhihuan Help2_freq: lpddr2 frequency, unit:MHz. 662820321cSZhihuan Heddr3_freq: ddr3 frequency, unit:MHz. 672820321cSZhihuan Help3_freq: lpddr3 frequency, unit:MHz. 682820321cSZhihuan Heddr4_freq: ddr4 frequency, unit:MHz. 692820321cSZhihuan Help4_freq: lpddr4 frequency, unit:MHz. 703e8d76b8SZhihuan Help4x_freq: lpddr4x frequency, unit:MHz. 7154a17cb1STang Yun ping 72*86251429SZhihuan HeThe 'X' as follows means not support change frequencies by tool. 73*86251429SZhihuan He+---------------+-----------------------------------------------------------------+ 74*86251429SZhihuan He| platform | support frequencies | 75*86251429SZhihuan He+---------------+-----------------------------------------------------------------+ 76*86251429SZhihuan He| RK1108 | DDR2 fix 400, LP2 not larger than 533, DDR3 not larger than 800 | 77*86251429SZhihuan He+---------------+-----------------------------------------------------------------+ 78*86251429SZhihuan He| PX30/RK3326 | X | 79*86251429SZhihuan He+---------------+-----------------------------------------------------------------+ 80*86251429SZhihuan He| RK1808 | 333,400,533,666,786,933 | 81*86251429SZhihuan He+---------------+-----------------------------------------------------------------+ 82*86251429SZhihuan He| RK322x | DDR2/LP2 not larger than 533, not larger than 800 | 83*86251429SZhihuan He+---------------+-----------------------------------------------------------------+ 84*86251429SZhihuan He| RK322xh | X | 85*86251429SZhihuan He+---------------+-----------------------------------------------------------------+ 86*86251429SZhihuan He| RK3288 | X | 87*86251429SZhihuan He+---------------+-----------------------------------------------------------------+ 88*86251429SZhihuan He| RK3308 | 393,451,589 | 89*86251429SZhihuan He+---------------+-----------------------------------------------------------------+ 90*86251429SZhihuan He| RK3368 | DDR3 not larger than 800, LP3 not larger than 666 | 91*86251429SZhihuan He+---------------+-----------------------------------------------------------------+ 92*86251429SZhihuan He| RK3328 | X | 93*86251429SZhihuan He+---------------+-----------------------------------------------------------------+ 94*86251429SZhihuan He| RK3399 | X | 95*86251429SZhihuan He+---------------+-----------------------------------------------------------------+ 96*86251429SZhihuan He| RK3399PRO NPU | 333,400,533,666,786,933 | 97*86251429SZhihuan He+---------------+-----------------------------------------------------------------+ 98*86251429SZhihuan He| RV1126/RV1109 | 328,396,528,664,784,924,1056 | 99*86251429SZhihuan He+---------------+-----------------------------------------------------------------+ 100*86251429SZhihuan He| RK3566/RK3568 | 324,396,528,630,780,920,1056,1184,1332,1560 | 101*86251429SZhihuan He+---------------+-----------------------------------------------------------------+ 102558a25b2STang Yun ping 103*86251429SZhihuan He* DDR frequencies(add more) 104eea48410SZhihuan He 10572640b4bSZhihuan Heddr2_f1_freq_mhz: ddr2 frequency number 1, unit:MHz. 10672640b4bSZhihuan Heddr2_f2_freq_mhz: ddr2 frequency number 2, unit:MHz. 10772640b4bSZhihuan Heddr2_f3_freq_mhz: ddr2 frequency number 3, unit:MHz. 10872640b4bSZhihuan Heddr2_f4_freq_mhz: ddr2 frequency number 4, unit:MHz. 10972640b4bSZhihuan Heddr2_f5_freq_mhz: ddr2 frequency number 5, unit:MHz. 11072640b4bSZhihuan He... 111*86251429SZhihuan He 112*86251429SZhihuan Heddr*_f*_freq_mhz/lp*_f*_freq_mhz: Only RV1126/RV1109, RK3566/RK3568 used.The program will initialize dram by following order. 113*86251429SZhihuan Hefor example: ddr4_f1_freq_mhz --> ddr4_f2_freq_mhz --> ddr4_f3_freq_mhz --> ddr4_freq. 114*86251429SZhihuan HeAnd the final frequency is 'ddr4_freq' to boot system. 115*86251429SZhihuan HeSo it is better to arrange the frequency values in order as above. That means the max freq is in final freq(lp*/ddr*_freq) and the min freq is in 'ddr*/lp*_f1_freq_mhz'. 116*86251429SZhihuan He ddr*/lp*_f1_freq_mhz < ddr*/lp*_f2_freq_mhz < ddr*/lp*_f3_freq_mhz < lp*/ddr*_freq(the final freq) 117*86251429SZhihuan HeFor example: 118*86251429SZhihuan He ... 119*86251429SZhihuan He ddr4_freq=1560 120*86251429SZhihuan He ... 121*86251429SZhihuan He ddr4_f1_freq_mhz=324 122*86251429SZhihuan He ddr4_f2_freq_mhz=528 123*86251429SZhihuan He ddr4_f3_freq_mhz=780 124*86251429SZhihuan He ... 125*86251429SZhihuan He 1263e8d76b8SZhihuan HeThe ddr frequency table in kernel dts/dtsi file need correspond to these frequencies. 1273e8d76b8SZhihuan He 128*86251429SZhihuan He* SR PD idle 129*86251429SZhihuan He 130*86251429SZhihuan Hesr_idle: auto self-refresh mode delay time. 131*86251429SZhihuan Hepd_idle: auto power-down mode delay time. 132*86251429SZhihuan He 133*86251429SZhihuan He* DDR 2T 134*86251429SZhihuan He 135*86251429SZhihuan Heddr_2t: ddr 2T timing mode. 1: enable ddr 2T, 0: disable ddr 2T. 136*86251429SZhihuan He 137*86251429SZhihuan He* PLL ssmod 138*86251429SZhihuan He 1393e8d76b8SZhihuan HeThese parameters are about Spread Spectrum Modulator(ssmod) for PLL. 1403e8d76b8SZhihuan Hessmod_downspread: ssmod work mode. 0: down spread, 1: center spread. 1413e8d76b8SZhihuan Hessmod_div: Divider required to set the modulation frequency. RK3308 suggests to ssmod_div=2, others platforms suggest to ssmod_div=5. 1423e8d76b8SZhihuan Hessmod_spread: spread amplitude % = 0.1 * ssmod_spread; 0: disable ssmod, others will enable ssmod, max to 0x1f. 143*86251429SZhihuan He 144*86251429SZhihuan He* driver strength 145*86251429SZhihuan He 146*86251429SZhihuan Hephy_ddr*_dq_drv_when_odten_ohm: The PHY DQ/DQS driver strength(write direction) when DRAM odt on. unit: ohm. 147*86251429SZhihuan Hephy_ddr*_ca_drv_when_odten_ohm: The PHY CMD/ADDR driver strength when DRAM odt on. unit: ohm. 148*86251429SZhihuan Hephy_ddr*_clk_drv_when_odten_ohm: The PHY clock driver strength when DRAM odt on. unit: ohm. 149*86251429SZhihuan Heddr*_dq_drv_when_odten_ohm: The DRAM DQ/DQS driver strength(read direction) when PHY odt on. unit: ohm. 150*86251429SZhihuan Hephy_ddr*_dq_drv_when_odtoff_ohm: The PHY DQ/DQS driver strength(write direction) when DRAM odt off. unit: ohm. 151*86251429SZhihuan Hephy_ddr*_ca_drv_when_odtoff_ohm: The PHY CMD/ADDR driver strength when DRAM odt off. unit: ohm. 152*86251429SZhihuan Hephy_ddr*_clk_drv_when_odtoff_ohm: The PHY clock driver strength when DRAM odt off. unit: ohm. 153*86251429SZhihuan Heddr*_dq_drv_when_odtoff_ohm: The DRAM DQ/DQS driver strength(read direction) when PHY odt off. unit: ohm. 154*86251429SZhihuan He 155*86251429SZhihuan HeThe phy side driver strength support value as follows: 156*86251429SZhihuan He+---------------+-------------------+-------------------+--------------+-----------------+----------------+----------------+ 157*86251429SZhihuan He| platform | DDR3 | DDR4 | LP3 | LP4 | LP4X pull up | LP4X pull down | 158*86251429SZhihuan He+---------------+-------------------+-------------------+--------------+-----------------+----------------+----------------+ 159*86251429SZhihuan He| | 455,230,153,115, | 482,244,162,122, | | 501,253,168,126,| | | 160*86251429SZhihuan He| | 91,76,65,57,51,46,| 97,81,69,61,54,48,| | 101,84,72,63,56,| | | 161*86251429SZhihuan He| RV1126/RV1109 | 41,38,35,32,30,28,| 44,40,37,34,32,30,| follow DDR4 | 50,46,42,38,36, | follow LP4 | follow LP4 | 162*86251429SZhihuan He| | 27,25,24,23,22,21,| 28,27,25,24,23,22,| | 33,31,29,28,26, | | | 163*86251429SZhihuan He| | 20 | 21 | | 25,24,23,22 | | | 164*86251429SZhihuan He+---------------+-------------------+-------------------+--------------+-----------------+----------------+----------------+ 165*86251429SZhihuan He| | 500,250,167,125, | 556,279,185,139, | | 576,289,192,144,| 646,323,215, | 513,259,172, | 166*86251429SZhihuan He| | 100,83,71,63,56, | 111,93,79,69,62, | | 115,96,82,72,64,| 162,129,108,92,| 130,104,86,74, | 167*86251429SZhihuan He| RK3566/RK3568 | 50,45,41,38,36,33,| 55,50,46,42,39,37,| follow DDR4 | 57,52,48,44,41, | 81,72,65,59,54,| 65,58,52,47,43,| 168*86251429SZhihuan He| | 31,29,28,26,25,24,| 34,32,31,29,27,26,| | 38,36,34,32,30, | 50,46,43,40,38,| 40,37,35,32,30,| 169*86251429SZhihuan He| | 23,22 | 25,24 | | 28,27,26,25 | 36,34,32,31,29,| 29,27,26,25,24,| 170*86251429SZhihuan He| | | | | | 28 | 23 | 171*86251429SZhihuan He+---------------+-------------------+-------------------+--------------+-----------------+----------------+----------------+ 172*86251429SZhihuan He 173*86251429SZhihuan HeThe DRAM side driver strength support value as follows: 174*86251429SZhihuan He+---------------+-------------------+-------------------+----------------+----------------------+----------------+ 175*86251429SZhihuan He| platform | DDR3 | DDR4 | LP3 | LP4 | LP4X | 176*86251429SZhihuan He+---------------+-------------------+-------------------+----------------+----------------------+----------------+ 177*86251429SZhihuan He| all | 40,34 | 34,48 | 34,40,48,60,80 | 40,48,60,80,120,240 | follow LP4 | 178*86251429SZhihuan He+---------------+-------------------+-------------------+----------------+----------------------+----------------+ 179*86251429SZhihuan He 180*86251429SZhihuan He* ODT 181*86251429SZhihuan Hephy_ddr*_odt_ohm: The PHY ODT strength(read direction). unit: ohm. 182*86251429SZhihuan Heddr*_odt_ohm: The DRAM ODT strength(write direction). unit: ohm. 183*86251429SZhihuan Hephy_ddr*_odt_pull_up_en: 1: enable PHY pull up odt. 0: disable 184*86251429SZhihuan Hephy_ddr*_odt_pull_dn_en: 1: enable PHY pull down odt. 0: disable 185*86251429SZhihuan Hephy_ddr*_odten_freq_mhz: The PHY odt enable when larger than this frequency. unit: MHz. 186*86251429SZhihuan Heddr*_odten_freq_mhz: The DRAM odt(DQ/DQS) enable when larger than this frequency. unit: MHz. 187*86251429SZhihuan He 188*86251429SZhihuan HeThe phy side ODT support value as follows: 189*86251429SZhihuan HeThe ODT "0" means disabled ODT. 190*86251429SZhihuan He+---------------+-------------------+--------------------+--------------+-------------------+----------------+----------------+ 191*86251429SZhihuan He| platform | DDR3 | DDR4 | LP3 | LP4 | LP4X pull up | LP4X pull down | 192*86251429SZhihuan He+---------------+-------------------+--------------------+--------------+-------------------+----------------+----------------+ 193*86251429SZhihuan He| | 0,561,282,188,141,| 0,586,294,196,148, | | 0,604,303,202,152,| | | 194*86251429SZhihuan He| | 113,94,81,72,64, | 118,99,58,76,67,60,| | 122,101,87,78,69, | | | 195*86251429SZhihuan He| RV1126/RV1109 | 58,52,48,44,41, | 55,50,46,43,40,38, | follow DDR4 | 62,56,52,48,44,41,| follow LP4 | follow LP4 | 196*86251429SZhihuan He| | 38,37,34,32,31,29,| 36,34,32,31,29,28, | | 39,37,35,33,32,30,| | | 197*86251429SZhihuan He| | 28,27,25 | 27 | | 29,27 | | | 198*86251429SZhihuan He+---------------+-------------------+--------------------+--------------+-------------------+----------------+----------------+ 199*86251429SZhihuan He| | 0,500,250,167,125,| 0,556,279,185,139, | | 0,576,289,192,144,| 0,646,323,215, | 0,513,259,172, | 200*86251429SZhihuan He| | 100,83,71,63,56, | 111,93,79,69,62, | | 115,96,82,72,64, | 162,129,108,92,| 130,104,86,74, | 201*86251429SZhihuan He| RK3566/RK3568 | 50,45,41,38,36,33,| 55,50,46,42,39,37, | follow DDR4 | 57,52,48,44,41, | 81,72,65,59,54,| 65,58,52,47,43,| 202*86251429SZhihuan He| | 31,29,28,26,25,24,| 34,32,31,29,27,26, | | 38,36,34,32,30, | 50,46,43,40,38,| 40,37,35,32,30,| 203*86251429SZhihuan He| | 23,22 | 25,24 | | 28,27,26,25 | 36,34,32,31,29,| 29,27,26,25,24,| 204*86251429SZhihuan He| | | | | | 28 | 23 | 205*86251429SZhihuan He+---------------+-------------------+--------------------+--------------+-------------------+----------------+----------------+ 206*86251429SZhihuan He 207*86251429SZhihuan HeThe DRAM side ODT support value as follows: 208*86251429SZhihuan He+---------------+-------------------+-------------------+--------------+-----------------------+----------------+ 209*86251429SZhihuan He| platform | DDR3 | DDR4 | LP3 | LP4(include DQ and CA)| LP4X | 210*86251429SZhihuan He+---------------+-------------------+-------------------+--------------+-----------------------+----------------+ 211*86251429SZhihuan He| all | 0,40,60,120 | 0,34,40,48,60,120 | 0,60,120,240 | 0,40,48,60,80,120,240 | follow LP4 | 212*86251429SZhihuan He+---------------+-------------------+-------------------+--------------+-----------------------+----------------+ 213*86251429SZhihuan He 214*86251429SZhihuan He* slew rate 215*86251429SZhihuan He 216*86251429SZhihuan Hephy_ddr*_dq_sr_when_odten: The PHY DQ/DQS slew rate when odt on. 217*86251429SZhihuan Hephy_ddr*_ca_sr_when_odten: The PHY CMD/ADDR slew rate when odt on. 218*86251429SZhihuan Hephy_ddr*_clk_sr_when_odten: The PHY clock slew rate when odt on. 219*86251429SZhihuan Hephy_ddr*_dq_sr_when_odtoff: The PHY DQ/DQS slew rate when odt off. 220*86251429SZhihuan Hephy_ddr*_ca_sr_when_odtoff: The PHY CMD/ADDR slew rate when odt off. 221*86251429SZhihuan Hephy_ddr*_clk_sr_when_odtoff: The PHY clock slew rate when odt off. 222*86251429SZhihuan He 223*86251429SZhihuan He* byte map 224*86251429SZhihuan He 225*86251429SZhihuan Heddr*_bytes_map: Reserve function. 226*86251429SZhihuan He 227*86251429SZhihuan He* dq remap 228*86251429SZhihuan He 229*86251429SZhihuan Help*_dq*_*_map: Reserve function. 230*86251429SZhihuan Heddr*_cs*_dq*_dq*_map: Reserve function. 231*86251429SZhihuan He 232*86251429SZhihuan He* lp4/lp4x more information 233*86251429SZhihuan He 234*86251429SZhihuan Help4*_ca_odten_freq_mhz: The DRAM CMD/ADDR odt enable when larger than this frequency. unit: MHz. 235*86251429SZhihuan Hephy_lp4*_dq_vref_when_odten: The PHY VrefDQ when PHY odt on. uint: parts per thousand. 236*86251429SZhihuan Help4*_dq_vref_when_odten: The DRAM VrefDQ when DRAM DQ/DQS odt on. uint: parts per thousand. 237*86251429SZhihuan Help4*_ca_vref_when_odten: The DRAM VrefCA when DRAM CA odt on. uint: parts per thousand. 238*86251429SZhihuan Hephy_lp4_dq_vref_when_odtoff: The PHY VrefDQ when PHY odt off. uint: parts per thousand. 239*86251429SZhihuan Help4_dq_vref_when_odtoff: The DRAM VrefDQ when DRAM DQ/DQS odt off. uint: parts per thousand. 240*86251429SZhihuan Help4_ca_vref_when_odtoff: The DRAM VrefCA when DRAM CA odt off. uint: parts per thousand. 241